From eb7eba2d926e578e0ca7814b9ee6046812889f52 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 11 May 2021 10:54:57 +1000 Subject: [PATCH 1/4] dcache: Snoop writes to memory by other agents This adds a path where the wishbone that goes out to memory and I/O also gets fed back to the dcache, which looks for writes that it didn't initiate, and invalidates any cache line that gets written to. This involves a second read port on the cache tag RAM for looking up the snooped writes, and effectively a second write port on the cache valid bit array to clear bits corresponding to snoop hits. Signed-off-by: Paul Mackerras --- core.vhdl | 3 +++ dcache.vhdl | 35 ++++++++++++++++++++++++++++++++++- soc.vhdl | 14 ++++++++++++++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/core.vhdl b/core.vhdl index 6c637c7..cd2bb07 100644 --- a/core.vhdl +++ b/core.vhdl @@ -37,6 +37,8 @@ entity core is wishbone_data_in : in wishbone_slave_out; wishbone_data_out : out wishbone_master_out; + wb_snoop_in : in wishbone_master_out; + dmi_addr : in std_ulogic_vector(3 downto 0); dmi_din : in std_ulogic_vector(63 downto 0); dmi_dout : out std_ulogic_vector(63 downto 0); @@ -423,6 +425,7 @@ begin stall_out => dcache_stall_out, wishbone_in => wishbone_data_in, wishbone_out => wishbone_data_out, + snoop_in => wb_snoop_in, log_out => log_data(170 downto 151) ); diff --git a/dcache.vhdl b/dcache.vhdl index bb93148..9916279 100644 --- a/dcache.vhdl +++ b/dcache.vhdl @@ -39,6 +39,8 @@ entity dcache is m_in : in MmuToDcacheType; m_out : out DcacheToMmuType; + snoop_in : in wishbone_master_out := wishbone_master_out_init; + stall_out : out std_ulogic; wishbone_out : out wishbone_master_out; @@ -415,6 +417,11 @@ architecture rtl of dcache is type tlb_plru_out_t is array(tlb_index_t) of std_ulogic_vector(TLB_WAY_BITS-1 downto 0); signal tlb_plru_victim : tlb_plru_out_t; + signal snoop_tag_set : cache_tags_set_t; + signal snoop_valid : std_ulogic; + signal snoop_wrtag : cache_tag_t; + signal snoop_index : index_t; + -- -- Helper functions to decode incoming requests -- @@ -528,7 +535,8 @@ begin assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE; assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE; assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE; - assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE; + assert ispow2(ROW_PER_LINE) and ROW_PER_LINE > 1 + report "ROW_PER_LINE not power of 2 greater than 1" severity FAILURE; assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS) report "geometry bits don't add up" severity FAILURE; assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS) @@ -783,6 +791,24 @@ begin end if; end process; + -- Cache tag RAM second read port, for snooping + cache_tag_read_2 : process(clk) + variable addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + begin + if rising_edge(clk) then + addr := (others => '0'); + addr(snoop_in.adr'left downto 0) := snoop_in.adr; + snoop_tag_set <= cache_tags(get_index(addr)); + snoop_wrtag <= get_tag(addr); + snoop_index <= get_index(addr); + -- Don't snoop our own cycles + snoop_valid <= '0'; + if not (r1.wb.cyc = '1' and wishbone_in.stall = '0') then + snoop_valid <= snoop_in.cyc and snoop_in.stb and snoop_in.we; + end if; + end if; + end process; + -- Cache request parsing and hit detection dcache_request : process(all) variable is_hit : std_ulogic; @@ -1293,6 +1319,13 @@ begin end if; end if; + -- Do invalidations from snooped stores to memory + for i in way_t loop + if snoop_valid = '1' and read_tag(i, snoop_tag_set) = snoop_wrtag then + cache_valids(snoop_index)(i) <= '0'; + end if; + end loop; + if r1.write_tag = '1' then -- Store new tag in selected way for i in 0 to NUM_WAYS-1 loop diff --git a/soc.vhdl b/soc.vhdl index d03f114..38bd5df 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -133,6 +133,7 @@ architecture behaviour of soc is -- Wishbone master (output of arbiter): signal wb_master_in : wishbone_slave_out; signal wb_master_out : wishbone_master_out; + signal wb_snoop : wishbone_master_out; -- Main "IO" bus, from main slave decoder to the latch signal wb_io_in : wishbone_master_out; @@ -284,6 +285,7 @@ begin wishbone_insn_out => wishbone_icore_out, wishbone_data_in => wishbone_dcore_in, wishbone_data_out => wishbone_dcore_out, + wb_snoop_in => wb_snoop, dmi_addr => dmi_addr(3 downto 0), dmi_dout => dmi_core_dout, dmi_din => dmi_dout, @@ -313,6 +315,18 @@ begin wb_slave_in => wb_master_in ); + -- Snoop bus going to caches. + -- Gate stb with stall so the caches don't see the stalled strobes. + -- That way if the caches see a strobe when their wishbone is stalled, + -- they know it is an access by another master. + process(all) + begin + wb_snoop <= wb_master_out; + if wb_master_in.stall = '1' then + wb_snoop.stb <= '0'; + end if; + end process; + -- Top level Wishbone slaves address decoder & mux -- -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0 From 4c11c9c6619f5ca0ad4e5d54b9d760ffdbb017d6 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 11 May 2021 11:29:46 +1000 Subject: [PATCH 2/4] dcache: Simplify logic in RELOAD_WAIT_ACK state Since the expression is_last_row(r1.store_row, r1.end_row_ix) can only be true when stbs_done is true, there is no need to include stbs_done in the expression for the reload being completed, and hence no need to compute stbs_done in the RELOAD_WAIT_ACK state. Signed-off-by: Paul Mackerras --- dcache.vhdl | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/dcache.vhdl b/dcache.vhdl index 9916279..50060b2 100644 --- a/dcache.vhdl +++ b/dcache.vhdl @@ -1458,18 +1458,11 @@ begin end case; when RELOAD_WAIT_ACK => - -- Requests are all sent if stb is 0 - stbs_done := r1.wb.stb = '0'; - -- If we are still sending requests, was one accepted ? - if wishbone_in.stall = '0' and not stbs_done then - -- That was the last word ? We are done sending. Clear - -- stb and set stbs_done so we can handle an eventual last - -- ack on the same cycle. - -- + if wishbone_in.stall = '0' and r1.wb.stb = '1' then + -- That was the last word ? We are done sending. Clear stb. if is_last_row_addr(r1.wb.adr, r1.end_row_ix) then r1.wb.stb <= '0'; - stbs_done := true; end if; -- Calculate the next row address @@ -1500,7 +1493,7 @@ begin end if; -- Check for completion - if stbs_done and is_last_row(r1.store_row, r1.end_row_ix) then + if is_last_row(r1.store_row, r1.end_row_ix) then -- Complete wishbone cycle r1.wb.cyc <= '0'; From 231003f7c7fdb3654bda4bdb61719c5fb80cfe06 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 11 May 2021 14:04:08 +1000 Subject: [PATCH 3/4] icache: Snoop writes to memory by other agents This makes the icache snoop writes to memory in the same way that the dcache does, thus making DMA cache-coherent for the icache as well as the dcache. This also simplifies the logic for the WAIT_ACK state by removing the stbs_done variable, since is_last_row(r.store_row, r.end_row_ix) can only be true when stbs_done is true. Signed-off-by: Paul Mackerras --- core.vhdl | 1 + icache.vhdl | 55 +++++++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 46 insertions(+), 10 deletions(-) diff --git a/core.vhdl b/core.vhdl index cd2bb07..c36f9cf 100644 --- a/core.vhdl +++ b/core.vhdl @@ -243,6 +243,7 @@ begin stall_out => icache_stall_out, wishbone_out => wishbone_insn_out, wishbone_in => wishbone_insn_in, + wb_snoop_in => wb_snoop_in, log_out => log_data(96 downto 43) ); diff --git a/icache.vhdl b/icache.vhdl index a658783..4d3b12e 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -68,6 +68,8 @@ entity icache is wishbone_out : out wishbone_master_out; wishbone_in : in wishbone_slave_out; + wb_snoop_in : in wishbone_master_out := wishbone_master_out_init; + log_out : out std_ulogic_vector(53 downto 0) ); end entity icache; @@ -220,8 +222,13 @@ architecture rtl of icache is signal plru_victim : plru_out_t; signal replace_way : way_t; + -- Memory write snoop signals + signal snoop_valid : std_ulogic; + signal snoop_index : index_t; + signal snoop_hits : cache_way_valids_t; + -- Return the cache line index (tag index) for an address - function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is + function get_index(addr: std_ulogic_vector) return index_t is begin return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS))); end; @@ -614,7 +621,10 @@ begin -- Cache miss/reload synchronous machine icache_miss : process(clk) variable tagset : cache_tags_set_t; - variable stbs_done : boolean; + variable tag : cache_tag_t; + variable snoop_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + variable snoop_tag : cache_tag_t; + variable snoop_cache_tags : cache_tags_set_t; begin if rising_edge(clk) then -- On reset, clear all valid bits to force misses @@ -633,13 +643,43 @@ begin -- Not useful normally but helps avoiding tons of sim warnings r.wb.adr <= (others => '0'); + + snoop_valid <= '0'; + snoop_index <= 0; + snoop_hits <= (others => '0'); else + -- Detect snooped writes and decode address into index and tag + -- Since we never write, any write should be snooped + snoop_valid <= wb_snoop_in.cyc and wb_snoop_in.stb and wb_snoop_in.we; + snoop_addr := (others => '0'); + snoop_addr(wb_snoop_in.adr'left downto 0) := wb_snoop_in.adr; + snoop_index <= get_index(snoop_addr); + snoop_cache_tags := cache_tags(get_index(snoop_addr)); + snoop_tag := get_tag(snoop_addr, '0'); + snoop_hits <= (others => '0'); + for i in way_t loop + tag := read_tag(i, snoop_cache_tags); + -- Ignore endian bit in comparison + tag(TAG_BITS - 1) := '0'; + if tag = snoop_tag then + snoop_hits(i) <= '1'; + end if; + end loop; + -- Process cache invalidations if inval_in = '1' then for i in index_t loop cache_valids(i) <= (others => '0'); end loop; r.store_valid <= '0'; + else + -- Do invalidations from snooped stores to memory, one + -- cycle after the address appears on wb_snoop_in. + for i in way_t loop + if snoop_valid = '1' and snoop_hits(i) = '1' then + cache_valids(snoop_index)(i) <= '0'; + end if; + end loop; end if; -- Main state machine @@ -697,18 +737,13 @@ begin r.state <= WAIT_ACK; end if; - -- Requests are all sent if stb is 0 - stbs_done := r.wb.stb = '0'; -- If we are still sending requests, was one accepted ? - if wishbone_in.stall = '0' and not stbs_done then - -- That was the last word ? We are done sending. Clear - -- stb and set stbs_done so we can handle an eventual last - -- ack on the same cycle. + if wishbone_in.stall = '0' and r.wb.stb = '1' then + -- That was the last word ? We are done sending. Clear stb. -- if is_last_row_addr(r.wb.adr, r.end_row_ix) then r.wb.stb <= '0'; - stbs_done := true; end if; -- Calculate the next row address @@ -719,7 +754,7 @@ begin if wishbone_in.ack = '1' then r.rows_valid(r.store_row mod ROW_PER_LINE) <= '1'; -- Check for completion - if stbs_done and is_last_row(r.store_row, r.end_row_ix) then + if is_last_row(r.store_row, r.end_row_ix) then -- Complete wishbone cycle r.wb.cyc <= '0'; From 21ed730514eb367245bc67dccaaf64b00648a1f7 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Thu, 15 Apr 2021 17:22:31 +1000 Subject: [PATCH 4/4] arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras --- fpga/arty_a7.xdc | 23 + fpga/top-arty.vhdl | 139 +- include/microwatt_soc.h | 2 + litesdcard/fusesoc-add-files.py | 27 + litesdcard/gen-src/generate.sh | 35 + litesdcard/generated/arty/litesdcard_core.v | 4159 +++++++++++++++++++ litesdcard/litesdcard.core | 15 + microwatt.core | 29 +- soc.vhdl | 60 +- syscon.vhdl | 19 +- wishbone_types.vhdl | 2 + 11 files changed, 4489 insertions(+), 21 deletions(-) create mode 100644 litesdcard/fusesoc-add-files.py create mode 100755 litesdcard/gen-src/generate.sh create mode 100644 litesdcard/generated/arty/litesdcard_core.v create mode 100644 litesdcard/litesdcard.core diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 7cdad8d..bf8310c 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -72,6 +72,19 @@ set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_ #set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_9 }]; #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_10 }]; +# connection to Digilent PmodSD on JA +set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[3] }]; +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_cmd }]; +set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[0] }]; +set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }]; +set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[1] }]; +set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[2] }]; +set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }]; +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { sdcard_wp }]; + +# Put registers into IOBs to improve timing +set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}] + ################################################################################ # PMOD header JB (high-speed, no protection resisters) ################################################################################ @@ -85,6 +98,16 @@ set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_ #set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_9 }]; #set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_10 }]; +# connection to Digilent PmodSD on JB +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[3] }]; +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_cmd }]; +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[0] }]; +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }]; +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[1] }]; +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[2] }]; +#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }]; +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sdcard_wp }]; + ################################################################################ # PMOD header JC (high-speed, no protection resisters) ################################################################################ diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 68d1e89..cb7f781 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -26,7 +26,8 @@ entity toplevel is LOG_LENGTH : natural := 512; USE_LITEETH : boolean := false; UART_IS_16550 : boolean := false; - HAS_UART1 : boolean := true + HAS_UART1 : boolean := true; + USE_LITESDCARD : boolean := false ); port( ext_clk : in std_ulogic; @@ -74,6 +75,12 @@ entity toplevel is eth_col : in std_ulogic; eth_crs : in std_ulogic; + -- SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + -- DRAM wires ddram_a : out std_ulogic_vector(13 downto 0); ddram_ba : out std_ulogic_vector(2 downto 0); @@ -110,6 +117,7 @@ architecture behaviour of toplevel is signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; signal wb_ext_is_eth : std_ulogic; + signal wb_ext_is_sdcard : std_ulogic; -- DRAM main data wishbone connection signal wb_dram_in : wishbone_master_out; @@ -122,6 +130,16 @@ architecture behaviour of toplevel is signal ext_irq_eth : std_ulogic; signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init; + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + -- Control/status signal core_alt_reset : std_ulogic; @@ -184,7 +202,8 @@ begin LOG_LENGTH => LOG_LENGTH, HAS_LITEETH => USE_LITEETH, UART0_IS_16550 => UART_IS_16550, - HAS_UART1 => HAS_UART1 + HAS_UART1 => HAS_UART1, + HAS_SD_CARD => USE_LITESDCARD ) port map ( -- System signals @@ -208,15 +227,24 @@ begin -- External interrupts ext_irq_eth => ext_irq_eth, + ext_irq_sdcard => ext_irq_sdcard, -- DRAM wishbone wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, + + -- IO wishbone wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_init => wb_ext_is_dram_init, wb_ext_is_eth => wb_ext_is_eth, + wb_ext_is_sdcard => wb_ext_is_sdcard, + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out, + alt_reset => core_alt_reset ); @@ -523,8 +551,113 @@ begin ext_irq_eth <= '0'; end generate; + -- SD card pmod + has_sdcard : if USE_LITESDCARD generate + component litesdcard_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + -- wishbone for accessing control registers + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + -- wishbone for SD card core to use for DMA + wb_dma_adr : out std_ulogic_vector(29 downto 0); + wb_dma_dat_w : out std_ulogic_vector(31 downto 0); + wb_dma_dat_r : in std_ulogic_vector(31 downto 0); + wb_dma_sel : out std_ulogic_vector(3 downto 0); + wb_dma_cyc : out std_ulogic; + wb_dma_stb : out std_ulogic; + wb_dma_ack : in std_ulogic; + wb_dma_we : out std_ulogic; + wb_dma_cti : out std_ulogic_vector(2 downto 0); + wb_dma_bte : out std_ulogic_vector(1 downto 0); + wb_dma_err : in std_ulogic; + -- connections to SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + irq : out std_ulogic + ); + end component; + + signal wb_sdcard_cyc : std_ulogic; + signal wb_sdcard_adr : std_ulogic_vector(29 downto 0); + + begin + litesdcard : litesdcard_core + port map ( + clk => system_clk, + rst => soc_rst, + wb_ctrl_adr => wb_sdcard_adr, + wb_ctrl_dat_w => wb_ext_io_in.dat, + wb_ctrl_dat_r => wb_sdcard_out.dat, + wb_ctrl_sel => wb_ext_io_in.sel, + wb_ctrl_cyc => wb_sdcard_cyc, + wb_ctrl_stb => wb_ext_io_in.stb, + wb_ctrl_ack => wb_sdcard_out.ack, + wb_ctrl_we => wb_ext_io_in.we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + wb_dma_adr => wb_sddma_nr.adr, + wb_dma_dat_w => wb_sddma_nr.dat, + wb_dma_dat_r => wb_sddma_ir.dat, + wb_dma_sel => wb_sddma_nr.sel, + wb_dma_cyc => wb_sddma_nr.cyc, + wb_dma_stb => wb_sddma_nr.stb, + wb_dma_ack => wb_sddma_ir.ack, + wb_dma_we => wb_sddma_nr.we, + wb_dma_cti => open, + wb_dma_bte => open, + wb_dma_err => '0', + sdcard_data => sdcard_data, + sdcard_cmd => sdcard_cmd, + sdcard_clk => sdcard_clk, + sdcard_cd => sdcard_cd, + irq => ext_irq_sdcard + ); + + -- Gate cyc with chip select from SoC + wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard; + + wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(15 downto 2); + + wb_sdcard_out.stall <= not wb_sdcard_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_sddma_out <= wb_sddma_nr; + if wb_sddma_stb_sent = '1' or + (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then + wb_sddma_out.stb <= '0'; + end if; + if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then + wb_sddma_stb_sent <= '0'; + elsif wb_sddma_in.stall = '0' then + wb_sddma_stb_sent <= wb_sddma_nr.stb; + end if; + wb_sddma_ir <= wb_sddma_in; + end if; + end process; + + end generate; + -- Mux WB response on the IO bus - wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else wb_dram_ctrl_out; + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else + wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_dram_ctrl_out; leds_pwm : process(system_clk) begin diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index a224d74..b138be1 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -17,6 +17,7 @@ #define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */ #define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */ #define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */ +#define LSDC_CSR_BASE 0xc8040000 /* LiteSDCard MMIO space */ #define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */ #define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */ @@ -40,6 +41,7 @@ #define SYS_REG_INFO_HAS_LARGE_SYSCON (1ull << 5) #define SYS_REG_INFO_HAS_UART1 (1ull << 6) #define SYS_REG_INFO_HAS_ARTB (1ull << 7) +#define SYS_REG_INFO_HAS_LITESDCARD (1ull << 8) #define SYS_REG_BRAMINFO 0x10 #define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull #define SYS_REG_DRAMINFO 0x18 diff --git a/litesdcard/fusesoc-add-files.py b/litesdcard/fusesoc-add-files.py new file mode 100644 index 0000000..0ae2759 --- /dev/null +++ b/litesdcard/fusesoc-add-files.py @@ -0,0 +1,27 @@ +#!/usr/bin/python3 +from fusesoc.capi2.generator import Generator +import os +import sys +import pathlib + +class LiteSDCardGenerator(Generator): + def run(self): + board = self.config.get('board') + + # Collect a bunch of directory path + script_dir = os.path.dirname(sys.argv[0]) + gen_dir = os.path.join(script_dir, "generated", board) + + print("Adding LiteSDCard for board... ", board) + + # Add files to fusesoc + files = [] + f = os.path.join(gen_dir, "litesdcard_core.v") + files.append({f : {'file_type' : 'verilogSource'}}) + + self.add_files(files) + +g = LiteSDCardGenerator() +g.run() +g.write() + diff --git a/litesdcard/gen-src/generate.sh b/litesdcard/gen-src/generate.sh new file mode 100755 index 0000000..0cde805 --- /dev/null +++ b/litesdcard/gen-src/generate.sh @@ -0,0 +1,35 @@ +#!/bin/bash + +TARGETS=arty + +ME=$(realpath $0) +echo ME=$ME +MY_PATH=$(dirname $ME) +echo MYPATH=$MY_PATH +PARENT_PATH=$(realpath $MY_PATH/..) +echo PARENT=$PARENT_PATH +BUILD_PATH=$PARENT_PATH/build +mkdir -p $BUILD_PATH +GEN_PATH=$PARENT_PATH/generated +mkdir -p $GEN_PATH + +# Note litesdcard/gen.py doesn't parse a YAML file, instead it takes +# a --vendor=xxx parameter, where xxx = xilinx or lattice. If we +# want to generate litesdcard for ecp5 we'll have to invent a way to +# map arty to xilinx and ecp5 to lattice + +for i in $TARGETS +do + TARGET_BUILD_PATH=$BUILD_PATH/$i + TARGET_GEN_PATH=$GEN_PATH/$i + rm -rf $TARGET_BUILD_PATH + rm -rf $TARGET_GEN_PATH + mkdir -p $TARGET_BUILD_PATH + mkdir -p $TARGET_GEN_PATH + + echo "Generating $i in $TARGET_BUILD_PATH" + (cd $TARGET_BUILD_PATH && litesdcard_gen) + + cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/ +done + diff --git a/litesdcard/generated/arty/litesdcard_core.v b/litesdcard/generated/arty/litesdcard_core.v new file mode 100644 index 0000000..8100e72 --- /dev/null +++ b/litesdcard/generated/arty/litesdcard_core.v @@ -0,0 +1,4159 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (3ffd64c) & LiteX (b55af215) on 2021-04-22 14:46:05 +//-------------------------------------------------------------------------------- +module litesdcard_core( + input wire clk, + input wire rst, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire [29:0] wb_dma_adr, + output wire [31:0] wb_dma_dat_w, + input wire [31:0] wb_dma_dat_r, + output wire [3:0] wb_dma_sel, + output wire wb_dma_cyc, + output wire wb_dma_stb, + input wire wb_dma_ack, + output wire wb_dma_we, + output wire [2:0] wb_dma_cti, + output wire [1:0] wb_dma_bte, + input wire wb_dma_err, + inout wire [3:0] sdcard_data, + inout wire sdcard_cmd, + output reg sdcard_clk, + input wire sdcard_cd, + output wire irq +); + +wire sys_clk; +wire sys_rst; +wire por_clk; +reg int_rst = 1'd1; +reg reset_storage = 1'd0; +reg reset_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg scratch_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg bus_errors_re = 1'd0; +wire reset; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +wire [29:0] wb_ctrl_adr_1; +wire [31:0] wb_ctrl_dat_w_1; +wire [31:0] wb_ctrl_dat_r_1; +wire [3:0] wb_ctrl_sel_1; +wire wb_ctrl_cyc_1; +wire wb_ctrl_stb_1; +wire wb_ctrl_ack_1; +wire wb_ctrl_we_1; +wire [2:0] wb_ctrl_cti_1; +wire [1:0] wb_ctrl_bte_1; +wire wb_ctrl_err_1; +wire [29:0] wb_dma_adr_1; +wire [31:0] wb_dma_dat_w_1; +wire [31:0] wb_dma_dat_r_1; +wire [3:0] wb_dma_sel_1; +wire wb_dma_cyc_1; +wire wb_dma_stb_1; +wire wb_dma_ack_1; +wire wb_dma_we_1; +wire [2:0] wb_dma_cti_1; +wire [1:0] wb_dma_bte_1; +wire wb_dma_err_1; +wire card_detect_status0; +wire card_detect_we; +reg card_detect_re = 1'd0; +reg [8:0] clocker_storage = 9'd256; +reg clocker_re = 1'd0; +wire clocker_stop; +wire clocker_ce; +wire clocker_clk_en; +wire clocker_clk0; +reg [8:0] clocker_clks = 9'd0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +reg init_initialize_re = 1'd0; +wire init_initialize_r; +reg init_initialize_we = 1'd0; +reg init_initialize_w = 1'd0; +wire init_pads_in_valid; +wire init_pads_in_payload_cmd_i; +wire [3:0] init_pads_in_payload_data_i; +wire init_pads_out_ready; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +reg [7:0] init_count = 8'd0; +wire cmdw_pads_in_valid; +wire cmdw_pads_in_payload_cmd_i; +wire [3:0] cmdw_pads_in_payload_data_i; +wire cmdw_pads_out_ready; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_last = 1'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg cmdw_done = 1'd0; +reg [7:0] cmdw_count = 8'd0; +wire cmdr_pads_in_pads_in_valid; +wire cmdr_pads_in_pads_in_ready; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +wire cmdr_pads_in_pads_in_payload_cmd_i; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] cmdr_pads_in_pads_in_payload_data_i; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +wire cmdr_pads_out_ready; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_sink_ready = 1'd0; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_source_valid = 1'd0; +reg cmdr_source_ready = 1'd0; +reg cmdr_source_last = 1'd0; +reg [7:0] cmdr_source_payload_data = 8'd0; +reg [2:0] cmdr_source_payload_status = 3'd0; +reg [31:0] cmdr_timeout = 32'd100000000; +reg [7:0] cmdr_count = 8'd0; +reg cmdr_busy = 1'd0; +wire cmdr_cmdr_pads_in_valid; +reg cmdr_cmdr_pads_in_ready = 1'd0; +wire cmdr_cmdr_pads_in_first; +wire cmdr_cmdr_pads_in_last; +wire cmdr_cmdr_pads_in_payload_clk; +wire cmdr_cmdr_pads_in_payload_cmd_i; +wire cmdr_cmdr_pads_in_payload_cmd_o; +wire cmdr_cmdr_pads_in_payload_cmd_oe; +wire [3:0] cmdr_cmdr_pads_in_payload_data_i; +wire [3:0] cmdr_cmdr_pads_in_payload_data_o; +wire cmdr_cmdr_pads_in_payload_data_oe; +wire cmdr_cmdr_pads_in_payload_data_i_ce; +wire cmdr_cmdr_source_source_valid0; +reg cmdr_cmdr_source_source_ready0 = 1'd0; +wire cmdr_cmdr_source_source_first0; +wire cmdr_cmdr_source_source_last0; +wire [7:0] cmdr_cmdr_source_source_payload_data0; +wire cmdr_cmdr_start; +reg cmdr_cmdr_run = 1'd0; +wire cmdr_cmdr_converter_sink_valid; +wire cmdr_cmdr_converter_sink_ready; +reg cmdr_cmdr_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_sink_last = 1'd0; +wire cmdr_cmdr_converter_sink_payload_data; +wire cmdr_cmdr_converter_source_valid; +wire cmdr_cmdr_converter_source_ready; +reg cmdr_cmdr_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_source_payload_valid_token_count = 4'd0; +reg [2:0] cmdr_cmdr_converter_demux = 3'd0; +wire cmdr_cmdr_converter_load_part; +reg cmdr_cmdr_converter_strobe_all = 1'd0; +wire cmdr_cmdr_source_source_valid1; +wire cmdr_cmdr_source_source_ready1; +wire cmdr_cmdr_source_source_first1; +wire cmdr_cmdr_source_source_last1; +wire [7:0] cmdr_cmdr_source_source_payload_data1; +wire cmdr_cmdr_buf_sink_valid; +wire cmdr_cmdr_buf_sink_ready; +wire cmdr_cmdr_buf_sink_first; +wire cmdr_cmdr_buf_sink_last; +wire [7:0] cmdr_cmdr_buf_sink_payload_data; +reg cmdr_cmdr_buf_source_valid = 1'd0; +wire cmdr_cmdr_buf_source_ready; +reg cmdr_cmdr_buf_source_first = 1'd0; +reg cmdr_cmdr_buf_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_source_payload_data = 8'd0; +reg cmdr_cmdr_reset = 1'd0; +wire dataw_pads_in_pads_in_valid; +reg dataw_pads_in_pads_in_ready = 1'd0; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; +wire dataw_pads_in_pads_in_payload_cmd_i; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] dataw_pads_in_pads_in_payload_data_i; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +wire dataw_pads_out_ready; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +reg dataw_sink_valid = 1'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_stop = 1'd0; +wire dataw_accepted0; +wire dataw_crc_error0; +wire dataw_write_error0; +reg [2:0] dataw_status = 3'd0; +wire dataw_we; +reg dataw_re = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg dataw_accepted1 = 1'd0; +reg dataw_crc_error1 = 1'd0; +reg dataw_write_error1 = 1'd0; +wire dataw_crc_pads_in_valid; +wire dataw_crc_pads_in_ready; +wire dataw_crc_pads_in_first; +wire dataw_crc_pads_in_last; +wire dataw_crc_pads_in_payload_clk; +wire dataw_crc_pads_in_payload_cmd_i; +wire dataw_crc_pads_in_payload_cmd_o; +wire dataw_crc_pads_in_payload_cmd_oe; +wire [3:0] dataw_crc_pads_in_payload_data_i; +wire [3:0] dataw_crc_pads_in_payload_data_o; +wire dataw_crc_pads_in_payload_data_oe; +wire dataw_crc_pads_in_payload_data_i_ce; +wire dataw_crc_source_source_valid0; +reg dataw_crc_source_source_ready0 = 1'd0; +wire dataw_crc_source_source_first0; +wire dataw_crc_source_source_last0; +wire [7:0] dataw_crc_source_source_payload_data0; +wire dataw_crc_start; +reg dataw_crc_run = 1'd0; +wire dataw_crc_converter_sink_valid; +wire dataw_crc_converter_sink_ready; +reg dataw_crc_converter_sink_first = 1'd0; +reg dataw_crc_converter_sink_last = 1'd0; +wire dataw_crc_converter_sink_payload_data; +wire dataw_crc_converter_source_valid; +wire dataw_crc_converter_source_ready; +reg dataw_crc_converter_source_first = 1'd0; +reg dataw_crc_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_source_payload_valid_token_count = 4'd0; +reg [2:0] dataw_crc_converter_demux = 3'd0; +wire dataw_crc_converter_load_part; +reg dataw_crc_converter_strobe_all = 1'd0; +wire dataw_crc_source_source_valid1; +wire dataw_crc_source_source_ready1; +wire dataw_crc_source_source_first1; +wire dataw_crc_source_source_last1; +wire [7:0] dataw_crc_source_source_payload_data1; +wire dataw_crc_buf_sink_valid; +wire dataw_crc_buf_sink_ready; +wire dataw_crc_buf_sink_first; +wire dataw_crc_buf_sink_last; +wire [7:0] dataw_crc_buf_sink_payload_data; +reg dataw_crc_buf_source_valid = 1'd0; +wire dataw_crc_buf_source_ready; +reg dataw_crc_buf_source_first = 1'd0; +reg dataw_crc_buf_source_last = 1'd0; +reg [7:0] dataw_crc_buf_source_payload_data = 8'd0; +reg dataw_crc_reset = 1'd0; +wire datar_pads_in_pads_in_valid; +wire datar_pads_in_pads_in_ready; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; +wire datar_pads_in_pads_in_payload_cmd_i; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] datar_pads_in_pads_in_payload_data_i; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +wire datar_pads_out_ready; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_source_valid = 1'd0; +reg datar_source_ready = 1'd0; +reg datar_source_first = 1'd0; +reg datar_source_last = 1'd0; +reg [7:0] datar_source_payload_data = 8'd0; +reg [2:0] datar_source_payload_status = 3'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd100000000; +reg [9:0] datar_count = 10'd0; +wire datar_datar_pads_in_valid; +reg datar_datar_pads_in_ready = 1'd0; +wire datar_datar_pads_in_first; +wire datar_datar_pads_in_last; +wire datar_datar_pads_in_payload_clk; +wire datar_datar_pads_in_payload_cmd_i; +wire datar_datar_pads_in_payload_cmd_o; +wire datar_datar_pads_in_payload_cmd_oe; +wire [3:0] datar_datar_pads_in_payload_data_i; +wire [3:0] datar_datar_pads_in_payload_data_o; +wire datar_datar_pads_in_payload_data_oe; +wire datar_datar_pads_in_payload_data_i_ce; +wire datar_datar_source_source_valid0; +reg datar_datar_source_source_ready0 = 1'd0; +wire datar_datar_source_source_first0; +wire datar_datar_source_source_last0; +wire [7:0] datar_datar_source_source_payload_data0; +wire datar_datar_start; +reg datar_datar_run = 1'd0; +wire datar_datar_converter_sink_valid; +wire datar_datar_converter_sink_ready; +reg datar_datar_converter_sink_first = 1'd0; +reg datar_datar_converter_sink_last = 1'd0; +wire [3:0] datar_datar_converter_sink_payload_data; +wire datar_datar_converter_source_valid; +wire datar_datar_converter_source_ready; +reg datar_datar_converter_source_first = 1'd0; +reg datar_datar_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_source_payload_valid_token_count = 2'd0; +reg datar_datar_converter_demux = 1'd0; +wire datar_datar_converter_load_part; +reg datar_datar_converter_strobe_all = 1'd0; +wire datar_datar_source_source_valid1; +wire datar_datar_source_source_ready1; +wire datar_datar_source_source_first1; +wire datar_datar_source_source_last1; +wire [7:0] datar_datar_source_source_payload_data1; +wire datar_datar_buf_sink_valid; +wire datar_datar_buf_sink_ready; +wire datar_datar_buf_sink_first; +wire datar_datar_buf_sink_last; +wire [7:0] datar_datar_buf_sink_payload_data; +reg datar_datar_buf_source_valid = 1'd0; +wire datar_datar_buf_source_ready; +reg datar_datar_buf_source_first = 1'd0; +reg datar_datar_buf_source_last = 1'd0; +reg [7:0] datar_datar_buf_source_payload_data = 8'd0; +reg datar_datar_reset = 1'd0; +wire sdpads_clk; +reg sdpads_cmd_i = 1'd0; +wire sdpads_cmd_o; +wire sdpads_cmd_oe; +reg [3:0] sdpads_data_i = 4'd0; +wire [3:0] sdpads_data_o; +wire sdpads_data_oe; +reg sdpads_data_i_ce = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +reg card_detect_irq = 1'd0; +reg card_detect_d = 1'd0; +wire sdcore_sink_sink_valid0; +wire sdcore_sink_sink_ready0; +wire sdcore_sink_sink_first0; +wire sdcore_sink_sink_last0; +wire [7:0] sdcore_sink_sink_payload_data0; +wire sdcore_source_source_valid0; +wire sdcore_source_source_ready0; +wire sdcore_source_source_first0; +wire sdcore_source_source_last0; +wire [7:0] sdcore_source_source_payload_data0; +reg [31:0] sdcore_cmd_argument_storage = 32'd0; +reg sdcore_cmd_argument_re = 1'd0; +wire [1:0] sdcore_csrfield_cmd_type; +wire [1:0] sdcore_csrfield_data_type; +wire [5:0] sdcore_csrfield_cmd; +reg [13:0] sdcore_cmd_command_storage = 14'd0; +reg sdcore_cmd_command_re = 1'd0; +reg sdcore_cmd_send_storage = 1'd0; +reg sdcore_cmd_send_re = 1'd0; +reg [127:0] sdcore_cmd_response_status = 128'd0; +wire sdcore_cmd_response_we; +reg sdcore_cmd_response_re = 1'd0; +wire sdcore_csrfield_done0; +wire sdcore_csrfield_error0; +wire sdcore_csrfield_timeout0; +wire sdcore_csrfield_crc0; +reg [3:0] sdcore_cmd_event_status = 4'd0; +wire sdcore_cmd_event_we; +reg sdcore_cmd_event_re = 1'd0; +wire sdcore_csrfield_done1; +wire sdcore_csrfield_error1; +wire sdcore_csrfield_timeout1; +wire sdcore_csrfield_crc1; +reg [3:0] sdcore_data_event_status = 4'd0; +wire sdcore_data_event_we; +reg sdcore_data_event_re = 1'd0; +reg [9:0] sdcore_block_length_storage = 10'd0; +reg sdcore_block_length_re = 1'd0; +reg [31:0] sdcore_block_count_storage = 32'd0; +reg sdcore_block_count_re = 1'd0; +wire sdcore_crc7_inserter_reset; +wire sdcore_crc7_inserter_enable; +wire [39:0] sdcore_crc7_inserter_din; +reg [6:0] sdcore_crc7_inserter_crc = 7'd0; +reg [6:0] sdcore_crc7_inserter_reg0 = 7'd0; +wire [6:0] sdcore_crc7_inserter_reg1; +wire [6:0] sdcore_crc7_inserter_reg2; +wire [6:0] sdcore_crc7_inserter_reg3; +wire [6:0] sdcore_crc7_inserter_reg4; +wire [6:0] sdcore_crc7_inserter_reg5; +wire [6:0] sdcore_crc7_inserter_reg6; +wire [6:0] sdcore_crc7_inserter_reg7; +wire [6:0] sdcore_crc7_inserter_reg8; +wire [6:0] sdcore_crc7_inserter_reg9; +wire [6:0] sdcore_crc7_inserter_reg10; +wire [6:0] sdcore_crc7_inserter_reg11; +wire [6:0] sdcore_crc7_inserter_reg12; +wire [6:0] sdcore_crc7_inserter_reg13; +wire [6:0] sdcore_crc7_inserter_reg14; +wire [6:0] sdcore_crc7_inserter_reg15; +wire [6:0] sdcore_crc7_inserter_reg16; +wire [6:0] sdcore_crc7_inserter_reg17; +wire [6:0] sdcore_crc7_inserter_reg18; +wire [6:0] sdcore_crc7_inserter_reg19; +wire [6:0] sdcore_crc7_inserter_reg20; +wire [6:0] sdcore_crc7_inserter_reg21; +wire [6:0] sdcore_crc7_inserter_reg22; +wire [6:0] sdcore_crc7_inserter_reg23; +wire [6:0] sdcore_crc7_inserter_reg24; +wire [6:0] sdcore_crc7_inserter_reg25; +wire [6:0] sdcore_crc7_inserter_reg26; +wire [6:0] sdcore_crc7_inserter_reg27; +wire [6:0] sdcore_crc7_inserter_reg28; +wire [6:0] sdcore_crc7_inserter_reg29; +wire [6:0] sdcore_crc7_inserter_reg30; +wire [6:0] sdcore_crc7_inserter_reg31; +wire [6:0] sdcore_crc7_inserter_reg32; +wire [6:0] sdcore_crc7_inserter_reg33; +wire [6:0] sdcore_crc7_inserter_reg34; +wire [6:0] sdcore_crc7_inserter_reg35; +wire [6:0] sdcore_crc7_inserter_reg36; +wire [6:0] sdcore_crc7_inserter_reg37; +wire [6:0] sdcore_crc7_inserter_reg38; +wire [6:0] sdcore_crc7_inserter_reg39; +wire [6:0] sdcore_crc7_inserter_reg40; +wire sdcore_crc16_inserter_sink_valid; +reg sdcore_crc16_inserter_sink_ready = 1'd0; +wire sdcore_crc16_inserter_sink_first; +wire sdcore_crc16_inserter_sink_last; +wire [7:0] sdcore_crc16_inserter_sink_payload_data; +reg sdcore_crc16_inserter_source_valid = 1'd0; +reg sdcore_crc16_inserter_source_ready = 1'd0; +reg sdcore_crc16_inserter_source_first = 1'd0; +reg sdcore_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcore_crc16_inserter_source_payload_data = 8'd0; +reg [2:0] sdcore_crc16_inserter_count = 3'd0; +wire sdcore_crc16_inserter_crc0_reset; +wire sdcore_crc16_inserter_crc0_enable; +reg [1:0] sdcore_crc16_inserter_crc0_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc0_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc0_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc0_reg1; +wire [15:0] sdcore_crc16_inserter_crc0_reg2; +wire sdcore_crc16_inserter_crc1_reset; +wire sdcore_crc16_inserter_crc1_enable; +reg [1:0] sdcore_crc16_inserter_crc1_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc1_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc1_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc1_reg1; +wire [15:0] sdcore_crc16_inserter_crc1_reg2; +wire sdcore_crc16_inserter_crc2_reset; +wire sdcore_crc16_inserter_crc2_enable; +reg [1:0] sdcore_crc16_inserter_crc2_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc2_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc2_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc2_reg1; +wire [15:0] sdcore_crc16_inserter_crc2_reg2; +wire sdcore_crc16_inserter_crc3_reset; +wire sdcore_crc16_inserter_crc3_enable; +reg [1:0] sdcore_crc16_inserter_crc3_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc3_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc3_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc3_reg1; +wire [15:0] sdcore_crc16_inserter_crc3_reg2; +reg sdcore_sink_sink_valid1 = 1'd0; +wire sdcore_sink_sink_ready1; +reg sdcore_sink_sink_first1 = 1'd0; +reg sdcore_sink_sink_last1 = 1'd0; +reg [7:0] sdcore_sink_sink_payload_data1 = 8'd0; +wire sdcore_source_source_valid1; +wire sdcore_source_source_ready1; +wire sdcore_source_source_first1; +wire sdcore_source_source_last1; +wire [7:0] sdcore_source_source_payload_data1; +wire sdcore_fifo_sink_valid; +wire sdcore_fifo_sink_ready; +wire sdcore_fifo_sink_first; +wire sdcore_fifo_sink_last; +wire [7:0] sdcore_fifo_sink_payload_data; +wire sdcore_fifo_source_valid; +wire sdcore_fifo_source_ready; +wire sdcore_fifo_source_first; +wire sdcore_fifo_source_last; +wire [7:0] sdcore_fifo_source_payload_data; +wire sdcore_fifo_syncfifo_we; +wire sdcore_fifo_syncfifo_writable; +wire sdcore_fifo_syncfifo_re; +wire sdcore_fifo_syncfifo_readable; +wire [9:0] sdcore_fifo_syncfifo_din; +wire [9:0] sdcore_fifo_syncfifo_dout; +reg [3:0] sdcore_fifo_level = 4'd0; +reg sdcore_fifo_replace = 1'd0; +reg [2:0] sdcore_fifo_produce = 3'd0; +reg [2:0] sdcore_fifo_consume = 3'd0; +reg [2:0] sdcore_fifo_wrport_adr = 3'd0; +wire [9:0] sdcore_fifo_wrport_dat_r; +wire sdcore_fifo_wrport_we; +wire [9:0] sdcore_fifo_wrport_dat_w; +wire sdcore_fifo_do_read; +wire [2:0] sdcore_fifo_rdport_adr; +wire [9:0] sdcore_fifo_rdport_dat_r; +wire [7:0] sdcore_fifo_fifo_in_payload_data; +wire sdcore_fifo_fifo_in_first; +wire sdcore_fifo_fifo_in_last; +wire [7:0] sdcore_fifo_fifo_out_payload_data; +wire sdcore_fifo_fifo_out_first; +wire sdcore_fifo_fifo_out_last; +wire sdcore_fifo_reset; +wire [1:0] sdcore_cmd_type; +reg [2:0] sdcore_cmd_count = 3'd0; +reg sdcore_cmd_done = 1'd0; +reg sdcore_cmd_error = 1'd0; +reg sdcore_cmd_timeout = 1'd0; +wire [1:0] sdcore_data_type; +reg [31:0] sdcore_data_count = 32'd0; +reg sdcore_data_done = 1'd0; +reg sdcore_data_error = 1'd0; +reg sdcore_data_timeout = 1'd0; +wire [5:0] sdcore_cmd; +wire [31:0] interface0_bus_adr; +wire [31:0] interface0_bus_dat_w; +wire [31:0] interface0_bus_dat_r; +wire [3:0] interface0_bus_sel; +wire interface0_bus_cyc; +wire interface0_bus_stb; +wire interface0_bus_ack; +wire interface0_bus_we; +reg [2:0] interface0_bus_cti = 3'd0; +reg [1:0] interface0_bus_bte = 2'd0; +wire interface0_bus_err; +wire sdblock2mem_sink_sink_valid0; +reg sdblock2mem_sink_sink_ready0 = 1'd0; +wire sdblock2mem_sink_sink_first; +wire sdblock2mem_sink_sink_last0; +wire [7:0] sdblock2mem_sink_sink_payload_data0; +reg sdblock2mem_irq = 1'd0; +reg sdblock2mem_fifo_sink_valid = 1'd0; +wire sdblock2mem_fifo_sink_ready; +reg sdblock2mem_fifo_sink_first = 1'd0; +reg sdblock2mem_fifo_sink_last = 1'd0; +reg [7:0] sdblock2mem_fifo_sink_payload_data = 8'd0; +wire sdblock2mem_fifo_source_valid; +wire sdblock2mem_fifo_source_ready; +wire sdblock2mem_fifo_source_first; +wire sdblock2mem_fifo_source_last; +wire [7:0] sdblock2mem_fifo_source_payload_data; +wire sdblock2mem_fifo_syncfifo_we; +wire sdblock2mem_fifo_syncfifo_writable; +wire sdblock2mem_fifo_syncfifo_re; +wire sdblock2mem_fifo_syncfifo_readable; +wire [9:0] sdblock2mem_fifo_syncfifo_din; +wire [9:0] sdblock2mem_fifo_syncfifo_dout; +reg [9:0] sdblock2mem_fifo_level = 10'd0; +reg sdblock2mem_fifo_replace = 1'd0; +reg [8:0] sdblock2mem_fifo_produce = 9'd0; +reg [8:0] sdblock2mem_fifo_consume = 9'd0; +reg [8:0] sdblock2mem_fifo_wrport_adr = 9'd0; +wire [9:0] sdblock2mem_fifo_wrport_dat_r; +wire sdblock2mem_fifo_wrport_we; +wire [9:0] sdblock2mem_fifo_wrport_dat_w; +wire sdblock2mem_fifo_do_read; +wire [8:0] sdblock2mem_fifo_rdport_adr; +wire [9:0] sdblock2mem_fifo_rdport_dat_r; +wire [7:0] sdblock2mem_fifo_fifo_in_payload_data; +wire sdblock2mem_fifo_fifo_in_first; +wire sdblock2mem_fifo_fifo_in_last; +wire [7:0] sdblock2mem_fifo_fifo_out_payload_data; +wire sdblock2mem_fifo_fifo_out_first; +wire sdblock2mem_fifo_fifo_out_last; +wire sdblock2mem_converter_sink_valid; +wire sdblock2mem_converter_sink_ready; +wire sdblock2mem_converter_sink_first; +wire sdblock2mem_converter_sink_last; +wire [7:0] sdblock2mem_converter_sink_payload_data; +wire sdblock2mem_converter_source_valid; +wire sdblock2mem_converter_source_ready; +reg sdblock2mem_converter_source_first = 1'd0; +reg sdblock2mem_converter_source_last = 1'd0; +reg [31:0] sdblock2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdblock2mem_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] sdblock2mem_converter_demux = 2'd0; +wire sdblock2mem_converter_load_part; +reg sdblock2mem_converter_strobe_all = 1'd0; +wire sdblock2mem_source_source_valid; +wire sdblock2mem_source_source_ready; +wire sdblock2mem_source_source_first; +wire sdblock2mem_source_source_last; +wire [31:0] sdblock2mem_source_source_payload_data; +reg sdblock2mem_sink_sink_valid1 = 1'd0; +wire sdblock2mem_sink_sink_ready1; +reg sdblock2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdblock2mem_sink_sink_payload_address = 32'd0; +reg [31:0] sdblock2mem_sink_sink_payload_data1 = 32'd0; +wire sdblock2mem_wishbonedmawriter_sink_valid; +reg sdblock2mem_wishbonedmawriter_sink_ready = 1'd0; +wire sdblock2mem_wishbonedmawriter_sink_first; +wire sdblock2mem_wishbonedmawriter_sink_last; +wire [31:0] sdblock2mem_wishbonedmawriter_sink_payload_data; +reg [63:0] sdblock2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdblock2mem_wishbonedmawriter_base_re = 1'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdblock2mem_wishbonedmawriter_length_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_enable_storage = 1'd0; +reg sdblock2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_done_status = 1'd0; +wire sdblock2mem_wishbonedmawriter_done_we; +reg sdblock2mem_wishbonedmawriter_done_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_loop_storage = 1'd0; +reg sdblock2mem_wishbonedmawriter_loop_re = 1'd0; +wire [31:0] sdblock2mem_wishbonedmawriter_offset_status; +wire sdblock2mem_wishbonedmawriter_offset_we; +reg sdblock2mem_wishbonedmawriter_offset_re = 1'd0; +wire [31:0] sdblock2mem_wishbonedmawriter_base; +reg [31:0] sdblock2mem_wishbonedmawriter_offset = 32'd0; +wire [31:0] sdblock2mem_wishbonedmawriter_length; +wire sdblock2mem_wishbonedmawriter_reset; +wire sdblock2mem_start; +reg sdblock2mem_connect = 1'd0; +reg sdblock2mem_done_d = 1'd0; +reg [31:0] interface1_bus_adr = 32'd0; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire [31:0] interface1_bus_dat_r; +reg [3:0] interface1_bus_sel = 4'd0; +reg interface1_bus_cyc = 1'd0; +reg interface1_bus_stb = 1'd0; +wire interface1_bus_ack; +reg interface1_bus_we = 1'd0; +reg [2:0] interface1_bus_cti = 3'd0; +reg [1:0] interface1_bus_bte = 2'd0; +wire interface1_bus_err; +wire sdmem2block_source_source_valid0; +wire sdmem2block_source_source_ready0; +wire sdmem2block_source_source_first0; +reg sdmem2block_source_source_last0 = 1'd0; +wire [7:0] sdmem2block_source_source_payload_data0; +reg sdmem2block_irq = 1'd0; +reg sdmem2block_dma_sink_valid = 1'd0; +reg sdmem2block_dma_sink_ready = 1'd0; +reg sdmem2block_dma_sink_last = 1'd0; +reg [31:0] sdmem2block_dma_sink_payload_address = 32'd0; +reg sdmem2block_dma_source_valid = 1'd0; +wire sdmem2block_dma_source_ready; +reg sdmem2block_dma_source_first = 1'd0; +reg sdmem2block_dma_source_last = 1'd0; +reg [31:0] sdmem2block_dma_source_payload_data = 32'd0; +reg [31:0] sdmem2block_dma_data = 32'd0; +reg [63:0] sdmem2block_dma_base_storage = 64'd0; +reg sdmem2block_dma_base_re = 1'd0; +reg [31:0] sdmem2block_dma_length_storage = 32'd0; +reg sdmem2block_dma_length_re = 1'd0; +reg sdmem2block_dma_enable_storage = 1'd0; +reg sdmem2block_dma_enable_re = 1'd0; +reg sdmem2block_dma_done_status = 1'd0; +wire sdmem2block_dma_done_we; +reg sdmem2block_dma_done_re = 1'd0; +reg sdmem2block_dma_loop_storage = 1'd0; +reg sdmem2block_dma_loop_re = 1'd0; +wire [31:0] sdmem2block_dma_offset_status; +wire sdmem2block_dma_offset_we; +reg sdmem2block_dma_offset_re = 1'd0; +wire [31:0] sdmem2block_dma_base; +reg [31:0] sdmem2block_dma_offset = 32'd0; +wire [31:0] sdmem2block_dma_length; +wire sdmem2block_dma_reset; +wire sdmem2block_converter_sink_valid; +wire sdmem2block_converter_sink_ready; +wire sdmem2block_converter_sink_first; +wire sdmem2block_converter_sink_last; +wire [31:0] sdmem2block_converter_sink_payload_data; +wire sdmem2block_converter_source_valid; +wire sdmem2block_converter_source_ready; +wire sdmem2block_converter_source_first; +wire sdmem2block_converter_source_last; +reg [7:0] sdmem2block_converter_source_payload_data = 8'd0; +wire sdmem2block_converter_source_payload_valid_token_count; +reg [1:0] sdmem2block_converter_mux = 2'd0; +wire sdmem2block_converter_first; +wire sdmem2block_converter_last; +wire sdmem2block_source_source_valid1; +wire sdmem2block_source_source_ready1; +wire sdmem2block_source_source_first1; +wire sdmem2block_source_source_last1; +wire [7:0] sdmem2block_source_source_payload_data1; +wire sdmem2block_fifo_sink_valid; +wire sdmem2block_fifo_sink_ready; +wire sdmem2block_fifo_sink_first; +wire sdmem2block_fifo_sink_last; +wire [7:0] sdmem2block_fifo_sink_payload_data; +wire sdmem2block_fifo_source_valid; +wire sdmem2block_fifo_source_ready; +wire sdmem2block_fifo_source_first; +wire sdmem2block_fifo_source_last; +wire [7:0] sdmem2block_fifo_source_payload_data; +wire sdmem2block_fifo_syncfifo_we; +wire sdmem2block_fifo_syncfifo_writable; +wire sdmem2block_fifo_syncfifo_re; +wire sdmem2block_fifo_syncfifo_readable; +wire [9:0] sdmem2block_fifo_syncfifo_din; +wire [9:0] sdmem2block_fifo_syncfifo_dout; +reg [9:0] sdmem2block_fifo_level = 10'd0; +reg sdmem2block_fifo_replace = 1'd0; +reg [8:0] sdmem2block_fifo_produce = 9'd0; +reg [8:0] sdmem2block_fifo_consume = 9'd0; +reg [8:0] sdmem2block_fifo_wrport_adr = 9'd0; +wire [9:0] sdmem2block_fifo_wrport_dat_r; +wire sdmem2block_fifo_wrport_we; +wire [9:0] sdmem2block_fifo_wrport_dat_w; +wire sdmem2block_fifo_do_read; +wire [8:0] sdmem2block_fifo_rdport_adr; +wire [9:0] sdmem2block_fifo_rdport_dat_r; +wire [7:0] sdmem2block_fifo_fifo_in_payload_data; +wire sdmem2block_fifo_fifo_in_first; +wire sdmem2block_fifo_fifo_in_last; +wire [7:0] sdmem2block_fifo_fifo_out_payload_data; +wire sdmem2block_fifo_fifo_out_first; +wire sdmem2block_fifo_fifo_out_last; +reg [8:0] sdmem2block_count = 9'd0; +reg sdmem2block_done_d = 1'd0; +wire sdirq_irq; +wire card_detect_status1; +reg card_detect_pending = 1'd0; +wire card_detect_trigger; +reg card_detect_clear = 1'd0; +wire block2mem_dma_status; +reg block2mem_dma_pending = 1'd0; +wire block2mem_dma_trigger; +reg block2mem_dma_clear = 1'd0; +wire mem2block_dma_status; +reg mem2block_dma_pending = 1'd0; +wire mem2block_dma_trigger; +reg mem2block_dma_clear = 1'd0; +wire cmd_done_status; +wire cmd_done_pending; +wire cmd_done_trigger; +reg cmd_done_clear = 1'd0; +wire eventmanager_card_detect0; +wire eventmanager_block2mem_dma0; +wire eventmanager_mem2block_dma0; +wire eventmanager_cmd_done0; +reg [3:0] eventmanager_status_status = 4'd0; +wire eventmanager_status_we; +reg eventmanager_status_re = 1'd0; +wire eventmanager_card_detect1; +wire eventmanager_block2mem_dma1; +wire eventmanager_mem2block_dma1; +wire eventmanager_cmd_done1; +reg [3:0] eventmanager_pending_status = 4'd0; +wire eventmanager_pending_we; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_r = 4'd0; +wire eventmanager_card_detect2; +wire eventmanager_block2mem_dma2; +wire eventmanager_mem2block_dma2; +wire eventmanager_cmd_done2; +reg [3:0] eventmanager_enable_storage = 4'd0; +reg eventmanager_enable_re = 1'd0; +reg subfragments_sdphyinit_state = 1'd0; +reg subfragments_sdphyinit_next_state = 1'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +reg [1:0] subfragments_sdphycmdw_state = 2'd0; +reg [1:0] subfragments_sdphycmdw_next_state = 2'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg [2:0] subfragments_sdphycmdr_state = 3'd0; +reg [2:0] subfragments_sdphycmdr_next_state = 3'd0; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg [2:0] subfragments_sdphydataw_state = 3'd0; +reg [2:0] subfragments_sdphydataw_next_state = 3'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +reg [2:0] subfragments_sdphydatar_state = 3'd0; +reg [2:0] subfragments_sdphydatar_next_state = 3'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg subfragments_sdcore_crc16inserter_state = 1'd0; +reg subfragments_sdcore_crc16inserter_next_state = 1'd0; +reg [2:0] sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value = 3'd0; +reg sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce = 1'd0; +reg [2:0] subfragments_sdcore_fsm_state = 3'd0; +reg [2:0] subfragments_sdcore_fsm_next_state = 3'd0; +reg sdcore_cmd_done_sdcore_fsm_next_value0 = 1'd0; +reg sdcore_cmd_done_sdcore_fsm_next_value_ce0 = 1'd0; +reg sdcore_data_done_sdcore_fsm_next_value1 = 1'd0; +reg sdcore_data_done_sdcore_fsm_next_value_ce1 = 1'd0; +reg [2:0] sdcore_cmd_count_sdcore_fsm_next_value2 = 3'd0; +reg sdcore_cmd_count_sdcore_fsm_next_value_ce2 = 1'd0; +reg [31:0] sdcore_data_count_sdcore_fsm_next_value3 = 32'd0; +reg sdcore_data_count_sdcore_fsm_next_value_ce3 = 1'd0; +reg sdcore_cmd_error_sdcore_fsm_next_value4 = 1'd0; +reg sdcore_cmd_error_sdcore_fsm_next_value_ce4 = 1'd0; +reg sdcore_cmd_timeout_sdcore_fsm_next_value5 = 1'd0; +reg sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 = 1'd0; +reg sdcore_data_error_sdcore_fsm_next_value6 = 1'd0; +reg sdcore_data_error_sdcore_fsm_next_value_ce6 = 1'd0; +reg sdcore_data_timeout_sdcore_fsm_next_value7 = 1'd0; +reg sdcore_data_timeout_sdcore_fsm_next_value_ce7 = 1'd0; +reg [127:0] sdcore_cmd_response_status_sdcore_fsm_next_value8 = 128'd0; +reg sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 = 1'd0; +reg [1:0] subfragments_state = 2'd0; +reg [1:0] subfragments_next_state = 2'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_offset_next_value = 32'd0; +reg sdblock2mem_wishbonedmawriter_offset_next_value_ce = 1'd0; +reg subfragments_sdmem2blockdma_fsm_state = 1'd0; +reg subfragments_sdmem2blockdma_fsm_next_state = 1'd0; +reg [31:0] sdmem2block_dma_data_sdmem2blockdma_fsm_next_value = 32'd0; +reg sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce = 1'd0; +reg [1:0] subfragments_sdmem2blockdma_resetinserter_state = 2'd0; +reg [1:0] subfragments_sdmem2blockdma_resetinserter_next_state = 2'd0; +reg [31:0] sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value = 32'd0; +reg sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce = 1'd0; +reg [13:0] litesdcardcore_litesdcardcore_adr = 14'd0; +reg litesdcardcore_litesdcardcore_we = 1'd0; +reg [31:0] litesdcardcore_litesdcardcore_dat_w = 32'd0; +wire [31:0] litesdcardcore_litesdcardcore_dat_r; +wire [29:0] litesdcardcore_litesdcardcore_wishbone_adr; +wire [31:0] litesdcardcore_litesdcardcore_wishbone_dat_w; +reg [31:0] litesdcardcore_litesdcardcore_wishbone_dat_r = 32'd0; +wire [3:0] litesdcardcore_litesdcardcore_wishbone_sel; +wire litesdcardcore_litesdcardcore_wishbone_cyc; +wire litesdcardcore_litesdcardcore_wishbone_stb; +reg litesdcardcore_litesdcardcore_wishbone_ack = 1'd0; +wire litesdcardcore_litesdcardcore_wishbone_we; +wire [2:0] litesdcardcore_litesdcardcore_wishbone_cti; +wire [1:0] litesdcardcore_litesdcardcore_wishbone_bte; +reg litesdcardcore_litesdcardcore_wishbone_err = 1'd0; +wire [29:0] litesdcardcore_shared_adr; +wire [31:0] litesdcardcore_shared_dat_w; +reg [31:0] litesdcardcore_shared_dat_r = 32'd0; +wire [3:0] litesdcardcore_shared_sel; +wire litesdcardcore_shared_cyc; +wire litesdcardcore_shared_stb; +reg litesdcardcore_shared_ack = 1'd0; +wire litesdcardcore_shared_we; +wire [2:0] litesdcardcore_shared_cti; +wire [1:0] litesdcardcore_shared_bte; +wire litesdcardcore_shared_err; +wire [1:0] litesdcardcore_request; +reg litesdcardcore_grant = 1'd0; +wire litesdcardcore_slave_sel; +reg litesdcardcore_slave_sel_r = 1'd0; +reg litesdcardcore_error = 1'd0; +wire litesdcardcore_wait; +wire litesdcardcore_done; +reg [19:0] litesdcardcore_count = 20'd1000000; +wire [13:0] litesdcardcore_interface0_bank_bus_adr; +wire litesdcardcore_interface0_bank_bus_we; +wire [31:0] litesdcardcore_interface0_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface0_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank0_reset0_re = 1'd0; +wire litesdcardcore_csrbank0_reset0_r; +reg litesdcardcore_csrbank0_reset0_we = 1'd0; +wire litesdcardcore_csrbank0_reset0_w; +reg litesdcardcore_csrbank0_scratch0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank0_scratch0_r; +reg litesdcardcore_csrbank0_scratch0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank0_scratch0_w; +reg litesdcardcore_csrbank0_bus_errors_re = 1'd0; +wire [31:0] litesdcardcore_csrbank0_bus_errors_r; +reg litesdcardcore_csrbank0_bus_errors_we = 1'd0; +wire [31:0] litesdcardcore_csrbank0_bus_errors_w; +wire litesdcardcore_csrbank0_sel; +wire [13:0] litesdcardcore_interface1_bank_bus_adr; +wire litesdcardcore_interface1_bank_bus_we; +wire [31:0] litesdcardcore_interface1_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface1_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank1_dma_base1_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base1_r; +reg litesdcardcore_csrbank1_dma_base1_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base1_w; +reg litesdcardcore_csrbank1_dma_base0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base0_r; +reg litesdcardcore_csrbank1_dma_base0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base0_w; +reg litesdcardcore_csrbank1_dma_length0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_length0_r; +reg litesdcardcore_csrbank1_dma_length0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_length0_w; +reg litesdcardcore_csrbank1_dma_enable0_re = 1'd0; +wire litesdcardcore_csrbank1_dma_enable0_r; +reg litesdcardcore_csrbank1_dma_enable0_we = 1'd0; +wire litesdcardcore_csrbank1_dma_enable0_w; +reg litesdcardcore_csrbank1_dma_done_re = 1'd0; +wire litesdcardcore_csrbank1_dma_done_r; +reg litesdcardcore_csrbank1_dma_done_we = 1'd0; +wire litesdcardcore_csrbank1_dma_done_w; +reg litesdcardcore_csrbank1_dma_loop0_re = 1'd0; +wire litesdcardcore_csrbank1_dma_loop0_r; +reg litesdcardcore_csrbank1_dma_loop0_we = 1'd0; +wire litesdcardcore_csrbank1_dma_loop0_w; +reg litesdcardcore_csrbank1_dma_offset_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_offset_r; +reg litesdcardcore_csrbank1_dma_offset_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_offset_w; +wire litesdcardcore_csrbank1_sel; +wire [13:0] litesdcardcore_interface2_bank_bus_adr; +wire litesdcardcore_interface2_bank_bus_we; +wire [31:0] litesdcardcore_interface2_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface2_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank2_cmd_argument0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_argument0_r; +reg litesdcardcore_csrbank2_cmd_argument0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_argument0_w; +reg litesdcardcore_csrbank2_cmd_command0_re = 1'd0; +wire [13:0] litesdcardcore_csrbank2_cmd_command0_r; +reg litesdcardcore_csrbank2_cmd_command0_we = 1'd0; +wire [13:0] litesdcardcore_csrbank2_cmd_command0_w; +reg litesdcardcore_csrbank2_cmd_send0_re = 1'd0; +wire litesdcardcore_csrbank2_cmd_send0_r; +reg litesdcardcore_csrbank2_cmd_send0_we = 1'd0; +wire litesdcardcore_csrbank2_cmd_send0_w; +reg litesdcardcore_csrbank2_cmd_response3_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response3_r; +reg litesdcardcore_csrbank2_cmd_response3_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response3_w; +reg litesdcardcore_csrbank2_cmd_response2_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response2_r; +reg litesdcardcore_csrbank2_cmd_response2_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response2_w; +reg litesdcardcore_csrbank2_cmd_response1_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response1_r; +reg litesdcardcore_csrbank2_cmd_response1_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response1_w; +reg litesdcardcore_csrbank2_cmd_response0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response0_r; +reg litesdcardcore_csrbank2_cmd_response0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response0_w; +reg litesdcardcore_csrbank2_cmd_event_re = 1'd0; +wire [3:0] litesdcardcore_csrbank2_cmd_event_r; +reg litesdcardcore_csrbank2_cmd_event_we = 1'd0; +wire [3:0] litesdcardcore_csrbank2_cmd_event_w; +reg litesdcardcore_csrbank2_data_event_re = 1'd0; +wire [3:0] litesdcardcore_csrbank2_data_event_r; +reg litesdcardcore_csrbank2_data_event_we = 1'd0; +wire [3:0] litesdcardcore_csrbank2_data_event_w; +reg litesdcardcore_csrbank2_block_length0_re = 1'd0; +wire [9:0] litesdcardcore_csrbank2_block_length0_r; +reg litesdcardcore_csrbank2_block_length0_we = 1'd0; +wire [9:0] litesdcardcore_csrbank2_block_length0_w; +reg litesdcardcore_csrbank2_block_count0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_block_count0_r; +reg litesdcardcore_csrbank2_block_count0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_block_count0_w; +wire litesdcardcore_csrbank2_sel; +wire [13:0] litesdcardcore_interface3_bank_bus_adr; +wire litesdcardcore_interface3_bank_bus_we; +wire [31:0] litesdcardcore_interface3_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface3_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank3_status_re = 1'd0; +wire [3:0] litesdcardcore_csrbank3_status_r; +reg litesdcardcore_csrbank3_status_we = 1'd0; +wire [3:0] litesdcardcore_csrbank3_status_w; +reg litesdcardcore_csrbank3_pending_re = 1'd0; +wire [3:0] litesdcardcore_csrbank3_pending_r; +reg litesdcardcore_csrbank3_pending_we = 1'd0; +wire [3:0] litesdcardcore_csrbank3_pending_w; +reg litesdcardcore_csrbank3_enable0_re = 1'd0; +wire [3:0] litesdcardcore_csrbank3_enable0_r; +reg litesdcardcore_csrbank3_enable0_we = 1'd0; +wire [3:0] litesdcardcore_csrbank3_enable0_w; +wire litesdcardcore_csrbank3_sel; +wire [13:0] litesdcardcore_interface4_bank_bus_adr; +wire litesdcardcore_interface4_bank_bus_we; +wire [31:0] litesdcardcore_interface4_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface4_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank4_dma_base1_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base1_r; +reg litesdcardcore_csrbank4_dma_base1_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base1_w; +reg litesdcardcore_csrbank4_dma_base0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base0_r; +reg litesdcardcore_csrbank4_dma_base0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base0_w; +reg litesdcardcore_csrbank4_dma_length0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_length0_r; +reg litesdcardcore_csrbank4_dma_length0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_length0_w; +reg litesdcardcore_csrbank4_dma_enable0_re = 1'd0; +wire litesdcardcore_csrbank4_dma_enable0_r; +reg litesdcardcore_csrbank4_dma_enable0_we = 1'd0; +wire litesdcardcore_csrbank4_dma_enable0_w; +reg litesdcardcore_csrbank4_dma_done_re = 1'd0; +wire litesdcardcore_csrbank4_dma_done_r; +reg litesdcardcore_csrbank4_dma_done_we = 1'd0; +wire litesdcardcore_csrbank4_dma_done_w; +reg litesdcardcore_csrbank4_dma_loop0_re = 1'd0; +wire litesdcardcore_csrbank4_dma_loop0_r; +reg litesdcardcore_csrbank4_dma_loop0_we = 1'd0; +wire litesdcardcore_csrbank4_dma_loop0_w; +reg litesdcardcore_csrbank4_dma_offset_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_offset_r; +reg litesdcardcore_csrbank4_dma_offset_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_offset_w; +wire litesdcardcore_csrbank4_sel; +wire [13:0] litesdcardcore_interface5_bank_bus_adr; +wire litesdcardcore_interface5_bank_bus_we; +wire [31:0] litesdcardcore_interface5_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface5_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank5_card_detect_re = 1'd0; +wire litesdcardcore_csrbank5_card_detect_r; +reg litesdcardcore_csrbank5_card_detect_we = 1'd0; +wire litesdcardcore_csrbank5_card_detect_w; +reg litesdcardcore_csrbank5_clocker_divider0_re = 1'd0; +wire [8:0] litesdcardcore_csrbank5_clocker_divider0_r; +reg litesdcardcore_csrbank5_clocker_divider0_we = 1'd0; +wire [8:0] litesdcardcore_csrbank5_clocker_divider0_w; +reg litesdcardcore_csrbank5_dataw_status_re = 1'd0; +wire [2:0] litesdcardcore_csrbank5_dataw_status_r; +reg litesdcardcore_csrbank5_dataw_status_we = 1'd0; +wire [2:0] litesdcardcore_csrbank5_dataw_status_w; +wire litesdcardcore_csrbank5_sel; +wire [13:0] litesdcardcore_csr_interconnect_adr; +wire litesdcardcore_csr_interconnect_we; +wire [31:0] litesdcardcore_csr_interconnect_dat_w; +wire [31:0] litesdcardcore_csr_interconnect_dat_r; +reg litesdcardcore_state = 1'd0; +reg litesdcardcore_next_state = 1'd0; +reg [31:0] array_muxed0 = 32'd0; +reg [31:0] array_muxed1 = 32'd0; +reg [3:0] array_muxed2 = 4'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg [2:0] array_muxed6 = 3'd0; +reg [1:0] array_muxed7 = 2'd0; +wire sdrio_clk; +reg xilinxsdrtristateimpl0__o = 1'd0; +reg xilinxsdrtristateimpl0_oe_n = 1'd0; +wire xilinxsdrtristateimpl0__i; +reg xilinxsdrtristateimpl1__o = 1'd0; +reg xilinxsdrtristateimpl1_oe_n = 1'd0; +wire xilinxsdrtristateimpl1__i; +reg xilinxsdrtristateimpl2__o = 1'd0; +reg xilinxsdrtristateimpl2_oe_n = 1'd0; +wire xilinxsdrtristateimpl2__i; +reg xilinxsdrtristateimpl3__o = 1'd0; +reg xilinxsdrtristateimpl3_oe_n = 1'd0; +wire xilinxsdrtristateimpl3__i; +reg xilinxsdrtristateimpl4__o = 1'd0; +reg xilinxsdrtristateimpl4_oe_n = 1'd0; +wire xilinxsdrtristateimpl4__i; +wire sdrio_clk_1; +wire sdrio_clk_2; +wire sdrio_clk_3; +wire sdrio_clk_4; +wire sdrio_clk_5; +wire sdrio_clk_6; +wire sdrio_clk_7; +wire sdrio_clk_8; +wire sdrio_clk_9; +wire sdrio_clk_10; +wire sdrio_clk_11; +wire sdrio_clk_12; +wire sdrio_clk_13; +wire sdrio_clk_14; +wire sdrio_clk_15; + +assign wb_ctrl_adr_1 = wb_ctrl_adr; +assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; +assign wb_ctrl_sel_1 = wb_ctrl_sel; +assign wb_ctrl_cyc_1 = wb_ctrl_cyc; +assign wb_ctrl_stb_1 = wb_ctrl_stb; +assign wb_ctrl_ack = wb_ctrl_ack_1; +assign wb_ctrl_we_1 = wb_ctrl_we; +assign wb_ctrl_cti_1 = wb_ctrl_cti; +assign wb_ctrl_bte_1 = wb_ctrl_bte; +assign wb_ctrl_err = wb_ctrl_err_1; +assign wb_dma_adr = wb_dma_adr_1; +assign wb_dma_dat_w = wb_dma_dat_w_1; +assign wb_dma_dat_r_1 = wb_dma_dat_r; +assign wb_dma_sel = wb_dma_sel_1; +assign wb_dma_cyc = wb_dma_cyc_1; +assign wb_dma_stb = wb_dma_stb_1; +assign wb_dma_ack_1 = wb_dma_ack; +assign wb_dma_we = wb_dma_we_1; +assign wb_dma_cti = wb_dma_cti_1; +assign wb_dma_bte = wb_dma_bte_1; +assign wb_dma_err_1 = wb_dma_err; +assign sdblock2mem_sink_sink_valid0 = sdcore_source_source_valid0; +assign sdcore_source_source_ready0 = sdblock2mem_sink_sink_ready0; +assign sdblock2mem_sink_sink_first = sdcore_source_source_first0; +assign sdblock2mem_sink_sink_last0 = sdcore_source_source_last0; +assign sdblock2mem_sink_sink_payload_data0 = sdcore_source_source_payload_data0; +assign sdcore_sink_sink_valid0 = sdmem2block_source_source_valid0; +assign sdmem2block_source_source_ready0 = sdcore_sink_sink_ready0; +assign sdcore_sink_sink_first0 = sdmem2block_source_source_first0; +assign sdcore_sink_sink_last0 = sdmem2block_source_source_last0; +assign sdcore_sink_sink_payload_data0 = sdmem2block_source_source_payload_data0; +assign card_detect_trigger = card_detect_irq; +assign block2mem_dma_trigger = sdblock2mem_irq; +assign mem2block_dma_trigger = sdmem2block_irq; +assign cmd_done_trigger = sdcore_csrfield_done0; +assign irq = sdirq_irq; +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +assign reset = reset_re; +assign bus_errors_status = bus_errors; +assign card_detect_status0 = sdcard_cd; +assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); +assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); +assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); +assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); +assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); +assign init_pads_out_ready = clocker_ce; +assign cmdw_pads_out_ready = clocker_ce; +assign cmdr_pads_out_ready = clocker_ce; +assign dataw_pads_out_ready = clocker_ce; +assign datar_pads_out_ready = clocker_ce; +assign clocker_clk_en = sdpads_clk; +assign init_pads_in_valid = sdpads_data_i_ce; +assign init_pads_in_payload_cmd_i = sdpads_cmd_i; +assign init_pads_in_payload_data_i = sdpads_data_i; +assign cmdw_pads_in_valid = sdpads_data_i_ce; +assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdw_pads_in_payload_data_i = sdpads_data_i; +assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; +assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; +assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; +assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign clocker_stop = (dataw_stop | datar_stop); +always @(*) begin + clocker_clk1 <= 1'd0; + case (clocker_storage) + 3'd4: begin + clocker_clk1 <= clocker_clks[1]; + end + 4'd8: begin + clocker_clk1 <= clocker_clks[2]; + end + 5'd16: begin + clocker_clk1 <= clocker_clks[3]; + end + 6'd32: begin + clocker_clk1 <= clocker_clks[4]; + end + 7'd64: begin + clocker_clk1 <= clocker_clks[5]; + end + 8'd128: begin + clocker_clk1 <= clocker_clks[6]; + end + 9'd256: begin + clocker_clk1 <= clocker_clks[7]; + end + default: begin + clocker_clk1 <= clocker_clks[0]; + end + endcase +end +assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); +always @(*) begin + clocker_ce_latched <= 1'd0; + if (clocker_clk_d) begin + clocker_ce_latched <= clocker_clk_en; + end else begin + clocker_ce_latched <= clocker_ce_delayed; + end +end +assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); +always @(*) begin + subfragments_sdphyinit_next_state <= 1'd0; + init_count_sdphyinit_next_value <= 8'd0; + init_count_sdphyinit_next_value_ce <= 1'd0; + init_pads_out_payload_clk <= 1'd0; + init_pads_out_payload_cmd_o <= 1'd0; + init_pads_out_payload_cmd_oe <= 1'd0; + init_pads_out_payload_data_o <= 4'd0; + init_pads_out_payload_data_oe <= 1'd0; + subfragments_sdphyinit_next_state <= subfragments_sdphyinit_state; + case (subfragments_sdphyinit_state) + 1'd1: begin + init_pads_out_payload_clk <= 1'd1; + init_pads_out_payload_cmd_oe <= 1'd1; + init_pads_out_payload_cmd_o <= 1'd1; + init_pads_out_payload_data_oe <= 1'd1; + init_pads_out_payload_data_o <= 4'd15; + if (init_pads_out_ready) begin + init_count_sdphyinit_next_value <= (init_count + 1'd1); + init_count_sdphyinit_next_value_ce <= 1'd1; + if ((init_count == 7'd79)) begin + subfragments_sdphyinit_next_state <= 1'd0; + end + end + end + default: begin + init_count_sdphyinit_next_value <= 1'd0; + init_count_sdphyinit_next_value_ce <= 1'd1; + if (init_initialize_re) begin + subfragments_sdphyinit_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + cmdw_done <= 1'd0; + cmdw_pads_out_payload_clk <= 1'd0; + cmdw_pads_out_payload_cmd_o <= 1'd0; + cmdw_pads_out_payload_cmd_oe <= 1'd0; + cmdw_sink_ready <= 1'd0; + subfragments_sdphycmdw_next_state <= 2'd0; + cmdw_count_sdphycmdw_next_value <= 8'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd0; + subfragments_sdphycmdw_next_state <= subfragments_sdphycmdw_state; + case (subfragments_sdphycmdw_state) + 1'd1: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + case (cmdw_count) + 1'd0: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; + end + 1'd1: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; + end + 2'd2: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; + end + 2'd3: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; + end + 3'd4: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; + end + 3'd5: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; + end + 3'd6: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; + end + 3'd7: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; + end + endcase + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin + subfragments_sdphycmdw_next_state <= 2'd2; + end else begin + cmdw_sink_ready <= 1'd1; + subfragments_sdphycmdw_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + cmdw_pads_out_payload_cmd_o <= 1'd1; + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + cmdw_sink_ready <= 1'd1; + subfragments_sdphycmdw_next_state <= 1'd0; + end + end + end + default: begin + cmdw_count_sdphycmdw_next_value <= 1'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin + subfragments_sdphycmdw_next_state <= 1'd1; + end else begin + cmdw_done <= 1'd1; + end + end + endcase +end +assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; +assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; +assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; +assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; +assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; +assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; +assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; +assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; +assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; +assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; +assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; +assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; +assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); +assign cmdr_cmdr_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); +assign cmdr_cmdr_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; +assign cmdr_cmdr_buf_sink_valid = cmdr_cmdr_source_source_valid1; +assign cmdr_cmdr_source_source_ready1 = cmdr_cmdr_buf_sink_ready; +assign cmdr_cmdr_buf_sink_first = cmdr_cmdr_source_source_first1; +assign cmdr_cmdr_buf_sink_last = cmdr_cmdr_source_source_last1; +assign cmdr_cmdr_buf_sink_payload_data = cmdr_cmdr_source_source_payload_data1; +assign cmdr_cmdr_source_source_valid0 = cmdr_cmdr_buf_source_valid; +assign cmdr_cmdr_buf_source_ready = cmdr_cmdr_source_source_ready0; +assign cmdr_cmdr_source_source_first0 = cmdr_cmdr_buf_source_first; +assign cmdr_cmdr_source_source_last0 = cmdr_cmdr_buf_source_last; +assign cmdr_cmdr_source_source_payload_data0 = cmdr_cmdr_buf_source_payload_data; +assign cmdr_cmdr_source_source_valid1 = cmdr_cmdr_converter_source_valid; +assign cmdr_cmdr_converter_source_ready = cmdr_cmdr_source_source_ready1; +assign cmdr_cmdr_source_source_first1 = cmdr_cmdr_converter_source_first; +assign cmdr_cmdr_source_source_last1 = cmdr_cmdr_converter_source_last; +assign cmdr_cmdr_source_source_payload_data1 = cmdr_cmdr_converter_source_payload_data; +assign cmdr_cmdr_converter_sink_ready = ((~cmdr_cmdr_converter_strobe_all) | cmdr_cmdr_converter_source_ready); +assign cmdr_cmdr_converter_source_valid = cmdr_cmdr_converter_strobe_all; +assign cmdr_cmdr_converter_load_part = (cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready); +assign cmdr_cmdr_buf_sink_ready = ((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready); +always @(*) begin + cmdr_pads_out_payload_clk <= 1'd0; + cmdr_pads_out_payload_cmd_o <= 1'd0; + cmdr_pads_out_payload_cmd_oe <= 1'd0; + cmdr_cmdr_source_source_ready0 <= 1'd0; + subfragments_sdphycmdr_next_state <= 3'd0; + cmdr_sink_ready <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; + cmdr_count_sdphycmdr_next_value1 <= 8'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; + cmdr_source_valid <= 1'd0; + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; + cmdr_source_last <= 1'd0; + cmdr_source_payload_data <= 8'd0; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_source_payload_status <= 3'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; + subfragments_sdphycmdr_next_state <= subfragments_sdphycmdr_state; + case (subfragments_sdphycmdr_state) + 1'd1: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + if (cmdr_cmdr_source_source_valid0) begin + subfragments_sdphycmdr_next_state <= 2'd2; + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + subfragments_sdphycmdr_next_state <= 3'd5; + end + end + 2'd2: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_source_valid <= cmdr_cmdr_source_source_valid0; + cmdr_source_payload_status <= 1'd0; + cmdr_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); + cmdr_source_payload_data <= cmdr_cmdr_source_source_payload_data0; + if ((cmdr_cmdr_source_source_valid0 & cmdr_source_ready)) begin + cmdr_cmdr_source_source_ready0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if (cmdr_source_last) begin + cmdr_sink_ready <= 1'd1; + if ((cmdr_sink_payload_cmd_type == 2'd3)) begin + cmdr_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + subfragments_sdphycmdr_next_state <= 2'd3; + end else begin + if ((cmdr_sink_payload_data_type == 1'd0)) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + subfragments_sdphycmdr_next_state <= 3'd4; + end else begin + subfragments_sdphycmdr_next_state <= 1'd0; + end + end + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + subfragments_sdphycmdr_next_state <= 3'd5; + end + end + 2'd3: begin + cmdr_pads_out_payload_clk <= 1'd1; + if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + end + if ((~cmdr_busy)) begin + cmdr_source_valid <= 1'd1; + cmdr_source_last <= 1'd1; + cmdr_source_payload_status <= 1'd0; + if (cmdr_source_ready) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + subfragments_sdphycmdr_next_state <= 3'd4; + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + subfragments_sdphycmdr_next_state <= 3'd5; + end + end + 3'd4: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_pads_out_payload_cmd_oe <= 1'd1; + cmdr_pads_out_payload_cmd_o <= 1'd1; + if (cmdr_pads_out_ready) begin + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if ((cmdr_count == 3'd7)) begin + subfragments_sdphycmdr_next_state <= 1'd0; + end + end + end + 3'd5: begin + cmdr_sink_ready <= 1'd1; + cmdr_source_valid <= 1'd1; + cmdr_source_last <= 1'd1; + cmdr_source_payload_status <= 1'd1; + if (cmdr_source_ready) begin + subfragments_sdphycmdr_next_state <= 1'd0; + end + end + default: begin + cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + cmdr_busy_sdphycmdr_next_value2 <= 1'd1; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + subfragments_sdphycmdr_next_state <= 1'd1; + end + end + endcase +end +assign dataw_accepted0 = dataw_accepted1; +assign dataw_crc_error0 = dataw_crc_error1; +assign dataw_write_error0 = dataw_write_error1; +assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; +assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; +assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; +assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; +assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; +assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; +assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; +assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; +assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; +assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; +assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; +assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; +assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); +assign dataw_crc_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); +assign dataw_crc_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; +assign dataw_crc_buf_sink_valid = dataw_crc_source_source_valid1; +assign dataw_crc_source_source_ready1 = dataw_crc_buf_sink_ready; +assign dataw_crc_buf_sink_first = dataw_crc_source_source_first1; +assign dataw_crc_buf_sink_last = dataw_crc_source_source_last1; +assign dataw_crc_buf_sink_payload_data = dataw_crc_source_source_payload_data1; +assign dataw_crc_source_source_valid0 = dataw_crc_buf_source_valid; +assign dataw_crc_buf_source_ready = dataw_crc_source_source_ready0; +assign dataw_crc_source_source_first0 = dataw_crc_buf_source_first; +assign dataw_crc_source_source_last0 = dataw_crc_buf_source_last; +assign dataw_crc_source_source_payload_data0 = dataw_crc_buf_source_payload_data; +assign dataw_crc_source_source_valid1 = dataw_crc_converter_source_valid; +assign dataw_crc_converter_source_ready = dataw_crc_source_source_ready1; +assign dataw_crc_source_source_first1 = dataw_crc_converter_source_first; +assign dataw_crc_source_source_last1 = dataw_crc_converter_source_last; +assign dataw_crc_source_source_payload_data1 = dataw_crc_converter_source_payload_data; +assign dataw_crc_converter_sink_ready = ((~dataw_crc_converter_strobe_all) | dataw_crc_converter_source_ready); +assign dataw_crc_converter_source_valid = dataw_crc_converter_strobe_all; +assign dataw_crc_converter_load_part = (dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready); +assign dataw_crc_buf_sink_ready = ((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready); +always @(*) begin + dataw_count_sdphydataw_next_value_ce3 <= 1'd0; + dataw_pads_out_payload_clk <= 1'd0; + dataw_crc_reset <= 1'd0; + dataw_pads_out_payload_cmd_o <= 1'd0; + dataw_pads_out_payload_cmd_oe <= 1'd0; + dataw_pads_out_payload_data_o <= 4'd0; + dataw_pads_out_payload_data_oe <= 1'd0; + subfragments_sdphydataw_next_state <= 3'd0; + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_sink_ready <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; + dataw_stop <= 1'd0; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; + dataw_count_sdphydataw_next_value3 <= 8'd0; + subfragments_sdphydataw_next_state <= subfragments_sdphydataw_state; + case (subfragments_sdphydataw_state) + 1'd1: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_cmd_oe <= 1'd1; + dataw_pads_out_payload_cmd_o <= 1'd1; + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 3'd7)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + subfragments_sdphydataw_next_state <= 2'd2; + end + end + end + 2'd2: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 1'd0; + if (dataw_pads_out_ready) begin + subfragments_sdphydataw_next_state <= 2'd3; + end + end + 2'd3: begin + dataw_stop <= (~dataw_sink_valid); + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + case (dataw_count) + 1'd0: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; + end + 1'd1: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; + end + endcase + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 1'd1)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if (dataw_sink_last) begin + subfragments_sdphydataw_next_state <= 3'd4; + end else begin + dataw_sink_ready <= 1'd1; + end + end + end + end + 3'd4: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 4'd15; + if (dataw_pads_out_ready) begin + dataw_crc_reset <= 1'd1; + subfragments_sdphydataw_next_state <= 3'd5; + end + end + 3'd5: begin + dataw_pads_out_payload_clk <= 1'd1; + if (dataw_crc_source_source_valid0) begin + dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_source_payload_data0[7:5] == 2'd2); + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd5); + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd6); + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + subfragments_sdphydataw_next_state <= 3'd6; + end + end + 3'd6: begin + dataw_pads_out_payload_clk <= 1'd1; + if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin + dataw_sink_ready <= 1'd1; + subfragments_sdphydataw_next_state <= 1'd0; + end + end + default: begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_sink_valid & dataw_pads_out_ready)) begin + subfragments_sdphydataw_next_state <= 1'd1; + end + end + endcase +end +assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; +assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; +assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; +assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; +assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; +assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; +assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; +assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; +assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; +assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; +assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; +assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; +assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); +assign datar_datar_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_buf_sink_valid = datar_datar_source_source_valid1; +assign datar_datar_source_source_ready1 = datar_datar_buf_sink_ready; +assign datar_datar_buf_sink_first = datar_datar_source_source_first1; +assign datar_datar_buf_sink_last = datar_datar_source_source_last1; +assign datar_datar_buf_sink_payload_data = datar_datar_source_source_payload_data1; +assign datar_datar_source_source_valid0 = datar_datar_buf_source_valid; +assign datar_datar_buf_source_ready = datar_datar_source_source_ready0; +assign datar_datar_source_source_first0 = datar_datar_buf_source_first; +assign datar_datar_source_source_last0 = datar_datar_buf_source_last; +assign datar_datar_source_source_payload_data0 = datar_datar_buf_source_payload_data; +assign datar_datar_source_source_valid1 = datar_datar_converter_source_valid; +assign datar_datar_converter_source_ready = datar_datar_source_source_ready1; +assign datar_datar_source_source_first1 = datar_datar_converter_source_first; +assign datar_datar_source_source_last1 = datar_datar_converter_source_last; +assign datar_datar_source_source_payload_data1 = datar_datar_converter_source_payload_data; +assign datar_datar_converter_sink_ready = ((~datar_datar_converter_strobe_all) | datar_datar_converter_source_ready); +assign datar_datar_converter_source_valid = datar_datar_converter_strobe_all; +assign datar_datar_converter_load_part = (datar_datar_converter_sink_valid & datar_datar_converter_sink_ready); +assign datar_datar_buf_sink_ready = ((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready); +always @(*) begin + datar_source_valid <= 1'd0; + datar_source_first <= 1'd0; + datar_source_last <= 1'd0; + datar_source_payload_data <= 8'd0; + datar_source_payload_status <= 3'd0; + datar_stop <= 1'd0; + datar_pads_out_payload_clk <= 1'd0; + subfragments_sdphydatar_next_state <= 3'd0; + datar_count_sdphydatar_next_value0 <= 10'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd0; + datar_datar_source_source_ready0 <= 1'd0; + datar_timeout_sdphydatar_next_value1 <= 32'd0; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_sink_ready <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; + subfragments_sdphydatar_next_state <= subfragments_sdphydatar_state; + case (subfragments_sdphydatar_state) + 1'd1: begin + datar_pads_out_payload_clk <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if (datar_datar_source_source_valid0) begin + subfragments_sdphydatar_next_state <= 2'd2; + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + subfragments_sdphydatar_next_state <= 3'd4; + end + end + 2'd2: begin + datar_pads_out_payload_clk <= 1'd1; + datar_source_valid <= datar_datar_source_source_valid0; + datar_source_payload_status <= 1'd0; + datar_source_first <= (datar_count == 1'd0); + datar_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); + datar_source_payload_data <= datar_datar_source_source_payload_data0; + if (datar_source_valid) begin + if (datar_source_ready) begin + datar_datar_source_source_ready0 <= 1'd1; + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if (datar_source_last) begin + datar_sink_ready <= 1'd1; + if (datar_sink_last) begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + subfragments_sdphydatar_next_state <= 2'd3; + end else begin + subfragments_sdphydatar_next_state <= 1'd0; + end + end + end else begin + datar_stop <= 1'd1; + end + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + subfragments_sdphydatar_next_state <= 3'd4; + end + end + 2'd3: begin + datar_pads_out_payload_clk <= 1'd1; + if (datar_pads_out_ready) begin + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_count == 6'd39)) begin + subfragments_sdphydatar_next_state <= 1'd0; + end + end + end + 3'd4: begin + datar_source_valid <= 1'd1; + datar_source_payload_status <= 1'd1; + datar_source_last <= 1'd1; + if (datar_source_ready) begin + subfragments_sdphydatar_next_state <= 1'd0; + end + end + default: begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_sink_valid & datar_pads_out_ready)) begin + datar_pads_out_payload_clk <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= 32'd100000000; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd1; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + subfragments_sdphydatar_next_state <= 1'd1; + end + end + endcase +end +assign sdcore_crc16_inserter_sink_valid = sdcore_sink_sink_valid0; +assign sdcore_sink_sink_ready0 = sdcore_crc16_inserter_sink_ready; +assign sdcore_crc16_inserter_sink_first = sdcore_sink_sink_first0; +assign sdcore_crc16_inserter_sink_last = sdcore_sink_sink_last0; +assign sdcore_crc16_inserter_sink_payload_data = sdcore_sink_sink_payload_data0; +assign sdcore_source_source_valid0 = sdcore_source_source_valid1; +assign sdcore_source_source_ready1 = sdcore_source_source_ready0; +assign sdcore_source_source_first0 = sdcore_source_source_first1; +assign sdcore_source_source_last0 = sdcore_source_source_last1; +assign sdcore_source_source_payload_data0 = sdcore_source_source_payload_data1; +assign sdcore_cmd_type = sdcore_csrfield_cmd_type; +assign sdcore_data_type = sdcore_csrfield_data_type; +assign sdcore_cmd = sdcore_csrfield_cmd; +assign sdcore_csrfield_done0 = sdcore_cmd_done; +assign sdcore_csrfield_error0 = sdcore_cmd_error; +assign sdcore_csrfield_timeout0 = sdcore_cmd_timeout; +assign sdcore_csrfield_crc0 = 1'd0; +assign sdcore_csrfield_done1 = sdcore_data_done; +assign sdcore_csrfield_error1 = sdcore_data_error; +assign sdcore_csrfield_timeout1 = sdcore_data_timeout; +assign sdcore_csrfield_crc1 = 1'd0; +assign sdcore_crc7_inserter_din = {1'd0, 1'd1, sdcore_cmd, sdcore_cmd_argument_storage}; +assign sdcore_crc7_inserter_reset = 1'd1; +assign sdcore_crc7_inserter_enable = 1'd1; +assign sdcore_crc7_inserter_reg1 = {sdcore_crc7_inserter_reg0[5], sdcore_crc7_inserter_reg0[4], sdcore_crc7_inserter_reg0[3], (sdcore_crc7_inserter_reg0[2] ^ (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])), sdcore_crc7_inserter_reg0[1], sdcore_crc7_inserter_reg0[0], (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])}; +assign sdcore_crc7_inserter_reg2 = {sdcore_crc7_inserter_reg1[5], sdcore_crc7_inserter_reg1[4], sdcore_crc7_inserter_reg1[3], (sdcore_crc7_inserter_reg1[2] ^ (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])), sdcore_crc7_inserter_reg1[1], sdcore_crc7_inserter_reg1[0], (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])}; +assign sdcore_crc7_inserter_reg3 = {sdcore_crc7_inserter_reg2[5], sdcore_crc7_inserter_reg2[4], sdcore_crc7_inserter_reg2[3], (sdcore_crc7_inserter_reg2[2] ^ (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])), sdcore_crc7_inserter_reg2[1], sdcore_crc7_inserter_reg2[0], (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])}; +assign sdcore_crc7_inserter_reg4 = {sdcore_crc7_inserter_reg3[5], sdcore_crc7_inserter_reg3[4], sdcore_crc7_inserter_reg3[3], (sdcore_crc7_inserter_reg3[2] ^ (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])), sdcore_crc7_inserter_reg3[1], sdcore_crc7_inserter_reg3[0], (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])}; +assign sdcore_crc7_inserter_reg5 = {sdcore_crc7_inserter_reg4[5], sdcore_crc7_inserter_reg4[4], sdcore_crc7_inserter_reg4[3], (sdcore_crc7_inserter_reg4[2] ^ (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])), sdcore_crc7_inserter_reg4[1], sdcore_crc7_inserter_reg4[0], (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])}; +assign sdcore_crc7_inserter_reg6 = {sdcore_crc7_inserter_reg5[5], sdcore_crc7_inserter_reg5[4], sdcore_crc7_inserter_reg5[3], (sdcore_crc7_inserter_reg5[2] ^ (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])), sdcore_crc7_inserter_reg5[1], sdcore_crc7_inserter_reg5[0], (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])}; +assign sdcore_crc7_inserter_reg7 = {sdcore_crc7_inserter_reg6[5], sdcore_crc7_inserter_reg6[4], sdcore_crc7_inserter_reg6[3], (sdcore_crc7_inserter_reg6[2] ^ (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])), sdcore_crc7_inserter_reg6[1], sdcore_crc7_inserter_reg6[0], (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])}; +assign sdcore_crc7_inserter_reg8 = {sdcore_crc7_inserter_reg7[5], sdcore_crc7_inserter_reg7[4], sdcore_crc7_inserter_reg7[3], (sdcore_crc7_inserter_reg7[2] ^ (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])), sdcore_crc7_inserter_reg7[1], sdcore_crc7_inserter_reg7[0], (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])}; +assign sdcore_crc7_inserter_reg9 = {sdcore_crc7_inserter_reg8[5], sdcore_crc7_inserter_reg8[4], sdcore_crc7_inserter_reg8[3], (sdcore_crc7_inserter_reg8[2] ^ (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])), sdcore_crc7_inserter_reg8[1], sdcore_crc7_inserter_reg8[0], (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])}; +assign sdcore_crc7_inserter_reg10 = {sdcore_crc7_inserter_reg9[5], sdcore_crc7_inserter_reg9[4], sdcore_crc7_inserter_reg9[3], (sdcore_crc7_inserter_reg9[2] ^ (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])), sdcore_crc7_inserter_reg9[1], sdcore_crc7_inserter_reg9[0], (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])}; +assign sdcore_crc7_inserter_reg11 = {sdcore_crc7_inserter_reg10[5], sdcore_crc7_inserter_reg10[4], sdcore_crc7_inserter_reg10[3], (sdcore_crc7_inserter_reg10[2] ^ (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])), sdcore_crc7_inserter_reg10[1], sdcore_crc7_inserter_reg10[0], (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])}; +assign sdcore_crc7_inserter_reg12 = {sdcore_crc7_inserter_reg11[5], sdcore_crc7_inserter_reg11[4], sdcore_crc7_inserter_reg11[3], (sdcore_crc7_inserter_reg11[2] ^ (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])), sdcore_crc7_inserter_reg11[1], sdcore_crc7_inserter_reg11[0], (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])}; +assign sdcore_crc7_inserter_reg13 = {sdcore_crc7_inserter_reg12[5], sdcore_crc7_inserter_reg12[4], sdcore_crc7_inserter_reg12[3], (sdcore_crc7_inserter_reg12[2] ^ (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])), sdcore_crc7_inserter_reg12[1], sdcore_crc7_inserter_reg12[0], (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])}; +assign sdcore_crc7_inserter_reg14 = {sdcore_crc7_inserter_reg13[5], sdcore_crc7_inserter_reg13[4], sdcore_crc7_inserter_reg13[3], (sdcore_crc7_inserter_reg13[2] ^ (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])), sdcore_crc7_inserter_reg13[1], sdcore_crc7_inserter_reg13[0], (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])}; +assign sdcore_crc7_inserter_reg15 = {sdcore_crc7_inserter_reg14[5], sdcore_crc7_inserter_reg14[4], sdcore_crc7_inserter_reg14[3], (sdcore_crc7_inserter_reg14[2] ^ (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])), sdcore_crc7_inserter_reg14[1], sdcore_crc7_inserter_reg14[0], (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])}; +assign sdcore_crc7_inserter_reg16 = {sdcore_crc7_inserter_reg15[5], sdcore_crc7_inserter_reg15[4], sdcore_crc7_inserter_reg15[3], (sdcore_crc7_inserter_reg15[2] ^ (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])), sdcore_crc7_inserter_reg15[1], sdcore_crc7_inserter_reg15[0], (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])}; +assign sdcore_crc7_inserter_reg17 = {sdcore_crc7_inserter_reg16[5], sdcore_crc7_inserter_reg16[4], sdcore_crc7_inserter_reg16[3], (sdcore_crc7_inserter_reg16[2] ^ (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])), sdcore_crc7_inserter_reg16[1], sdcore_crc7_inserter_reg16[0], (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])}; +assign sdcore_crc7_inserter_reg18 = {sdcore_crc7_inserter_reg17[5], sdcore_crc7_inserter_reg17[4], sdcore_crc7_inserter_reg17[3], (sdcore_crc7_inserter_reg17[2] ^ (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])), sdcore_crc7_inserter_reg17[1], sdcore_crc7_inserter_reg17[0], (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])}; +assign sdcore_crc7_inserter_reg19 = {sdcore_crc7_inserter_reg18[5], sdcore_crc7_inserter_reg18[4], sdcore_crc7_inserter_reg18[3], (sdcore_crc7_inserter_reg18[2] ^ (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])), sdcore_crc7_inserter_reg18[1], sdcore_crc7_inserter_reg18[0], (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])}; +assign sdcore_crc7_inserter_reg20 = {sdcore_crc7_inserter_reg19[5], sdcore_crc7_inserter_reg19[4], sdcore_crc7_inserter_reg19[3], (sdcore_crc7_inserter_reg19[2] ^ (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])), sdcore_crc7_inserter_reg19[1], sdcore_crc7_inserter_reg19[0], (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])}; +assign sdcore_crc7_inserter_reg21 = {sdcore_crc7_inserter_reg20[5], sdcore_crc7_inserter_reg20[4], sdcore_crc7_inserter_reg20[3], (sdcore_crc7_inserter_reg20[2] ^ (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])), sdcore_crc7_inserter_reg20[1], sdcore_crc7_inserter_reg20[0], (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])}; +assign sdcore_crc7_inserter_reg22 = {sdcore_crc7_inserter_reg21[5], sdcore_crc7_inserter_reg21[4], sdcore_crc7_inserter_reg21[3], (sdcore_crc7_inserter_reg21[2] ^ (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])), sdcore_crc7_inserter_reg21[1], sdcore_crc7_inserter_reg21[0], (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])}; +assign sdcore_crc7_inserter_reg23 = {sdcore_crc7_inserter_reg22[5], sdcore_crc7_inserter_reg22[4], sdcore_crc7_inserter_reg22[3], (sdcore_crc7_inserter_reg22[2] ^ (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])), sdcore_crc7_inserter_reg22[1], sdcore_crc7_inserter_reg22[0], (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])}; +assign sdcore_crc7_inserter_reg24 = {sdcore_crc7_inserter_reg23[5], sdcore_crc7_inserter_reg23[4], sdcore_crc7_inserter_reg23[3], (sdcore_crc7_inserter_reg23[2] ^ (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])), sdcore_crc7_inserter_reg23[1], sdcore_crc7_inserter_reg23[0], (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])}; +assign sdcore_crc7_inserter_reg25 = {sdcore_crc7_inserter_reg24[5], sdcore_crc7_inserter_reg24[4], sdcore_crc7_inserter_reg24[3], (sdcore_crc7_inserter_reg24[2] ^ (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])), sdcore_crc7_inserter_reg24[1], sdcore_crc7_inserter_reg24[0], (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])}; +assign sdcore_crc7_inserter_reg26 = {sdcore_crc7_inserter_reg25[5], sdcore_crc7_inserter_reg25[4], sdcore_crc7_inserter_reg25[3], (sdcore_crc7_inserter_reg25[2] ^ (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])), sdcore_crc7_inserter_reg25[1], sdcore_crc7_inserter_reg25[0], (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])}; +assign sdcore_crc7_inserter_reg27 = {sdcore_crc7_inserter_reg26[5], sdcore_crc7_inserter_reg26[4], sdcore_crc7_inserter_reg26[3], (sdcore_crc7_inserter_reg26[2] ^ (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])), sdcore_crc7_inserter_reg26[1], sdcore_crc7_inserter_reg26[0], (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])}; +assign sdcore_crc7_inserter_reg28 = {sdcore_crc7_inserter_reg27[5], sdcore_crc7_inserter_reg27[4], sdcore_crc7_inserter_reg27[3], (sdcore_crc7_inserter_reg27[2] ^ (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])), sdcore_crc7_inserter_reg27[1], sdcore_crc7_inserter_reg27[0], (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])}; +assign sdcore_crc7_inserter_reg29 = {sdcore_crc7_inserter_reg28[5], sdcore_crc7_inserter_reg28[4], sdcore_crc7_inserter_reg28[3], (sdcore_crc7_inserter_reg28[2] ^ (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])), sdcore_crc7_inserter_reg28[1], sdcore_crc7_inserter_reg28[0], (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])}; +assign sdcore_crc7_inserter_reg30 = {sdcore_crc7_inserter_reg29[5], sdcore_crc7_inserter_reg29[4], sdcore_crc7_inserter_reg29[3], (sdcore_crc7_inserter_reg29[2] ^ (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])), sdcore_crc7_inserter_reg29[1], sdcore_crc7_inserter_reg29[0], (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])}; +assign sdcore_crc7_inserter_reg31 = {sdcore_crc7_inserter_reg30[5], sdcore_crc7_inserter_reg30[4], sdcore_crc7_inserter_reg30[3], (sdcore_crc7_inserter_reg30[2] ^ (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])), sdcore_crc7_inserter_reg30[1], sdcore_crc7_inserter_reg30[0], (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])}; +assign sdcore_crc7_inserter_reg32 = {sdcore_crc7_inserter_reg31[5], sdcore_crc7_inserter_reg31[4], sdcore_crc7_inserter_reg31[3], (sdcore_crc7_inserter_reg31[2] ^ (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])), sdcore_crc7_inserter_reg31[1], sdcore_crc7_inserter_reg31[0], (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])}; +assign sdcore_crc7_inserter_reg33 = {sdcore_crc7_inserter_reg32[5], sdcore_crc7_inserter_reg32[4], sdcore_crc7_inserter_reg32[3], (sdcore_crc7_inserter_reg32[2] ^ (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])), sdcore_crc7_inserter_reg32[1], sdcore_crc7_inserter_reg32[0], (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])}; +assign sdcore_crc7_inserter_reg34 = {sdcore_crc7_inserter_reg33[5], sdcore_crc7_inserter_reg33[4], sdcore_crc7_inserter_reg33[3], (sdcore_crc7_inserter_reg33[2] ^ (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])), sdcore_crc7_inserter_reg33[1], sdcore_crc7_inserter_reg33[0], (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])}; +assign sdcore_crc7_inserter_reg35 = {sdcore_crc7_inserter_reg34[5], sdcore_crc7_inserter_reg34[4], sdcore_crc7_inserter_reg34[3], (sdcore_crc7_inserter_reg34[2] ^ (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])), sdcore_crc7_inserter_reg34[1], sdcore_crc7_inserter_reg34[0], (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])}; +assign sdcore_crc7_inserter_reg36 = {sdcore_crc7_inserter_reg35[5], sdcore_crc7_inserter_reg35[4], sdcore_crc7_inserter_reg35[3], (sdcore_crc7_inserter_reg35[2] ^ (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])), sdcore_crc7_inserter_reg35[1], sdcore_crc7_inserter_reg35[0], (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])}; +assign sdcore_crc7_inserter_reg37 = {sdcore_crc7_inserter_reg36[5], sdcore_crc7_inserter_reg36[4], sdcore_crc7_inserter_reg36[3], (sdcore_crc7_inserter_reg36[2] ^ (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])), sdcore_crc7_inserter_reg36[1], sdcore_crc7_inserter_reg36[0], (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])}; +assign sdcore_crc7_inserter_reg38 = {sdcore_crc7_inserter_reg37[5], sdcore_crc7_inserter_reg37[4], sdcore_crc7_inserter_reg37[3], (sdcore_crc7_inserter_reg37[2] ^ (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])), sdcore_crc7_inserter_reg37[1], sdcore_crc7_inserter_reg37[0], (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])}; +assign sdcore_crc7_inserter_reg39 = {sdcore_crc7_inserter_reg38[5], sdcore_crc7_inserter_reg38[4], sdcore_crc7_inserter_reg38[3], (sdcore_crc7_inserter_reg38[2] ^ (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])), sdcore_crc7_inserter_reg38[1], sdcore_crc7_inserter_reg38[0], (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])}; +assign sdcore_crc7_inserter_reg40 = {sdcore_crc7_inserter_reg39[5], sdcore_crc7_inserter_reg39[4], sdcore_crc7_inserter_reg39[3], (sdcore_crc7_inserter_reg39[2] ^ (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])), sdcore_crc7_inserter_reg39[1], sdcore_crc7_inserter_reg39[0], (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])}; +always @(*) begin + sdcore_crc7_inserter_crc <= 7'd0; + if (sdcore_crc7_inserter_enable) begin + sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg40; + end else begin + sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg0; + end +end +assign sdcore_crc16_inserter_crc0_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc0_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc0_din <= 2'd0; + sdcore_crc16_inserter_crc0_din[0] <= sdcore_crc16_inserter_sink_payload_data[0]; + sdcore_crc16_inserter_crc0_din[1] <= sdcore_crc16_inserter_sink_payload_data[4]; +end +assign sdcore_crc16_inserter_crc1_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc1_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc1_din <= 2'd0; + sdcore_crc16_inserter_crc1_din[0] <= sdcore_crc16_inserter_sink_payload_data[1]; + sdcore_crc16_inserter_crc1_din[1] <= sdcore_crc16_inserter_sink_payload_data[5]; +end +assign sdcore_crc16_inserter_crc2_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc2_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc2_din <= 2'd0; + sdcore_crc16_inserter_crc2_din[0] <= sdcore_crc16_inserter_sink_payload_data[2]; + sdcore_crc16_inserter_crc2_din[1] <= sdcore_crc16_inserter_sink_payload_data[6]; +end +assign sdcore_crc16_inserter_crc3_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc3_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc3_din <= 2'd0; + sdcore_crc16_inserter_crc3_din[0] <= sdcore_crc16_inserter_sink_payload_data[3]; + sdcore_crc16_inserter_crc3_din[1] <= sdcore_crc16_inserter_sink_payload_data[7]; +end +assign sdcore_crc16_inserter_crc0_reg1 = {sdcore_crc16_inserter_crc0_reg0[14], sdcore_crc16_inserter_crc0_reg0[13], sdcore_crc16_inserter_crc0_reg0[12], (sdcore_crc16_inserter_crc0_reg0[11] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[10], sdcore_crc16_inserter_crc0_reg0[9], sdcore_crc16_inserter_crc0_reg0[8], sdcore_crc16_inserter_crc0_reg0[7], sdcore_crc16_inserter_crc0_reg0[6], sdcore_crc16_inserter_crc0_reg0[5], (sdcore_crc16_inserter_crc0_reg0[4] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[3], sdcore_crc16_inserter_crc0_reg0[2], sdcore_crc16_inserter_crc0_reg0[1], sdcore_crc16_inserter_crc0_reg0[0], (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])}; +assign sdcore_crc16_inserter_crc0_reg2 = {sdcore_crc16_inserter_crc0_reg1[14], sdcore_crc16_inserter_crc0_reg1[13], sdcore_crc16_inserter_crc0_reg1[12], (sdcore_crc16_inserter_crc0_reg1[11] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[10], sdcore_crc16_inserter_crc0_reg1[9], sdcore_crc16_inserter_crc0_reg1[8], sdcore_crc16_inserter_crc0_reg1[7], sdcore_crc16_inserter_crc0_reg1[6], sdcore_crc16_inserter_crc0_reg1[5], (sdcore_crc16_inserter_crc0_reg1[4] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[3], sdcore_crc16_inserter_crc0_reg1[2], sdcore_crc16_inserter_crc0_reg1[1], sdcore_crc16_inserter_crc0_reg1[0], (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc0_crc <= 16'd0; + if (sdcore_crc16_inserter_crc0_enable) begin + sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg2; + end else begin + sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg0; + end +end +assign sdcore_crc16_inserter_crc1_reg1 = {sdcore_crc16_inserter_crc1_reg0[14], sdcore_crc16_inserter_crc1_reg0[13], sdcore_crc16_inserter_crc1_reg0[12], (sdcore_crc16_inserter_crc1_reg0[11] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[10], sdcore_crc16_inserter_crc1_reg0[9], sdcore_crc16_inserter_crc1_reg0[8], sdcore_crc16_inserter_crc1_reg0[7], sdcore_crc16_inserter_crc1_reg0[6], sdcore_crc16_inserter_crc1_reg0[5], (sdcore_crc16_inserter_crc1_reg0[4] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[3], sdcore_crc16_inserter_crc1_reg0[2], sdcore_crc16_inserter_crc1_reg0[1], sdcore_crc16_inserter_crc1_reg0[0], (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])}; +assign sdcore_crc16_inserter_crc1_reg2 = {sdcore_crc16_inserter_crc1_reg1[14], sdcore_crc16_inserter_crc1_reg1[13], sdcore_crc16_inserter_crc1_reg1[12], (sdcore_crc16_inserter_crc1_reg1[11] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[10], sdcore_crc16_inserter_crc1_reg1[9], sdcore_crc16_inserter_crc1_reg1[8], sdcore_crc16_inserter_crc1_reg1[7], sdcore_crc16_inserter_crc1_reg1[6], sdcore_crc16_inserter_crc1_reg1[5], (sdcore_crc16_inserter_crc1_reg1[4] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[3], sdcore_crc16_inserter_crc1_reg1[2], sdcore_crc16_inserter_crc1_reg1[1], sdcore_crc16_inserter_crc1_reg1[0], (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc1_crc <= 16'd0; + if (sdcore_crc16_inserter_crc1_enable) begin + sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg2; + end else begin + sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg0; + end +end +assign sdcore_crc16_inserter_crc2_reg1 = {sdcore_crc16_inserter_crc2_reg0[14], sdcore_crc16_inserter_crc2_reg0[13], sdcore_crc16_inserter_crc2_reg0[12], (sdcore_crc16_inserter_crc2_reg0[11] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[10], sdcore_crc16_inserter_crc2_reg0[9], sdcore_crc16_inserter_crc2_reg0[8], sdcore_crc16_inserter_crc2_reg0[7], sdcore_crc16_inserter_crc2_reg0[6], sdcore_crc16_inserter_crc2_reg0[5], (sdcore_crc16_inserter_crc2_reg0[4] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[3], sdcore_crc16_inserter_crc2_reg0[2], sdcore_crc16_inserter_crc2_reg0[1], sdcore_crc16_inserter_crc2_reg0[0], (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])}; +assign sdcore_crc16_inserter_crc2_reg2 = {sdcore_crc16_inserter_crc2_reg1[14], sdcore_crc16_inserter_crc2_reg1[13], sdcore_crc16_inserter_crc2_reg1[12], (sdcore_crc16_inserter_crc2_reg1[11] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[10], sdcore_crc16_inserter_crc2_reg1[9], sdcore_crc16_inserter_crc2_reg1[8], sdcore_crc16_inserter_crc2_reg1[7], sdcore_crc16_inserter_crc2_reg1[6], sdcore_crc16_inserter_crc2_reg1[5], (sdcore_crc16_inserter_crc2_reg1[4] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[3], sdcore_crc16_inserter_crc2_reg1[2], sdcore_crc16_inserter_crc2_reg1[1], sdcore_crc16_inserter_crc2_reg1[0], (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc2_crc <= 16'd0; + if (sdcore_crc16_inserter_crc2_enable) begin + sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg2; + end else begin + sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg0; + end +end +assign sdcore_crc16_inserter_crc3_reg1 = {sdcore_crc16_inserter_crc3_reg0[14], sdcore_crc16_inserter_crc3_reg0[13], sdcore_crc16_inserter_crc3_reg0[12], (sdcore_crc16_inserter_crc3_reg0[11] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[10], sdcore_crc16_inserter_crc3_reg0[9], sdcore_crc16_inserter_crc3_reg0[8], sdcore_crc16_inserter_crc3_reg0[7], sdcore_crc16_inserter_crc3_reg0[6], sdcore_crc16_inserter_crc3_reg0[5], (sdcore_crc16_inserter_crc3_reg0[4] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[3], sdcore_crc16_inserter_crc3_reg0[2], sdcore_crc16_inserter_crc3_reg0[1], sdcore_crc16_inserter_crc3_reg0[0], (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])}; +assign sdcore_crc16_inserter_crc3_reg2 = {sdcore_crc16_inserter_crc3_reg1[14], sdcore_crc16_inserter_crc3_reg1[13], sdcore_crc16_inserter_crc3_reg1[12], (sdcore_crc16_inserter_crc3_reg1[11] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[10], sdcore_crc16_inserter_crc3_reg1[9], sdcore_crc16_inserter_crc3_reg1[8], sdcore_crc16_inserter_crc3_reg1[7], sdcore_crc16_inserter_crc3_reg1[6], sdcore_crc16_inserter_crc3_reg1[5], (sdcore_crc16_inserter_crc3_reg1[4] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[3], sdcore_crc16_inserter_crc3_reg1[2], sdcore_crc16_inserter_crc3_reg1[1], sdcore_crc16_inserter_crc3_reg1[0], (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc3_crc <= 16'd0; + if (sdcore_crc16_inserter_crc3_enable) begin + sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg2; + end else begin + sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg0; + end +end +always @(*) begin + subfragments_sdcore_crc16inserter_next_state <= 1'd0; + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 3'd0; + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd0; + sdcore_crc16_inserter_source_valid <= 1'd0; + sdcore_crc16_inserter_source_first <= 1'd0; + sdcore_crc16_inserter_source_last <= 1'd0; + sdcore_crc16_inserter_source_payload_data <= 8'd0; + sdcore_crc16_inserter_sink_ready <= 1'd0; + subfragments_sdcore_crc16inserter_next_state <= subfragments_sdcore_crc16inserter_state; + case (subfragments_sdcore_crc16inserter_state) + 1'd1: begin + sdcore_crc16_inserter_source_valid <= 1'd1; + sdcore_crc16_inserter_source_last <= (sdcore_crc16_inserter_count == 3'd7); + case (sdcore_crc16_inserter_count) + 1'd0: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[14]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[14]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[14]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[14]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[15]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[15]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[15]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[15]; + end + 1'd1: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[12]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[12]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[12]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[12]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[13]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[13]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[13]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[13]; + end + 2'd2: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[10]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[10]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[10]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[10]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[11]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[11]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[11]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[11]; + end + 2'd3: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[8]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[8]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[8]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[8]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[9]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[9]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[9]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[9]; + end + 3'd4: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[6]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[6]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[6]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[6]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[7]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[7]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[7]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[7]; + end + 3'd5: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[4]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[4]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[4]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[4]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[5]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[5]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[5]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[5]; + end + 3'd6: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[2]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[2]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[2]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[2]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[3]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[3]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[3]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[3]; + end + 3'd7: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[0]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[0]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[0]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[0]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[1]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[1]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[1]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[1]; + end + endcase + if ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready)) begin + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= (sdcore_crc16_inserter_count + 1'd1); + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; + if (sdcore_crc16_inserter_source_last) begin + subfragments_sdcore_crc16inserter_next_state <= 1'd0; + end + end + end + default: begin + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 1'd0; + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; + sdcore_crc16_inserter_source_valid <= sdcore_crc16_inserter_sink_valid; + sdcore_crc16_inserter_sink_ready <= sdcore_crc16_inserter_source_ready; + sdcore_crc16_inserter_source_first <= sdcore_crc16_inserter_sink_first; + sdcore_crc16_inserter_source_payload_data <= sdcore_crc16_inserter_sink_payload_data; + sdcore_crc16_inserter_source_last <= 1'd0; + if ((sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready)) begin + if (sdcore_crc16_inserter_sink_last) begin + subfragments_sdcore_crc16inserter_next_state <= 1'd1; + end + end + end + endcase +end +assign sdcore_fifo_sink_valid = sdcore_sink_sink_valid1; +assign sdcore_sink_sink_ready1 = sdcore_fifo_sink_ready; +assign sdcore_fifo_sink_first = sdcore_sink_sink_first1; +assign sdcore_fifo_sink_last = sdcore_sink_sink_last1; +assign sdcore_fifo_sink_payload_data = sdcore_sink_sink_payload_data1; +assign sdcore_source_source_first1 = sdcore_fifo_source_first; +assign sdcore_source_source_last1 = sdcore_fifo_source_last; +assign sdcore_source_source_payload_data1 = sdcore_fifo_source_payload_data; +assign sdcore_source_source_valid1 = (sdcore_fifo_level >= 4'd8); +assign sdcore_fifo_source_ready = (sdcore_source_source_valid1 & sdcore_source_source_ready1); +assign sdcore_fifo_reset = ((sdcore_sink_sink_valid1 & sdcore_sink_sink_ready1) & sdcore_sink_sink_last1); +assign sdcore_fifo_syncfifo_din = {sdcore_fifo_fifo_in_last, sdcore_fifo_fifo_in_first, sdcore_fifo_fifo_in_payload_data}; +assign {sdcore_fifo_fifo_out_last, sdcore_fifo_fifo_out_first, sdcore_fifo_fifo_out_payload_data} = sdcore_fifo_syncfifo_dout; +assign sdcore_fifo_sink_ready = sdcore_fifo_syncfifo_writable; +assign sdcore_fifo_syncfifo_we = sdcore_fifo_sink_valid; +assign sdcore_fifo_fifo_in_first = sdcore_fifo_sink_first; +assign sdcore_fifo_fifo_in_last = sdcore_fifo_sink_last; +assign sdcore_fifo_fifo_in_payload_data = sdcore_fifo_sink_payload_data; +assign sdcore_fifo_source_valid = sdcore_fifo_syncfifo_readable; +assign sdcore_fifo_source_first = sdcore_fifo_fifo_out_first; +assign sdcore_fifo_source_last = sdcore_fifo_fifo_out_last; +assign sdcore_fifo_source_payload_data = sdcore_fifo_fifo_out_payload_data; +assign sdcore_fifo_syncfifo_re = sdcore_fifo_source_ready; +always @(*) begin + sdcore_fifo_wrport_adr <= 3'd0; + if (sdcore_fifo_replace) begin + sdcore_fifo_wrport_adr <= (sdcore_fifo_produce - 1'd1); + end else begin + sdcore_fifo_wrport_adr <= sdcore_fifo_produce; + end +end +assign sdcore_fifo_wrport_dat_w = sdcore_fifo_syncfifo_din; +assign sdcore_fifo_wrport_we = (sdcore_fifo_syncfifo_we & (sdcore_fifo_syncfifo_writable | sdcore_fifo_replace)); +assign sdcore_fifo_do_read = (sdcore_fifo_syncfifo_readable & sdcore_fifo_syncfifo_re); +assign sdcore_fifo_rdport_adr = sdcore_fifo_consume; +assign sdcore_fifo_syncfifo_dout = sdcore_fifo_rdport_dat_r; +assign sdcore_fifo_syncfifo_writable = (sdcore_fifo_level != 4'd8); +assign sdcore_fifo_syncfifo_readable = (sdcore_fifo_level != 1'd0); +always @(*) begin + sdcore_cmd_response_status_sdcore_fsm_next_value8 <= 128'd0; + sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd0; + cmdr_sink_valid <= 1'd0; + cmdr_sink_payload_cmd_type <= 2'd0; + cmdr_sink_payload_data_type <= 2'd0; + cmdr_sink_payload_length <= 8'd0; + cmdr_source_ready <= 1'd0; + dataw_sink_valid <= 1'd0; + dataw_sink_first <= 1'd0; + dataw_sink_last <= 1'd0; + dataw_sink_payload_data <= 8'd0; + subfragments_sdcore_fsm_next_state <= 3'd0; + cmdw_sink_valid <= 1'd0; + sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; + sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd0; + datar_sink_valid <= 1'd0; + cmdw_sink_last <= 1'd0; + sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; + sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd0; + cmdw_sink_payload_data <= 8'd0; + cmdw_sink_payload_cmd_type <= 2'd0; + datar_sink_payload_block_length <= 10'd0; + sdcore_cmd_count_sdcore_fsm_next_value2 <= 3'd0; + datar_source_ready <= 1'd0; + sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd0; + sdcore_crc16_inserter_source_ready <= 1'd0; + sdcore_data_count_sdcore_fsm_next_value3 <= 32'd0; + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd0; + datar_sink_last <= 1'd0; + sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; + sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd0; + sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; + sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd0; + sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; + sdcore_sink_sink_valid1 <= 1'd0; + sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd0; + sdcore_sink_sink_first1 <= 1'd0; + sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; + sdcore_sink_sink_last1 <= 1'd0; + sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd0; + sdcore_sink_sink_payload_data1 <= 8'd0; + subfragments_sdcore_fsm_next_state <= subfragments_sdcore_fsm_state; + case (subfragments_sdcore_fsm_state) + 1'd1: begin + cmdw_sink_valid <= 1'd1; + cmdw_sink_last <= (sdcore_cmd_count == 3'd5); + cmdw_sink_payload_cmd_type <= sdcore_cmd_type; + case (sdcore_cmd_count) + 1'd0: begin + cmdw_sink_payload_data <= {1'd0, 1'd1, sdcore_cmd}; + end + 1'd1: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[31:24]; + end + 2'd2: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[23:16]; + end + 2'd3: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[15:8]; + end + 3'd4: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[7:0]; + end + 3'd5: begin + cmdw_sink_payload_data <= {sdcore_crc7_inserter_crc, 1'd1}; + end + endcase + if (cmdw_sink_ready) begin + sdcore_cmd_count_sdcore_fsm_next_value2 <= (sdcore_cmd_count + 1'd1); + sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; + if (cmdw_sink_last) begin + if ((sdcore_cmd_type == 1'd0)) begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end else begin + subfragments_sdcore_fsm_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cmdr_sink_valid <= 1'd1; + cmdr_sink_payload_cmd_type <= sdcore_cmd_type; + cmdr_sink_payload_data_type <= sdcore_data_type; + if ((sdcore_cmd_type == 2'd2)) begin + cmdr_sink_payload_length <= 5'd18; + end else begin + cmdr_sink_payload_length <= 3'd6; + end + cmdr_source_ready <= 1'd1; + if (cmdr_source_valid) begin + if ((cmdr_source_payload_status == 1'd1)) begin + sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd1; + sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; + subfragments_sdcore_fsm_next_state <= 1'd0; + end else begin + if (cmdr_source_last) begin + if ((sdcore_data_type == 2'd2)) begin + subfragments_sdcore_fsm_next_state <= 2'd3; + end else begin + if ((sdcore_data_type == 1'd1)) begin + subfragments_sdcore_fsm_next_state <= 3'd4; + end else begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + end else begin + sdcore_cmd_response_status_sdcore_fsm_next_value8 <= {sdcore_cmd_response_status, cmdr_source_payload_data}; + sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd1; + end + end + end + end + 2'd3: begin + dataw_sink_valid <= sdcore_crc16_inserter_source_valid; + sdcore_crc16_inserter_source_ready <= dataw_sink_ready; + dataw_sink_first <= sdcore_crc16_inserter_source_first; + dataw_sink_last <= sdcore_crc16_inserter_source_last; + dataw_sink_payload_data <= sdcore_crc16_inserter_source_payload_data; + if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin + sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; + if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + datar_source_ready <= 1'd1; + if (datar_source_valid) begin + if ((datar_source_payload_status != 2'd2)) begin + sdcore_data_error_sdcore_fsm_next_value6 <= 1'd1; + sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; + end + end + end + 3'd4: begin + datar_sink_valid <= 1'd1; + datar_sink_payload_block_length <= sdcore_block_length_storage; + datar_sink_last <= (sdcore_data_count == (sdcore_block_count_storage - 1'd1)); + if (datar_source_valid) begin + if ((datar_source_payload_status == 1'd0)) begin + sdcore_sink_sink_valid1 <= datar_source_valid; + datar_source_ready <= sdcore_sink_sink_ready1; + sdcore_sink_sink_first1 <= datar_source_first; + sdcore_sink_sink_last1 <= datar_source_last; + sdcore_sink_sink_payload_data1 <= datar_source_payload_data; + if ((datar_source_last & datar_source_ready)) begin + sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; + if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + end else begin + if ((datar_source_payload_status == 1'd1)) begin + sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd1; + sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; + datar_source_ready <= 1'd1; + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + end + end + default: begin + sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd1; + sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; + sdcore_data_done_sdcore_fsm_next_value1 <= 1'd1; + sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; + sdcore_cmd_count_sdcore_fsm_next_value2 <= 1'd0; + sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; + sdcore_data_count_sdcore_fsm_next_value3 <= 1'd0; + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; + if (sdcore_cmd_send_re) begin + sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; + sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; + sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; + sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd1; + sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; + sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; + sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; + sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; + sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; + sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; + sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; + sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; + subfragments_sdcore_fsm_next_state <= 1'd1; + end + end + endcase +end +assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first); +always @(*) begin + sdblock2mem_fifo_sink_last <= 1'd0; + sdblock2mem_fifo_sink_valid <= 1'd0; + sdblock2mem_fifo_sink_first <= 1'd0; + sdblock2mem_sink_sink_ready0 <= 1'd0; + sdblock2mem_fifo_sink_payload_data <= 8'd0; + if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin + sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0; + sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready; + sdblock2mem_fifo_sink_first <= sdblock2mem_sink_sink_first; + sdblock2mem_fifo_sink_last <= sdblock2mem_sink_sink_last0; + sdblock2mem_fifo_sink_payload_data <= sdblock2mem_sink_sink_payload_data0; + end else begin + sdblock2mem_sink_sink_ready0 <= 1'd1; + end +end +assign sdblock2mem_converter_sink_valid = sdblock2mem_fifo_source_valid; +assign sdblock2mem_fifo_source_ready = sdblock2mem_converter_sink_ready; +assign sdblock2mem_converter_sink_first = sdblock2mem_fifo_source_first; +assign sdblock2mem_converter_sink_last = sdblock2mem_fifo_source_last; +assign sdblock2mem_converter_sink_payload_data = sdblock2mem_fifo_source_payload_data; +assign sdblock2mem_wishbonedmawriter_sink_valid = sdblock2mem_source_source_valid; +assign sdblock2mem_source_source_ready = sdblock2mem_wishbonedmawriter_sink_ready; +assign sdblock2mem_wishbonedmawriter_sink_first = sdblock2mem_source_source_first; +assign sdblock2mem_wishbonedmawriter_sink_last = sdblock2mem_source_source_last; +assign sdblock2mem_wishbonedmawriter_sink_payload_data = sdblock2mem_source_source_payload_data; +assign sdblock2mem_fifo_syncfifo_din = {sdblock2mem_fifo_fifo_in_last, sdblock2mem_fifo_fifo_in_first, sdblock2mem_fifo_fifo_in_payload_data}; +assign {sdblock2mem_fifo_fifo_out_last, sdblock2mem_fifo_fifo_out_first, sdblock2mem_fifo_fifo_out_payload_data} = sdblock2mem_fifo_syncfifo_dout; +assign sdblock2mem_fifo_sink_ready = sdblock2mem_fifo_syncfifo_writable; +assign sdblock2mem_fifo_syncfifo_we = sdblock2mem_fifo_sink_valid; +assign sdblock2mem_fifo_fifo_in_first = sdblock2mem_fifo_sink_first; +assign sdblock2mem_fifo_fifo_in_last = sdblock2mem_fifo_sink_last; +assign sdblock2mem_fifo_fifo_in_payload_data = sdblock2mem_fifo_sink_payload_data; +assign sdblock2mem_fifo_source_valid = sdblock2mem_fifo_syncfifo_readable; +assign sdblock2mem_fifo_source_first = sdblock2mem_fifo_fifo_out_first; +assign sdblock2mem_fifo_source_last = sdblock2mem_fifo_fifo_out_last; +assign sdblock2mem_fifo_source_payload_data = sdblock2mem_fifo_fifo_out_payload_data; +assign sdblock2mem_fifo_syncfifo_re = sdblock2mem_fifo_source_ready; +always @(*) begin + sdblock2mem_fifo_wrport_adr <= 9'd0; + if (sdblock2mem_fifo_replace) begin + sdblock2mem_fifo_wrport_adr <= (sdblock2mem_fifo_produce - 1'd1); + end else begin + sdblock2mem_fifo_wrport_adr <= sdblock2mem_fifo_produce; + end +end +assign sdblock2mem_fifo_wrport_dat_w = sdblock2mem_fifo_syncfifo_din; +assign sdblock2mem_fifo_wrport_we = (sdblock2mem_fifo_syncfifo_we & (sdblock2mem_fifo_syncfifo_writable | sdblock2mem_fifo_replace)); +assign sdblock2mem_fifo_do_read = (sdblock2mem_fifo_syncfifo_readable & sdblock2mem_fifo_syncfifo_re); +assign sdblock2mem_fifo_rdport_adr = sdblock2mem_fifo_consume; +assign sdblock2mem_fifo_syncfifo_dout = sdblock2mem_fifo_rdport_dat_r; +assign sdblock2mem_fifo_syncfifo_writable = (sdblock2mem_fifo_level != 10'd512); +assign sdblock2mem_fifo_syncfifo_readable = (sdblock2mem_fifo_level != 1'd0); +assign sdblock2mem_source_source_valid = sdblock2mem_converter_source_valid; +assign sdblock2mem_converter_source_ready = sdblock2mem_source_source_ready; +assign sdblock2mem_source_source_first = sdblock2mem_converter_source_first; +assign sdblock2mem_source_source_last = sdblock2mem_converter_source_last; +assign sdblock2mem_source_source_payload_data = sdblock2mem_converter_source_payload_data; +assign sdblock2mem_converter_sink_ready = ((~sdblock2mem_converter_strobe_all) | sdblock2mem_converter_source_ready); +assign sdblock2mem_converter_source_valid = sdblock2mem_converter_strobe_all; +assign sdblock2mem_converter_load_part = (sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready); +assign interface0_bus_stb = sdblock2mem_sink_sink_valid1; +assign interface0_bus_cyc = sdblock2mem_sink_sink_valid1; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sdblock2mem_sink_sink_payload_address; +assign interface0_bus_dat_w = {sdblock2mem_sink_sink_payload_data1[7:0], sdblock2mem_sink_sink_payload_data1[15:8], sdblock2mem_sink_sink_payload_data1[23:16], sdblock2mem_sink_sink_payload_data1[31:24]}; +assign sdblock2mem_sink_sink_ready1 = interface0_bus_ack; +assign sdblock2mem_wishbonedmawriter_base = sdblock2mem_wishbonedmawriter_base_storage[63:2]; +assign sdblock2mem_wishbonedmawriter_length = sdblock2mem_wishbonedmawriter_length_storage[31:2]; +assign sdblock2mem_wishbonedmawriter_offset_status = sdblock2mem_wishbonedmawriter_offset; +assign sdblock2mem_wishbonedmawriter_reset = (~sdblock2mem_wishbonedmawriter_enable_storage); +always @(*) begin + sdblock2mem_sink_sink_last1 <= 1'd0; + sdblock2mem_sink_sink_payload_address <= 32'd0; + sdblock2mem_sink_sink_payload_data1 <= 32'd0; + subfragments_next_state <= 2'd0; + sdblock2mem_wishbonedmawriter_offset_next_value <= 32'd0; + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd0; + sdblock2mem_wishbonedmawriter_done_status <= 1'd0; + sdblock2mem_wishbonedmawriter_sink_ready <= 1'd0; + sdblock2mem_sink_sink_valid1 <= 1'd0; + subfragments_next_state <= subfragments_state; + case (subfragments_state) + 1'd1: begin + sdblock2mem_sink_sink_valid1 <= sdblock2mem_wishbonedmawriter_sink_valid; + sdblock2mem_sink_sink_last1 <= (sdblock2mem_wishbonedmawriter_offset == (sdblock2mem_wishbonedmawriter_length - 1'd1)); + sdblock2mem_sink_sink_payload_address <= (sdblock2mem_wishbonedmawriter_base + sdblock2mem_wishbonedmawriter_offset); + sdblock2mem_sink_sink_payload_data1 <= sdblock2mem_wishbonedmawriter_sink_payload_data; + sdblock2mem_wishbonedmawriter_sink_ready <= sdblock2mem_sink_sink_ready1; + if ((sdblock2mem_wishbonedmawriter_sink_valid & sdblock2mem_wishbonedmawriter_sink_ready)) begin + sdblock2mem_wishbonedmawriter_offset_next_value <= (sdblock2mem_wishbonedmawriter_offset + 1'd1); + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; + if (sdblock2mem_sink_sink_last1) begin + if (sdblock2mem_wishbonedmawriter_loop_storage) begin + sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; + end else begin + subfragments_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdblock2mem_wishbonedmawriter_done_status <= 1'd1; + end + default: begin + sdblock2mem_wishbonedmawriter_sink_ready <= 1'd1; + sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; + subfragments_next_state <= 1'd1; + end + endcase +end +assign sdmem2block_converter_sink_valid = sdmem2block_dma_source_valid; +assign sdmem2block_dma_source_ready = sdmem2block_converter_sink_ready; +assign sdmem2block_converter_sink_first = sdmem2block_dma_source_first; +assign sdmem2block_converter_sink_last = sdmem2block_dma_source_last; +assign sdmem2block_converter_sink_payload_data = sdmem2block_dma_source_payload_data; +assign sdmem2block_fifo_sink_valid = sdmem2block_source_source_valid1; +assign sdmem2block_source_source_ready1 = sdmem2block_fifo_sink_ready; +assign sdmem2block_fifo_sink_first = sdmem2block_source_source_first1; +assign sdmem2block_fifo_sink_last = sdmem2block_source_source_last1; +assign sdmem2block_fifo_sink_payload_data = sdmem2block_source_source_payload_data1; +assign sdmem2block_source_source_valid0 = sdmem2block_fifo_source_valid; +assign sdmem2block_fifo_source_ready = sdmem2block_source_source_ready0; +assign sdmem2block_source_source_first0 = sdmem2block_fifo_source_first; +assign sdmem2block_source_source_payload_data0 = sdmem2block_fifo_source_payload_data; +always @(*) begin + sdmem2block_source_source_last0 <= 1'd0; + sdmem2block_source_source_last0 <= sdmem2block_fifo_source_last; + if ((sdmem2block_count == 9'd511)) begin + sdmem2block_source_source_last0 <= 1'd1; + end +end +assign sdmem2block_dma_base = sdmem2block_dma_base_storage[63:2]; +assign sdmem2block_dma_length = sdmem2block_dma_length_storage[31:2]; +assign sdmem2block_dma_offset_status = sdmem2block_dma_offset; +assign sdmem2block_dma_reset = (~sdmem2block_dma_enable_storage); +always @(*) begin + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= 32'd0; + sdmem2block_dma_sink_ready <= 1'd0; + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd0; + interface1_bus_sel <= 4'd0; + interface1_bus_cyc <= 1'd0; + interface1_bus_stb <= 1'd0; + sdmem2block_dma_source_valid <= 1'd0; + interface1_bus_we <= 1'd0; + subfragments_sdmem2blockdma_fsm_next_state <= 1'd0; + sdmem2block_dma_source_last <= 1'd0; + sdmem2block_dma_source_payload_data <= 32'd0; + interface1_bus_adr <= 32'd0; + subfragments_sdmem2blockdma_fsm_next_state <= subfragments_sdmem2blockdma_fsm_state; + case (subfragments_sdmem2blockdma_fsm_state) + 1'd1: begin + sdmem2block_dma_source_valid <= 1'd1; + sdmem2block_dma_source_last <= sdmem2block_dma_sink_last; + sdmem2block_dma_source_payload_data <= sdmem2block_dma_data; + if (sdmem2block_dma_source_ready) begin + sdmem2block_dma_sink_ready <= 1'd1; + subfragments_sdmem2blockdma_fsm_next_state <= 1'd0; + end + end + default: begin + interface1_bus_stb <= sdmem2block_dma_sink_valid; + interface1_bus_cyc <= sdmem2block_dma_sink_valid; + interface1_bus_we <= 1'd0; + interface1_bus_sel <= 4'd15; + interface1_bus_adr <= sdmem2block_dma_sink_payload_address; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd1; + subfragments_sdmem2blockdma_fsm_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + sdmem2block_dma_sink_valid <= 1'd0; + sdmem2block_dma_done_status <= 1'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0; + sdmem2block_dma_sink_last <= 1'd0; + sdmem2block_dma_sink_payload_address <= 32'd0; + subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0; + subfragments_sdmem2blockdma_resetinserter_next_state <= subfragments_sdmem2blockdma_resetinserter_state; + case (subfragments_sdmem2blockdma_resetinserter_state) + 1'd1: begin + sdmem2block_dma_sink_valid <= 1'd1; + sdmem2block_dma_sink_last <= (sdmem2block_dma_offset == (sdmem2block_dma_length - 1'd1)); + sdmem2block_dma_sink_payload_address <= (sdmem2block_dma_base + sdmem2block_dma_offset); + if (sdmem2block_dma_sink_ready) begin + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= (sdmem2block_dma_offset + 1'd1); + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; + if (sdmem2block_dma_sink_last) begin + if (sdmem2block_dma_loop_storage) begin + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; + end else begin + subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdmem2block_dma_done_status <= 1'd1; + end + default: begin + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; + subfragments_sdmem2blockdma_resetinserter_next_state <= 1'd1; + end + endcase +end +assign sdmem2block_source_source_valid1 = sdmem2block_converter_source_valid; +assign sdmem2block_converter_source_ready = sdmem2block_source_source_ready1; +assign sdmem2block_source_source_first1 = sdmem2block_converter_source_first; +assign sdmem2block_source_source_last1 = sdmem2block_converter_source_last; +assign sdmem2block_source_source_payload_data1 = sdmem2block_converter_source_payload_data; +assign sdmem2block_converter_first = (sdmem2block_converter_mux == 1'd0); +assign sdmem2block_converter_last = (sdmem2block_converter_mux == 2'd3); +assign sdmem2block_converter_source_valid = sdmem2block_converter_sink_valid; +assign sdmem2block_converter_source_first = (sdmem2block_converter_sink_first & sdmem2block_converter_first); +assign sdmem2block_converter_source_last = (sdmem2block_converter_sink_last & sdmem2block_converter_last); +assign sdmem2block_converter_sink_ready = (sdmem2block_converter_last & sdmem2block_converter_source_ready); +always @(*) begin + sdmem2block_converter_source_payload_data <= 8'd0; + case (sdmem2block_converter_mux) + 1'd0: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[31:24]; + end + 1'd1: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[23:16]; + end + 2'd2: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[15:8]; + end + default: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[7:0]; + end + endcase +end +assign sdmem2block_converter_source_payload_valid_token_count = sdmem2block_converter_last; +assign sdmem2block_fifo_syncfifo_din = {sdmem2block_fifo_fifo_in_last, sdmem2block_fifo_fifo_in_first, sdmem2block_fifo_fifo_in_payload_data}; +assign {sdmem2block_fifo_fifo_out_last, sdmem2block_fifo_fifo_out_first, sdmem2block_fifo_fifo_out_payload_data} = sdmem2block_fifo_syncfifo_dout; +assign sdmem2block_fifo_sink_ready = sdmem2block_fifo_syncfifo_writable; +assign sdmem2block_fifo_syncfifo_we = sdmem2block_fifo_sink_valid; +assign sdmem2block_fifo_fifo_in_first = sdmem2block_fifo_sink_first; +assign sdmem2block_fifo_fifo_in_last = sdmem2block_fifo_sink_last; +assign sdmem2block_fifo_fifo_in_payload_data = sdmem2block_fifo_sink_payload_data; +assign sdmem2block_fifo_source_valid = sdmem2block_fifo_syncfifo_readable; +assign sdmem2block_fifo_source_first = sdmem2block_fifo_fifo_out_first; +assign sdmem2block_fifo_source_last = sdmem2block_fifo_fifo_out_last; +assign sdmem2block_fifo_source_payload_data = sdmem2block_fifo_fifo_out_payload_data; +assign sdmem2block_fifo_syncfifo_re = sdmem2block_fifo_source_ready; +always @(*) begin + sdmem2block_fifo_wrport_adr <= 9'd0; + if (sdmem2block_fifo_replace) begin + sdmem2block_fifo_wrport_adr <= (sdmem2block_fifo_produce - 1'd1); + end else begin + sdmem2block_fifo_wrport_adr <= sdmem2block_fifo_produce; + end +end +assign sdmem2block_fifo_wrport_dat_w = sdmem2block_fifo_syncfifo_din; +assign sdmem2block_fifo_wrport_we = (sdmem2block_fifo_syncfifo_we & (sdmem2block_fifo_syncfifo_writable | sdmem2block_fifo_replace)); +assign sdmem2block_fifo_do_read = (sdmem2block_fifo_syncfifo_readable & sdmem2block_fifo_syncfifo_re); +assign sdmem2block_fifo_rdport_adr = sdmem2block_fifo_consume; +assign sdmem2block_fifo_syncfifo_dout = sdmem2block_fifo_rdport_dat_r; +assign sdmem2block_fifo_syncfifo_writable = (sdmem2block_fifo_level != 10'd512); +assign sdmem2block_fifo_syncfifo_readable = (sdmem2block_fifo_level != 1'd0); +assign eventmanager_card_detect0 = card_detect_status1; +assign eventmanager_card_detect1 = card_detect_pending; +always @(*) begin + card_detect_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + card_detect_clear <= 1'd1; + end +end +assign eventmanager_block2mem_dma0 = block2mem_dma_status; +assign eventmanager_block2mem_dma1 = block2mem_dma_pending; +always @(*) begin + block2mem_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + block2mem_dma_clear <= 1'd1; + end +end +assign eventmanager_mem2block_dma0 = mem2block_dma_status; +assign eventmanager_mem2block_dma1 = mem2block_dma_pending; +always @(*) begin + mem2block_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin + mem2block_dma_clear <= 1'd1; + end +end +assign eventmanager_cmd_done0 = cmd_done_status; +assign eventmanager_cmd_done1 = cmd_done_pending; +always @(*) begin + cmd_done_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin + cmd_done_clear <= 1'd1; + end +end +assign sdirq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); +assign card_detect_status1 = 1'd0; +assign block2mem_dma_status = 1'd0; +assign mem2block_dma_status = 1'd0; +assign cmd_done_status = cmd_done_trigger; +assign cmd_done_pending = cmd_done_trigger; +always @(*) begin + litesdcardcore_litesdcardcore_wishbone_dat_r <= 32'd0; + litesdcardcore_next_state <= 1'd0; + litesdcardcore_litesdcardcore_adr <= 14'd0; + litesdcardcore_litesdcardcore_we <= 1'd0; + litesdcardcore_litesdcardcore_wishbone_ack <= 1'd0; + litesdcardcore_litesdcardcore_dat_w <= 32'd0; + litesdcardcore_next_state <= litesdcardcore_state; + case (litesdcardcore_state) + 1'd1: begin + litesdcardcore_litesdcardcore_wishbone_ack <= 1'd1; + litesdcardcore_litesdcardcore_wishbone_dat_r <= litesdcardcore_litesdcardcore_dat_r; + litesdcardcore_next_state <= 1'd0; + end + default: begin + litesdcardcore_litesdcardcore_dat_w <= litesdcardcore_litesdcardcore_wishbone_dat_w; + if ((litesdcardcore_litesdcardcore_wishbone_cyc & litesdcardcore_litesdcardcore_wishbone_stb)) begin + litesdcardcore_litesdcardcore_adr <= litesdcardcore_litesdcardcore_wishbone_adr; + litesdcardcore_litesdcardcore_we <= (litesdcardcore_litesdcardcore_wishbone_we & (litesdcardcore_litesdcardcore_wishbone_sel != 1'd0)); + litesdcardcore_next_state <= 1'd1; + end + end + endcase +end +assign litesdcardcore_litesdcardcore_wishbone_adr = wb_ctrl_adr_1; +assign litesdcardcore_litesdcardcore_wishbone_dat_w = wb_ctrl_dat_w_1; +assign wb_ctrl_dat_r_1 = litesdcardcore_litesdcardcore_wishbone_dat_r; +assign litesdcardcore_litesdcardcore_wishbone_sel = wb_ctrl_sel_1; +assign litesdcardcore_litesdcardcore_wishbone_cyc = wb_ctrl_cyc_1; +assign litesdcardcore_litesdcardcore_wishbone_stb = wb_ctrl_stb_1; +assign wb_ctrl_ack_1 = litesdcardcore_litesdcardcore_wishbone_ack; +assign litesdcardcore_litesdcardcore_wishbone_we = wb_ctrl_we_1; +assign litesdcardcore_litesdcardcore_wishbone_cti = wb_ctrl_cti_1; +assign litesdcardcore_litesdcardcore_wishbone_bte = wb_ctrl_bte_1; +assign wb_ctrl_err_1 = litesdcardcore_litesdcardcore_wishbone_err; +assign litesdcardcore_shared_adr = array_muxed0; +assign litesdcardcore_shared_dat_w = array_muxed1; +assign litesdcardcore_shared_sel = array_muxed2; +assign litesdcardcore_shared_cyc = array_muxed3; +assign litesdcardcore_shared_stb = array_muxed4; +assign litesdcardcore_shared_we = array_muxed5; +assign litesdcardcore_shared_cti = array_muxed6; +assign litesdcardcore_shared_bte = array_muxed7; +assign interface0_bus_dat_r = litesdcardcore_shared_dat_r; +assign interface1_bus_dat_r = litesdcardcore_shared_dat_r; +assign interface0_bus_ack = (litesdcardcore_shared_ack & (litesdcardcore_grant == 1'd0)); +assign interface1_bus_ack = (litesdcardcore_shared_ack & (litesdcardcore_grant == 1'd1)); +assign interface0_bus_err = (litesdcardcore_shared_err & (litesdcardcore_grant == 1'd0)); +assign interface1_bus_err = (litesdcardcore_shared_err & (litesdcardcore_grant == 1'd1)); +assign litesdcardcore_request = {interface1_bus_cyc, interface0_bus_cyc}; +assign litesdcardcore_slave_sel = 1'd1; +assign wb_dma_adr_1 = litesdcardcore_shared_adr; +assign wb_dma_dat_w_1 = litesdcardcore_shared_dat_w; +assign wb_dma_sel_1 = litesdcardcore_shared_sel; +assign wb_dma_stb_1 = litesdcardcore_shared_stb; +assign wb_dma_we_1 = litesdcardcore_shared_we; +assign wb_dma_cti_1 = litesdcardcore_shared_cti; +assign wb_dma_bte_1 = litesdcardcore_shared_bte; +assign wb_dma_cyc_1 = (litesdcardcore_shared_cyc & litesdcardcore_slave_sel); +assign litesdcardcore_shared_err = wb_dma_err_1; +assign litesdcardcore_wait = ((litesdcardcore_shared_stb & litesdcardcore_shared_cyc) & (~litesdcardcore_shared_ack)); +always @(*) begin + litesdcardcore_shared_dat_r <= 32'd0; + litesdcardcore_shared_ack <= 1'd0; + litesdcardcore_error <= 1'd0; + litesdcardcore_shared_ack <= wb_dma_ack_1; + litesdcardcore_shared_dat_r <= ({32{litesdcardcore_slave_sel_r}} & wb_dma_dat_r_1); + if (litesdcardcore_done) begin + litesdcardcore_shared_dat_r <= 32'd4294967295; + litesdcardcore_shared_ack <= 1'd1; + litesdcardcore_error <= 1'd1; + end +end +assign litesdcardcore_done = (litesdcardcore_count == 1'd0); +assign litesdcardcore_csrbank0_sel = (litesdcardcore_interface0_bank_bus_adr[13:9] == 1'd0); +assign litesdcardcore_csrbank0_reset0_r = litesdcardcore_interface0_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank0_reset0_re <= 1'd0; + litesdcardcore_csrbank0_reset0_we <= 1'd0; + if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank0_reset0_re <= litesdcardcore_interface0_bank_bus_we; + litesdcardcore_csrbank0_reset0_we <= (~litesdcardcore_interface0_bank_bus_we); + end +end +assign litesdcardcore_csrbank0_scratch0_r = litesdcardcore_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank0_scratch0_re <= 1'd0; + litesdcardcore_csrbank0_scratch0_we <= 1'd0; + if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank0_scratch0_re <= litesdcardcore_interface0_bank_bus_we; + litesdcardcore_csrbank0_scratch0_we <= (~litesdcardcore_interface0_bank_bus_we); + end +end +assign litesdcardcore_csrbank0_bus_errors_r = litesdcardcore_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank0_bus_errors_we <= 1'd0; + litesdcardcore_csrbank0_bus_errors_re <= 1'd0; + if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank0_bus_errors_re <= litesdcardcore_interface0_bank_bus_we; + litesdcardcore_csrbank0_bus_errors_we <= (~litesdcardcore_interface0_bank_bus_we); + end +end +assign litesdcardcore_csrbank0_reset0_w = reset_storage; +assign litesdcardcore_csrbank0_scratch0_w = scratch_storage[31:0]; +assign litesdcardcore_csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = litesdcardcore_csrbank0_bus_errors_we; +assign litesdcardcore_csrbank1_sel = (litesdcardcore_interface1_bank_bus_adr[13:9] == 1'd1); +assign litesdcardcore_csrbank1_dma_base1_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_base1_we <= 1'd0; + litesdcardcore_csrbank1_dma_base1_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank1_dma_base1_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_base1_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_base0_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_base0_we <= 1'd0; + litesdcardcore_csrbank1_dma_base0_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank1_dma_base0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_base0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_length0_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_length0_re <= 1'd0; + litesdcardcore_csrbank1_dma_length0_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank1_dma_length0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_length0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_enable0_r = litesdcardcore_interface1_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank1_dma_enable0_we <= 1'd0; + litesdcardcore_csrbank1_dma_enable0_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank1_dma_enable0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_enable0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_done_r = litesdcardcore_interface1_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank1_dma_done_re <= 1'd0; + litesdcardcore_csrbank1_dma_done_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 3'd4))) begin + litesdcardcore_csrbank1_dma_done_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_done_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_loop0_r = litesdcardcore_interface1_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank1_dma_loop0_re <= 1'd0; + litesdcardcore_csrbank1_dma_loop0_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 3'd5))) begin + litesdcardcore_csrbank1_dma_loop0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_loop0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_offset_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_offset_we <= 1'd0; + litesdcardcore_csrbank1_dma_offset_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 3'd6))) begin + litesdcardcore_csrbank1_dma_offset_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_offset_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_base1_w = sdblock2mem_wishbonedmawriter_base_storage[63:32]; +assign litesdcardcore_csrbank1_dma_base0_w = sdblock2mem_wishbonedmawriter_base_storage[31:0]; +assign litesdcardcore_csrbank1_dma_length0_w = sdblock2mem_wishbonedmawriter_length_storage[31:0]; +assign litesdcardcore_csrbank1_dma_enable0_w = sdblock2mem_wishbonedmawriter_enable_storage; +assign litesdcardcore_csrbank1_dma_done_w = sdblock2mem_wishbonedmawriter_done_status; +assign sdblock2mem_wishbonedmawriter_done_we = litesdcardcore_csrbank1_dma_done_we; +assign litesdcardcore_csrbank1_dma_loop0_w = sdblock2mem_wishbonedmawriter_loop_storage; +assign litesdcardcore_csrbank1_dma_offset_w = sdblock2mem_wishbonedmawriter_offset_status[31:0]; +assign sdblock2mem_wishbonedmawriter_offset_we = litesdcardcore_csrbank1_dma_offset_we; +assign litesdcardcore_csrbank2_sel = (litesdcardcore_interface2_bank_bus_adr[13:9] == 2'd2); +assign litesdcardcore_csrbank2_cmd_argument0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_argument0_we <= 1'd0; + litesdcardcore_csrbank2_cmd_argument0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank2_cmd_argument0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_argument0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_command0_r = litesdcardcore_interface2_bank_bus_dat_w[13:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_command0_re <= 1'd0; + litesdcardcore_csrbank2_cmd_command0_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank2_cmd_command0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_command0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_send0_r = litesdcardcore_interface2_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_send0_we <= 1'd0; + litesdcardcore_csrbank2_cmd_send0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank2_cmd_send0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_send0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response3_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response3_re <= 1'd0; + litesdcardcore_csrbank2_cmd_response3_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank2_cmd_response3_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response3_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response2_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response2_re <= 1'd0; + litesdcardcore_csrbank2_cmd_response2_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd4))) begin + litesdcardcore_csrbank2_cmd_response2_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response2_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response1_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response1_we <= 1'd0; + litesdcardcore_csrbank2_cmd_response1_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd5))) begin + litesdcardcore_csrbank2_cmd_response1_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response1_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response0_we <= 1'd0; + litesdcardcore_csrbank2_cmd_response0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd6))) begin + litesdcardcore_csrbank2_cmd_response0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_event_r = litesdcardcore_interface2_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_event_re <= 1'd0; + litesdcardcore_csrbank2_cmd_event_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd7))) begin + litesdcardcore_csrbank2_cmd_event_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_event_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_data_event_r = litesdcardcore_interface2_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank2_data_event_re <= 1'd0; + litesdcardcore_csrbank2_data_event_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd8))) begin + litesdcardcore_csrbank2_data_event_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_data_event_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_block_length0_r = litesdcardcore_interface2_bank_bus_dat_w[9:0]; +always @(*) begin + litesdcardcore_csrbank2_block_length0_we <= 1'd0; + litesdcardcore_csrbank2_block_length0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd9))) begin + litesdcardcore_csrbank2_block_length0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_block_length0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_block_count0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_block_count0_we <= 1'd0; + litesdcardcore_csrbank2_block_count0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd10))) begin + litesdcardcore_csrbank2_block_count0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_block_count0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_argument0_w = sdcore_cmd_argument_storage[31:0]; +assign sdcore_csrfield_cmd_type = sdcore_cmd_command_storage[1:0]; +assign sdcore_csrfield_data_type = sdcore_cmd_command_storage[6:5]; +assign sdcore_csrfield_cmd = sdcore_cmd_command_storage[13:8]; +assign litesdcardcore_csrbank2_cmd_command0_w = sdcore_cmd_command_storage[13:0]; +assign litesdcardcore_csrbank2_cmd_send0_w = sdcore_cmd_send_storage; +assign litesdcardcore_csrbank2_cmd_response3_w = sdcore_cmd_response_status[127:96]; +assign litesdcardcore_csrbank2_cmd_response2_w = sdcore_cmd_response_status[95:64]; +assign litesdcardcore_csrbank2_cmd_response1_w = sdcore_cmd_response_status[63:32]; +assign litesdcardcore_csrbank2_cmd_response0_w = sdcore_cmd_response_status[31:0]; +assign sdcore_cmd_response_we = litesdcardcore_csrbank2_cmd_response0_we; +always @(*) begin + sdcore_cmd_event_status <= 4'd0; + sdcore_cmd_event_status[0] <= sdcore_csrfield_done0; + sdcore_cmd_event_status[1] <= sdcore_csrfield_error0; + sdcore_cmd_event_status[2] <= sdcore_csrfield_timeout0; + sdcore_cmd_event_status[3] <= sdcore_csrfield_crc0; +end +assign litesdcardcore_csrbank2_cmd_event_w = sdcore_cmd_event_status[3:0]; +assign sdcore_cmd_event_we = litesdcardcore_csrbank2_cmd_event_we; +always @(*) begin + sdcore_data_event_status <= 4'd0; + sdcore_data_event_status[0] <= sdcore_csrfield_done1; + sdcore_data_event_status[1] <= sdcore_csrfield_error1; + sdcore_data_event_status[2] <= sdcore_csrfield_timeout1; + sdcore_data_event_status[3] <= sdcore_csrfield_crc1; +end +assign litesdcardcore_csrbank2_data_event_w = sdcore_data_event_status[3:0]; +assign sdcore_data_event_we = litesdcardcore_csrbank2_data_event_we; +assign litesdcardcore_csrbank2_block_length0_w = sdcore_block_length_storage[9:0]; +assign litesdcardcore_csrbank2_block_count0_w = sdcore_block_count_storage[31:0]; +assign litesdcardcore_csrbank3_sel = (litesdcardcore_interface3_bank_bus_adr[13:9] == 2'd3); +assign litesdcardcore_csrbank3_status_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank3_status_we <= 1'd0; + litesdcardcore_csrbank3_status_re <= 1'd0; + if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank3_status_re <= litesdcardcore_interface3_bank_bus_we; + litesdcardcore_csrbank3_status_we <= (~litesdcardcore_interface3_bank_bus_we); + end +end +assign litesdcardcore_csrbank3_pending_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank3_pending_re <= 1'd0; + litesdcardcore_csrbank3_pending_we <= 1'd0; + if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank3_pending_re <= litesdcardcore_interface3_bank_bus_we; + litesdcardcore_csrbank3_pending_we <= (~litesdcardcore_interface3_bank_bus_we); + end +end +assign litesdcardcore_csrbank3_enable0_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank3_enable0_re <= 1'd0; + litesdcardcore_csrbank3_enable0_we <= 1'd0; + if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank3_enable0_re <= litesdcardcore_interface3_bank_bus_we; + litesdcardcore_csrbank3_enable0_we <= (~litesdcardcore_interface3_bank_bus_we); + end +end +always @(*) begin + eventmanager_status_status <= 4'd0; + eventmanager_status_status[0] <= eventmanager_card_detect0; + eventmanager_status_status[1] <= eventmanager_block2mem_dma0; + eventmanager_status_status[2] <= eventmanager_mem2block_dma0; + eventmanager_status_status[3] <= eventmanager_cmd_done0; +end +assign litesdcardcore_csrbank3_status_w = eventmanager_status_status[3:0]; +assign eventmanager_status_we = litesdcardcore_csrbank3_status_we; +always @(*) begin + eventmanager_pending_status <= 4'd0; + eventmanager_pending_status[0] <= eventmanager_card_detect1; + eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; + eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; + eventmanager_pending_status[3] <= eventmanager_cmd_done1; +end +assign litesdcardcore_csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign eventmanager_pending_we = litesdcardcore_csrbank3_pending_we; +assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; +assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; +assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; +assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; +assign litesdcardcore_csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign litesdcardcore_csrbank4_sel = (litesdcardcore_interface4_bank_bus_adr[13:9] == 3'd4); +assign litesdcardcore_csrbank4_dma_base1_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_base1_re <= 1'd0; + litesdcardcore_csrbank4_dma_base1_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank4_dma_base1_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_base1_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_base0_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_base0_we <= 1'd0; + litesdcardcore_csrbank4_dma_base0_re <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank4_dma_base0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_base0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_length0_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_length0_re <= 1'd0; + litesdcardcore_csrbank4_dma_length0_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank4_dma_length0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_length0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_enable0_r = litesdcardcore_interface4_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank4_dma_enable0_re <= 1'd0; + litesdcardcore_csrbank4_dma_enable0_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank4_dma_enable0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_enable0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_done_r = litesdcardcore_interface4_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank4_dma_done_we <= 1'd0; + litesdcardcore_csrbank4_dma_done_re <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd4))) begin + litesdcardcore_csrbank4_dma_done_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_done_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_loop0_r = litesdcardcore_interface4_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank4_dma_loop0_re <= 1'd0; + litesdcardcore_csrbank4_dma_loop0_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd5))) begin + litesdcardcore_csrbank4_dma_loop0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_loop0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_offset_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_offset_re <= 1'd0; + litesdcardcore_csrbank4_dma_offset_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd6))) begin + litesdcardcore_csrbank4_dma_offset_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_offset_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_base1_w = sdmem2block_dma_base_storage[63:32]; +assign litesdcardcore_csrbank4_dma_base0_w = sdmem2block_dma_base_storage[31:0]; +assign litesdcardcore_csrbank4_dma_length0_w = sdmem2block_dma_length_storage[31:0]; +assign litesdcardcore_csrbank4_dma_enable0_w = sdmem2block_dma_enable_storage; +assign litesdcardcore_csrbank4_dma_done_w = sdmem2block_dma_done_status; +assign sdmem2block_dma_done_we = litesdcardcore_csrbank4_dma_done_we; +assign litesdcardcore_csrbank4_dma_loop0_w = sdmem2block_dma_loop_storage; +assign litesdcardcore_csrbank4_dma_offset_w = sdmem2block_dma_offset_status[31:0]; +assign sdmem2block_dma_offset_we = litesdcardcore_csrbank4_dma_offset_we; +assign litesdcardcore_csrbank5_sel = (litesdcardcore_interface5_bank_bus_adr[13:9] == 3'd5); +assign litesdcardcore_csrbank5_card_detect_r = litesdcardcore_interface5_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank5_card_detect_we <= 1'd0; + litesdcardcore_csrbank5_card_detect_re <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank5_card_detect_re <= litesdcardcore_interface5_bank_bus_we; + litesdcardcore_csrbank5_card_detect_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign litesdcardcore_csrbank5_clocker_divider0_r = litesdcardcore_interface5_bank_bus_dat_w[8:0]; +always @(*) begin + litesdcardcore_csrbank5_clocker_divider0_we <= 1'd0; + litesdcardcore_csrbank5_clocker_divider0_re <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank5_clocker_divider0_re <= litesdcardcore_interface5_bank_bus_we; + litesdcardcore_csrbank5_clocker_divider0_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign init_initialize_r = litesdcardcore_interface5_bank_bus_dat_w[0]; +always @(*) begin + init_initialize_we <= 1'd0; + init_initialize_re <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 2'd2))) begin + init_initialize_re <= litesdcardcore_interface5_bank_bus_we; + init_initialize_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign litesdcardcore_csrbank5_dataw_status_r = litesdcardcore_interface5_bank_bus_dat_w[2:0]; +always @(*) begin + litesdcardcore_csrbank5_dataw_status_re <= 1'd0; + litesdcardcore_csrbank5_dataw_status_we <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank5_dataw_status_re <= litesdcardcore_interface5_bank_bus_we; + litesdcardcore_csrbank5_dataw_status_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign litesdcardcore_csrbank5_card_detect_w = card_detect_status0; +assign card_detect_we = litesdcardcore_csrbank5_card_detect_we; +assign litesdcardcore_csrbank5_clocker_divider0_w = clocker_storage[8:0]; +always @(*) begin + dataw_status <= 3'd0; + dataw_status[0] <= dataw_accepted0; + dataw_status[1] <= dataw_crc_error0; + dataw_status[2] <= dataw_write_error0; +end +assign litesdcardcore_csrbank5_dataw_status_w = dataw_status[2:0]; +assign dataw_we = litesdcardcore_csrbank5_dataw_status_we; +assign litesdcardcore_csr_interconnect_adr = litesdcardcore_litesdcardcore_adr; +assign litesdcardcore_csr_interconnect_we = litesdcardcore_litesdcardcore_we; +assign litesdcardcore_csr_interconnect_dat_w = litesdcardcore_litesdcardcore_dat_w; +assign litesdcardcore_litesdcardcore_dat_r = litesdcardcore_csr_interconnect_dat_r; +assign litesdcardcore_interface0_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface1_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface2_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface3_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface4_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface5_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface0_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface1_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface2_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface3_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface4_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface5_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface0_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface1_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface2_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface3_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface4_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface5_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_csr_interconnect_dat_r = (((((litesdcardcore_interface0_bank_bus_dat_r | litesdcardcore_interface1_bank_bus_dat_r) | litesdcardcore_interface2_bank_bus_dat_r) | litesdcardcore_interface3_bank_bus_dat_r) | litesdcardcore_interface4_bank_bus_dat_r) | litesdcardcore_interface5_bank_bus_dat_r); +always @(*) begin + array_muxed0 <= 32'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed0 <= interface0_bus_adr; + end + default: begin + array_muxed0 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + array_muxed1 <= 32'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed1 <= interface0_bus_dat_w; + end + default: begin + array_muxed1 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + array_muxed2 <= 4'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed2 <= interface0_bus_sel; + end + default: begin + array_muxed2 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed3 <= interface0_bus_cyc; + end + default: begin + array_muxed3 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed4 <= interface0_bus_stb; + end + default: begin + array_muxed4 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed5 <= interface0_bus_we; + end + default: begin + array_muxed5 <= interface1_bus_we; + end + endcase +end +always @(*) begin + array_muxed6 <= 3'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed6 <= interface0_bus_cti; + end + default: begin + array_muxed6 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + array_muxed7 <= 2'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed7 <= interface0_bus_bte; + end + default: begin + array_muxed7 <= interface1_bus_bte; + end + endcase +end +assign sdrio_clk = sys_clk; +assign sdrio_clk_1 = sys_clk; +assign sdrio_clk_2 = sys_clk; +assign sdrio_clk_3 = sys_clk; +assign sdrio_clk_4 = sys_clk; +assign sdrio_clk_5 = sys_clk; +assign sdrio_clk_6 = sys_clk; +assign sdrio_clk_7 = sys_clk; +assign sdrio_clk_8 = sys_clk; +assign sdrio_clk_9 = sys_clk; +assign sdrio_clk_10 = sys_clk; +assign sdrio_clk_11 = sys_clk; +assign sdrio_clk_12 = sys_clk; +assign sdrio_clk_13 = sys_clk; +assign sdrio_clk_14 = sys_clk; +assign sdrio_clk_15 = sys_clk; + +always @(posedge por_clk) begin + int_rst <= rst; +end + +always @(posedge sdrio_clk) begin + sdcard_clk <= clocker_clk0; + xilinxsdrtristateimpl0__o <= sdpads_cmd_o; + xilinxsdrtristateimpl0_oe_n <= (~sdpads_cmd_oe); + sdpads_cmd_i <= xilinxsdrtristateimpl0__i; + xilinxsdrtristateimpl1__o <= sdpads_data_o[0]; + xilinxsdrtristateimpl1_oe_n <= (~sdpads_data_oe); + sdpads_data_i[0] <= xilinxsdrtristateimpl1__i; + xilinxsdrtristateimpl2__o <= sdpads_data_o[1]; + xilinxsdrtristateimpl2_oe_n <= (~sdpads_data_oe); + sdpads_data_i[1] <= xilinxsdrtristateimpl2__i; + xilinxsdrtristateimpl3__o <= sdpads_data_o[2]; + xilinxsdrtristateimpl3_oe_n <= (~sdpads_data_oe); + sdpads_data_i[2] <= xilinxsdrtristateimpl3__i; + xilinxsdrtristateimpl4__o <= sdpads_data_o[3]; + xilinxsdrtristateimpl4_oe_n <= (~sdpads_data_oe); + sdpads_data_i[3] <= xilinxsdrtristateimpl4__i; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + card_detect_d <= card_detect_status0; + card_detect_irq <= (card_detect_status0 ^ card_detect_d); + if ((~clocker_stop)) begin + clocker_clks <= (clocker_clks + 1'd1); + end + clocker_clk_d <= clocker_clk1; + if (clocker_clk_d) begin + clocker_ce_delayed <= clocker_clk_en; + end + subfragments_sdphyinit_state <= subfragments_sdphyinit_next_state; + if (init_count_sdphyinit_next_value_ce) begin + init_count <= init_count_sdphyinit_next_value; + end + subfragments_sdphycmdw_state <= subfragments_sdphycmdw_next_state; + if (cmdw_count_sdphycmdw_next_value_ce) begin + cmdw_count <= cmdw_count_sdphycmdw_next_value; + end + if (cmdr_cmdr_pads_in_valid) begin + cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); + end + if (cmdr_cmdr_converter_source_ready) begin + cmdr_cmdr_converter_strobe_all <= 1'd0; + end + if (cmdr_cmdr_converter_load_part) begin + if (((cmdr_cmdr_converter_demux == 3'd7) | cmdr_cmdr_converter_sink_last)) begin + cmdr_cmdr_converter_demux <= 1'd0; + cmdr_cmdr_converter_strobe_all <= 1'd1; + end else begin + cmdr_cmdr_converter_demux <= (cmdr_cmdr_converter_demux + 1'd1); + end + end + if ((cmdr_cmdr_converter_source_valid & cmdr_cmdr_converter_source_ready)) begin + if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin + cmdr_cmdr_converter_source_first <= cmdr_cmdr_converter_sink_first; + cmdr_cmdr_converter_source_last <= cmdr_cmdr_converter_sink_last; + end else begin + cmdr_cmdr_converter_source_first <= 1'd0; + cmdr_cmdr_converter_source_last <= 1'd0; + end + end else begin + if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin + cmdr_cmdr_converter_source_first <= (cmdr_cmdr_converter_sink_first | cmdr_cmdr_converter_source_first); + cmdr_cmdr_converter_source_last <= (cmdr_cmdr_converter_sink_last | cmdr_cmdr_converter_source_last); + end + end + if (cmdr_cmdr_converter_load_part) begin + case (cmdr_cmdr_converter_demux) + 1'd0: begin + cmdr_cmdr_converter_source_payload_data[7] <= cmdr_cmdr_converter_sink_payload_data; + end + 1'd1: begin + cmdr_cmdr_converter_source_payload_data[6] <= cmdr_cmdr_converter_sink_payload_data; + end + 2'd2: begin + cmdr_cmdr_converter_source_payload_data[5] <= cmdr_cmdr_converter_sink_payload_data; + end + 2'd3: begin + cmdr_cmdr_converter_source_payload_data[4] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd4: begin + cmdr_cmdr_converter_source_payload_data[3] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd5: begin + cmdr_cmdr_converter_source_payload_data[2] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd6: begin + cmdr_cmdr_converter_source_payload_data[1] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd7: begin + cmdr_cmdr_converter_source_payload_data[0] <= cmdr_cmdr_converter_sink_payload_data; + end + endcase + end + if (cmdr_cmdr_converter_load_part) begin + cmdr_cmdr_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_demux + 1'd1); + end + if (((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready)) begin + cmdr_cmdr_buf_source_valid <= cmdr_cmdr_buf_sink_valid; + cmdr_cmdr_buf_source_first <= cmdr_cmdr_buf_sink_first; + cmdr_cmdr_buf_source_last <= cmdr_cmdr_buf_sink_last; + cmdr_cmdr_buf_source_payload_data <= cmdr_cmdr_buf_sink_payload_data; + end + if (cmdr_cmdr_reset) begin + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_demux <= 3'd0; + cmdr_cmdr_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_source_valid <= 1'd0; + cmdr_cmdr_buf_source_payload_data <= 8'd0; + end + subfragments_sdphycmdr_state <= subfragments_sdphycmdr_next_state; + if (cmdr_timeout_sdphycmdr_next_value_ce0) begin + cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; + end + if (cmdr_count_sdphycmdr_next_value_ce1) begin + cmdr_count <= cmdr_count_sdphycmdr_next_value1; + end + if (cmdr_busy_sdphycmdr_next_value_ce2) begin + cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; + end + if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin + cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; + end + if (dataw_crc_pads_in_valid) begin + dataw_crc_run <= (dataw_crc_start | dataw_crc_run); + end + if (dataw_crc_converter_source_ready) begin + dataw_crc_converter_strobe_all <= 1'd0; + end + if (dataw_crc_converter_load_part) begin + if (((dataw_crc_converter_demux == 3'd7) | dataw_crc_converter_sink_last)) begin + dataw_crc_converter_demux <= 1'd0; + dataw_crc_converter_strobe_all <= 1'd1; + end else begin + dataw_crc_converter_demux <= (dataw_crc_converter_demux + 1'd1); + end + end + if ((dataw_crc_converter_source_valid & dataw_crc_converter_source_ready)) begin + if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin + dataw_crc_converter_source_first <= dataw_crc_converter_sink_first; + dataw_crc_converter_source_last <= dataw_crc_converter_sink_last; + end else begin + dataw_crc_converter_source_first <= 1'd0; + dataw_crc_converter_source_last <= 1'd0; + end + end else begin + if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin + dataw_crc_converter_source_first <= (dataw_crc_converter_sink_first | dataw_crc_converter_source_first); + dataw_crc_converter_source_last <= (dataw_crc_converter_sink_last | dataw_crc_converter_source_last); + end + end + if (dataw_crc_converter_load_part) begin + case (dataw_crc_converter_demux) + 1'd0: begin + dataw_crc_converter_source_payload_data[7] <= dataw_crc_converter_sink_payload_data; + end + 1'd1: begin + dataw_crc_converter_source_payload_data[6] <= dataw_crc_converter_sink_payload_data; + end + 2'd2: begin + dataw_crc_converter_source_payload_data[5] <= dataw_crc_converter_sink_payload_data; + end + 2'd3: begin + dataw_crc_converter_source_payload_data[4] <= dataw_crc_converter_sink_payload_data; + end + 3'd4: begin + dataw_crc_converter_source_payload_data[3] <= dataw_crc_converter_sink_payload_data; + end + 3'd5: begin + dataw_crc_converter_source_payload_data[2] <= dataw_crc_converter_sink_payload_data; + end + 3'd6: begin + dataw_crc_converter_source_payload_data[1] <= dataw_crc_converter_sink_payload_data; + end + 3'd7: begin + dataw_crc_converter_source_payload_data[0] <= dataw_crc_converter_sink_payload_data; + end + endcase + end + if (dataw_crc_converter_load_part) begin + dataw_crc_converter_source_payload_valid_token_count <= (dataw_crc_converter_demux + 1'd1); + end + if (((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready)) begin + dataw_crc_buf_source_valid <= dataw_crc_buf_sink_valid; + dataw_crc_buf_source_first <= dataw_crc_buf_sink_first; + dataw_crc_buf_source_last <= dataw_crc_buf_sink_last; + dataw_crc_buf_source_payload_data <= dataw_crc_buf_sink_payload_data; + end + if (dataw_crc_reset) begin + dataw_crc_run <= 1'd0; + dataw_crc_converter_source_payload_data <= 8'd0; + dataw_crc_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_demux <= 3'd0; + dataw_crc_converter_strobe_all <= 1'd0; + dataw_crc_buf_source_valid <= 1'd0; + dataw_crc_buf_source_payload_data <= 8'd0; + end + subfragments_sdphydataw_state <= subfragments_sdphydataw_next_state; + if (dataw_accepted1_sdphydataw_next_value_ce0) begin + dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; + end + if (dataw_crc_error1_sdphydataw_next_value_ce1) begin + dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; + end + if (dataw_write_error1_sdphydataw_next_value_ce2) begin + dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; + end + if (dataw_count_sdphydataw_next_value_ce3) begin + dataw_count <= dataw_count_sdphydataw_next_value3; + end + if (datar_datar_pads_in_valid) begin + datar_datar_run <= (datar_datar_start | datar_datar_run); + end + if (datar_datar_converter_source_ready) begin + datar_datar_converter_strobe_all <= 1'd0; + end + if (datar_datar_converter_load_part) begin + if (((datar_datar_converter_demux == 1'd1) | datar_datar_converter_sink_last)) begin + datar_datar_converter_demux <= 1'd0; + datar_datar_converter_strobe_all <= 1'd1; + end else begin + datar_datar_converter_demux <= (datar_datar_converter_demux + 1'd1); + end + end + if ((datar_datar_converter_source_valid & datar_datar_converter_source_ready)) begin + if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin + datar_datar_converter_source_first <= datar_datar_converter_sink_first; + datar_datar_converter_source_last <= datar_datar_converter_sink_last; + end else begin + datar_datar_converter_source_first <= 1'd0; + datar_datar_converter_source_last <= 1'd0; + end + end else begin + if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin + datar_datar_converter_source_first <= (datar_datar_converter_sink_first | datar_datar_converter_source_first); + datar_datar_converter_source_last <= (datar_datar_converter_sink_last | datar_datar_converter_source_last); + end + end + if (datar_datar_converter_load_part) begin + case (datar_datar_converter_demux) + 1'd0: begin + datar_datar_converter_source_payload_data[7:4] <= datar_datar_converter_sink_payload_data; + end + 1'd1: begin + datar_datar_converter_source_payload_data[3:0] <= datar_datar_converter_sink_payload_data; + end + endcase + end + if (datar_datar_converter_load_part) begin + datar_datar_converter_source_payload_valid_token_count <= (datar_datar_converter_demux + 1'd1); + end + if (((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready)) begin + datar_datar_buf_source_valid <= datar_datar_buf_sink_valid; + datar_datar_buf_source_first <= datar_datar_buf_sink_first; + datar_datar_buf_source_last <= datar_datar_buf_sink_last; + datar_datar_buf_source_payload_data <= datar_datar_buf_sink_payload_data; + end + if (datar_datar_reset) begin + datar_datar_run <= 1'd0; + datar_datar_converter_source_payload_data <= 8'd0; + datar_datar_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_demux <= 1'd0; + datar_datar_converter_strobe_all <= 1'd0; + datar_datar_buf_source_valid <= 1'd0; + datar_datar_buf_source_payload_data <= 8'd0; + end + subfragments_sdphydatar_state <= subfragments_sdphydatar_next_state; + if (datar_count_sdphydatar_next_value_ce0) begin + datar_count <= datar_count_sdphydatar_next_value0; + end + if (datar_timeout_sdphydatar_next_value_ce1) begin + datar_timeout <= datar_timeout_sdphydatar_next_value1; + end + if (datar_datar_reset_sdphydatar_next_value_ce2) begin + datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; + end + clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; + sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + if (sdcore_crc7_inserter_reset) begin + sdcore_crc7_inserter_reg0 <= 1'd0; + end else begin + if (sdcore_crc7_inserter_enable) begin + sdcore_crc7_inserter_reg0 <= sdcore_crc7_inserter_reg40; + end + end + if (sdcore_crc16_inserter_crc0_reset) begin + sdcore_crc16_inserter_crc0_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc0_enable) begin + sdcore_crc16_inserter_crc0_reg0 <= sdcore_crc16_inserter_crc0_reg2; + end + end + if (sdcore_crc16_inserter_crc1_reset) begin + sdcore_crc16_inserter_crc1_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc1_enable) begin + sdcore_crc16_inserter_crc1_reg0 <= sdcore_crc16_inserter_crc1_reg2; + end + end + if (sdcore_crc16_inserter_crc2_reset) begin + sdcore_crc16_inserter_crc2_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc2_enable) begin + sdcore_crc16_inserter_crc2_reg0 <= sdcore_crc16_inserter_crc2_reg2; + end + end + if (sdcore_crc16_inserter_crc3_reset) begin + sdcore_crc16_inserter_crc3_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc3_enable) begin + sdcore_crc16_inserter_crc3_reg0 <= sdcore_crc16_inserter_crc3_reg2; + end + end + subfragments_sdcore_crc16inserter_state <= subfragments_sdcore_crc16inserter_next_state; + if (sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce) begin + sdcore_crc16_inserter_count <= sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value; + end + if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin + sdcore_fifo_produce <= (sdcore_fifo_produce + 1'd1); + end + if (sdcore_fifo_do_read) begin + sdcore_fifo_consume <= (sdcore_fifo_consume + 1'd1); + end + if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin + if ((~sdcore_fifo_do_read)) begin + sdcore_fifo_level <= (sdcore_fifo_level + 1'd1); + end + end else begin + if (sdcore_fifo_do_read) begin + sdcore_fifo_level <= (sdcore_fifo_level - 1'd1); + end + end + if (sdcore_fifo_reset) begin + sdcore_fifo_level <= 4'd0; + sdcore_fifo_produce <= 3'd0; + sdcore_fifo_consume <= 3'd0; + end + subfragments_sdcore_fsm_state <= subfragments_sdcore_fsm_next_state; + if (sdcore_cmd_done_sdcore_fsm_next_value_ce0) begin + sdcore_cmd_done <= sdcore_cmd_done_sdcore_fsm_next_value0; + end + if (sdcore_data_done_sdcore_fsm_next_value_ce1) begin + sdcore_data_done <= sdcore_data_done_sdcore_fsm_next_value1; + end + if (sdcore_cmd_count_sdcore_fsm_next_value_ce2) begin + sdcore_cmd_count <= sdcore_cmd_count_sdcore_fsm_next_value2; + end + if (sdcore_data_count_sdcore_fsm_next_value_ce3) begin + sdcore_data_count <= sdcore_data_count_sdcore_fsm_next_value3; + end + if (sdcore_cmd_error_sdcore_fsm_next_value_ce4) begin + sdcore_cmd_error <= sdcore_cmd_error_sdcore_fsm_next_value4; + end + if (sdcore_cmd_timeout_sdcore_fsm_next_value_ce5) begin + sdcore_cmd_timeout <= sdcore_cmd_timeout_sdcore_fsm_next_value5; + end + if (sdcore_data_error_sdcore_fsm_next_value_ce6) begin + sdcore_data_error <= sdcore_data_error_sdcore_fsm_next_value6; + end + if (sdcore_data_timeout_sdcore_fsm_next_value_ce7) begin + sdcore_data_timeout <= sdcore_data_timeout_sdcore_fsm_next_value7; + end + if (sdcore_cmd_response_status_sdcore_fsm_next_value_ce8) begin + sdcore_cmd_response_status <= sdcore_cmd_response_status_sdcore_fsm_next_value8; + end + if ((~sdblock2mem_wishbonedmawriter_enable_storage)) begin + sdblock2mem_connect <= 1'd0; + end else begin + if (sdblock2mem_start) begin + sdblock2mem_connect <= 1'd1; + end + end + sdblock2mem_done_d <= sdblock2mem_wishbonedmawriter_done_status; + sdblock2mem_irq <= (sdblock2mem_wishbonedmawriter_done_status & (~sdblock2mem_done_d)); + if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin + sdblock2mem_fifo_produce <= (sdblock2mem_fifo_produce + 1'd1); + end + if (sdblock2mem_fifo_do_read) begin + sdblock2mem_fifo_consume <= (sdblock2mem_fifo_consume + 1'd1); + end + if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin + if ((~sdblock2mem_fifo_do_read)) begin + sdblock2mem_fifo_level <= (sdblock2mem_fifo_level + 1'd1); + end + end else begin + if (sdblock2mem_fifo_do_read) begin + sdblock2mem_fifo_level <= (sdblock2mem_fifo_level - 1'd1); + end + end + if (sdblock2mem_converter_source_ready) begin + sdblock2mem_converter_strobe_all <= 1'd0; + end + if (sdblock2mem_converter_load_part) begin + if (((sdblock2mem_converter_demux == 2'd3) | sdblock2mem_converter_sink_last)) begin + sdblock2mem_converter_demux <= 1'd0; + sdblock2mem_converter_strobe_all <= 1'd1; + end else begin + sdblock2mem_converter_demux <= (sdblock2mem_converter_demux + 1'd1); + end + end + if ((sdblock2mem_converter_source_valid & sdblock2mem_converter_source_ready)) begin + if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin + sdblock2mem_converter_source_first <= sdblock2mem_converter_sink_first; + sdblock2mem_converter_source_last <= sdblock2mem_converter_sink_last; + end else begin + sdblock2mem_converter_source_first <= 1'd0; + sdblock2mem_converter_source_last <= 1'd0; + end + end else begin + if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin + sdblock2mem_converter_source_first <= (sdblock2mem_converter_sink_first | sdblock2mem_converter_source_first); + sdblock2mem_converter_source_last <= (sdblock2mem_converter_sink_last | sdblock2mem_converter_source_last); + end + end + if (sdblock2mem_converter_load_part) begin + case (sdblock2mem_converter_demux) + 1'd0: begin + sdblock2mem_converter_source_payload_data[31:24] <= sdblock2mem_converter_sink_payload_data; + end + 1'd1: begin + sdblock2mem_converter_source_payload_data[23:16] <= sdblock2mem_converter_sink_payload_data; + end + 2'd2: begin + sdblock2mem_converter_source_payload_data[15:8] <= sdblock2mem_converter_sink_payload_data; + end + 2'd3: begin + sdblock2mem_converter_source_payload_data[7:0] <= sdblock2mem_converter_sink_payload_data; + end + endcase + end + if (sdblock2mem_converter_load_part) begin + sdblock2mem_converter_source_payload_valid_token_count <= (sdblock2mem_converter_demux + 1'd1); + end + subfragments_state <= subfragments_next_state; + if (sdblock2mem_wishbonedmawriter_offset_next_value_ce) begin + sdblock2mem_wishbonedmawriter_offset <= sdblock2mem_wishbonedmawriter_offset_next_value; + end + if (sdblock2mem_wishbonedmawriter_reset) begin + sdblock2mem_wishbonedmawriter_offset <= 32'd0; + subfragments_state <= 2'd0; + end + if ((sdmem2block_source_source_valid0 & sdmem2block_source_source_ready0)) begin + sdmem2block_count <= (sdmem2block_count + 1'd1); + if (sdmem2block_source_source_last0) begin + sdmem2block_count <= 1'd0; + end + end + sdmem2block_done_d <= sdmem2block_dma_done_status; + sdmem2block_irq <= (sdmem2block_dma_done_status & (~sdmem2block_done_d)); + subfragments_sdmem2blockdma_fsm_state <= subfragments_sdmem2blockdma_fsm_next_state; + if (sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce) begin + sdmem2block_dma_data <= sdmem2block_dma_data_sdmem2blockdma_fsm_next_value; + end + subfragments_sdmem2blockdma_resetinserter_state <= subfragments_sdmem2blockdma_resetinserter_next_state; + if (sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce) begin + sdmem2block_dma_offset <= sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value; + end + if (sdmem2block_dma_reset) begin + sdmem2block_dma_offset <= 32'd0; + subfragments_sdmem2blockdma_resetinserter_state <= 2'd0; + end + if ((sdmem2block_converter_source_valid & sdmem2block_converter_source_ready)) begin + if (sdmem2block_converter_last) begin + sdmem2block_converter_mux <= 1'd0; + end else begin + sdmem2block_converter_mux <= (sdmem2block_converter_mux + 1'd1); + end + end + if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin + sdmem2block_fifo_produce <= (sdmem2block_fifo_produce + 1'd1); + end + if (sdmem2block_fifo_do_read) begin + sdmem2block_fifo_consume <= (sdmem2block_fifo_consume + 1'd1); + end + if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin + if ((~sdmem2block_fifo_do_read)) begin + sdmem2block_fifo_level <= (sdmem2block_fifo_level + 1'd1); + end + end else begin + if (sdmem2block_fifo_do_read) begin + sdmem2block_fifo_level <= (sdmem2block_fifo_level - 1'd1); + end + end + if (card_detect_clear) begin + card_detect_pending <= 1'd0; + end + if (card_detect_trigger) begin + card_detect_pending <= 1'd1; + end + if (block2mem_dma_clear) begin + block2mem_dma_pending <= 1'd0; + end + if (block2mem_dma_trigger) begin + block2mem_dma_pending <= 1'd1; + end + if (mem2block_dma_clear) begin + mem2block_dma_pending <= 1'd0; + end + if (mem2block_dma_trigger) begin + mem2block_dma_pending <= 1'd1; + end + litesdcardcore_state <= litesdcardcore_next_state; + case (litesdcardcore_grant) + 1'd0: begin + if ((~litesdcardcore_request[0])) begin + if (litesdcardcore_request[1]) begin + litesdcardcore_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~litesdcardcore_request[1])) begin + if (litesdcardcore_request[0]) begin + litesdcardcore_grant <= 1'd0; + end + end + end + endcase + litesdcardcore_slave_sel_r <= litesdcardcore_slave_sel; + if (litesdcardcore_wait) begin + if ((~litesdcardcore_done)) begin + litesdcardcore_count <= (litesdcardcore_count - 1'd1); + end + end else begin + litesdcardcore_count <= 20'd1000000; + end + litesdcardcore_interface0_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank0_sel) begin + case (litesdcardcore_interface0_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface0_bank_bus_dat_r <= litesdcardcore_csrbank0_reset0_w; + end + 1'd1: begin + litesdcardcore_interface0_bank_bus_dat_r <= litesdcardcore_csrbank0_scratch0_w; + end + 2'd2: begin + litesdcardcore_interface0_bank_bus_dat_r <= litesdcardcore_csrbank0_bus_errors_w; + end + endcase + end + if (litesdcardcore_csrbank0_reset0_re) begin + reset_storage <= litesdcardcore_csrbank0_reset0_r; + end + reset_re <= litesdcardcore_csrbank0_reset0_re; + if (litesdcardcore_csrbank0_scratch0_re) begin + scratch_storage[31:0] <= litesdcardcore_csrbank0_scratch0_r; + end + scratch_re <= litesdcardcore_csrbank0_scratch0_re; + bus_errors_re <= litesdcardcore_csrbank0_bus_errors_re; + litesdcardcore_interface1_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank1_sel) begin + case (litesdcardcore_interface1_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_base1_w; + end + 1'd1: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_base0_w; + end + 2'd2: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_length0_w; + end + 2'd3: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_enable0_w; + end + 3'd4: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_done_w; + end + 3'd5: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_loop0_w; + end + 3'd6: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_offset_w; + end + endcase + end + if (litesdcardcore_csrbank1_dma_base1_re) begin + sdblock2mem_wishbonedmawriter_base_storage[63:32] <= litesdcardcore_csrbank1_dma_base1_r; + end + if (litesdcardcore_csrbank1_dma_base0_re) begin + sdblock2mem_wishbonedmawriter_base_storage[31:0] <= litesdcardcore_csrbank1_dma_base0_r; + end + sdblock2mem_wishbonedmawriter_base_re <= litesdcardcore_csrbank1_dma_base0_re; + if (litesdcardcore_csrbank1_dma_length0_re) begin + sdblock2mem_wishbonedmawriter_length_storage[31:0] <= litesdcardcore_csrbank1_dma_length0_r; + end + sdblock2mem_wishbonedmawriter_length_re <= litesdcardcore_csrbank1_dma_length0_re; + if (litesdcardcore_csrbank1_dma_enable0_re) begin + sdblock2mem_wishbonedmawriter_enable_storage <= litesdcardcore_csrbank1_dma_enable0_r; + end + sdblock2mem_wishbonedmawriter_enable_re <= litesdcardcore_csrbank1_dma_enable0_re; + sdblock2mem_wishbonedmawriter_done_re <= litesdcardcore_csrbank1_dma_done_re; + if (litesdcardcore_csrbank1_dma_loop0_re) begin + sdblock2mem_wishbonedmawriter_loop_storage <= litesdcardcore_csrbank1_dma_loop0_r; + end + sdblock2mem_wishbonedmawriter_loop_re <= litesdcardcore_csrbank1_dma_loop0_re; + sdblock2mem_wishbonedmawriter_offset_re <= litesdcardcore_csrbank1_dma_offset_re; + litesdcardcore_interface2_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank2_sel) begin + case (litesdcardcore_interface2_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_argument0_w; + end + 1'd1: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_command0_w; + end + 2'd2: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_send0_w; + end + 2'd3: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response3_w; + end + 3'd4: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response2_w; + end + 3'd5: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response1_w; + end + 3'd6: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response0_w; + end + 3'd7: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_event_w; + end + 4'd8: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_data_event_w; + end + 4'd9: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_block_length0_w; + end + 4'd10: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_block_count0_w; + end + endcase + end + if (litesdcardcore_csrbank2_cmd_argument0_re) begin + sdcore_cmd_argument_storage[31:0] <= litesdcardcore_csrbank2_cmd_argument0_r; + end + sdcore_cmd_argument_re <= litesdcardcore_csrbank2_cmd_argument0_re; + if (litesdcardcore_csrbank2_cmd_command0_re) begin + sdcore_cmd_command_storage[13:0] <= litesdcardcore_csrbank2_cmd_command0_r; + end + sdcore_cmd_command_re <= litesdcardcore_csrbank2_cmd_command0_re; + if (litesdcardcore_csrbank2_cmd_send0_re) begin + sdcore_cmd_send_storage <= litesdcardcore_csrbank2_cmd_send0_r; + end + sdcore_cmd_send_re <= litesdcardcore_csrbank2_cmd_send0_re; + sdcore_cmd_response_re <= litesdcardcore_csrbank2_cmd_response0_re; + sdcore_cmd_event_re <= litesdcardcore_csrbank2_cmd_event_re; + sdcore_data_event_re <= litesdcardcore_csrbank2_data_event_re; + if (litesdcardcore_csrbank2_block_length0_re) begin + sdcore_block_length_storage[9:0] <= litesdcardcore_csrbank2_block_length0_r; + end + sdcore_block_length_re <= litesdcardcore_csrbank2_block_length0_re; + if (litesdcardcore_csrbank2_block_count0_re) begin + sdcore_block_count_storage[31:0] <= litesdcardcore_csrbank2_block_count0_r; + end + sdcore_block_count_re <= litesdcardcore_csrbank2_block_count0_re; + litesdcardcore_interface3_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank3_sel) begin + case (litesdcardcore_interface3_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface3_bank_bus_dat_r <= litesdcardcore_csrbank3_status_w; + end + 1'd1: begin + litesdcardcore_interface3_bank_bus_dat_r <= litesdcardcore_csrbank3_pending_w; + end + 2'd2: begin + litesdcardcore_interface3_bank_bus_dat_r <= litesdcardcore_csrbank3_enable0_w; + end + endcase + end + eventmanager_status_re <= litesdcardcore_csrbank3_status_re; + if (litesdcardcore_csrbank3_pending_re) begin + eventmanager_pending_r[3:0] <= litesdcardcore_csrbank3_pending_r; + end + eventmanager_pending_re <= litesdcardcore_csrbank3_pending_re; + if (litesdcardcore_csrbank3_enable0_re) begin + eventmanager_enable_storage[3:0] <= litesdcardcore_csrbank3_enable0_r; + end + eventmanager_enable_re <= litesdcardcore_csrbank3_enable0_re; + litesdcardcore_interface4_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank4_sel) begin + case (litesdcardcore_interface4_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_base1_w; + end + 1'd1: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_base0_w; + end + 2'd2: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_length0_w; + end + 2'd3: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_enable0_w; + end + 3'd4: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_done_w; + end + 3'd5: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_loop0_w; + end + 3'd6: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_offset_w; + end + endcase + end + if (litesdcardcore_csrbank4_dma_base1_re) begin + sdmem2block_dma_base_storage[63:32] <= litesdcardcore_csrbank4_dma_base1_r; + end + if (litesdcardcore_csrbank4_dma_base0_re) begin + sdmem2block_dma_base_storage[31:0] <= litesdcardcore_csrbank4_dma_base0_r; + end + sdmem2block_dma_base_re <= litesdcardcore_csrbank4_dma_base0_re; + if (litesdcardcore_csrbank4_dma_length0_re) begin + sdmem2block_dma_length_storage[31:0] <= litesdcardcore_csrbank4_dma_length0_r; + end + sdmem2block_dma_length_re <= litesdcardcore_csrbank4_dma_length0_re; + if (litesdcardcore_csrbank4_dma_enable0_re) begin + sdmem2block_dma_enable_storage <= litesdcardcore_csrbank4_dma_enable0_r; + end + sdmem2block_dma_enable_re <= litesdcardcore_csrbank4_dma_enable0_re; + sdmem2block_dma_done_re <= litesdcardcore_csrbank4_dma_done_re; + if (litesdcardcore_csrbank4_dma_loop0_re) begin + sdmem2block_dma_loop_storage <= litesdcardcore_csrbank4_dma_loop0_r; + end + sdmem2block_dma_loop_re <= litesdcardcore_csrbank4_dma_loop0_re; + sdmem2block_dma_offset_re <= litesdcardcore_csrbank4_dma_offset_re; + litesdcardcore_interface5_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank5_sel) begin + case (litesdcardcore_interface5_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface5_bank_bus_dat_r <= litesdcardcore_csrbank5_card_detect_w; + end + 1'd1: begin + litesdcardcore_interface5_bank_bus_dat_r <= litesdcardcore_csrbank5_clocker_divider0_w; + end + 2'd2: begin + litesdcardcore_interface5_bank_bus_dat_r <= init_initialize_w; + end + 2'd3: begin + litesdcardcore_interface5_bank_bus_dat_r <= litesdcardcore_csrbank5_dataw_status_w; + end + endcase + end + card_detect_re <= litesdcardcore_csrbank5_card_detect_re; + if (litesdcardcore_csrbank5_clocker_divider0_re) begin + clocker_storage[8:0] <= litesdcardcore_csrbank5_clocker_divider0_r; + end + clocker_re <= litesdcardcore_csrbank5_clocker_divider0_re; + dataw_re <= litesdcardcore_csrbank5_dataw_status_re; + if (sys_rst) begin + reset_storage <= 1'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + card_detect_re <= 1'd0; + clocker_storage <= 9'd256; + clocker_re <= 1'd0; + clocker_clks <= 9'd0; + clocker_clk_d <= 1'd0; + clocker_ce_delayed <= 1'd0; + init_count <= 8'd0; + cmdw_count <= 8'd0; + cmdr_timeout <= 32'd100000000; + cmdr_count <= 8'd0; + cmdr_busy <= 1'd0; + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_demux <= 3'd0; + cmdr_cmdr_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_source_valid <= 1'd0; + cmdr_cmdr_buf_source_payload_data <= 8'd0; + cmdr_cmdr_reset <= 1'd0; + dataw_re <= 1'd0; + dataw_count <= 8'd0; + dataw_accepted1 <= 1'd0; + dataw_crc_error1 <= 1'd0; + dataw_write_error1 <= 1'd0; + dataw_crc_run <= 1'd0; + dataw_crc_converter_source_payload_data <= 8'd0; + dataw_crc_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_demux <= 3'd0; + dataw_crc_converter_strobe_all <= 1'd0; + dataw_crc_buf_source_valid <= 1'd0; + dataw_crc_buf_source_payload_data <= 8'd0; + datar_timeout <= 32'd100000000; + datar_count <= 10'd0; + datar_datar_run <= 1'd0; + datar_datar_converter_source_payload_data <= 8'd0; + datar_datar_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_demux <= 1'd0; + datar_datar_converter_strobe_all <= 1'd0; + datar_datar_buf_source_valid <= 1'd0; + datar_datar_buf_source_payload_data <= 8'd0; + datar_datar_reset <= 1'd0; + sdpads_data_i_ce <= 1'd0; + clocker_clk_delay <= 2'd0; + card_detect_irq <= 1'd0; + card_detect_d <= 1'd0; + sdcore_cmd_argument_storage <= 32'd0; + sdcore_cmd_argument_re <= 1'd0; + sdcore_cmd_command_storage <= 14'd0; + sdcore_cmd_command_re <= 1'd0; + sdcore_cmd_send_storage <= 1'd0; + sdcore_cmd_send_re <= 1'd0; + sdcore_cmd_response_status <= 128'd0; + sdcore_cmd_response_re <= 1'd0; + sdcore_cmd_event_re <= 1'd0; + sdcore_data_event_re <= 1'd0; + sdcore_block_length_storage <= 10'd0; + sdcore_block_length_re <= 1'd0; + sdcore_block_count_storage <= 32'd0; + sdcore_block_count_re <= 1'd0; + sdcore_crc7_inserter_reg0 <= 7'd0; + sdcore_crc16_inserter_count <= 3'd0; + sdcore_crc16_inserter_crc0_reg0 <= 16'd0; + sdcore_crc16_inserter_crc1_reg0 <= 16'd0; + sdcore_crc16_inserter_crc2_reg0 <= 16'd0; + sdcore_crc16_inserter_crc3_reg0 <= 16'd0; + sdcore_fifo_level <= 4'd0; + sdcore_fifo_produce <= 3'd0; + sdcore_fifo_consume <= 3'd0; + sdcore_cmd_count <= 3'd0; + sdcore_cmd_done <= 1'd0; + sdcore_cmd_error <= 1'd0; + sdcore_cmd_timeout <= 1'd0; + sdcore_data_count <= 32'd0; + sdcore_data_done <= 1'd0; + sdcore_data_error <= 1'd0; + sdcore_data_timeout <= 1'd0; + sdblock2mem_irq <= 1'd0; + sdblock2mem_fifo_level <= 10'd0; + sdblock2mem_fifo_produce <= 9'd0; + sdblock2mem_fifo_consume <= 9'd0; + sdblock2mem_converter_source_payload_data <= 32'd0; + sdblock2mem_converter_source_payload_valid_token_count <= 3'd0; + sdblock2mem_converter_demux <= 2'd0; + sdblock2mem_converter_strobe_all <= 1'd0; + sdblock2mem_wishbonedmawriter_base_storage <= 64'd0; + sdblock2mem_wishbonedmawriter_base_re <= 1'd0; + sdblock2mem_wishbonedmawriter_length_storage <= 32'd0; + sdblock2mem_wishbonedmawriter_length_re <= 1'd0; + sdblock2mem_wishbonedmawriter_enable_storage <= 1'd0; + sdblock2mem_wishbonedmawriter_enable_re <= 1'd0; + sdblock2mem_wishbonedmawriter_done_re <= 1'd0; + sdblock2mem_wishbonedmawriter_loop_storage <= 1'd0; + sdblock2mem_wishbonedmawriter_loop_re <= 1'd0; + sdblock2mem_wishbonedmawriter_offset_re <= 1'd0; + sdblock2mem_wishbonedmawriter_offset <= 32'd0; + sdblock2mem_connect <= 1'd0; + sdblock2mem_done_d <= 1'd0; + sdmem2block_irq <= 1'd0; + sdmem2block_dma_data <= 32'd0; + sdmem2block_dma_base_storage <= 64'd0; + sdmem2block_dma_base_re <= 1'd0; + sdmem2block_dma_length_storage <= 32'd0; + sdmem2block_dma_length_re <= 1'd0; + sdmem2block_dma_enable_storage <= 1'd0; + sdmem2block_dma_enable_re <= 1'd0; + sdmem2block_dma_done_re <= 1'd0; + sdmem2block_dma_loop_storage <= 1'd0; + sdmem2block_dma_loop_re <= 1'd0; + sdmem2block_dma_offset_re <= 1'd0; + sdmem2block_dma_offset <= 32'd0; + sdmem2block_converter_mux <= 2'd0; + sdmem2block_fifo_level <= 10'd0; + sdmem2block_fifo_produce <= 9'd0; + sdmem2block_fifo_consume <= 9'd0; + sdmem2block_count <= 9'd0; + sdmem2block_done_d <= 1'd0; + card_detect_pending <= 1'd0; + block2mem_dma_pending <= 1'd0; + mem2block_dma_pending <= 1'd0; + eventmanager_status_re <= 1'd0; + eventmanager_pending_re <= 1'd0; + eventmanager_pending_r <= 4'd0; + eventmanager_enable_storage <= 4'd0; + eventmanager_enable_re <= 1'd0; + subfragments_sdphyinit_state <= 1'd0; + subfragments_sdphycmdw_state <= 2'd0; + subfragments_sdphycmdr_state <= 3'd0; + subfragments_sdphydataw_state <= 3'd0; + subfragments_sdphydatar_state <= 3'd0; + subfragments_sdcore_crc16inserter_state <= 1'd0; + subfragments_sdcore_fsm_state <= 3'd0; + subfragments_state <= 2'd0; + subfragments_sdmem2blockdma_fsm_state <= 1'd0; + subfragments_sdmem2blockdma_resetinserter_state <= 2'd0; + litesdcardcore_grant <= 1'd0; + litesdcardcore_slave_sel_r <= 1'd0; + litesdcardcore_count <= 20'd1000000; + litesdcardcore_state <= 1'd0; + end +end + +reg [9:0] storage[0:7]; +reg [9:0] memdat; +always @(posedge sys_clk) begin + if (sdcore_fifo_wrport_we) + storage[sdcore_fifo_wrport_adr] <= sdcore_fifo_wrport_dat_w; + memdat <= storage[sdcore_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdcore_fifo_wrport_dat_r = memdat; +assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr]; + +reg [9:0] storage_1[0:511]; +reg [9:0] memdat_1; +always @(posedge sys_clk) begin + if (sdblock2mem_fifo_wrport_we) + storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w; + memdat_1 <= storage_1[sdblock2mem_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdblock2mem_fifo_wrport_dat_r = memdat_1; +assign sdblock2mem_fifo_rdport_dat_r = storage_1[sdblock2mem_fifo_rdport_adr]; + +reg [9:0] storage_2[0:511]; +reg [9:0] memdat_2; +always @(posedge sys_clk) begin + if (sdmem2block_fifo_wrport_we) + storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w; + memdat_2 <= storage_2[sdmem2block_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign sdmem2block_fifo_wrport_dat_r = memdat_2; +assign sdmem2block_fifo_rdport_dat_r = storage_2[sdmem2block_fifo_rdport_adr]; + +IOBUF IOBUF( + .I(xilinxsdrtristateimpl0__o), + .T(xilinxsdrtristateimpl0_oe_n), + .IO(sdcard_cmd), + .O(xilinxsdrtristateimpl0__i) +); + +IOBUF IOBUF_1( + .I(xilinxsdrtristateimpl1__o), + .T(xilinxsdrtristateimpl1_oe_n), + .IO(sdcard_data[0]), + .O(xilinxsdrtristateimpl1__i) +); + +IOBUF IOBUF_2( + .I(xilinxsdrtristateimpl2__o), + .T(xilinxsdrtristateimpl2_oe_n), + .IO(sdcard_data[1]), + .O(xilinxsdrtristateimpl2__i) +); + +IOBUF IOBUF_3( + .I(xilinxsdrtristateimpl3__o), + .T(xilinxsdrtristateimpl3_oe_n), + .IO(sdcard_data[2]), + .O(xilinxsdrtristateimpl3__i) +); + +IOBUF IOBUF_4( + .I(xilinxsdrtristateimpl4__o), + .T(xilinxsdrtristateimpl4_oe_n), + .IO(sdcard_data[3]), + .O(xilinxsdrtristateimpl4__i) +); + +endmodule diff --git a/litesdcard/litesdcard.core b/litesdcard/litesdcard.core new file mode 100644 index 0000000..9abda3e --- /dev/null +++ b/litesdcard/litesdcard.core @@ -0,0 +1,15 @@ +CAPI=2: + +name : :microwatt:litesdcard:0 + +generators: + litesdcard_gen: + interpreter: python3 + command: fusesoc-add-files.py + description: Generate a litesdcard SD-card controller + usage: | + litesdcard_gen adds the pre-generated LiteX LiteSDCard SD-card controller + based on the board type. + + Parameters: + board: The board type (arty) diff --git a/microwatt.core b/microwatt.core index 79af3c1..4911809 100644 --- a/microwatt.core +++ b/microwatt.core @@ -116,6 +116,9 @@ filesets: liteeth: depend : [":microwatt:liteeth"] + litesdcard: + depend : [":microwatt:litesdcard"] + uart16550: depend : ["::uart16550"] @@ -243,7 +246,7 @@ targets: arty_a7-35-nodram: default_tool: vivado - filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific] + filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard] parameters : - memory_size - ram_init_file @@ -256,18 +259,20 @@ targets: - has_uart1 - has_fpu=false - has_btc=false + - use_litesdcard tools: vivado: {part : xc7a35ticsg324-1L} toplevel : toplevel arty_a7-35: default_tool: vivado - filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific] + filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard] parameters : - memory_size - ram_init_file - use_litedram=true - use_liteeth=true + - use_litesdcard - disable_flatten_core - no_bram - spi_flash_offset=3145728 @@ -276,14 +281,14 @@ targets: - has_uart1 - has_fpu=false - has_btc=false - generate: [litedram_arty, liteeth_arty] + generate: [litedram_arty, liteeth_arty, litesdcard_arty] tools: vivado: {part : xc7a35ticsg324-1L} toplevel : toplevel arty_a7-100-nodram: default_tool: vivado - filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific] + filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard] parameters : - memory_size - ram_init_file @@ -296,18 +301,20 @@ targets: - has_uart1 - has_fpu - has_btc + - use_litesdcard tools: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel arty_a7-100: default_tool: vivado - filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific] + filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard] parameters: - memory_size - ram_init_file - use_litedram=true - use_liteeth=true + - use_litesdcard - disable_flatten_core - no_bram - spi_flash_offset=4194304 @@ -316,7 +323,7 @@ targets: - has_uart1 - has_fpu - has_btc - generate: [litedram_arty, liteeth_arty] + generate: [litedram_arty, liteeth_arty, litesdcard_arty] tools: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel @@ -354,6 +361,10 @@ generate: generator: liteeth_gen parameters: {board : arty} + litesdcard_arty: + generator: litesdcard_gen + parameters: {board : arty} + litedram_nexys_video: generator: litedram_gen parameters: {board : nexys-video} @@ -425,6 +436,12 @@ parameters: paramtype : generic default : false + use_litesdcard: + datatype : bool + description : Use LiteSDCard + paramtype : generic + default : false + uart_is_16550: datatype : bool description : Use 16550-compatible UART from OpenCores diff --git a/soc.vhdl b/soc.vhdl index 38bd5df..cee4753 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -32,6 +32,7 @@ use work.wishbone_types.all; -- 0xc8000000: LiteDRAM control (CSRs) -- 0xc8020000: LiteEth CSRs (*) -- 0xc8030000: LiteEth MMIO (*) +-- 0xc8040000: LiteSDCard CSRs -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs -- are actually decoded as a single wishbone which LiteEth will @@ -45,6 +46,8 @@ use work.wishbone_types.all; -- -- 0 : UART0 -- 1 : Ethernet +-- 2 : UART1 +-- 3 : SD card entity soc is generic ( @@ -74,7 +77,8 @@ entity soc is DCACHE_NUM_LINES : natural := 64; DCACHE_NUM_WAYS : natural := 2; DCACHE_TLB_SET_SIZE : natural := 64; - DCACHE_TLB_NUM_WAYS : natural := 2 + DCACHE_TLB_NUM_WAYS : natural := 2; + HAS_SD_CARD : boolean := false ); port( rst : in std_ulogic; @@ -90,9 +94,15 @@ entity soc is wb_ext_is_dram_csr : out std_ulogic; wb_ext_is_dram_init : out std_ulogic; wb_ext_is_eth : out std_ulogic; + wb_ext_is_sdcard : out std_ulogic; + + -- external DMA wishbone with 32-bit data/address + wishbone_dma_in : out wb_io_slave_out := wb_io_slave_out_init; + wishbone_dma_out : in wb_io_master_out := wb_io_master_out_init; -- External interrupts ext_irq_eth : in std_ulogic := '0'; + ext_irq_sdcard : in std_ulogic := '0'; -- UART0 signals: uart0_txd : out std_ulogic; @@ -121,12 +131,12 @@ architecture behaviour of soc is signal wishbone_dcore_out : wishbone_master_out; signal wishbone_icore_in : wishbone_slave_out; signal wishbone_icore_out : wishbone_master_out; - signal wishbone_debug_in : wishbone_slave_out; + signal wishbone_debug_in : wishbone_slave_out; signal wishbone_debug_out : wishbone_master_out; -- Arbiter array (ghdl doesnt' support assigning the array -- elements in the entity instantiation) - constant NUM_WB_MASTERS : positive := 3; + constant NUM_WB_MASTERS : positive := 4; signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1); signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1); @@ -219,6 +229,37 @@ architecture behaviour of soc is SLAVE_IO_NONE); signal slave_io_dbg : slave_io_type; + function wishbone_widen_data(wb : wb_io_master_out) return wishbone_master_out is + variable wwb : wishbone_master_out; + begin + wwb.adr := wb.adr & "00"; -- XXX note wrong adr usage in wishbone_master_out + wwb.dat := wb.dat & wb.dat; + wwb.sel := x"00"; + if wwb.adr(2) = '0' then + wwb.sel(3 downto 0) := wb.sel; + else + wwb.sel(7 downto 4) := wb.sel; + end if; + wwb.cyc := wb.cyc; + wwb.stb := wb.stb; + wwb.we := wb.we; + return wwb; + end; + + function wishbone_narrow_data(wwbs : wishbone_slave_out; adr : std_ulogic_vector(29 downto 0)) + return wb_io_slave_out is + variable wbs : wb_io_slave_out; + begin + wbs.ack := wwbs.ack; + wbs.stall := wwbs.stall; + if adr(0) = '0' then + wbs.dat := wwbs.dat(31 downto 0); + else + wbs.dat := wwbs.dat(63 downto 32); + end if; + return wbs; + end; + -- This is the component exported by the 16550 compatible -- UART from FuseSoC. -- @@ -243,6 +284,7 @@ architecture behaviour of soc is dcd_pad_i : in std_ulogic ); end component; + begin resets: process(system_clk) @@ -298,10 +340,12 @@ begin -- Wishbone bus master arbiter & mux wb_masters_out <= (0 => wishbone_dcore_out, 1 => wishbone_icore_out, - 2 => wishbone_debug_out); + 2 => wishbone_widen_data(wishbone_dma_out), + 3 => wishbone_debug_out); wishbone_dcore_in <= wb_masters_in(0); wishbone_icore_in <= wb_masters_in(1); - wishbone_debug_in <= wb_masters_in(2); + wishbone_dma_in <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr); + wishbone_debug_in <= wb_masters_in(3); wishbone_arbiter_0: entity work.wishbone_arbiter generic map( NUM_MASTERS => NUM_WB_MASTERS @@ -589,6 +633,7 @@ begin wb_ext_is_dram_csr <= '0'; wb_ext_is_dram_init <= '0'; wb_ext_is_eth <= '0'; + wb_ext_is_sdcard <= '0'; -- Default response, ack & return all 1's wb_sio_in.dat <= (others => '1'); @@ -616,6 +661,9 @@ begin elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then wb_ext_is_eth <= '1'; ext_valid := true; + elsif wb_sio_out.adr(23 downto 16) = x"04" and HAS_SD_CARD then + wb_ext_is_sdcard <= '1'; + ext_valid := true; end if; if ext_valid then wb_ext_io_in.cyc <= wb_sio_out.cyc; @@ -665,6 +713,7 @@ begin HAS_SPI_FLASH => HAS_SPI_FLASH, SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, HAS_LITEETH => HAS_LITEETH, + HAS_SD_CARD => HAS_SD_CARD, UART0_IS_16550 => UART0_IS_16550, HAS_UART1 => HAS_UART1 ) @@ -848,6 +897,7 @@ begin int_level_in(0) <= uart0_irq; int_level_in(1) <= ext_irq_eth; int_level_in(2) <= uart1_irq; + int_level_in(3) <= ext_irq_sdcard; end process; -- BRAM Memory slave diff --git a/syscon.vhdl b/syscon.vhdl index 31d8d0a..2f8bd47 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -18,6 +18,7 @@ entity syscon is HAS_SPI_FLASH : boolean; SPI_FLASH_OFFSET : integer; HAS_LITEETH : boolean; + HAS_SD_CARD : boolean; UART0_IS_16550 : boolean; HAS_UART1 : boolean ); @@ -65,6 +66,7 @@ architecture behaviour of syscon is constant SYS_REG_INFO_HAS_LSYS : integer := 5; -- Has 6-bit address syscon constant SYS_REG_INFO_HAS_URT1 : integer := 6; -- Has second UART constant SYS_REG_INFO_HAS_ARTB : integer := 7; -- Has architected TB frequency + constant SYS_REG_INFO_HAS_SDCARD : integer := 8; -- Has LiteSDCard SD-card interface -- BRAMINFO contains the BRAM size in the bottom 52 bits -- DRAMINFO contains the DRAM size if any in the bottom 52 bits @@ -107,6 +109,7 @@ architecture behaviour of syscon is signal info_has_uart : std_ulogic; signal info_has_spif : std_ulogic; signal info_has_leth : std_ulogic; + signal info_has_lsdc : std_ulogic; signal info_has_urt1 : std_ulogic; signal info_clk : std_ulogic_vector(39 downto 0); signal info_fl_off : std_ulogic_vector(31 downto 0); @@ -128,15 +131,17 @@ begin info_has_bram <= '1' when BRAM_SIZE /= 0 else '0'; info_has_spif <= '1' when HAS_SPI_FLASH else '0'; info_has_leth <= '1' when HAS_LITEETH else '0'; + info_has_lsdc <= '1' when HAS_SD_CARD else '0'; info_has_urt1 <= '1' when HAS_UART1 else '0'; info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40)); - reg_info <= (SYS_REG_INFO_HAS_UART => info_has_uart, - SYS_REG_INFO_HAS_DRAM => info_has_dram, - SYS_REG_INFO_HAS_BRAM => info_has_bram, - SYS_REG_INFO_HAS_SPIF => info_has_spif, - SYS_REG_INFO_HAS_LETH => info_has_leth, - SYS_REG_INFO_HAS_LSYS => '1', - SYS_REG_INFO_HAS_URT1 => info_has_urt1, + reg_info <= (SYS_REG_INFO_HAS_UART => info_has_uart, + SYS_REG_INFO_HAS_DRAM => info_has_dram, + SYS_REG_INFO_HAS_BRAM => info_has_bram, + SYS_REG_INFO_HAS_SPIF => info_has_spif, + SYS_REG_INFO_HAS_LETH => info_has_leth, + SYS_REG_INFO_HAS_SDCARD => info_has_lsdc, + SYS_REG_INFO_HAS_LSYS => '1', + SYS_REG_INFO_HAS_URT1 => info_has_urt1, others => '0'); reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl index 210ac43..2df1eb3 100644 --- a/wishbone_types.vhdl +++ b/wishbone_types.vhdl @@ -44,6 +44,8 @@ package wishbone_types is stb : std_ulogic; we : std_ulogic; end record; + constant wb_io_master_out_init : wb_io_master_out := (adr => (others => '0'), dat => (others => '0'), + sel => "0000", cyc => '0', stb => '0', we => '0'); type wb_io_slave_out is record dat : std_ulogic_vector(31 downto 0);