diff --git a/Makefile b/Makefile
index b584895..097bf3e 100644
--- a/Makefile
+++ b/Makefile
@@ -52,7 +52,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
 
 soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
 	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
-	spi_rxtx.vhdl spi_flash_ctrl.vhdl
+	spi_rxtx.vhdl spi_flash_ctrl.vhdl git.vhdl
 
 uart_files = $(wildcard uart16550/*.v)
 
diff --git a/git.vhdl b/git.vhdl
new file mode 100644
index 0000000..f63f0a7
--- /dev/null
+++ b/git.vhdl
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+
+package git is
+    constant GIT_HASH : std_ulogic_vector(55 downto 0) := x"1234567890abcd";
+    constant GIT_DIRTY : std_ulogic := '0';
+end git;
diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h
index a224d74..7f20ce7 100644
--- a/include/microwatt_soc.h
+++ b/include/microwatt_soc.h
@@ -56,6 +56,8 @@
 #define SYS_REG_UART0_INFO		0x40
 #define SYS_REG_UART1_INFO		0x48
 #define   SYS_REG_UART_IS_16550			(1ull << 32)
+#define SYS_REG_GIT_INFO		0x50
+#define   SYS_REG_GIT_IS_DIRTY			(1ull << 63)
 
 
 /*
diff --git a/syscon.vhdl b/syscon.vhdl
index 31d8d0a..fa856a4 100644
--- a/syscon.vhdl
+++ b/syscon.vhdl
@@ -4,6 +4,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
+use work.git.all;
 use work.wishbone_types.all;
 
 entity syscon is
@@ -52,6 +53,7 @@ architecture behaviour of syscon is
     constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000111";
     constant SYS_REG_UART0_INFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001000";
     constant SYS_REG_UART1_INFO   : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001001";
+    constant SYS_REG_GIT_INFO     : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001010";
 
     -- Muxed reg read signal
     signal reg_out	: std_ulogic_vector(63 downto 0);
@@ -89,6 +91,12 @@ architecture behaviour of syscon is
     --      32  : UART is 16550 (otherwise pp)
     --
 
+    -- GIT info register bits
+    --
+    --  0 ..55  : git hash (56 bits)
+    --      63  : dirty flag
+    --
+
     -- Ctrl register
     signal reg_ctrl	: std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
     signal reg_ctrl_out	: std_ulogic_vector(63 downto 0);
@@ -102,6 +110,7 @@ architecture behaviour of syscon is
     signal reg_spiinfo   : std_ulogic_vector(63 downto 0);
     signal reg_uart0info : std_ulogic_vector(63 downto 0);
     signal reg_uart1info : std_ulogic_vector(63 downto 0);
+    signal reg_gitinfo   : std_ulogic_vector(63 downto 0);
     signal info_has_dram : std_ulogic;
     signal info_has_bram : std_ulogic;
     signal info_has_uart : std_ulogic;
@@ -164,6 +173,11 @@ begin
                       31 downto 0  => uinfo_freq,
                       others       => '0');
 
+    -- GIT info register composition
+    reg_gitinfo <= (63          => GIT_DIRTY,
+                    55 downto 0 => GIT_HASH,
+                    others      => '0');
+
     -- Wishbone response
     wb_rsp.ack <= wishbone_in.cyc and wishbone_in.stb;
     with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select reg_out <=
@@ -177,6 +191,7 @@ begin
 	reg_spiinfo	when SYS_REG_SPIFLASHINFO,
         reg_uart0info   when SYS_REG_UART0_INFO,
         reg_uart1info   when SYS_REG_UART1_INFO,
+        reg_gitinfo     when SYS_REG_GIT_INFO,
 	(others => '0') when others;
     wb_rsp.dat   <= reg_out(63 downto 32) when wishbone_in.adr(2) = '1' else
                   reg_out(31 downto 0);