diff --git a/common.vhdl b/common.vhdl index 0207fe1..b92b87a 100644 --- a/common.vhdl +++ b/common.vhdl @@ -189,7 +189,6 @@ package common is constant SPRSEL_LOGD : spr_selector := 4x"5"; constant SPRSEL_CFAR : spr_selector := 4x"6"; constant SPRSEL_FSCR : spr_selector := 4x"7"; - constant SPRSEL_HFSCR : spr_selector := 4x"8"; constant SPRSEL_HEIR : spr_selector := 4x"9"; constant SPRSEL_CTRL : spr_selector := 4x"a"; constant SPRSEL_DSCR : spr_selector := 4x"b"; @@ -198,17 +197,11 @@ package common is constant SPRSEL_DEXCR : spr_selector := 4x"e"; constant SPRSEL_XER : spr_selector := 4x"f"; - -- FSCR and HFSCR bit numbers + -- FSCR bit numbers constant FSCR_PREFIX : integer := 63 - 50; constant FSCR_SCV : integer := 63 - 51; constant FSCR_TAR : integer := 63 - 55; constant FSCR_DSCR : integer := 63 - 61; - constant HFSCR_PREFIX : integer := 63 - 50; - constant HFSCR_MSG : integer := 63 - 53; - constant HFSCR_TAR : integer := 63 - 55; - constant HFSCR_PMUSPR : integer := 63 - 60; - constant HFSCR_DSCR : integer := 63 - 61; - constant HFSCR_FP : integer := 63 - 63; -- FPSCR bit numbers constant FPSCR_FX : integer := 63 - 32; @@ -301,11 +294,6 @@ package common is fscr_scv: std_ulogic; fscr_tar: std_ulogic; fscr_dscr: std_ulogic; - hfscr_ic: std_ulogic_vector(3 downto 0); - hfscr_pref: std_ulogic; - hfscr_tar: std_ulogic; - hfscr_dscr: std_ulogic; - hfscr_fp: std_ulogic; heir: std_ulogic_vector(63 downto 0); dscr: std_ulogic_vector(24 downto 0); ciabr: std_ulogic_vector(63 downto 0); @@ -317,7 +305,6 @@ package common is constant ctrl_t_init : ctrl_t := (wait_state => '0', run => '1', xer_low => 18x"0", fscr_ic => x"0", fscr_pref => '1', fscr_scv => '1', fscr_tar => '1', fscr_dscr => '1', - hfscr_ic => x"0", hfscr_pref => '1', hfscr_tar => '1', hfscr_dscr => '1', hfscr_fp => '1', dscr => (others => '0'), dexcr_pnh => aspect_bits_init, dexcr_pro => aspect_bits_init, hdexcr_hyp => aspect_bits_init, hdexcr_enf => aspect_bits_init, diff --git a/core_debug.vhdl b/core_debug.vhdl index 67b41fb..e839832 100644 --- a/core_debug.vhdl +++ b/core_debug.vhdl @@ -327,9 +327,6 @@ begin when 5x"0e" => isram := '0'; sel := SPRSEL_FSCR; - when 5x"0f" => - isram := '0'; - sel := SPRSEL_HFSCR; when 5x"10" => isram := '0'; sel := SPRSEL_HEIR; diff --git a/decode1.vhdl b/decode1.vhdl index 2fb1ad4..c3f215d 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -490,8 +490,6 @@ architecture behaviour of decode1 is i.sel := SPRSEL_XER; when SPR_FSCR => i.sel := SPRSEL_FSCR; - when SPR_HFSCR => - i.sel := SPRSEL_HFSCR; when SPR_HEIR => i.sel := SPRSEL_HEIR; when SPR_CTRL => diff --git a/execute1.vhdl b/execute1.vhdl index ee38863..cea2f37 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -92,8 +92,6 @@ architecture behaviour of execute1 is mult_32s : std_ulogic; write_fscr : std_ulogic; write_ic : std_ulogic; - write_hfscr : std_ulogic; - write_hic : std_ulogic; write_heir : std_ulogic; set_heir : std_ulogic; write_ctrl : std_ulogic; @@ -410,18 +408,6 @@ architecture behaviour of execute1 is return ret; end; - function assemble_hfscr(c: ctrl_t) return std_ulogic_vector is - variable ret : std_ulogic_vector(63 downto 0); - begin - ret := (others => '0'); - ret(59 downto 56) := c.hfscr_ic; - ret(HFSCR_PREFIX) := c.hfscr_pref; - ret(HFSCR_TAR) := c.hfscr_tar; - ret(HFSCR_DSCR) := c.hfscr_dscr; - ret(HFSCR_FP) := c.hfscr_fp; - return ret; - end; - function assemble_ctrl(c: ctrl_t; msrpr: std_ulogic) return std_ulogic_vector is variable ret : std_ulogic_vector(63 downto 0); begin @@ -796,8 +782,6 @@ begin case dbg_spr_addr(3 downto 0) is when SPRSEL_FSCR => dbg_spr_data <= assemble_fscr(ctrl); - when SPRSEL_HFSCR => - dbg_spr_data <= assemble_hfscr(ctrl); when SPRSEL_HEIR => dbg_spr_data <= ctrl.heir; when SPRSEL_CFAR => @@ -1457,8 +1441,6 @@ begin v.se.write_cfar := '1'; when SPRSEL_FSCR => v.se.write_fscr := '1'; - when SPRSEL_HFSCR => - v.se.write_hfscr := '1'; when SPRSEL_HEIR => v.se.write_heir := '1'; when SPRSEL_CTRL => @@ -1548,22 +1530,15 @@ begin end case; if ex1.msr(MSR_PR) = '1' and e_in.prefixed = '1' and - (ctrl.hfscr_pref = '0' or ctrl.fscr_pref = '0') then - -- [Hypervisor] facility unavailable for prefixed instructions, + ctrl.fscr_pref = '0' then + -- Facility unavailable for prefixed instructions, -- which has higher priority than the alignment interrupt for -- misaligned prefixed instructions, which has higher priority than - -- other [hypervisor] facility unavailable interrupts (e.g. for - -- plfs with HFSCR[FP] = 0). + -- other facility unavailable interrupts. v.exception := '1'; v.ic := x"b"; - if ctrl.hfscr_pref = '0' then - v.e.hv_intr := '1'; - v.e.intr_vec := 16#f80#; - v.se.write_hic := '1'; - else - v.e.intr_vec := 16#f60#; - v.se.write_ic := '1'; - end if; + v.e.intr_vec := 16#f60#; + v.se.write_ic := '1'; elsif misaligned = '1' then -- generate an alignment interrupt @@ -1608,41 +1583,20 @@ begin v.se.write_ic := '1'; elsif ex1.msr(MSR_PR) = '1' and e_in.uses_tar = '1' and - (ctrl.hfscr_tar = '0' or ctrl.fscr_tar = '0') then - -- [Hypervisor] facility unavailable for TAR access + ctrl.fscr_tar = '0' then + -- Facility unavailable for TAR access v.exception := '1'; v.ic := x"8"; - if ctrl.hfscr_tar = '0' then - v.e.hv_intr := '1'; - v.e.intr_vec := 16#f80#; - v.se.write_hic := '1'; - else - v.e.intr_vec := 16#f60#; - v.se.write_ic := '1'; - end if; + v.e.intr_vec := 16#f60#; + v.se.write_ic := '1'; elsif ex1.msr(MSR_PR) = '1' and e_in.uses_dscr = '1' and - (ctrl.hfscr_dscr = '0' or ctrl.fscr_dscr = '0') then - -- [Hypervisor] facility unavailable for DSCR access + ctrl.fscr_dscr = '0' then + -- Facility unavailable for DSCR access v.exception := '1'; v.ic := x"2"; - if ctrl.hfscr_dscr = '0' then - v.e.hv_intr := '1'; - v.e.intr_vec := 16#f80#; - v.se.write_hic := '1'; - else - v.e.intr_vec := 16#f60#; - v.se.write_ic := '1'; - end if; - - elsif HAS_FPU and ex1.msr(MSR_PR) = '1' and e_in.fac = FPU and - ctrl.hfscr_fp = '0' then - -- Hypervisor facility unavailable for FP instructions - v.exception := '1'; - v.ic := x"0"; - v.e.hv_intr := '1'; - v.e.intr_vec := 16#f80#; - v.se.write_hic := '1'; + v.e.intr_vec := 16#f60#; + v.se.write_ic := '1'; elsif HAS_FPU and ex1.msr(MSR_FP) = '0' and e_in.fac = FPU then -- generate a floating-point unavailable interrupt @@ -1977,7 +1931,6 @@ begin log_rd_data when SPRSEL_LOGD, ctrl.cfar when SPRSEL_CFAR, assemble_fscr(ctrl) when SPRSEL_FSCR, - assemble_hfscr(ctrl) when SPRSEL_HFSCR, ctrl.heir when SPRSEL_HEIR, assemble_ctrl(ctrl, ex1.msr(MSR_PR)) when SPRSEL_CTRL, 39x"0" & ctrl.dscr when SPRSEL_DSCR, @@ -2127,15 +2080,6 @@ begin v.log_addr_spr := std_ulogic_vector(unsigned(ex2.log_addr_spr) + 1); end if; x_to_pmu.mtspr <= ex1.se.write_pmuspr; - if ex1.se.write_hfscr = '1' then - ctrl_tmp.hfscr_ic <= ex1.e.write_data(59 downto 56); - ctrl_tmp.hfscr_pref <= ex1.e.write_data(HFSCR_PREFIX); - ctrl_tmp.hfscr_tar <= ex1.e.write_data(HFSCR_TAR); - ctrl_tmp.hfscr_dscr <= ex1.e.write_data(HFSCR_DSCR); - ctrl_tmp.hfscr_fp <= ex1.e.write_data(HFSCR_FP); - elsif ex1.se.write_hic = '1' then - ctrl_tmp.hfscr_ic <= ex1.ic; - end if; if ex1.se.write_fscr = '1' then ctrl_tmp.fscr_ic <= ex1.e.write_data(59 downto 56); ctrl_tmp.fscr_pref <= ex1.e.write_data(FSCR_PREFIX); diff --git a/scripts/mw_debug/mw_debug.c b/scripts/mw_debug/mw_debug.c index 1a0b96b..6b82943 100644 --- a/scripts/mw_debug/mw_debug.c +++ b/scripts/mw_debug/mw_debug.c @@ -552,7 +552,7 @@ static const char *fast_spr_names[] = "lr", "ctr", "srr0", "srr1", "hsrr0", "hsrr1", "sprg0", "sprg1", "sprg2", "sprg3", "hsprg0", "hsprg1", "xer", "tar", - "fscr", "hfscr", "heir", "cfar", + "fscr", "unused", "heir", "cfar", }; static const char *ldst_spr_names[] = {