diff --git a/core_debug.vhdl b/core_debug.vhdl
index 592cf85..afebc7c 100644
--- a/core_debug.vhdl
+++ b/core_debug.vhdl
@@ -173,6 +173,7 @@ begin
                 terminated <= '0';
                 log_trigger_delay <= 0;
                 gspr_index <= (others => '0');
+                log_dmi_addr <= (others => '0');
             else
                 if do_log_trigger = '1' or log_trigger_delay /= 0 then
                     if log_trigger_delay = 255 or
@@ -334,6 +335,7 @@ begin
                               addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
             variable firstbit : integer;
         begin
+            assert not is_X(addr);
             firstbit := to_integer(unsigned(addr(1 downto 0))) * 64;
             return data(firstbit + 63 downto firstbit);
         end;
@@ -351,9 +353,14 @@ begin
         begin
             if rising_edge(clk) then
                 if log_wr_enable = '1' then
+                    assert not is_X(log_wr_ptr);
                     log_array(to_integer(log_wr_ptr)) <= log_data;
                 end if;
-                log_rd <= log_array(to_integer(log_rd_ptr_latched));
+                if is_X(log_rd_ptr_latched) then
+                    log_rd <= (others => 'X');
+                else
+                    log_rd <= log_array(to_integer(log_rd_ptr_latched));
+                end if;
             end if;
         end process;
 
@@ -366,6 +373,7 @@ begin
                 if rst = '1' then
                     log_wr_ptr <= (others => '0');
                     log_toggle <= '0';
+                    log_rd_ptr_latched <= (others => '0');
                 elsif log_wr_enable = '1' then
                     if log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS) then
                         log_toggle <= not log_toggle;