Merge pull request #283 from antonblanchard/whitespace

Fix a few whitespace issues.  Only changes whitespace and comments.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
pull/288/head
Paul Mackerras 3 years ago committed by GitHub
commit 4a8ab3331c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23

@ -5,21 +5,21 @@ use ieee.math_real.all;

entity cache_ram is
generic(
ROW_BITS : integer := 16;
WIDTH : integer := 64;
TRACE : boolean := false;
ADD_BUF : boolean := false
);
ROW_BITS : integer := 16;
WIDTH : integer := 64;
TRACE : boolean := false;
ADD_BUF : boolean := false
);

port(
clk : in std_logic;
rd_en : in std_logic;
rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
rd_data : out std_logic_vector(WIDTH - 1 downto 0);
wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
wr_data : in std_logic_vector(WIDTH - 1 downto 0)
);
clk : in std_logic;
rd_en : in std_logic;
rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
rd_data : out std_logic_vector(WIDTH - 1 downto 0);
wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
wr_data : in std_logic_vector(WIDTH - 1 downto 0)
);

end cache_ram;

@ -35,13 +35,13 @@ architecture rtl of cache_ram is

begin
process(clk)
variable lbit : integer range 0 to WIDTH - 1;
variable mbit : integer range 0 to WIDTH - 1;
variable widx : integer range 0 to SIZE - 1;
constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
variable lbit : integer range 0 to WIDTH - 1;
variable mbit : integer range 0 to WIDTH - 1;
variable widx : integer range 0 to SIZE - 1;
constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
:= (others => '0');
begin
if rising_edge(clk) then
if rising_edge(clk) then
if TRACE then
if wr_sel /= sel0 then
report "write a:" & to_hstring(wr_addr) &
@ -57,29 +57,29 @@ begin
ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
end if;
end loop;
if rd_en = '1' then
rd_data0 <= ram(to_integer(unsigned(rd_addr)));
if TRACE then
report "read a:" & to_hstring(rd_addr) &
" dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
end if;
end if;
end if;
if rd_en = '1' then
rd_data0 <= ram(to_integer(unsigned(rd_addr)));
if TRACE then
report "read a:" & to_hstring(rd_addr) &
" dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
end if;
end if;
end if;
end process;

buf: if ADD_BUF generate
begin
process(clk)
begin
if rising_edge(clk) then
rd_data <= rd_data0;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
rd_data <= rd_data0;
end if;
end process;
end generate;

nobuf: if not ADD_BUF generate
begin
rd_data <= rd_data0;
rd_data <= rd_data0;
end generate;

end;

@ -17,7 +17,7 @@ entity control is
valid_in : in std_ulogic;
repeated : in std_ulogic;
flush_in : in std_ulogic;
busy_in : in std_ulogic;
busy_in : in std_ulogic;
deferred : in std_ulogic;
sgl_pipe_in : in std_ulogic;
stop_mark_in : in std_ulogic;

@ -9,7 +9,7 @@ use work.utils.all;

entity core_dram_tb is
generic (
MEMORY_SIZE : natural := (384*1024);
MEMORY_SIZE : natural := (384*1024);
MAIN_RAM_FILE : string := "main_ram.bin";
DRAM_INIT_FILE : string := "";
DRAM_INIT_SIZE : natural := 16#c000#
@ -57,25 +57,25 @@ architecture behave of core_dram_tb is
begin

soc0: entity work.soc
generic map(
SIM => true,
MEMORY_SIZE => MEMORY_SIZE,
RAM_INIT_FILE => MAIN_RAM_FILE,
generic map(
SIM => true,
MEMORY_SIZE => MEMORY_SIZE,
RAM_INIT_FILE => MAIN_RAM_FILE,
HAS_DRAM => true,
DRAM_SIZE => 256 * 1024 * 1024,
DRAM_SIZE => 256 * 1024 * 1024,
DRAM_INIT_SIZE => ROM_SIZE,
CLK_FREQ => 100000000,
CLK_FREQ => 100000000,
HAS_SPI_FLASH => true,
SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => 0
)
port map(
rst => soc_rst,
system_clk => system_clk,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
)
port map(
rst => soc_rst,
system_clk => system_clk,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init,
spi_flash_sck => spi_sck,
@ -83,8 +83,8 @@ begin
spi_flash_sdat_o => spi_sdat_o,
spi_flash_sdat_oe => spi_sdat_oe,
spi_flash_sdat_i => spi_sdat_i,
alt_reset => core_alt_reset
);
alt_reset => core_alt_reset
);

flash: entity work.s25fl128s
generic map (
@ -142,18 +142,18 @@ begin

clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

rst_process: process
begin
rst <= '1';
wait for 10*clk_period;
rst <= '0';
wait;
rst <= '1';
wait for 10*clk_period;
rst <= '0';
wait;
end process;

jtag: entity work.sim_jtag;

@ -10,10 +10,10 @@ entity core_flash_tb is
end core_flash_tb;

architecture behave of core_flash_tb is
signal clk, rst: std_logic;
signal clk, rst: std_logic;

-- testbench signals
constant clk_period : time := 10 ns;
-- testbench signals
constant clk_period : time := 10 ns;

-- SPI
signal spi_sck : std_ulogic;
@ -28,24 +28,24 @@ architecture behave of core_flash_tb is
begin

soc0: entity work.soc
generic map(
SIM => true,
MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin",
CLK_FREQ => 100000000,
generic map(
SIM => true,
MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin",
CLK_FREQ => 100000000,
HAS_SPI_FLASH => true,
SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => 0
)
port map(
rst => rst,
system_clk => clk,
)
port map(
rst => rst,
system_clk => clk,
spi_flash_sck => spi_sck,
spi_flash_cs_n => spi_cs_n,
spi_flash_sdat_o => spi_sdat_o,
spi_flash_sdat_oe => spi_sdat_oe,
spi_flash_sdat_i => spi_sdat_i
);
);

flash: entity work.s25fl128s
generic map (
@ -78,18 +78,18 @@ begin
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

rst_process: process
begin
rst <= '1';
wait for 10*clk_period;
rst <= '0';
wait;
rst <= '1';
wait for 10*clk_period;
rst <= '0';
wait;
end process;

jtag: entity work.sim_jtag;

@ -10,38 +10,38 @@ entity core_tb is
end core_tb;

architecture behave of core_tb is
signal clk, rst: std_logic;
signal clk, rst: std_logic;

-- testbench signals
constant clk_period : time := 10 ns;
-- testbench signals
constant clk_period : time := 10 ns;
begin

soc0: entity work.soc
generic map(
SIM => true,
MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin",
CLK_FREQ => 100000000
)
port map(
rst => rst,
system_clk => clk
);
generic map(
SIM => true,
MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin",
CLK_FREQ => 100000000
)
port map(
rst => rst,
system_clk => clk
);

clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

rst_process: process
begin
rst <= '1';
wait for 10*clk_period;
rst <= '0';
wait;
rst <= '1';
wait for 10*clk_period;
rst <= '0';
wait;
end process;

jtag: entity work.sim_jtag;

@ -8,11 +8,11 @@ use work.helpers.all;
entity zero_counter is
port (
clk : in std_logic;
rs : in std_ulogic_vector(63 downto 0);
count_right : in std_ulogic;
is_32bit : in std_ulogic;
result : out std_ulogic_vector(63 downto 0)
);
rs : in std_ulogic_vector(63 downto 0);
count_right : in std_ulogic;
is_32bit : in std_ulogic;
result : out std_ulogic_vector(63 downto 0)
);
end entity zero_counter;

architecture behaviour of zero_counter is

@ -19,13 +19,13 @@ architecture behave of countzero_tb is

begin
zerocounter_0: entity work.zero_counter
port map (
port map (
clk => clk,
rs => rs,
result => result,
count_right => count_right,
is_32bit => is_32bit
);
rs => rs,
result => result,
count_right => count_right,
is_32bit => is_32bit
);

clk_process: process
begin
@ -109,6 +109,6 @@ begin
end loop;
end loop;

std.env.finish;
std.env.finish;
end process;
end behave;

@ -48,11 +48,11 @@ begin

crs_updated <= cr_tmp;

if w_in.write_xerc_enable = '1' then
xerc_updated <= w_in.write_xerc_data;
else
xerc_updated <= xerc;
end if;
if w_in.write_xerc_enable = '1' then
xerc_updated <= w_in.write_xerc_data;
else
xerc_updated <= xerc;
end if;

end process;

@ -62,12 +62,12 @@ begin
if rising_edge(clk) then
if w_in.write_cr_enable = '1' then
report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
crs <= crs_updated;
crs <= crs_updated;
end if;
if w_in.write_xerc_enable = '1' then
if w_in.write_xerc_enable = '1' then
report "Writing XERC";
xerc <= xerc_updated;
end if;
xerc <= xerc_updated;
end if;
end if;
end process;

@ -87,7 +87,7 @@ begin
begin
if sim_dump = '1' then
report "CR 00000000" & to_hstring(crs);
assert false report "end of test" severity failure;
assert false report "end of test" severity failure;
end if;
end process;
end generate;

@ -70,69 +70,69 @@ begin

stim: process
begin
-- Clear stuff
d_in.valid <= '0';
d_in.load <= '0';
d_in.nc <= '0';
d_in.addr <= (others => '0');
d_in.data <= (others => '0');
-- Clear stuff
d_in.valid <= '0';
d_in.load <= '0';
d_in.nc <= '0';
d_in.addr <= (others => '0');
d_in.data <= (others => '0');
m_in.valid <= '0';
m_in.addr <= (others => '0');
m_in.pte <= (others => '0');

wait for 4*clk_period;
wait until rising_edge(clk);
wait until rising_edge(clk);

-- Cacheable read of address 4
d_in.load <= '1';
d_in.nc <= '0';
-- Cacheable read of address 4
d_in.load <= '1';
d_in.nc <= '0';
d_in.addr <= x"0000000000000004";
d_in.valid <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
d_in.valid <= '0';

wait until rising_edge(clk) and d_out.valid = '1';
wait until rising_edge(clk) and d_out.valid = '1';
assert d_out.data = x"0000000100000000"
report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) &
" expected 0000000100000000"
severity failure;
report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) &
" expected 0000000100000000"
severity failure;
-- wait for clk_period;

-- Cacheable read of address 30
d_in.load <= '1';
d_in.nc <= '0';
-- Cacheable read of address 30
d_in.load <= '1';
d_in.nc <= '0';
d_in.addr <= x"0000000000000030";
d_in.valid <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
d_in.valid <= '0';

wait until rising_edge(clk) and d_out.valid = '1';
wait until rising_edge(clk) and d_out.valid = '1';
assert d_out.data = x"0000000D0000000C"
report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) &
" expected 0000000D0000000C"
severity failure;

-- Non-cacheable read of address 100
d_in.load <= '1';
d_in.nc <= '1';
report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) &
" expected 0000000D0000000C"
severity failure;

-- Non-cacheable read of address 100
d_in.load <= '1';
d_in.nc <= '1';
d_in.addr <= x"0000000000000100";
d_in.valid <= '1';
wait until rising_edge(clk);
d_in.valid <= '0';
wait until rising_edge(clk) and d_out.valid = '1';
wait until rising_edge(clk);
d_in.valid <= '0';
wait until rising_edge(clk) and d_out.valid = '1';
assert d_out.data = x"0000004100000040"
report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) &
" expected 0000004100000040"
severity failure;
report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) &
" expected 0000004100000040"
severity failure;

wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);

std.env.finish;
std.env.finish;
end process;
end;

@ -123,9 +123,9 @@ begin
divider_out: process(clk)
begin
if rising_edge(clk) then
d_out.valid <= '0';
d_out.valid <= '0';
d_out.write_reg_data <= oresult;
d_out.overflow <= did_ovf;
d_out.overflow <= did_ovf;
if count = "1000000" then
d_out.valid <= '1';
end if;

@ -19,12 +19,12 @@ architecture behave of dmi_dtm_tb is
constant jclk_period : time := 30 ns;

-- DMI debug bus signals
signal dmi_addr : std_ulogic_vector(7 downto 0);
signal dmi_din : std_ulogic_vector(63 downto 0);
signal dmi_dout : std_ulogic_vector(63 downto 0);
signal dmi_req : std_ulogic;
signal dmi_wr : std_ulogic;
signal dmi_ack : std_ulogic;
signal dmi_addr : std_ulogic_vector(7 downto 0);
signal dmi_din : std_ulogic_vector(63 downto 0);
signal dmi_dout : std_ulogic_vector(63 downto 0);
signal dmi_req : std_ulogic;
signal dmi_wr : std_ulogic;
signal dmi_ack : std_ulogic;

-- Global JTAG signals (used by BSCANE2 inside dmi_dtm
alias j : glob_jtag_t is glob_jtag;
@ -35,216 +35,216 @@ architecture behave of dmi_dtm_tb is

begin
dtm: entity work.dmi_dtm
generic map(
ABITS => 8,
DBITS => 64
)
port map(
sys_clk => clk,
sys_reset => rst,
dmi_addr => dmi_addr,
dmi_din => dmi_din,
dmi_dout => dmi_dout,
dmi_req => dmi_req,
dmi_wr => dmi_wr,
dmi_ack => dmi_ack
);
generic map(
ABITS => 8,
DBITS => 64
)
port map(
sys_clk => clk,
sys_reset => rst,
dmi_addr => dmi_addr,
dmi_din => dmi_din,
dmi_dout => dmi_dout,
dmi_req => dmi_req,
dmi_wr => dmi_wr,
dmi_ack => dmi_ack
);

simple_ram_0: entity work.wishbone_bram_wrapper
generic map(RAM_INIT_FILE => "main_ram.bin",
MEMORY_SIZE => 524288)
port map(clk => clk, rst => rst,
wishbone_in => wishbone_ram_out,
wishbone_out => wishbone_ram_in);
generic map(RAM_INIT_FILE => "main_ram.bin",
MEMORY_SIZE => 524288)
port map(clk => clk, rst => rst,
wishbone_in => wishbone_ram_out,
wishbone_out => wishbone_ram_in);

wishbone_debug_0: entity work.wishbone_debug_master
port map(clk => clk, rst => rst,
dmi_addr => dmi_addr(1 downto 0),
dmi_dout => dmi_din,
dmi_din => dmi_dout,
dmi_wr => dmi_wr,
dmi_ack => dmi_ack,
dmi_req => dmi_req,
wb_in => wishbone_ram_in,
wb_out => wishbone_ram_out);
port map(clk => clk, rst => rst,
dmi_addr => dmi_addr(1 downto 0),
dmi_dout => dmi_din,
dmi_din => dmi_dout,
dmi_wr => dmi_wr,
dmi_ack => dmi_ack,
dmi_req => dmi_req,
wb_in => wishbone_ram_in,
wb_out => wishbone_ram_out);

-- system clock
sys_clk: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process sys_clk;

-- system sim: just reset and wait
sys_sim: process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;

-- jtag sim process
sim_jtag: process
procedure clock(count: in INTEGER) is
begin
for i in 1 to count loop
j.tck <= '0';
wait for jclk_period/2;
j.tck <= '1';
wait for jclk_period/2;
end loop;
end procedure clock;

procedure shift_out(val: in std_ulogic_vector) is
begin
for i in 0 to val'length-1 loop
j.tdi <= val(i);
clock(1);
end loop;
end procedure shift_out;

procedure shift_in(val: out std_ulogic_vector) is
begin
for i in val'length-1 downto 0 loop
val := j.tdo & val(val'length-1 downto 1);
clock(1);
end loop;
end procedure shift_in;

procedure send_command(
addr : in std_ulogic_vector(7 downto 0);
data : in std_ulogic_vector(63 downto 0);
op : in std_ulogic_vector(1 downto 0)) is
begin
j.capture <= '1';
clock(1);
j.capture <= '0';
clock(1);
j.shift <= '1';
shift_out(op);
shift_out(data);
shift_out(addr);
j.shift <= '0';
j.update <= '1';
clock(1);
j.update <= '0';
clock(1);
end procedure send_command;

procedure read_resp(
op : out std_ulogic_vector(1 downto 0);
data : out std_ulogic_vector(63 downto 0)) is

variable addr : std_ulogic_vector(7 downto 0);
begin
j.capture <= '1';
clock(1);
j.capture <= '0';
clock(1);
j.shift <= '1';
shift_in(op);
shift_in(data);
shift_in(addr);
j.shift <= '0';
j.update <= '1';
clock(1);
j.update <= '0';
clock(1);
end procedure read_resp;

procedure dmi_write(addr : in std_ulogic_vector(7 downto 0);
data : in std_ulogic_vector(63 downto 0)) is
variable resp_op : std_ulogic_vector(1 downto 0);
variable resp_data : std_ulogic_vector(63 downto 0);
variable timeout : integer;
begin
send_command(addr, data, "10");
loop
read_resp(resp_op, resp_data);
case resp_op is
when "00" =>
return;
when "11" =>
timeout := timeout + 1;
assert timeout < 0
report "dmi_write timed out !" severity error;
when others =>
assert 0 > 1 report "dmi_write got odd status: " &
to_hstring(resp_op) severity error;
end case;
end loop;
end procedure dmi_write;

procedure dmi_read(addr : in std_ulogic_vector(7 downto 0);
data : out std_ulogic_vector(63 downto 0)) is
variable resp_op : std_ulogic_vector(1 downto 0);
variable timeout : integer;
begin
send_command(addr, (others => '0'), "01");
loop
read_resp(resp_op, data);
case resp_op is
when "00" =>
return;
when "11" =>
timeout := timeout + 1;
assert timeout < 0
report "dmi_read timed out !" severity error;
when others =>
assert 0 > 1 report "dmi_read got odd status: " &
to_hstring(resp_op) severity error;
end case;
end loop;
end procedure dmi_read;

variable data : std_ulogic_vector(63 downto 0);
procedure clock(count: in INTEGER) is
begin
for i in 1 to count loop
j.tck <= '0';
wait for jclk_period/2;
j.tck <= '1';
wait for jclk_period/2;
end loop;
end procedure clock;

procedure shift_out(val: in std_ulogic_vector) is
begin
for i in 0 to val'length-1 loop
j.tdi <= val(i);
clock(1);
end loop;
end procedure shift_out;

procedure shift_in(val: out std_ulogic_vector) is
begin
for i in val'length-1 downto 0 loop
val := j.tdo & val(val'length-1 downto 1);
clock(1);
end loop;
end procedure shift_in;

procedure send_command(
addr : in std_ulogic_vector(7 downto 0);
data : in std_ulogic_vector(63 downto 0);
op : in std_ulogic_vector(1 downto 0)) is
begin
j.capture <= '1';
clock(1);
j.capture <= '0';
clock(1);
j.shift <= '1';
shift_out(op);
shift_out(data);
shift_out(addr);
j.shift <= '0';
j.update <= '1';
clock(1);
j.update <= '0';
clock(1);
end procedure send_command;

procedure read_resp(
op : out std_ulogic_vector(1 downto 0);
data : out std_ulogic_vector(63 downto 0)) is

variable addr : std_ulogic_vector(7 downto 0);
begin
j.capture <= '1';
clock(1);
j.capture <= '0';
clock(1);
j.shift <= '1';
shift_in(op);
shift_in(data);
shift_in(addr);
j.shift <= '0';
j.update <= '1';
clock(1);
j.update <= '0';
clock(1);
end procedure read_resp;

procedure dmi_write(addr : in std_ulogic_vector(7 downto 0);
data : in std_ulogic_vector(63 downto 0)) is
variable resp_op : std_ulogic_vector(1 downto 0);
variable resp_data : std_ulogic_vector(63 downto 0);
variable timeout : integer;
begin
send_command(addr, data, "10");
loop
read_resp(resp_op, resp_data);
case resp_op is
when "00" =>
return;
when "11" =>
timeout := timeout + 1;
assert timeout < 0
report "dmi_write timed out !" severity error;
when others =>
assert 0 > 1 report "dmi_write got odd status: " &
to_hstring(resp_op) severity error;
end case;
end loop;
end procedure dmi_write;

procedure dmi_read(addr : in std_ulogic_vector(7 downto 0);
data : out std_ulogic_vector(63 downto 0)) is
variable resp_op : std_ulogic_vector(1 downto 0);
variable timeout : integer;
begin
send_command(addr, (others => '0'), "01");
loop
read_resp(resp_op, data);
case resp_op is
when "00" =>
return;
when "11" =>
timeout := timeout + 1;
assert timeout < 0
report "dmi_read timed out !" severity error;
when others =>
assert 0 > 1 report "dmi_read got odd status: " &
to_hstring(resp_op) severity error;
end case;
end loop;
end procedure dmi_read;

variable data : std_ulogic_vector(63 downto 0);
begin
-- init & reset
j.reset <= '1';
j.sel <= "0000";
j.capture <= '0';
j.update <= '0';
j.shift <= '0';
j.tdi <= '0';
j.tms <= '0';
j.runtest <= '0';
clock(5);
j.reset <= '0';
clock(5);

-- select chain 2
j.sel <= "0010";
clock(1);

-- send command
dmi_read(x"00", data);
report "Read addr reg:" & to_hstring(data);
report "Writing addr reg to all 1's";
dmi_write(x"00", (others => '1'));
dmi_read(x"00", data);
report "Read addr reg:" & to_hstring(data);

report "Writing ctrl reg to all 1's";
dmi_write(x"02", (others => '1'));
dmi_read(x"02", data);
report "Read ctrl reg:" & to_hstring(data);

report "Read memory at 0...\n";
dmi_write(x"00", x"0000000000000000");
dmi_write(x"02", x"00000000000007ff");
dmi_read(x"01", data);
report "00:" & to_hstring(data);
dmi_read(x"01", data);
report "08:" & to_hstring(data);
dmi_read(x"01", data);
report "10:" & to_hstring(data);
dmi_read(x"01", data);
report "18:" & to_hstring(data);
clock(10);
std.env.finish;
-- init & reset
j.reset <= '1';
j.sel <= "0000";
j.capture <= '0';
j.update <= '0';
j.shift <= '0';
j.tdi <= '0';
j.tms <= '0';
j.runtest <= '0';
clock(5);
j.reset <= '0';
clock(5);

-- select chain 2
j.sel <= "0010";
clock(1);

-- send command
dmi_read(x"00", data);
report "Read addr reg:" & to_hstring(data);
report "Writing addr reg to all 1's";
dmi_write(x"00", (others => '1'));
dmi_read(x"00", data);
report "Read addr reg:" & to_hstring(data);

report "Writing ctrl reg to all 1's";
dmi_write(x"02", (others => '1'));
dmi_read(x"02", data);
report "Read ctrl reg:" & to_hstring(data);

report "Read memory at 0...\n";
dmi_write(x"00", x"0000000000000000");
dmi_write(x"02", x"00000000000007ff");
dmi_read(x"01", data);
report "00:" & to_hstring(data);
dmi_read(x"01", data);
report "08:" & to_hstring(data);
dmi_read(x"01", data);
report "10:" & to_hstring(data);
dmi_read(x"01", data);
report "18:" & to_hstring(data);
clock(10);
std.env.finish;
end process;
end behave;

@ -104,10 +104,10 @@ begin

-- Read data receive queue
data_queue: entity work.sync_fifo
generic map (
DEPTH => 16,
WIDTH => rd_data'length
)
generic map (
DEPTH => 16,
WIDTH => rd_data'length
)
port map (
clk => clk,
reset => soc_rst or reset_acks,

@ -34,7 +34,7 @@ begin
i_out => i_in,
m_in => m_out,
stall_in => '0',
flush_in => '0',
flush_in => '0',
inval_in => '0',
wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out
@ -73,7 +73,7 @@ begin
begin
i_out.req <= '0';
i_out.nia <= (others => '0');
i_out.stop_mark <= '0';
i_out.stop_mark <= '0';

m_out.tlbld <= '0';
m_out.tlbie <= '0';
@ -93,10 +93,10 @@ begin

assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000001"
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000001"
severity failure;
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000001"
severity failure;

i_out.req <= '0';

@ -109,10 +109,10 @@ begin
wait until rising_edge(clk);
assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000002"
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000002"
severity failure;
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000002"
severity failure;
wait until rising_edge(clk);

-- another miss
@ -124,10 +124,10 @@ begin

assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000010"
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000010"
severity failure;
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000010"
severity failure;

-- test something that aliases
i_out.req <= '1';
@ -142,10 +142,10 @@ begin

assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000040"
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000040"
severity failure;
report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) &
" expected 00000040"
severity failure;

i_out.req <= '0';


@ -5,17 +5,17 @@ use ieee.math_real.all;

entity plru is
generic (
BITS : positive := 2
)
;
BITS : positive := 2
)
;
port (
clk : in std_ulogic;
rst : in std_ulogic;
clk : in std_ulogic;
rst : in std_ulogic;

acc : in std_ulogic_vector(BITS-1 downto 0);
acc_en : in std_ulogic;
lru : out std_ulogic_vector(BITS-1 downto 0)
);
acc : in std_ulogic_vector(BITS-1 downto 0);
acc_en : in std_ulogic;
lru : out std_ulogic_vector(BITS-1 downto 0)
);
end entity plru;

architecture rtl of plru is
@ -28,50 +28,48 @@ begin

-- XXX Check if we can turn that into a little ROM instead that
-- takes the tree bit vector and returns the LRU. See if it's better
-- in term of FPGA resouces usage...
-- in term of FPGA resource usage...
get_lru: process(tree)
variable node : node_t;
variable node : node_t;
begin
node := 0;
for i in 0 to BITS-1 loop
-- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node));
lru(BITS-1-i) <= tree(node);
if i /= BITS-1 then
node := node * 2;
if tree(node) = '1' then
node := node + 2;
else
node := node + 1;
end if;
end if;
end loop;
node := 0;
for i in 0 to BITS-1 loop
-- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node));
lru(BITS-1-i) <= tree(node);
if i /= BITS-1 then
node := node * 2;
if tree(node) = '1' then
node := node + 2;
else
node := node + 1;
end if;
end if;
end loop;
end process;

update_lru: process(clk)
variable node : node_t;
variable abit : std_ulogic;
variable node : node_t;
variable abit : std_ulogic;
begin
if rising_edge(clk) then
if rst = '1' then
tree <= (others => '0');
elsif acc_en = '1' then
node := 0;
for i in 0 to BITS-1 loop
abit := acc(BITS-1-i);
tree(node) <= not abit;
-- report "UPD: i:" & integer'image(i) & " node:" & integer'image(node) & " val" & std_ulogic'image(not abit);
if i /= BITS-1 then
node := node * 2;
if abit = '1' then
node := node + 2;
else
node := node + 1;
end if;
end if;
end loop;
end if;
end if;
if rising_edge(clk) then
if rst = '1' then
tree <= (others => '0');
elsif acc_en = '1' then
node := 0;
for i in 0 to BITS-1 loop
abit := acc(BITS-1-i);
tree(node) <= not abit;
-- report "UPD: i:" & integer'image(i) & " node:" & integer'image(node) & " val" & std_ulogic'image(not abit);
if i /= BITS-1 then
node := node * 2;
if abit = '1' then
node := node + 2;
else
node := node + 1;
end if;
end if;
end loop;
end if;
end if;
end process;
end;



@ -27,9 +27,9 @@ begin
clk => clk,
rst => rst,

acc => acc,
acc_en => acc_en,
lru => lru
acc => acc,
acc_en => acc_en,
lru => lru
);

clk_process: process
@ -50,58 +50,58 @@ begin

stim: process
begin
wait for 4*clk_period;

report "accessing 1:";
acc <= "001";
acc_en <= '1';
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 2:";
acc <= "010";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 7:";
acc <= "111";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 4:";
acc <= "100";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 3:";
acc <= "011";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 5:";
acc <= "101";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 3:";
acc <= "011";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 5:";
acc <= "101";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 6:";
acc <= "110";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 0:";
acc <= "000";
wait for clk_period;
report "lru:" & to_hstring(lru);
wait for 4*clk_period;

report "accessing 1:";
acc <= "001";
acc_en <= '1';
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 2:";
acc <= "010";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 7:";
acc <= "111";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 4:";
acc <= "100";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 3:";
acc <= "011";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 5:";
acc <= "101";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 3:";
acc <= "011";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 5:";
acc <= "101";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 6:";
acc <= "110";
wait for clk_period;
report "lru:" & to_hstring(lru);

report "accessing 0:";
acc <= "000";
wait for clk_period;
report "lru:" & to_hstring(lru);

std.env.finish;
end process;

@ -134,21 +134,21 @@ begin

-- Dump registers if core terminates
sim_dump_test: if SIM generate
dump_registers: process(all)
begin
if sim_dump = '1' then
loop_0: for i in 0 to 31 loop
report "GPR" & integer'image(i) & " " & to_hstring(registers(i));
end loop loop_0;

report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR)))));
report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR)))));
report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER)))));
sim_dump_done <= '1';
else
sim_dump_done <= '0';
end if;
end process;
dump_registers: process(all)
begin
if sim_dump = '1' then
loop_0: for i in 0 to 31 loop
report "GPR" & integer'image(i) & " " & to_hstring(registers(i));
end loop loop_0;

report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR)))));
report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR)))));
report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER)))));
sim_dump_done <= '1';
else
sim_dump_done <= '0';
end if;
end process;
end generate;

-- Keep GHDL synthesis happy

@ -7,17 +7,17 @@ use work.common.all;

entity rotator is
port (rs: in std_ulogic_vector(63 downto 0);
ra: in std_ulogic_vector(63 downto 0);
shift: in std_ulogic_vector(6 downto 0);
insn: in std_ulogic_vector(31 downto 0);
is_32bit: in std_ulogic;
right_shift: in std_ulogic;
arith: in std_ulogic;
clear_left: in std_ulogic;
clear_right: in std_ulogic;
ra: in std_ulogic_vector(63 downto 0);
shift: in std_ulogic_vector(6 downto 0);
insn: in std_ulogic_vector(31 downto 0);
is_32bit: in std_ulogic;
right_shift: in std_ulogic;
arith: in std_ulogic;
clear_left: in std_ulogic;
clear_right: in std_ulogic;
sign_ext_rs: in std_ulogic;
result: out std_ulogic_vector(63 downto 0);
carry_out: out std_ulogic
result: out std_ulogic_vector(63 downto 0);
carry_out: out std_ulogic
);
end entity rotator;

@ -31,159 +31,159 @@ architecture behaviour of rotator is

-- note BE bit numbering
function right_mask(mask_begin: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
variable ret: std_ulogic_vector(63 downto 0);
variable ret: std_ulogic_vector(63 downto 0);
begin
ret := (others => '0');
for i in 0 to 63 loop
if i >= to_integer(unsigned(mask_begin)) then
ret(63 - i) := '1';
end if;
end loop;
return ret;
ret := (others => '0');
for i in 0 to 63 loop
if i >= to_integer(unsigned(mask_begin)) then
ret(63 - i) := '1';
end if;
end loop;
return ret;
end;

function left_mask(mask_end: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
variable ret: std_ulogic_vector(63 downto 0);
variable ret: std_ulogic_vector(63 downto 0);
begin
ret := (others => '0');
if mask_end(6) = '0' then
for i in 0 to 63 loop
if i <= to_integer(unsigned(mask_end)) then
ret(63 - i) := '1';
end if;
end loop;
end if;
return ret;
ret := (others => '0');
if mask_end(6) = '0' then
for i in 0 to 63 loop
if i <= to_integer(unsigned(mask_end)) then
ret(63 - i) := '1';
end if;
end loop;
end if;
return ret;
end;

begin
rotator_0: process(all)
variable hi32: std_ulogic_vector(31 downto 0);
begin
-- First replicate bottom 32 bits to both halves if 32-bit
if is_32bit = '1' then
-- First replicate bottom 32 bits to both halves if 32-bit
if is_32bit = '1' then
hi32 := rs(31 downto 0);
elsif sign_ext_rs = '1' then
elsif sign_ext_rs = '1' then
-- sign extend bottom 32 bits
hi32 := (others => rs(31));
else
hi32 := rs(63 downto 32);
end if;
hi32 := rs(63 downto 32);
end if;
repl32 <= hi32 & rs(31 downto 0);

-- Negate shift count for right shifts
if right_shift = '1' then
rot_count <= std_ulogic_vector(- signed(shift(5 downto 0)));
else
rot_count <= shift(5 downto 0);
end if;
-- Negate shift count for right shifts
if right_shift = '1' then
rot_count <= std_ulogic_vector(- signed(shift(5 downto 0)));
else
rot_count <= shift(5 downto 0);
end if;

-- Rotator works in 3 stages using 2 bits of the rotate count each
-- time. This gives 4:1 multiplexors which is ideal for the 6-input
-- LUTs in the Xilinx Artix 7.
-- We look at the low bits of the rotate count first because they will
-- have less delay through the negation above.
-- First rotate by 0, 1, 2, or 3
case rot_count(1 downto 0) is
when "00" =>
rot1 <= repl32;
when "01" =>
rot1 <= repl32(62 downto 0) & repl32(63);
when "10" =>
rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
when others =>
rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
end case;
-- Next rotate by 0, 4, 8 or 12
case rot_count(3 downto 2) is
when "00" =>
rot2 <= rot1;
when "01" =>
rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
when "10" =>
rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
when others =>
rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
end case;
-- Lastly rotate by 0, 16, 32 or 48
case rot_count(5 downto 4) is
when "00" =>
rot <= rot2;
when "01" =>
rot <= rot2(47 downto 0) & rot2(63 downto 48);
when "10" =>
rot <= rot2(31 downto 0) & rot2(63 downto 32);
when others =>
rot <= rot2(15 downto 0) & rot2(63 downto 16);
end case;
-- Rotator works in 3 stages using 2 bits of the rotate count each
-- time. This gives 4:1 multiplexors which is ideal for the 6-input
-- LUTs in the Xilinx Artix 7.
-- We look at the low bits of the rotate count first because they will
-- have less delay through the negation above.
-- First rotate by 0, 1, 2, or 3
case rot_count(1 downto 0) is
when "00" =>
rot1 <= repl32;
when "01" =>
rot1 <= repl32(62 downto 0) & repl32(63);
when "10" =>
rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
when others =>
rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
end case;
-- Next rotate by 0, 4, 8 or 12
case rot_count(3 downto 2) is
when "00" =>
rot2 <= rot1;
when "01" =>
rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
when "10" =>
rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
when others =>
rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
end case;
-- Lastly rotate by 0, 16, 32 or 48
case rot_count(5 downto 4) is
when "00" =>
rot <= rot2;
when "01" =>
rot <= rot2(47 downto 0) & rot2(63 downto 48);
when "10" =>
rot <= rot2(31 downto 0) & rot2(63 downto 32);
when others =>
rot <= rot2(15 downto 0) & rot2(63 downto 16);
end case;

-- Trim shift count to 6 bits for 32-bit shifts
sh <= (shift(6) and not is_32bit) & shift(5 downto 0);
-- Trim shift count to 6 bits for 32-bit shifts
sh <= (shift(6) and not is_32bit) & shift(5 downto 0);

-- Work out mask begin/end indexes (caution, big-endian bit numbering)
if clear_left = '1' then
if is_32bit = '1' then
mb <= "01" & insn(10 downto 6);
else
mb <= "0" & insn(5) & insn(10 downto 6);
end if;
elsif right_shift = '1' then
-- this is basically mb <= sh + (is_32bit? 32: 0);
if is_32bit = '1' then
mb <= sh(5) & not sh(5) & sh(4 downto 0);
else
mb <= sh;
end if;
else
mb <= ('0' & is_32bit & "00000");
end if;
if clear_right = '1' and is_32bit = '1' then
me <= "01" & insn(5 downto 1);
elsif clear_right = '1' and clear_left = '0' then
me <= "0" & insn(5) & insn(10 downto 6);
else
-- effectively, 63 - sh
me <= sh(6) & not sh(5 downto 0);
end if;
-- Work out mask begin/end indexes (caution, big-endian bit numbering)
if clear_left = '1' then
if is_32bit = '1' then
mb <= "01" & insn(10 downto 6);
else
mb <= "0" & insn(5) & insn(10 downto 6);
end if;
elsif right_shift = '1' then
-- this is basically mb <= sh + (is_32bit? 32: 0);
if is_32bit = '1' then
mb <= sh(5) & not sh(5) & sh(4 downto 0);
else
mb <= sh;
end if;
else
mb <= ('0' & is_32bit & "00000");
end if;
if clear_right = '1' and is_32bit = '1' then
me <= "01" & insn(5 downto 1);
elsif clear_right = '1' and clear_left = '0' then
me <= "0" & insn(5) & insn(10 downto 6);
else
-- effectively, 63 - sh
me <= sh(6) & not sh(5 downto 0);
end if;

-- Calculate left and right masks
mr <= right_mask(mb);
ml <= left_mask(me);
-- Calculate left and right masks
mr <= right_mask(mb);
ml <= left_mask(me);

-- Work out output mode
-- 00 for sl[wd]
-- 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
-- 10 for rldicl, sr[wd]
-- 1z for sra[wd][i], z = 1 if rs is negative
if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
output_mode(1) <= '1';
output_mode(0) <= arith and repl32(63);
else
output_mode(1) <= '0';
if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
output_mode(0) <= '1';
else
output_mode(0) <= '0';
end if;
end if;
-- Work out output mode
-- 00 for sl[wd]
-- 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
-- 10 for rldicl, sr[wd]
-- 1z for sra[wd][i], z = 1 if rs is negative
if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
output_mode(1) <= '1';
output_mode(0) <= arith and repl32(63);
else
output_mode(1) <= '0';
if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
output_mode(0) <= '1';
else
output_mode(0) <= '0';
end if;
end if;

-- Generate output from rotated input and masks
case output_mode is
when "00" =>
result <= (rot and (mr and ml)) or (ra and not (mr and ml));
when "01" =>
result <= (rot and (mr or ml)) or (ra and not (mr or ml));
when "10" =>
result <= rot and mr;
when others =>
result <= rot or not mr;
end case;
-- Generate output from rotated input and masks
case output_mode is
when "00" =>
result <= (rot and (mr and ml)) or (ra and not (mr and ml));
when "01" =>
result <= (rot and (mr or ml)) or (ra and not (mr or ml));
when "10" =>
result <= rot and mr;
when others =>
result <= rot or not mr;
end case;

-- Generate carry output for arithmetic shift right of negative value
if output_mode = "11" then
carry_out <= or (rs and not ml);
else
carry_out <= '0';
end if;
-- Generate carry output for arithmetic shift right of negative value
if output_mode = "11" then
carry_out <= or (rs and not ml);
else
carry_out <= '0';
end if;
end process;
end behaviour;

@ -23,272 +23,272 @@ architecture behave of rotator_tb is

begin
rotator_0: entity work.rotator
port map (
rs => rs,
ra => ra,
shift => shift,
insn => insn,
is_32bit => is_32bit,
right_shift => right_shift,
arith => arith,
clear_left => clear_left,
clear_right => clear_right,
port map (
rs => rs,
ra => ra,
shift => shift,
insn => insn,
is_32bit => is_32bit,
right_shift => right_shift,
arith => arith,
clear_left => clear_left,