From 3fb0a9ed26a7d863803542dc1f64bec5ca0b182d Mon Sep 17 00:00:00 2001
From: Paul Mackerras <paulus@ozlabs.org>
Date: Sat, 15 Feb 2025 19:55:15 +1100
Subject: [PATCH] litedram: Update generated code

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 .../acorn-cle-215/litedram_core.init          | 1773 ++++++------
 .../generated/acorn-cle-215/litedram_core.v   | 2321 +++++++--------
 litedram/generated/arty/litedram_core.init    | 1773 ++++++------
 litedram/generated/arty/litedram_core.v       | 2005 ++++++-------
 litedram/generated/ecpix-5/litedram_core.init | 1052 +++----
 litedram/generated/ecpix-5/litedram_core.v    | 1447 +++++-----
 .../generated/genesys2/litedram_core.init     | 2498 +++++++++--------
 litedram/generated/genesys2/litedram_core.v   | 1819 ++++++------
 .../generated/nexys-video/litedram_core.init  | 1773 ++++++------
 .../generated/nexys-video/litedram_core.v     | 2109 +++++++-------
 .../orangecrab-85-0.2/litedram_core.init      | 2154 +++++++-------
 .../orangecrab-85-0.2/litedram_core.v         | 1449 +++++-----
 litedram/generated/sim/litedram_core.init     | 1559 +++++-----
 litedram/generated/sim/litedram_core.v        | 1775 ++++++------
 .../generated/wukong-v2/litedram_core.init    | 1773 ++++++------
 litedram/generated/wukong-v2/litedram_core.v  | 2005 ++++++-------
 16 files changed, 14841 insertions(+), 14444 deletions(-)

diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init
index 0573632..843a495 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842adc83c4c0001
+3c4c000100000000
+7c0802a63842aea4
+f821ffc148002885
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+000000004800289c
+0000038001000000
+3842ae503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48002175f9410108
+480021b9f9410108
 7c7f1b7860000000
-48001bc538610020
+48001c1538610020
 382100b060000000
-480027e87fe3fb78
+480028447fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,273 +552,284 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842ad2c
-480027217d600026
-f821fed191610008
-6000000048001bc1
-38637a983c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842adb4
+480027797d600026
+f821fec191610008
+6000000048001c11
+38637a683c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637ab83be00008
+38637a883be00008
 4bffff1d67ffc000
-38637ad83c62ffff
+38637aa83c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637af0
+4bfffef538637ac0
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637af8
+4bfffedd38637ac8
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b00
+4bfffec538637ad0
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b08
+4bfffead38637ad8
 4182001073e90010
-38637b183c62ffff
+38637ae83c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637b28
-3b7b7b303f62ffff
-4bfffe757f63db78
+4bfffe8538637af8
+3b397b003f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637b387884b582
+38637b087884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637b50
+4bfffe2d38637b20
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637b68
+4bfffe0d38637b38
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637b807c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637ba057c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637b507c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637b7057e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637bc0
-4082009073a90002
-38637be03c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637b90
+4082006473c90002
+38637bb03c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637bf8
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637c087b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637c3838847c28
-48000bf54bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637c583c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637bc0
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637c70
-38a000403c9af000
+4bfffc2d38637c60
+38a000403c9cf000
 3861007078840020
-60000000480018b5
+60000000480019e5
 3d200002e9410070
 6129464c3c62ffff
-792983e438637c88
+792983e438637c78
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637ca83c62ffff
-892100774bfffae9
+38637c983c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d0888810070
+38637cf888810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637d38
-3880600038a00000
-6484ff0060a5a000
-480018113c604000
+3c62ffff4bfffb99
+4bfffb8d38637d28
+3880f80338a00000
+7884682860a5a000
+480019413c604000
 3c62ffff60000000
-4bfffa8538637d58
-4bffff184bfffafd
+4bfffb6538637d48
+480002184bfffbdd
 3f22ffffebe10090
-3b397cc03ba00000
-a12100a87ffafa14
+3b397cb03ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637ce8
-e86100884bfffac5
+4bfffb2d38637cd8
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-480022407d638120
+8161000838210140
+480023787d638120
 38a000383c9ff000
 386100b078840020
-6000000048001795
+60000000480018c5
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-600000004800174d
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+600000004800187d
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
-38637bf03c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637bc8
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637bd0
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
+38637be83c62ffff
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637bf87b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637c2838847c18
+48000a294bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637c483c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920100400000000
+7c0004ac6529c800
+394010087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-6529c80039201004
-7c604f2a7c0004ac
-3920000139401008
+3842a7283c4c0001
+4182004428030002
+4182001428030003
+4182005028030001
+4bffffa87c8307b4
+6529c8003920104c
+7c804f2a7c0004ac
+3940105039200001
 7c0004ac654ac800
 4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a6f4
-2803000341820044
-2803000141820014
-7c8307b441820050
-3920104c4bffffa8
-7c0004ac6529c800
-392000017c804f2a
-654ac80039401050
-7d20572a7c0004ac
-392010344e800020
+6529c80039201034
+7c804f2a7c0004ac
+3940103839200001
+3920101c4bffffd8
 7c0004ac6529c800
 392000017c804f2a
-4bffffd839401038
-6529c8003920101c
-7c804f2a7c0004ac
-3940102039200001
-000000004bffffbc
+4bffffbc39401020
+0000000000000000
+3d40555500000000
+614a55555469f87e
+7c6918507d295038
+612933333d203333
+5463f0be7d2a1838
+7d4a1a147c634838
+7d2952145549e13e
+614a0f0f3d400f0f
+552ac23e7d295038
+5523843e7d2a4a14
+786306a07c634a14
+000000004e800020
 0000000000000000
-5469f87e3d405555
-7d295038614a5555
-3d2033337c691850
-7d2a183861293333
-7c6348385463f0be
-5549e13e7d4a1a14
-3d400f0f7d295214
-7d295038614a0f0f
-7d2a4a14552ac23e
-7c634a145523843e
-4e800020786306a0
+3920000028030002
+4182002c39401040
+3920000028030003
+4182001c39401058
+3920000028030001
+4182000c39401028
+3940101039200000
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
 2803000200000000
-3940104039200000
+3940103c39200000
 280300034182002c
-3940105839200000
+3940105439200000
 280300014182001c
-3940102839200000
+3940102439200000
 392000004182000c
-654ac80039401010
+654ac8003940100c
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-3920000028030002
-4182002c3940103c
-3920000028030003
-4182001c39401054
-3920000028030001
-4182000c39401024
-3940100c39200000
-7c0004ac654ac800
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-7c0802a63842a554
-f821ff4148001f2d
-3f02ffff23a30001
-3b40100c3ae00003
-3ac010743b201010
-3bc0000020630003
-3b187e503b600000
-675ac80066f78020
-66d6c8006739c800
-7c7f07b47fbd07b4
-3a8100207bc91764
-3aa000047e87a378
-7e9ca3787d58482e
+3842a5883c4c0001
+48001f2d7c0802a6
+3ee2fffff821ff31
+3b20100c3ec0e008
+3aa010743b001010
+236300033b800830
+3ba000003bc00000
+7ad610203af77fac
+6718c8006739c800
+679cc80066b5c800
+687f00017f7b07b4
+3a4100207bc91764
+3a8000047e479378
+7e5a93787d57482e
 4800004439000000
 794a07e07949f862
-7d4ab8387d4a00d0
+7d4ab0387d4a00d0
 7d2a4b787d494a78
 7d293030552907fe
 7d292b7838c60001
@@ -812,253 +838,252 @@ f821ff4148001f2d
 4182001828280004
 38a0000039200008
 38c000007d2903a6
-3ab5ffff4bffffb0
-2c15000038e70004
+3a94ffff4bffffb0
+2c14000038e70004
 7c0004ac4082ff98
-7c0004ac7ea0d72a
-386000097ea0cf2a
-3860000f4bfffd41
-392010144bfffd1d
+7c0004ac7e80cf2a
+386000097e80c72a
+3860000f4bfffd3d
+392010144bfffd19
 38e000046529c800
-7ce903a63914ffff
-8ce8000139400000
+7ce903a63912ffff
+394000003a600004
+3a73ffff8ce80001
 7cea3b787947400c
-7c0004ac4200fff4
+7c0004ac4200fff0
 392900187ce04f2a
-7c29b0003a940004
-3a8008304082ffcc
-7c0004ac6694c800
-5463063e7c60a62a
-7c0004ac4bfffe61
-5463063e7c60a62a
-7c0004ac4bfffdfd
-388000177c60a62a
-4bfffcf95463063e
-3860000f3a80082c
-6694c8004bfffc95
-7c60a62a7c0004ac
-4bfffe1d5463063e
-7c60a62a7c0004ac
-4bfffdb95463063e
-7c60a62a7c0004ac
+7c29a8003a520004
+7c0004ac4082ffc4
+5463063e7c60e62a
+7c0004ac4bfffe5d
+5463063e7c60e62a
+7c0004ac4bfffdf9
+388000177c60e62a
+4bfffcf55463063e
+3860000f3a40082c
+6652c8004bfffc91
+7c60962a7c0004ac
+4bfffe195463063e
+7c60962a7c0004ac
+4bfffdb55463063e
+7c60962a7c0004ac
 5463063e38800025
-3860000f4bfffcb5
-392000004bfffc55
-7d20d72a7c0004ac
+3860000f4bfffcb1
+392000004bfffc51
 7d20cf2a7c0004ac
-7e9cea143860000b
-3860000f4bfffc51
-4bfffc293a601018
-6673c8003a001078
-7e91a3787f9cfa14
-7c0004ac6610c800
-390000047d209e2a
+7d20c72a7c0004ac
+39c010183860000b
+3860000f4bfffc4d
+4bfffc2565cec800
+7e5afa147dfada14
+7e7107b41d330018
+7c0004ac7d297214
+390000047d204e2a
 7d0903a679290020
 9d2affff39410034
 4200fff87929c202
-3a7300187d3da050
-7c69f8ae3a940004
-7c634a78893c0010
-4bfffcb55463063e
-7c721b7889310010
-7c634a788874fffc
-4bfffc9d5463063e
-7c6392147c338000
-4082ff987eb51a14
-7f7baa143bde0001
-4082fddc283e0003
-7f6307b4382100c0
-0000000048001d04
-0000108001000000
-3842a2c03c4c0001
-388000007c0802a6
-f821ff6148001cb5
-3b1864ec3f02ffff
-3bc000007c7d1b78
-7f05c3783b800000
-600000004800084d
-4bfffd397fa3eb78
-7c7f00342c030000
-4082006857ffd97e
-418200602c1c0000
-7ff9fb783bfeffff
-7fdbf3787ffcfb78
-3b5b00017fa3eb78
-2c0300004bfffd05
-7d39d85040820070
-7c0950007d5fe050
-2c1a001f41810068
-3ca2ffff4181006c
-3880000038a564a4
-7f5bd3787fa3eb78
-60000000480007d5
-3bde00014bffffb8
-418200242c1e0020
-38a564a43ca2ffff
+7a3117647a691764
+3a7300017e3a8a14
+892f00107c6f48ae
+5463063e7c634a78
+893200104bfffcad
+7c71f8ae7c701b78
+5463063e7c634a78
+283300044bfffc95
+7e941a147c638214
+3bde00014082ff88
+283e00037fbda214
+382100d04082fdd8
+48001cfc7fa307b4
+0100000000000000
+3c4c000100001280
+7c0802a63842a2ec
+48001cb538800000
+3f02fffff821ff61
+7c7d1b783b1864b4
+3b8000003bc00000
+480008417f05c378
+7fa3eb7860000000
+2c0300004bfffd31
+57ffd97e7c7f0034
+2c1c000040820068
+3bfeffff41820060
+7ffcfb787ff9fb78
+7fa3eb787fdbf378
+4bfffcfd3b5b0001
+408200702c030000
+7d5fe0507d39d850
+418100687c095000
+4181006c2c1a001f
+38a5646c3ca2ffff
 7fa3eb7838800000
-480007a97ffcfb78
-4bffff5c60000000
-4bffff783be0ffff
-4bffffa07f59d378
-7f3fcb787f7cdb78
-2c1c00004bffff94
-7fc907b440800024
-2129001f3b800000
-418000082c290000
-3bde0001239e001f
-2c1f00007f9cf214
-3c62ffff4080001c
-4bfff3cd38637d70
-382100a060000000
-7cbfe05048001bd4
-7ca50e707c9cfa14
-789bfee27ca50194
-7ca507b43c62ffff
-38637d807f64db78
-4bfff3953be00008
-7f05c37860000000
+480007c97f5bd378
+4bffffb860000000
+2c1e00203bde0001
+3ca2ffff41820024
+3880000038a5646c
+7ffcfb787fa3eb78
+600000004800079d
+3be0ffff4bffff5c
+7f59d3784bffff78
+7f7cdb784bffffa0
+4bffff947f3fcb78
+4080001c2c1c0000
+3b8000002c1e0020
+239e001f41820008
+7f9cf2143bde0001
+4080001c2c1f0000
+38637d603c62ffff
+600000004bfff379
+48001bdc382100a0
+7c9fe2147cbfe050
+7ca501947ca50e70
+3c62ffff789bfee2
+7f64db787ca507b4
+3be0000838637d70
+600000004bfff341
+388000007f05c378
+3bc000007fa3eb78
+60000000480006f5
+4bfff9ed38600064
+418100247c1bf000
+4bfffbd57fa3eb78
+4182ff942c030000
+2c1f00003bffffff
+4bffff844082ffc0
+38a5646c3ca2ffff
 7fa3eb7838800000
-480006f93bc00000
+480006a93bde0001
 3860006460000000
-7c1bf0004bfff9ed
-7fa3eb7841810024
-2c0300004bfffbd5
-3bffffff4182ff94
-4082ffc02c1f0000
-3ca2ffff4bffff84
-3880000038a564a4
-3bde00017fa3eb78
-60000000480006ad
-4bfff9a138600064
-000000004bffffb4
-0000088001000000
-3842a0d03c4c0001
-6529c80039201000
-7d404e2a7c0004ac
-4d820020280a000e
-3940000e7c0802a6
-f821ffa1f8010010
-7d404f2a7c0004ac
-38637d983c62ffff
-600000004bfff2d1
-e801001038210060
-4e8000207c0803a6
+4bffffb44bfff9a1
 0100000000000000
-3c4c000100000080
-392010003842a06c
+3c4c000100000880
+392010003842a104
 7c0004ac6529c800
-280a00017d404e2a
+280a000e7d404e2a
 7c0802a64d820020
-f801001039400001
+f80100103940000e
 7c0004acf821ffa1
 3c62ffff7d404f2a
-4bfff26d38637dc0
+4bfff27d38637d88
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-3842a0083c4c0001
-480019ed7c0802a6
-3f02fffff821ff31
-3ec2ffff3b186574
-3e82ffff3ea2ffff
-3e62ffff3ee2ffff
-3ad67de83b400000
-3a947e003ab57df8
-3a737e083af77b30
-7f05c3787f5f07b4
+3842a0a03c4c0001
+6529c80039201000
+7d404e2a7c0004ac
+4d820020280a0001
+394000017c0802a6
+f821ffa1f8010010
+7d404f2a7c0004ac
+38637db03c62ffff
+600000004bfff219
+e801001038210060
+4e8000207c0803a6
+0100000000000000
+3c4c000100000080
+7c0802a63842a03c
+f821ff31480019f5
+3b18653c3f02ffff
+3ea2ffff3ec2ffff
+3ee2ffff3e82ffff
+3b4000003e62ffff
+3ab57de83ad67dd8
+3af77b003a947df0
+7f5f07b43a737df8
+388000007f05c378
+480005697fe3fb78
+3b60000060000000
+3bc000003b800000
+7fdbf37848000030
+418200e42c1e0007
+38a564f43ca2ffff
 7fe3fb7838800000
-600000004800056d
-3b8000003b600000
-480000303bc00000
-2c1e00077fdbf378
-3ca2ffff418200e4
-3880000038a5652c
-3bde00017fe3fb78
-480005317fbceb78
-7fc507b460000000
-7ec3b3787fe4fb78
-4bfff19d3b200020
-3ca2ffff60000000
-3880000038a564ec
-3ba000007fe3fb78
-60000000480004fd
-4bfff9e97fe3fb78
-7c64003439400000
-5484d97e212300c0
+7fbceb783bde0001
+600000004800052d
+7fe4fb787fc507b4
+3b2000207ec3b378
+600000004bfff149
+38a564b43ca2ffff
+7fe3fb7838800000
+480004f93ba00000
+7fe3fb7860000000
+392000004bfff9e9
+5484d97e7c640034
 418200082c040000
-7d29521439401800
-7ea3ab78788407e0
-4bfff1457fbd4a14
-3ca2ffff60000000
-3880000038a564a4
-480004a97fe3fb78
-3739ffff60000000
-7e83a3784082ffa8
-600000004bfff119
-4bfffc157fe3fb78
-4bfff1057ee3bb78
-7c1ce84060000000
-7f9de3784180ff20
-7f6507b44bffff1c
-7e639b787fe4fb78
-4bfff0dd3bc00000
-7f05c37860000000
+206300c039201800
+7d291a14788407e0
+7fbd4a147ea3ab78
+600000004bfff0f1
+38a5646c3ca2ffff
+7fe3fb7838800000
+60000000480004a5
+4082ffa83739ffff
+4bfff0c57e83a378
+7fe3fb7860000000
+7ee3bb784bfffc1d
+600000004bfff0b1
+4180ff207c1ce840
+4bffff1c7f9de378
+7fe4fb787f6507b4
+3bc000007e639b78
+600000004bfff089
+388000007f05c378
+480004417fe3fb78
+7c1ed80060000000
+7fe3fb7840820030
+7ee3bb784bfffbc5
+600000004bfff059
+3b400001393a0001
+4082fe982c090002
+48001898382100d0
+38a564f43ca2ffff
 7fe3fb7838800000
-6000000048000445
-418000287c1ed800
-4bfffbbd7fe3fb78
-4bfff0ad7ee3bb78
-2c1a000060000000
-3b4000014082002c
-3ca2ffff4bfffe98
-3880000038a5652c
-3bde00017fe3fb78
-60000000480003fd
-382100d04bffffb8
-0000000048001870
-00000d8001000000
-38429e203c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-4bfffd3df821ff91
-3bde64ec3fc2ffff
+480003f13bde0001
+4bffffb060000000
+0100000000000000
+3c4c000100000d80
+7c0802a638429e54
+fbe1fff8fbc1fff0
+f821ff91f8010010
+3fc2ffff4bfffd3d
+388000003bde64b4
+7fc5f37838600000
+60000000480003a5
+3bff653c3fe2ffff
 3860000038800000
-480003a97fc5f378
-3fe2ffff60000000
-388000003bff6574
-7fe5fb7838600000
-600000004800038d
-388000007fc5f378
-4800037938600001
-7fe5fb7860000000
+480003897fe5fb78
+7fc5f37860000000
 3860000138800000
-6000000048000365
-38637e203c62ffff
-600000004bffefd9
-4bfffd294bfffd91
-3860000138210070
-0000000048001800
-0000028001000000
-38429d703c4c0001
-3920082c7c0802a6
-4800175d6529c800
+6000000048000375
+388000007fe5fb78
+4800036138600001
+3c62ffff60000000
+4bffef8538637e10
+4bfffd9160000000
+382100704bfffd29
+4800180838600001
+0100000000000000
+3c4c000100000280
+7c0802a638429da4
+3b80082c4800176d
 3b000002f821ff51
-7f004f2a7c0004ac
-3b20000339200830
-7c0004ac6529c800
-3c62ffff7f204f2a
-38637e303c804000
-4bffef653bc00800
-3b80000160000000
-67dec8004bfffc51
-7f80f72a7c0004ac
-3be00000386003e8
-7c0004ac4bfff5bd
-386003e87fe0f72a
-4bfff5a93f60c800
-7c0004ac7b7b0020
-3b4000047fe0df2a
+7c0004ac679cc800
+392008307f00e72a
+6529c8003b200003
+7f204f2a7c0004ac
+3c8040003c62ffff
+3bc0080038637e20
+600000004bffef11
+4bfffc513b600001
+7c0004ac67dec800
+386003e87f60f72a
+4bfff5bd3be00000
+7fe0f72a7c0004ac
+3b9cf7d4386003e8
+7c0004ac4bfff5a9
+3b4000047fe0e72a
 7c0004ac675ac800
 3ba0100c7fe0d72a
 7c0004ac67bdc800
@@ -1068,47 +1093,47 @@ f8010010fbe1fff8
 66f7c8003920000c
 7d20bf2a7c0004ac
 6063c35038600000
-7c0004ac4bfff54d
+7c0004ac4bfff551
 7c0004ac7fe0ef2a
 3920000e7fe0f72a
 7d20bf2a7c0004ac
-4bfff52938602710
+4bfff52d38602710
 7c0004ac39200200
 7c0004ac7d20ef2a
 3860000f7f00f72a
-7c0004ac4bfff529
+7c0004ac4bfff52d
 7c0004ac7fe0ef2a
 3860000f7f20f72a
-392000064bfff511
+392000064bfff515
 7d20ef2a7c0004ac
-7f80f72a7c0004ac
-4bfff4f53860000f
+7f60f72a7c0004ac
+4bfff4f93860000f
 7c0004ac39200930
 7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff4d9
-392004004bfff4b5
+386000c84bfff4dd
+392004004bfff4b9
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bfff4b538600003
-4bfff491386000c8
-4bfffb694bfffdb9
+4bfff4b938600003
+4bfff495386000c8
+4bfffb6d4bfffdbd
 3c6040003c800020
 600000004800085d
 408200242c030000
 7c0004ac7c691b78
-7c0004ac7f80d72a
-382100b07f80df2a
-480015e47d2307b4
+7c0004ac7f60d72a
+382100b07f60e72a
+480015f07d2307b4
 38a0000038c00000
 3c6040003c800020
 60000000480005e5
-7f80df2a7c0004ac
+7f60e72a7c0004ac
 4bffffd039200001
 0100000000000000
 3c4c000100000980
-6000000038429b5c
-3942802078631764
+6000000038429b94
+3942800878631764
 392900017d2a182e
 7d2a192e552906fe
 3920000139400818
@@ -1116,16 +1141,16 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429b14
-3922802078631764
+6000000038429b4c
+3922800878631764
 7d49192e39400000
 3920000139400814
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429ad4
-3942801878631764
+6000000038429b0c
+3942800078631764
 392900017d2a182e
 7d2a192e5529077e
 3920000139400820
@@ -1133,15 +1158,15 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429a8c
-3922801878631764
+6000000038429ac4
+3922800078631764
 7d49192e39400000
 392000013940081c
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-7c0802a638429a4c
+7c0802a638429a84
 39200001fbe1fff8
 7cac2b783be00804
 67ffc8007d291830
@@ -1151,46 +1176,46 @@ f84100187ca903a6
 e84100184e800421
 7c0004ac39200000
 382100307d20ff2a
-000000004800147c
+0000000048001488
 0000018001000000
-384299e83c4c0001
+38429a203c4c0001
 282303ff7c0802a6
 f821ffa1f8010010
 7c641b7841810028
-38637e603c62ffff
-600000004bffec01
+38637e403c62ffff
+600000004bffebb1
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffebc538637e68
+4bffeb7538637e48
 4bffffc460000000
 786465023d204000
 408000247c234840
 788955647863b282
 38a000667d291850
 7ca92b923c62ffff
-4bffffc838637e78
+4bffffc838637e58
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637e887ca54b92
+38637e687ca54b92
 000000004bffffa4
 0000008001000000
-384299183c4c0001
+384299503c4c0001
 fbe1fff87c0802a6
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-f801001038637e98
-4bffeb25f821ff91
+f801001038637e78
+4bffead5f821ff91
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffeb0d38637ea8
+4bffeabd38637e88
 3821007060000000
-0000000048001344
+0000000048001350
 0000018001000000
 418200242c240000
 786307e07869f842
@@ -1200,14 +1225,14 @@ f801001038637e98
 4bfffff438630001
 0000000000000000
 3c4c000100000000
-7c0802a638429874
+7c0802a6384298ac
 3d40aaaa78840764
 614aaaaa7c691b78
-7f8322144800126d
+7f83221448001279
 f821ffc17884f082
 7c7f1b7839040001
 7c7d1b787d0903a6
-4bffeae142000080
+4bffea9142000080
 7d3fe05060000000
 7929f0823d00aaaa
 392900017feafb78
@@ -1217,12 +1242,12 @@ f821ffc17884f082
 7feafb787929f082
 6108555539290001
 420000587d2903a6
-4bffea917fffe050
+4bffea417fffe050
 7bfff08260000000
 395f00013d205555
 7d4903a661295555
 3821004042000040
-480012207fc307b4
+4800122c7fc307b4
 3929000491490000
 812a00004bffff78
 418200087c094000
@@ -1234,44 +1259,44 @@ f821ffc17884f082
 4bffffac3bbd0004
 0100000000000000
 3c4c000100000480
-7d60002638429764
+7d6000263842979c
 916100087c0802a6
-480011452e260000
+480011512e260000
 7c7f1b78f821ff41
 7cde33787cba2b78
-419200c0789cf082
+419200e4789cf082
 82e6000081260004
-408200442c090000
-3ba000003f02ffff
-7bf900203b600001
-7c3ce8403b187eb0
-3c62ffff4082009c
-38637eb07b851028
-4bfffde57be40020
-38637b303c62ffff
-600000004bffe929
-600000004bffe98d
+418200d82c090000
+600000004bffe97d
 7ffbfb782d970000
 3ac000013ba00000
 7bf500203b200000
-7fb8eb787c3de040
-2c17000040820084
+7fb8eb787c3ce840
+2c170000408200c4
 3c62ffff41820028
-38637ec07b051028
-4bfffd8d7be40020
-38637b303c62ffff
-600000004bffe8d1
+38637ea07b051028
+4bfffdcd7be40020
+38637b003c62ffff
+600000004bffe8c1
 7f2307b4382100c0
 7d61812081610008
-3ae00001480010c0
-7b6300204bffff50
-4bfffdb57f44d378
+7b6300204800110c
+4bfffdfd7f44d378
 7c7f492e7ba91764
 7c7b1b7873a97fff
 7ba5102840820014
 7f03c3787f24cb78
-3bbd00014bfffd31
-7f44d3784bffff2c
+3bbd00014bfffd79
+4082ffc87c3ce840
+7b8510283c62ffff
+7be4002038637e90
+3c62ffff4bfffd59
+4bffe84d38637b00
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187e907bf90020
+7f44d3784bffffb8
 4bfffd7d7ac30020
 7c651b78809b0000
 7c0320407c761b78
@@ -1282,29 +1307,29 @@ e8de00107d8903a6
 f841001878840020
 4e8004217b630020
 2c030000e8410018
-73187fff4082ff58
+73187fff4082ff18
 418e00184082001c
 7ba510283c62ffff
-38637ec07ea4ab78
+38637ea07ea4ab78
 3bbd00014bfffcb1
-4bfffef43b7b0004
+4bfffeb43b7b0004
 0300000000000000
 3c4c000100000b80
-7d708026384295a4
+7d708026384295dc
 916100087c0802a6
-f821ff7148000f9d
+f821ff7148000fa9
 3ba4ffe07cdb3378
 7c7f1b782e3b0000
 7fa3ea147c9e2378
 3c62ffff7c641b78
-7cbc2b7838637ed0
-600000004bffe7a1
-38637ee83c62ffff
+7cbc2b7838637eb0
+600000004bffe751
+38637ec83c62ffff
 3c62ffff4092000c
-4bffe78538637ef8
+4bffe73538637ed8
 7fc3f37860000000
 3c62ffff4bfffb59
-4bffe76d38637f08
+4bffe71d38637ee8
 2c3c000060000000
 7cf602a6408200a8
 38bd002038df0020
@@ -1320,14 +1345,14 @@ f90a0018f90a0010
 639ce10078ea0020
 7f9ee1d279290020
 3c62ffff7d295050
-7f9c4b9238637f10
-600000004bffe6e9
+7f9c4b9238637ef0
+600000004bffe699
 4bfffabd7f83e378
-38637f203c62ffff
-600000004bffe6d1
-38637b303c62ffff
-600000004bffe6c1
-600000004bffe725
+38637f003c62ffff
+600000004bffe681
+38637b003c62ffff
+600000004bffe671
+600000004bffe6d5
 409200487f9602a6
 395f00207d3fe850
 7929d9423bbd0020
@@ -1344,16 +1369,16 @@ e95f0018e95f0010
 7b9c00203d4005f5
 79290020614ae100
 7d29e0507fde51d2
-38637f283c62ffff
-4bffe6257fde4b92
+38637f083c62ffff
+4bffe5d57fde4b92
 7fc3f37860000000
 3c62ffff4bfff9f9
-4bffe60d38637f20
+4bffe5bd38637f00
 3c62ffff60000000
-4bffe5fd38637b30
+4bffe5ad38637b00
 3821009060000000
 7d70812081610008
-7fa407b448000e04
+7fa407b448000e10
 4bfffaed79430020
 7d23db963bbd0001
 7d29d9d67c6a1b78
@@ -1361,16 +1386,16 @@ e95f0018e95f0010
 4bffff687d3f482a
 0300000000000000
 3c4c000100000680
-7c0802a63842936c
-48000d7128240200
+7c0802a6384293a4
+48000d7d28240200
 7c7e1b78f821ff81
 3b8002007c9f2378
 7c9c237841810008
 7fc4f3783c62ffff
-4bffe57538637f38
+4bffe52538637f18
 7fe3fb7860000000
 3c62ffff4bfff949
-4bffe55d38637f08
+4bffe50d38637ee8
 7f84e37860000000
 4bfffaa17fc3f378
 38a0000138c00000
@@ -1379,55 +1404,55 @@ e95f0018e95f0010
 7c7e1b787d23ea14
 418200802c090000
 7b85f8823c62ffff
-38637f487fa4eb78
-600000004bffe511
+38637f287fa4eb78
+600000004bffe4c1
 7fe5fb78283f8000
 38a0ffff4081000c
 3c62ffff54a50420
 3880000078a5f082
-4bffe4e538637f60
+4bffe49538637f40
 3c62ffff60000000
 7fc4f3787be5f082
-4bffe4cd38637f78
+4bffe47d38637f58
 3c62ffff60000000
-4bffe4bd38637f90
+4bffe46d38637f70
 3860000060000000
 786307e038210080
-3c62ffff48000ccc
-4bffe49d38637fa0
+3c62ffff48000cd8
+4bffe44d38637f80
 3860000160000000
 000000004bffffe0
 0000048001000000
-384292403c4c0001
-8922803060000000
-3942802860000000
+384292783c4c0001
+8922801860000000
+3942801060000000
 418200302c090000
 39290014e92a0000
 7d204eaa7c0004ac
 4182ffec71290020
-e922802860000000
+e922801060000000
 7c604faa7c0004ac
 e92a00004e800020
 7c0004ac39290010
 712900087d204eea
 5469063e4082ffec
-e942802860000000
+e942801060000000
 7d2057ea7c0004ac
 000000004e800020
 0000000000000000
-384291b83c4c0001
+384291f03c4c0001
 fbe1fff87c0802a6
 3be3fffffbc1fff0
 f821ffd1f8010010
 2c1e00008fdf0001
 3821003040820010
-48000c0438600000
+48000c1038600000
 4082000c2c1e000a
 4bffff3d3860000d
-4bffff3557c3063e
+4bffff357bc30020
 000000004bffffd0
 0000028001000000
-384291583c4c0001
+384291903c4c0001
 654ac00039400020
 7d4056ea7c0004ac
 794a060039200008
@@ -1438,377 +1463,378 @@ f821ffd1f8010010
 7929f8047d204eea
 79290fc339002000
 600000006508c000
-3d00001cf9028028
+3d00001cf9028010
 7d4a439261082000
 6000000041820080
-9922803039200001
+9922801839200001
 3920ff803900200c
 7c0004ac6508c000
-e92280287d2047aa
+e92280107d2047aa
 7d404faa7c0004ac
-794ac202e9228028
+794ac202e9228010
 7c0004ac39290004
-e92280287d404faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e9228028
+39290010e9228010
 7d404faa7c0004ac
-39400007e9228028
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
 394affff60000000
-3920201899228030
+3920201899228018
 7c0004ac6529c000
 4e8000207d404fea
 0000000000000000
 78a9e8c200000000
 3929000139400000
-420000287d2903a6
-78a5076078a90724
-7d434a1439050001
-7c844a147d0903a6
-4200001839200000
-7d24502a4e800020
-394a00087d23512a
-7d0448ae4bffffcc
-392900017d0a49ae
-000000004bffffdc
-0000000000000000
-386000007c691b78
-2c0a00007d4918ae
-386300014d820020
-000000004bfffff0
-0000000000000000
-408200082c240000
+4200002c7d2903a6
+3940000078a9e8c2
+7ca54a141d29fff8
+390500017c892050
+7d0903a67d291850
+4e80002042000018
+7d23512a7d24502a
+4bffffc8394a0008
+7d0951ae7d0450ae
+4bffffdc394a0001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
+0000000000000000
+2c24000000000000
+408200087c691b78
 280500243881fff0
-38600000f8640000
-3d2000014d810020
-612a2600792983e4
-89090000e9240000
-4181004028080020
-70e700017d474436
-2c25000040820028
-2c050010418200e0
-2c08003040820010
-38a0001041820048
-4800008038600000
-f924000039290001
-2c2500004bffffb8
-2c0800304082ffd4
-4082ffdc38a0000a
-2c0a007889490001
-392900024082ffd0
-4bffffc0f9240000
-2c0a007889490001
-4bffffe84082ffb4
-54e7063e38eaffd0
-4181003c28070009
-7d2a07343929ffd0
-4c8000207c0a2800
-7c6519d239080001
-f90400007d290734
-e90400007c691a14
-714900ff89480000
-4e8000204082ffc0
-54e7063e38eaff9f
-4181000c28070019
-4bffffb83929ffa9
-554a063e394affbf
-4d810020280a0019
-4bffffa03929ffc9
-4bffff3438a0000a
-0000000000000000
-3923ff9f00000000
-4181000828090019
-7c6307b43863ffe0
-000000004e800020
+38600000f9240000
+3d4000014d810020
+614a2600794a83e4
+2808002089090000
+7d47443641810038
+4082002070e70001
+418200d02c250000
+418200282c050010
+386000003929ffff
+3929000148000078
+4bffffc4f9240000
+4082ffdc2c250000
+2c08003038a0000a
+894900014082ffd8
+4082ffcc2c0a0078
+38a0001039290002
+4bffffbcf9240000
+54e7063e38e8ffd0
+4181004028070009
+7d480734394affd0
+4c8000207c082800
+392900027c6519d2
+f92400007d4a0734
+7c6a1a147cc93378
+38c9000189090001
+4082ffbc710a00ff
+38e8ff9f4e800020
+2807001954e7063e
+394affa94181000c
+3908ffbf4bffffb4
+280800195508063e
+394affc94d810020
+38a0000a4bffff9c
+000000004bffff38
+0000000000000000
+280900193923ff9f
+3863ffe041810008
+4e8000207c6307b4
 0000000000000000
-38428e583c4c0001
-480008557c0802a6
-7c7e1b78f821ffa1
-7ca32b787cfd3b78
-38a0000a7c9c2378
-eb3e000038800000
-7d1b43787cdf3378
-4bfffe657d3a4b78
-2b9d001060000000
-2c3f000039400000
-2c0a00004082005c
-3940000140820008
-7c0350007d4ad214
-7d2350504081003c
-792900207d2948f8
-7d2903a639290001
-7d594850e93e0000
-408000187c2ae040
-e93e00009b690000
-f93e000039290001
-382100604200ffe0
-409e001048000808
-394a00017bffe102
-7fffeb924bffff94
-000000004bfffff4
-0000078001000000
-38428d883c4c0001
-4800078d7c0802a6
-eb630000f821ffb1
-7c9c23787c7f1b78
-3bc000007cbd2b78
-4bfffd7d7fa3eb78
-7c3e184060000000
-e93f000040800014
-7c2ae0407d5b4850
-382100504180000c
-7d5df0ae48000798
-994900003bde0001
-39290001e93f0000
-4bffffbcf93f0000
+3c4c000100000000
+7c0802a638428e9c
+f821ffa14800086d
+7cfd3b787c7e1b78
+7c9c23787ca32b78
+3880000038a0000a
+7cdf3378eb3e0000
+7d3a4b787d1b4378
+600000004bfffe75
+394000002b9d0010
+4082005c2c3f0000
+418100082c0a0000
+7d4ad21439400001
+4081003c7c035000
+394affff7d4a1850
+392a0001794a0020
+e93e00007d2903a6
+7c2ae0407d594850
+9b69000040800018
+39290001e93e0000
+4200ffe0f93e0000
+4800082038210060
+7bffe102409e0010
+4bffff94394a0001
+4bfffff47fffeb92
 0100000000000000
-3c4c000100000580
-7c0802a638428d0c
-e9297fb03d22ffff
-7d7080262b860010
-916100087caa2b78
-f821ffa1480006f5
+3c4c000100000780
+7c0802a638428dcc
+f821ffb1480007a5
+7c7f1b78eb630000
+7cbd2b787c9c2378
+7fa3eb783bc00000
+600000004bfffd8d
+408000147c3e1840
+7d5b4850e93f0000
+4180000c7c2ae040
+480007b038210050
+3bde00017d5df0ae
+e93f000099490000
+f93f000039290001
+000000004bffffbc
+0000058001000000
+38428d503c4c0001
+3d22ffff7c0802a6
+2b860010e9297f90
+916100087d708026
+f821ffa148000711
 7cbe2b787c7c1b78
 3be000007cdd3378
 3d22fffff9210020
-f9210028e9297fb8
-408200342c2a0000
-408200082c1f0000
-7fff07b43be00001
-7c3f20402e270000
-408100303b7fffff
-8161000838210060
-480006e87d708120
-794ae102409e0010
-4bffffbc3bff0001
-4bfffff47d4aeb92
-7f5eeb927f5ed378
-7d29f0507d3ae9d2
-886900207d214a14
-5463063e41920010
-600000004bfffdd5
-e93c00007c3df040
-3b7bffff7c69d9ae
-e93c00004081ffc8
-f93c00007d29fa14
-000000004bffff90
-0000068003000000
-38428c183c4c0001
-480005e97c0802a6
-7c761b79f821fef1
-38600000f8610060
-2c2400004182003c
-3b04ffff41820034
-3a8000003aa10040
-ebc1006089250000
-7c76f050712a00ff
-7c23c0404182000c
-3920000041800018
-38210110993e0000
-480005e07c6307b4
-390500012c0a0025
-3920000040820564
-7cb32b7889450000
-7d49a9ae8ce50001
-280a007854ea063e
-280a006241810024
-2c0a004f41810024
-2c0a0058418200a0
-2c0a002541820098
-3929000141820090
-3907ff9d4bffffc0
-280400155504063e
-3c82ffff4181ffec
-790815a8388474d0
-7d0822147d0442aa
-4e8004207d0903a6
-0000005800000058
-ffffffccffffffcc
-ffffffccffffffcc
-ffffffcc00000058
-ffffffccffffffcc
-ffffffccffffffcc
-0000005800000058
-ffffffccffffffcc
-ffffffcc00000058
-ffffffcc00000058
-00000058ffffffcc
-2c0a002539090001
-38a1002039290002
-7d2907b47d0807b4
-7d254a147d054214
-9a89002098e80020
+f9210028e9297f98
+2c2900007ca92b78
+2c1f000040820034
+3be0000141810008
+2e2700007fff07b4
+3b7fffff7c3f2040
+3821006040810030
+7d70812081610008
+409e001048000700
+3bff00017929e102
+7d29eb924bffffbc
+7f5ed3784bfffff4
+7d3ae9d27f5eeb92
+7d214a147d29f050
+4192001088690020
+4bfffdd55463063e
+7c3df04060000000
+7c69d9aee93c0000
+4081ffc83b7bffff
+7d29fa14e93c0000
+4bffff90f93c0000
+0300000000000000
+3c4c000100000680
+7c0802a638428c5c
+f821fef148000601
+f86100607c751b79
+4182004438600000
+4182003c2c240000
+3ae4ffff7cbd2b78
+3b2100203a610040
+895d00003a400000
+714900ffebc10060
+4182000c7c75f050
+418000187c23b840
+993e000039200000
+7c6307b438210110
+2c090025480005f0
+40820574391d0001
+7d4999ae39200000
+389d0001895d0001
+280800785548063e
+2808006241810024
+2c08004f41810028
+2c080058418200a4
+2c0800254182009c
+3929000141820094
+4bffffc07c9d2378
+54e5063e38eaff9d
+4181ffe828050015
+38a574943ca2ffff
+7ce53aaa78e715a8
+7ce903a67ce72a14
+000000584e800420
+ffffffc800000058
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc800000058
+00000058ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+38e9000100000058
+392900022c080025
+7d2907b47ce707b4
+7d394a147cf93a14
+9a49002099470020
 393e000140820018
-f9210060995e0000
-4bfffebc38b30002
+995e0000f9210060
+4bfffec03bbd0002
 eb86000089210041
-3a2600087fe3c050
-3b4100423a400030
+3a2600087fe3b850
+3b4100423a800030
 712900fd3929ffd2
-5649063e40820428
-3ae000003de2ffff
-f92100683b200004
+5689063e4082043c
+3ac000003de2ffff
+f92100683b000004
 3a0000003b600000
-4800017039ef7fd0
-38da00012c07004f
-390affa8418201dc
-280500225505063e
-3ca2ffff418103bc
-790815a838a575e8
-7d082a147d0542aa
-4e8004207d0903a6
-0000039c00000158
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-000002680000039c
-0000039c0000008c
-0000039c0000039c
-0000008c00000380
-0000039c0000039c
-0000039c00000368
-000001ac0000039c
-0000039c00000204
-000002ac0000039c
-0000008c0000039c
-0000039c0000039c
-0000039c0000015c
-2c070075000003c0
+4800016c39ef7fb8
+38ba00012c06004f
+38e8ffa8418201e0
+2804002254e4063e
+3c82ffff418103d0
+78e715a8388475a8
+7ce722147ce43aaa
+4e8004207ce903a6
+000003b000000154
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+00000270000003b0
+000003b00000008c
+000003b0000003b0
+0000008c00000394
+000003b0000003b0
+000003b00000037c
+000001b0000003b0
+000003b00000020c
+000002b4000003b0
+0000008c000003b0
+000003b0000003b0
+000003b000000158
+2c060075000003d4
 7d4152147b6a0020
-7f9de37839000000
+7f8ee37839000000
 41820044990a0020
-3940000157281838
-7d4a40363908ffff
-4182002c7f8a5039
+3900000157071838
+7d08383638e7ffff
+4182002c7f884039
 392900013940002d
-9949ffff7fbc00d0
-f92100603d42ffff
-394a7fd07b291e68
-7fbd48387d2a482a
-38e0000ae8810060
-38a100207fa6eb78
-5648063e39200000
-7c9e205038610060
-4bfffabd7c84f850
-7ae707e0e8810060
-7fa5eb7838c0000a
-7c84f8507c9e2050
-4bfffbe938610060
-895a00003b5a0001
-714700ffe9210060
-7fbe485041820010
-4181fe7c7c3fe840
-4bfffe247e268b78
-7b6900203ae00001
-38e00010e9010068
-7c9df8507d214a14
-3861006038a10020
-7b291e689a090020
-392000007d4f482a
-7dc673787f8e5038
-e88100604bfffa39
-38c000107ae707e0
-7dc573787c9e2050
-7b6900204bffff7c
-7d214a1439400000
-7c9df85038e00008
-994900205648063e
-7b291e683d42ffff
-38a10020394a7fd0
-7d4a482a38610060
-7f8e503839200000
-4bfff9dd7dc67378
-7ae707e0e8810060
+7b081e683ce2ffff
+9949ffff38e77fb8
+7d5c00d0f9210060
+7d4e40387d07402a
+38e0000a7c9e4850
+7f25cb787dc67378
+392000007c84f850
+386100605688063e
+e88100604bfffabd
+38c0000a7ac707e0
+7c9e20507dc57378
+386100607c84f850
+3b5a00014bfffbe9
+e9210060891a0000
+41820010710600ff
+7c3f70407dde4850
+7e268b784181fe80
+3ac000014bfffe28
+e90100687b690020
+7d214a1438e00010
+7f25cb787c8ef850
+9a09002038610060
+7d6f482a7b091e68
+7f8b583839200000
+f96100707d665b78
+e88100604bfffa35
+38c000107ac707e0
+e96100707c9e2050
+4bffff747d655b78
+390000007b690020
+38e000087d214a14
+7f25cb787c8ef850
+3d02ffff99090020
+39087fb87b091e68
+7d68482a38610060
+5688063e39200000
+7d665b787f8b5838
+4bfff9d1f9610070
+7ac707e0e8810060
 7c9e205038c00008
-7b6900204bffffa4
-7d214a1439400000
+7b6900204bffff9c
+7d214a1439000000
 7f86e37838e00010
-9949002039000020
-3920000238a10020
-386100607c9df850
-e88100604bfff999
+990900207f25cb78
+392000027c8ef850
+3861006039000020
+e88100604bfff98d
 386100603ca2ffff
-7c9e205038a57fc8
-4bfffa4d7c84f850
-7ae707e0e8810060
+7c9e205038a57fa8
+4bfffa417c84f850
+7ac707e0e8810060
 7f85e37838c00010
-4bfffec07c9e2050
-394000007b690020
-390000207d214a14
-38c0000138e0000a
-38a1002099490020
-7c9df85039200000
-4bfff93538610060
+4bfffeb47c9e2050
+390000007b690020
+38e0000a7d214a14
+7f25cb7838c00001
+7c8ef85099090020
+3900002039200000
+4bfff92938610060
 9b890000e9210060
 f921006039290001
-7b6a00204bfffe88
-f921007039000000
-38a0000a7d415214
-3861002038800000
-4bfff795990a0020
-7c6e1b7860000000
-4bfff75d7f83e378
-7c2e184060000000
-e921007040810048
-7c6370507fbdf850
-38e0002039400000
-7d09f0503bbd0001
-7d08fa147c691a14
-408200082c280000
-2c3d00013ba00001
-408200283bbdffff
-40820034714a0001
-7f85e378e8810060
-7c9e205038610060
-4bfff9557c84f850
-98e900004bfffde8
-3940000139290001
-4082ffc07c291840
-4bffffccf9210060
-3b200008893a0001
-4082fdbc2c09006c
-4bfffdb47cda3378
-3b200002893a0001
-4082fda42c090068
-3b2000017cda3378
-392affd04bfffd98
-280900095529063e
-7b6900204181fd88
-7d214a143b7b0001
-4bfffd7499490020
-4bfffd6c3b200008
-3b4100413a400020
-993e00004bfffbd4
-7d0543783bde0001
-4bfffa54fbc10060
-0100000000000000
-f9c1ff7000001280
-fa01ff80f9e1ff78
-fa41ff90fa21ff88
-fa81ffa0fa61ff98
-fac1ffb0faa1ffa8
-fb01ffc0fae1ffb8
-fb41ffd0fb21ffc8
-fb81ffe0fb61ffd8
-fbc1fff0fba1ffe8
-f8010010fbe1fff8
-e9c1ff704e800020
-ea01ff80e9e1ff78
-ea41ff90ea21ff88
-ea81ffa0ea61ff98
-eac1ffb0eaa1ffa8
-eb01ffc0eae1ffb8
-eb41ffd0eb21ffc8
-eb81ffe0eb61ffd8
-eba1ffe8e8010010
-ebc1fff07c0803a6
-4e800020ebe1fff8
-e8010010ebc1fff0
-7c0803a6ebe1fff8
-600000004e800020
+7b6800204bfffe7c
+f921007838e00000
+38a0000a7d014214
+7f23cb7838800000
+4bfff79998e80020
+f861007060000000
+4bfff7617f83e378
+e901007060000000
+7c281840e9210078
+7d244b7841810020
+7f85e3787c9e2050
+386100607c84f850
+4bfffe184bfff985
+7c6340507ce9f050
+7d4ef8507ce7fa14
+7c691a142c270000
+390000007d244b78
+394a000138c00020
+3940000140820008
+394affff2c2a0001
+7108000140820010
+4bffffa04082001c
+3884000198c40000
+7c24184039000001
+f88100604082ffd8
+893a00014bffff88
+2c09006c3b000008
+7cba2b784082fda4
+893a00014bfffd9c
+2c0900683b000002
+7cba2b784082fd8c
+4bfffd803b000001
+5529063e3928ffd0
+4181fd7028090009
+3b7b00017b690020
+990900207d214a14
+3b0000084bfffd5c
+3a8000204bfffd54
+4bfffbc03b410041
+3bde0001995e0000
+fbc100607d1d4378
+000000004bfffa44
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
+eb21ffc8eb01ffc0
+eb61ffd8eb41ffd0
+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1853,14 +1879,18 @@ e8010010ebc1fff0
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1921,15 +1951,13 @@ e8010010ebc1fff0
 000000000000207c
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
@@ -1971,11 +1999,12 @@ e8010010ebc1fff0
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v
index 6125302..ea9fd89 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:09
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:45
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -83,15 +83,15 @@ LiteDRAMCore
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [FDCE]
+│    │    └─── [PLLE2_ADV]
+│    │    └─── [BUFG]
 │    │    └─── [BUFG]
 │    │    └─── [BUFG]
 │    │    └─── [BUFG]
-│    │    └─── [PLLE2_ADV]
-│    │    └─── [FDCE]
-│    │    └─── [FDCE]
 │    └─── idelayctrl (S7IDELAYCTRL)
 │    │    └─── [IDELAYCTRL]
 └─── ddrphy (A7DDRPHY)
@@ -136,103 +136,103 @@ LiteDRAMCore
 │    └─── bitslip_35* (BitSlip)
 │    └─── tappeddelayline_2* (TappedDelayLine)
 │    └─── tappeddelayline_3* (TappedDelayLine)
-│    └─── [IDELAYE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [OBUFDS]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [ISERDESE2]
-│    └─── [IOBUFDS]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IOBUFDS]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
+│    └─── [OBUFDS]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
@@ -545,6 +545,7 @@ wire   [29:0] builder_interface0_adr;
 wire   [13:0] builder_interface0_bank_bus_adr;
 reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_re;
 wire          builder_interface0_bank_bus_we;
 wire    [1:0] builder_interface0_bte;
 wire    [2:0] builder_interface0_cti;
@@ -561,17 +562,22 @@ reg           builder_interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] builder_interface1_bank_bus_adr;
 reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_re;
 wire          builder_interface1_bank_bus_we;
 wire   [31:0] builder_interface1_dat_r;
 reg    [31:0] builder_interface1_dat_w = 32'd0;
 reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
 reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_re = 1'd0;
+reg           builder_interface1_re_next_value2 = 1'd0;
+reg           builder_interface1_re_next_value_ce2 = 1'd0;
 reg           builder_interface1_we = 1'd0;
-reg           builder_interface1_we_next_value2 = 1'd0;
-reg           builder_interface1_we_next_value_ce2 = 1'd0;
+reg           builder_interface1_we_next_value3 = 1'd0;
+reg           builder_interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] builder_interface2_bank_bus_adr;
 reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_re;
 wire          builder_interface2_bank_bus_we;
 reg           builder_locked0 = 1'd0;
 reg           builder_locked1 = 1'd0;
@@ -596,6 +602,7 @@ reg           builder_new_master_wdata_ready0 = 1'd0;
 reg           builder_new_master_wdata_ready1 = 1'd0;
 reg     [1:0] builder_next_state = 2'd0;
 wire          builder_pll_fb;
+wire          builder_re;
 reg     [1:0] builder_refresher_next_state = 2'd0;
 reg     [1:0] builder_refresher_state = 2'd0;
 wire          builder_reset0;
@@ -702,14 +709,14 @@ reg           builder_t_self3 = 1'd0;
 reg           builder_t_self4 = 1'd0;
 reg           builder_t_self5 = 1'd0;
 wire          builder_we;
-wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0;
 wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1;
 wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2;
 wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3;
 wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
@@ -1897,9 +1904,9 @@ reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [15:0] main_litedramcore_csr_dfi_p0_address;
 wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
 reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_cke;
 reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_odt;
 reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p0_rddata_en;
@@ -1913,9 +1920,9 @@ reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [15:0] main_litedramcore_csr_dfi_p1_address;
 wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
 reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_cke;
 reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_odt;
 reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p1_rddata_en;
@@ -1929,9 +1936,9 @@ reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
 wire   [15:0] main_litedramcore_csr_dfi_p2_address;
 wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
 reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_cke;
 reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_odt;
 reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p2_rddata_en;
@@ -1945,9 +1952,9 @@ reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
 wire   [15:0] main_litedramcore_csr_dfi_p3_address;
 wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
 reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_cke;
 reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_odt;
 reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p3_rddata_en;
@@ -3865,42 +3872,6 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_
 assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
 assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
 assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
-always @(*) begin
-    main_litedramcore_master_p3_ras_n <= 1'd1;
-    if (main_litedramcore_sel) begin
-        if (main_litedramcore_ext_dfi_sel) begin
-            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
-        end else begin
-            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
-        end
-    end else begin
-        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
-    end
-end
-always @(*) begin
-    main_litedramcore_master_p3_we_n <= 1'd1;
-    if (main_litedramcore_sel) begin
-        if (main_litedramcore_ext_dfi_sel) begin
-            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
-        end else begin
-            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
-        end
-    end else begin
-        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
-    end
-end
-always @(*) begin
-    main_litedramcore_master_p3_cke <= 1'd0;
-    if (main_litedramcore_sel) begin
-        if (main_litedramcore_ext_dfi_sel) begin
-            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
-        end else begin
-            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
-        end
-    end else begin
-        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
-    end
-end
 always @(*) begin
     main_litedramcore_master_p3_odt <= 1'd0;
     if (main_litedramcore_sel) begin
@@ -4766,41 +4737,61 @@ always @(*) begin
     end
 end
 always @(*) begin
-    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
+    main_litedramcore_master_p3_ras_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n;
+        end else begin
+            main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+        end
+    end else begin
+        main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n;
+    end
 end
 always @(*) begin
-    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
+    main_litedramcore_master_p3_we_n <= 1'd1;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n;
+        end else begin
+            main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+        end
+    end else begin
+        main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n;
+    end
 end
 always @(*) begin
-    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
+    main_litedramcore_master_p3_cke <= 1'd0;
+    if (main_litedramcore_sel) begin
+        if (main_litedramcore_ext_dfi_sel) begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke;
+        end else begin
+            main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+        end
+    end else begin
+        main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke;
+    end
 end
+assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt;
 assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
+    end else begin
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4833,20 +4824,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector0_command_issue_re) begin
-        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
-    end else begin
-        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
 assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
 assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
+    end else begin
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4879,20 +4870,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector1_command_issue_re) begin
-        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
-    end else begin
-        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
 assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
 assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
+    end else begin
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4925,20 +4916,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
-    end else begin
-        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
 assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
 assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
+    end else begin
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4971,14 +4962,6 @@ always @(*) begin
         main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector3_command_issue_re) begin
-        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
-    end else begin
-        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
 assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
@@ -5086,22 +5069,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_sequencer_start0 <= 1'd0;
-    case (builder_refresher_state)
-        1'd1: begin
-            if (main_litedramcore_cmd_ready) begin
-                main_litedramcore_sequencer_start0 <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_cmd_valid <= 1'd0;
     case (builder_refresher_state)
@@ -5168,6 +5135,22 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
+        1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
 assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
@@ -5308,78 +5291,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine0_source_source_valid) begin
-                    if (main_litedramcore_bankmachine0_row_opened) begin
-                        if (main_litedramcore_bankmachine0_row_hit) begin
-                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine0_trccon_ready) begin
-                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
@@ -5739,6 +5651,77 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
 assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
@@ -5878,82 +5861,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine1_source_source_valid) begin
-                    if (main_litedramcore_bankmachine1_row_opened) begin
-                        if (main_litedramcore_bankmachine1_row_hit) begin
-                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
-                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine1_source_source_valid) begin
-                    if (main_litedramcore_bankmachine1_row_opened) begin
-                        if (main_litedramcore_bankmachine1_row_hit) begin
-                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
     case (builder_bankmachine1_state)
@@ -6310,45 +6217,121 @@ always @(*) begin
         end
     endcase
 end
-assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
-assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
-assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
-assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
-assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
-assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
-assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
-assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
-assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
-assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[22:7]);
-assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
-always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
-    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
-        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7];
-    end else begin
-        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
-    end
-end
-assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
-assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
-assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
 always @(*) begin
-    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
-    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
-        if ((main_litedramcore_bankmachine2_source_payload_addr[22:7] != main_litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin
-            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+    main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
         end
-    end
-end
-assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
-assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
-assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
-assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                                main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[22:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+    main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
+    if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7];
+    end else begin
+        main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+    end
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+always @(*) begin
+    main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+    if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin
+        if ((main_litedramcore_bankmachine2_source_payload_addr[22:7] != main_litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin
+            main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+        end
+    end
+end
+assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable;
 assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid;
 assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first;
 assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last;
@@ -6450,7 +6433,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6458,7 +6441,7 @@ always @(*) begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_open <= 1'd1;
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6476,19 +6459,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6506,7 +6483,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine2_source_source_valid) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
-                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6517,41 +6494,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_row_close <= 1'd0;
-    case (builder_bankmachine2_state)
-        1'd1: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -6569,9 +6523,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -6593,7 +6550,10 @@ always @(*) begin
                 if (main_litedramcore_bankmachine2_source_source_valid) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
-                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -6604,21 +6564,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6633,12 +6594,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -6661,8 +6619,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
                             if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6674,22 +6632,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6700,11 +6651,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6729,8 +6695,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
                             if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
                             end else begin
-                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6742,7 +6708,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6767,8 +6733,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
                             if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -6780,7 +6746,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6789,6 +6755,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -6799,32 +6768,49 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine2_source_source_valid) begin
-                    if (main_litedramcore_bankmachine2_row_opened) begin
-                        if (main_litedramcore_bankmachine2_row_hit) begin
-                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
             end
         end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6842,10 +6828,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine2_source_source_valid) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
-                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6856,18 +6839,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7020,32 +7003,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine3_state)
@@ -7360,15 +7317,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
     case (builder_bankmachine3_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_row_open <= 1'd1;
+                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -7382,22 +7342,57 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine3_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
     case (builder_bankmachine3_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -7411,34 +7406,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine3_source_source_valid) begin
-                    if (main_litedramcore_bankmachine3_row_opened) begin
-                        if (main_litedramcore_bankmachine3_row_hit) begin
-                            main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine3_row_close <= 1'd0;
+    main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine3_state)
         1'd1: begin
-            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine3_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -7522,146 +7505,75 @@ assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_
 assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready;
 assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first;
 assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last;
-assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
-assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
-assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
-assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
-assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
-assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
-assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
-assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
-always @(*) begin
-    builder_bankmachine4_next_state <= 4'd0;
-    builder_bankmachine4_next_state <= builder_bankmachine4_state;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-                if (main_litedramcore_bankmachine4_cmd_ready) begin
-                    builder_bankmachine4_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-                builder_bankmachine4_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine4_trccon_ready) begin
-                if (main_litedramcore_bankmachine4_cmd_ready) begin
-                    builder_bankmachine4_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
-                builder_bankmachine4_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            builder_bankmachine4_next_state <= 3'd6;
-        end
-        3'd6: begin
-            builder_bankmachine4_next_state <= 2'd3;
-        end
-        3'd7: begin
-            builder_bankmachine4_next_state <= 4'd8;
-        end
-        4'd8: begin
-            builder_bankmachine4_next_state <= 1'd0;
-        end
-        default: begin
-            if (main_litedramcore_bankmachine4_refresh_req) begin
-                builder_bankmachine4_next_state <= 3'd4;
-            end else begin
-                if (main_litedramcore_bankmachine4_source_source_valid) begin
-                    if (main_litedramcore_bankmachine4_row_opened) begin
-                        if (main_litedramcore_bankmachine4_row_hit) begin
-                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
-                                builder_bankmachine4_next_state <= 2'd2;
-                            end
-                        end else begin
-                            builder_bankmachine4_next_state <= 1'd1;
-                        end
-                    end else begin
-                        builder_bankmachine4_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we;
+assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready;
+assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first;
+assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last;
+assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
 always @(*) begin
-    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    builder_bankmachine4_next_state <= 4'd0;
+    builder_bankmachine4_next_state <= builder_bankmachine4_state;
     case (builder_bankmachine4_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                builder_bankmachine4_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                if (main_litedramcore_bankmachine4_cmd_ready) begin
+                    builder_bankmachine4_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+                builder_bankmachine4_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine4_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine4_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine4_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine4_next_state <= 1'd0;
         end
         default: begin
             if (main_litedramcore_bankmachine4_refresh_req) begin
+                builder_bankmachine4_next_state <= 3'd4;
             end else begin
                 if (main_litedramcore_bankmachine4_source_source_valid) begin
                     if (main_litedramcore_bankmachine4_row_opened) begin
                         if (main_litedramcore_bankmachine4_row_hit) begin
-                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
-                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-                            end else begin
+                            if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+                                builder_bankmachine4_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine4_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine4_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine4_trccon_ready) begin
-                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine4_state)
@@ -8023,6 +7935,77 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
 assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
@@ -8083,155 +8066,79 @@ always @(*) begin
 end
 assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din;
 assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace));
-assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
-assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
-assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
-assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
-assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
-assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
-assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
-assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
-assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
-assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
-assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
-assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
-assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
-assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
-assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
-assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
-assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
-assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
-always @(*) begin
-    builder_bankmachine5_next_state <= 4'd0;
-    builder_bankmachine5_next_state <= builder_bankmachine5_state;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                if (main_litedramcore_bankmachine5_cmd_ready) begin
-                    builder_bankmachine5_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                builder_bankmachine5_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                if (main_litedramcore_bankmachine5_cmd_ready) begin
-                    builder_bankmachine5_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-                builder_bankmachine5_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            builder_bankmachine5_next_state <= 3'd6;
-        end
-        3'd6: begin
-            builder_bankmachine5_next_state <= 2'd3;
-        end
-        3'd7: begin
-            builder_bankmachine5_next_state <= 4'd8;
-        end
-        4'd8: begin
-            builder_bankmachine5_next_state <= 1'd0;
-        end
-        default: begin
-            if (main_litedramcore_bankmachine5_refresh_req) begin
-                builder_bankmachine5_next_state <= 3'd4;
-            end else begin
-                if (main_litedramcore_bankmachine5_source_source_valid) begin
-                    if (main_litedramcore_bankmachine5_row_opened) begin
-                        if (main_litedramcore_bankmachine5_row_hit) begin
-                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-                                builder_bankmachine5_next_state <= 2'd2;
-                            end
-                        end else begin
-                            builder_bankmachine5_next_state <= 1'd1;
-                        end
-                    end else begin
-                        builder_bankmachine5_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine5_source_source_valid) begin
-                    if (main_litedramcore_bankmachine5_row_opened) begin
-                        if (main_litedramcore_bankmachine5_row_hit) begin
-                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
-                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
+assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re);
+assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume;
+assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r;
+assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16);
+assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid;
+assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we;
+assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready;
+assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first;
+assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last;
+assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
 always @(*) begin
-    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    builder_bankmachine5_next_state <= 4'd0;
+    builder_bankmachine5_next_state <= builder_bankmachine5_state;
     case (builder_bankmachine5_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
+            end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
             if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
                 if (main_litedramcore_bankmachine5_source_source_valid) begin
                     if (main_litedramcore_bankmachine5_row_opened) begin
                         if (main_litedramcore_bankmachine5_row_hit) begin
-                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
                             end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
@@ -8594,6 +8501,82 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
 assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
@@ -8734,7 +8717,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
@@ -8742,7 +8725,7 @@ always @(*) begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_open <= 1'd1;
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8760,19 +8743,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -8790,7 +8767,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine6_source_source_valid) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
-                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8801,41 +8778,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_row_close <= 1'd0;
-    case (builder_bankmachine6_state)
-        1'd1: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -8853,9 +8807,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -8877,7 +8834,10 @@ always @(*) begin
                 if (main_litedramcore_bankmachine6_source_source_valid) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
-                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -8888,21 +8848,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8917,12 +8878,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -8945,8 +8903,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
                             if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -8958,22 +8916,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8984,11 +8935,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
@@ -9013,8 +8979,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
                             if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
                             end else begin
-                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9026,7 +8992,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
@@ -9051,8 +9017,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
                             if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -9064,13 +9030,42 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -9083,32 +9078,23 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine6_source_source_valid) begin
-                    if (main_litedramcore_bankmachine6_row_opened) begin
-                        if (main_litedramcore_bankmachine6_row_hit) begin
-                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -9126,10 +9112,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine6_source_source_valid) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
-                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9140,18 +9123,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9304,32 +9287,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
-    case (builder_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine7_state)
@@ -9644,15 +9601,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_open <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_row_open <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -9666,22 +9626,57 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    case (builder_bankmachine7_state)
+        1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine7_row_open <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                main_litedramcore_bankmachine7_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -9695,34 +9690,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9899,151 +9882,86 @@ always @(*) begin
         main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3;
     end
 end
-always @(*) begin
-    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
-    if (main_litedramcore_choose_req_cmd_valid) begin
-        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
-    end
-end
-always @(*) begin
-    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
-    if (main_litedramcore_choose_req_cmd_valid) begin
-        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
-    end
-end
-assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
-assign main_litedramcore_dfi_p0_reset_n = 1'd1;
-assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
-assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
-assign main_litedramcore_dfi_p1_reset_n = 1'd1;
-assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
-assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
-assign main_litedramcore_dfi_p2_reset_n = 1'd1;
-assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
-assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
-assign main_litedramcore_dfi_p3_reset_n = 1'd1;
-assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
-assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
-assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
-always @(*) begin
-    builder_multiplexer_next_state <= 4'd0;
-    builder_multiplexer_next_state <= builder_multiplexer_state;
-    case (builder_multiplexer_state)
-        1'd1: begin
-            if (main_litedramcore_read_available) begin
-                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
-                    builder_multiplexer_next_state <= 2'd3;
-                end
-            end
-            if (main_litedramcore_go_to_refresh) begin
-                builder_multiplexer_next_state <= 2'd2;
-            end
-        end
-        2'd2: begin
-            if (main_litedramcore_cmd_last) begin
-                builder_multiplexer_next_state <= 1'd0;
-            end
-        end
-        2'd3: begin
-            if (main_litedramcore_twtrcon_ready) begin
-                builder_multiplexer_next_state <= 1'd0;
-            end
-        end
-        3'd4: begin
-            builder_multiplexer_next_state <= 3'd5;
-        end
-        3'd5: begin
-            builder_multiplexer_next_state <= 3'd6;
-        end
-        3'd6: begin
-            builder_multiplexer_next_state <= 3'd7;
-        end
-        3'd7: begin
-            builder_multiplexer_next_state <= 4'd8;
-        end
-        4'd8: begin
-            builder_multiplexer_next_state <= 4'd9;
-        end
-        4'd9: begin
-            builder_multiplexer_next_state <= 4'd10;
-        end
-        4'd10: begin
-            builder_multiplexer_next_state <= 1'd1;
-        end
-        default: begin
-            if (main_litedramcore_write_available) begin
-                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
-                    builder_multiplexer_next_state <= 3'd4;
-                end
-            end
-            if (main_litedramcore_go_to_refresh) begin
-                builder_multiplexer_next_state <= 2'd2;
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_choose_req_cmd_ready <= 1'd0;
-    case (builder_multiplexer_state)
-        1'd1: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        4'd9: begin
-        end
-        4'd10: begin
-        end
-        default: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-            end
-        end
-    endcase
+always @(*) begin
+    main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4;
+    end
 end
 always @(*) begin
-    main_litedramcore_en1 <= 1'd0;
+    main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+    if (main_litedramcore_choose_req_cmd_valid) begin
+        main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5;
+    end
+end
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+always @(*) begin
+    builder_multiplexer_next_state <= 4'd0;
+    builder_multiplexer_next_state <= builder_multiplexer_state;
     case (builder_multiplexer_state)
         1'd1: begin
-            main_litedramcore_en1 <= 1'd1;
+            if (main_litedramcore_read_available) begin
+                if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+                    builder_multiplexer_next_state <= 2'd3;
+                end
+            end
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
+            end
         end
         2'd2: begin
+            if (main_litedramcore_cmd_last) begin
+                builder_multiplexer_next_state <= 1'd0;
+            end
         end
         2'd3: begin
+            if (main_litedramcore_twtrcon_ready) begin
+                builder_multiplexer_next_state <= 1'd0;
+            end
         end
         3'd4: begin
+            builder_multiplexer_next_state <= 3'd5;
         end
         3'd5: begin
+            builder_multiplexer_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_multiplexer_next_state <= 3'd7;
         end
         3'd7: begin
+            builder_multiplexer_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_multiplexer_next_state <= 4'd9;
         end
         4'd9: begin
+            builder_multiplexer_next_state <= 4'd10;
         end
         4'd10: begin
+            builder_multiplexer_next_state <= 1'd1;
         end
         default: begin
+            if (main_litedramcore_write_available) begin
+                if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+                    builder_multiplexer_next_state <= 3'd4;
+                end
+            end
+            if (main_litedramcore_go_to_refresh) begin
+                builder_multiplexer_next_state <= 2'd2;
+            end
         end
     endcase
 end
@@ -10394,6 +10312,71 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
+        1'd1: begin
+            main_litedramcore_en1 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
+        1'd1: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
+        end
+    endcase
+end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
 assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
@@ -10486,26 +10469,26 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    builder_interface0_dat_r <= 32'd0;
+    builder_interface1_dat_w_next_value0 <= 32'd0;
     case (builder_state)
         1'd1: begin
         end
         2'd2: begin
-            builder_interface0_dat_r <= builder_interface1_dat_r;
         end
         default: begin
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_dat_w_next_value0 <= 32'd0;
+    builder_interface0_ack <= 1'd0;
     case (builder_state)
         1'd1: begin
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
@@ -10531,93 +10514,123 @@ always @(*) begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
+                builder_interface1_adr_next_value1 <= builder_interface0_adr;
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface0_ack <= 1'd0;
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
     case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            builder_interface0_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    builder_interface1_re_next_value2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_adr_next_value_ce1 <= 1'd1;
+            builder_interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value_ce1 <= 1'd1;
+                builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0));
+            end
+        end
+    endcase
+end
+always @(*) begin
+    builder_interface1_re_next_value_ce2 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_re_next_value_ce2 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_re_next_value_ce2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value2 <= 1'd0;
+    builder_interface1_we_next_value3 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value2 <= 1'd0;
+            builder_interface1_we_next_value3 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+                builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value_ce2 <= 1'd0;
+    builder_interface1_we_next_value_ce3 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value_ce2 <= 1'd1;
+            builder_interface1_we_next_value_ce3 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value_ce2 <= 1'd1;
+                builder_interface1_we_next_value_ce3 <= 1'd1;
             end
         end
     endcase
 end
+always @(*) begin
+    builder_interface0_dat_r <= 32'd0;
+    case (builder_state)
+        1'd1: begin
+        end
+        2'd2: begin
+            builder_interface0_dat_r <= builder_interface1_dat_r;
+        end
+        default: begin
+        end
+    endcase
+end
 assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_done0_re <= 1'd0;
+    builder_csrbank0_init_done0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_done0_we <= 1'd0;
+    builder_csrbank0_init_done0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_error0_we <= 1'd0;
+    builder_csrbank0_init_error0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_error0_re <= 1'd0;
+    builder_csrbank0_init_error0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re;
     end
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
@@ -10625,15 +10638,15 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage;
 assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_rst0_we <= 1'd0;
+    builder_csrbank1_rst0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_rst0_re <= 1'd0;
+    builder_csrbank1_rst0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
@@ -10646,79 +10659,79 @@ end
 always @(*) begin
     builder_csrbank1_dly_sel0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10729,61 +10742,61 @@ always @(*) begin
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_rdphase0_re <= 1'd0;
+    builder_csrbank1_rdphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_rdphase0_we <= 1'd0;
+    builder_csrbank1_rdphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
     builder_csrbank1_wrphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10793,11 +10806,11 @@ always @(*) begin
     end
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage;
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage;
 assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage;
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage;
 assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
@@ -10809,14 +10822,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_control0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10827,22 +10840,22 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10861,14 +10874,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10877,7 +10890,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
@@ -10887,7 +10900,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
@@ -10900,7 +10913,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
@@ -10913,14 +10926,14 @@ end
 always @(*) begin
     main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10939,10 +10952,10 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
@@ -10952,14 +10965,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10978,20 +10991,20 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0];
@@ -11004,14 +11017,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11020,7 +11033,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
@@ -11030,14 +11043,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11050,7 +11063,7 @@ assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[
 always @(*) begin
     builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11061,15 +11074,15 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0];
@@ -11082,14 +11095,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11098,11 +11111,11 @@ always @(*) begin
         builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11111,7 +11124,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
@@ -11121,14 +11134,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
 assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage;
 assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
 assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
 assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
@@ -11137,11 +11150,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
 assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
 assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage;
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage;
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage;
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status;
 assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
 assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
@@ -11151,11 +11164,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
 assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
 assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage;
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage;
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage;
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status;
 assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
 assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
@@ -11165,11 +11178,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
 assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
 assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage;
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage;
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage;
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status;
 assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
 assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
@@ -11179,19 +11192,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
 assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
 assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage;
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage;
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage;
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status;
 assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_adr = builder_interface1_adr;
+assign builder_re = builder_interface1_re;
 assign builder_we = builder_interface1_we;
 assign builder_dat_w = builder_interface1_dat_w;
 assign builder_interface1_dat_r = builder_dat_r;
 assign builder_interface0_bank_bus_adr = builder_adr;
 assign builder_interface1_bank_bus_adr = builder_adr;
 assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_re = builder_re;
+assign builder_interface1_bank_bus_re = builder_re;
+assign builder_interface2_bank_bus_re = builder_re;
 assign builder_interface0_bank_bus_we = builder_we;
 assign builder_interface1_bank_bus_we = builder_we;
 assign builder_interface2_bank_bus_we = builder_we;
@@ -11917,16 +11934,16 @@ always @(*) begin
     builder_self0 <= 3'd0;
     case (main_litedramcore_steerer0)
         1'd0: begin
-            builder_self0 <= main_litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12036,16 +12053,16 @@ always @(*) begin
     builder_self7 <= 3'd0;
     case (main_litedramcore_steerer1)
         1'd0: begin
-            builder_self7 <= main_litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12155,16 +12172,16 @@ always @(*) begin
     builder_self14 <= 3'd0;
     case (main_litedramcore_steerer2)
         1'd0: begin
-            builder_self14 <= main_litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12274,16 +12291,16 @@ always @(*) begin
     builder_self21 <= 3'd0;
     case (main_litedramcore_steerer3)
         1'd0: begin
-            builder_self21 <= main_litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12389,10 +12406,10 @@ always @(*) begin
         end
     endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -13991,8 +14008,11 @@ always @(posedge sys_clk) begin
     if (builder_interface1_adr_next_value_ce1) begin
         builder_interface1_adr <= builder_interface1_adr_next_value1;
     end
-    if (builder_interface1_we_next_value_ce2) begin
-        builder_interface1_we <= builder_interface1_we_next_value2;
+    if (builder_interface1_re_next_value_ce2) begin
+        builder_interface1_re <= builder_interface1_re_next_value2;
+    end
+    if (builder_interface1_we_next_value_ce3) begin
+        builder_interface1_we <= builder_interface1_we_next_value3;
     end
     builder_interface0_bank_bus_dat_r <= 1'd0;
     if (builder_csrbank0_sel) begin
@@ -14062,11 +14082,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
     if (builder_csrbank1_dly_sel0_re) begin
-        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+        main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r;
     end
     main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
     if (builder_csrbank1_half_sys8x_taps0_re) begin
-        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+        main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r;
     end
     main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
     if (builder_csrbank1_wlevel_en0_re) begin
@@ -14074,11 +14094,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
     if (builder_csrbank1_rdphase0_re) begin
-        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+        main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r;
     end
     main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
     if (builder_csrbank1_wrphase0_re) begin
-        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+        main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r;
     end
     main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
     builder_interface2_bank_bus_dat_r <= 1'd0;
@@ -14162,74 +14182,74 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (builder_csrbank2_dfii_control0_re) begin
-        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+        main_litedramcore_storage <= builder_csrbank2_dfii_control0_r;
     end
     main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
     if (builder_csrbank2_dfii_pi0_command0_re) begin
-        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
+        main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r;
     end
     main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
     if (builder_csrbank2_dfii_pi0_address0_re) begin
-        main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r;
+        main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r;
     end
     main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
     if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+        main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
     main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
     if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+        main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
     main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
     main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
     if (builder_csrbank2_dfii_pi1_command0_re) begin
-        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
+        main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r;
     end
     main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
     if (builder_csrbank2_dfii_pi1_address0_re) begin
-        main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r;
+        main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r;
     end
     main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
     if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+        main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
     main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
     if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+        main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
     main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
     main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
     if (builder_csrbank2_dfii_pi2_command0_re) begin
-        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
+        main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r;
     end
     main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
     if (builder_csrbank2_dfii_pi2_address0_re) begin
-        main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r;
+        main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r;
     end
     main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
     if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+        main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
     main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
     if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+        main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
     main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
     main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
     if (builder_csrbank2_dfii_pi3_command0_re) begin
-        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
+        main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r;
     end
     main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
     if (builder_csrbank2_dfii_pi3_address0_re) begin
-        main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r;
+        main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r;
     end
     main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
     if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+        main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
     main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
     if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+        main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
     main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
     main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
@@ -14502,6 +14522,7 @@ always @(posedge sys_clk) begin
         main_init_done_re <= 1'd0;
         main_init_error_storage <= 1'd0;
         main_init_error_re <= 1'd0;
+        builder_interface1_re <= 1'd0;
         builder_interface1_we <= 1'd0;
         builder_refresher_state <= 2'd0;
         builder_bankmachine0_state <= 4'd0;
@@ -17513,7 +17534,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
@@ -17531,7 +17552,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (iodelay_rst)
@@ -17549,7 +17570,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
@@ -17567,7 +17588,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (sys_rst)
@@ -17585,7 +17606,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
@@ -17603,7 +17624,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
@@ -17621,7 +17642,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
@@ -17639,7 +17660,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
@@ -17648,5 +17669,5 @@ FDPE #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:09.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:45.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 0573632..843a495 100644
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842adc83c4c0001
+3c4c000100000000
+7c0802a63842aea4
+f821ffc148002885
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+000000004800289c
+0000038001000000
+3842ae503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48002175f9410108
+480021b9f9410108
 7c7f1b7860000000
-48001bc538610020
+48001c1538610020
 382100b060000000
-480027e87fe3fb78
+480028447fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,273 +552,284 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842ad2c
-480027217d600026
-f821fed191610008
-6000000048001bc1
-38637a983c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842adb4
+480027797d600026
+f821fec191610008
+6000000048001c11
+38637a683c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637ab83be00008
+38637a883be00008
 4bffff1d67ffc000
-38637ad83c62ffff
+38637aa83c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637af0
+4bfffef538637ac0
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637af8
+4bfffedd38637ac8
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b00
+4bfffec538637ad0
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b08
+4bfffead38637ad8
 4182001073e90010
-38637b183c62ffff
+38637ae83c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637b28
-3b7b7b303f62ffff
-4bfffe757f63db78
+4bfffe8538637af8
+3b397b003f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637b387884b582
+38637b087884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637b50
+4bfffe2d38637b20
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637b68
+4bfffe0d38637b38
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637b807c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637ba057c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637b507c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637b7057e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637bc0
-4082009073a90002
-38637be03c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637b90
+4082006473c90002
+38637bb03c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637bf8
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637c087b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637c3838847c28
-48000bf54bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637c583c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637bc0
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637c70
-38a000403c9af000
+4bfffc2d38637c60
+38a000403c9cf000
 3861007078840020
-60000000480018b5
+60000000480019e5
 3d200002e9410070
 6129464c3c62ffff
-792983e438637c88
+792983e438637c78
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637ca83c62ffff
-892100774bfffae9
+38637c983c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d0888810070
+38637cf888810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637d38
-3880600038a00000
-6484ff0060a5a000
-480018113c604000
+3c62ffff4bfffb99
+4bfffb8d38637d28
+3880f80338a00000
+7884682860a5a000
+480019413c604000
 3c62ffff60000000
-4bfffa8538637d58
-4bffff184bfffafd
+4bfffb6538637d48
+480002184bfffbdd
 3f22ffffebe10090
-3b397cc03ba00000
-a12100a87ffafa14
+3b397cb03ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637ce8
-e86100884bfffac5
+4bfffb2d38637cd8
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-480022407d638120
+8161000838210140
+480023787d638120
 38a000383c9ff000
 386100b078840020
-6000000048001795
+60000000480018c5
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-600000004800174d
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+600000004800187d
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
-38637bf03c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637bc8
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637bd0
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
+38637be83c62ffff
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637bf87b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637c2838847c18
+48000a294bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637c483c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920100400000000
+7c0004ac6529c800
+394010087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-6529c80039201004
-7c604f2a7c0004ac
-3920000139401008
+3842a7283c4c0001
+4182004428030002
+4182001428030003
+4182005028030001
+4bffffa87c8307b4
+6529c8003920104c
+7c804f2a7c0004ac
+3940105039200001
 7c0004ac654ac800
 4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a6f4
-2803000341820044
-2803000141820014
-7c8307b441820050
-3920104c4bffffa8
-7c0004ac6529c800
-392000017c804f2a
-654ac80039401050
-7d20572a7c0004ac
-392010344e800020
+6529c80039201034
+7c804f2a7c0004ac
+3940103839200001
+3920101c4bffffd8
 7c0004ac6529c800
 392000017c804f2a
-4bffffd839401038
-6529c8003920101c
-7c804f2a7c0004ac
-3940102039200001
-000000004bffffbc
+4bffffbc39401020
+0000000000000000
+3d40555500000000
+614a55555469f87e
+7c6918507d295038
+612933333d203333
+5463f0be7d2a1838
+7d4a1a147c634838
+7d2952145549e13e
+614a0f0f3d400f0f
+552ac23e7d295038
+5523843e7d2a4a14
+786306a07c634a14
+000000004e800020
 0000000000000000
-5469f87e3d405555
-7d295038614a5555
-3d2033337c691850
-7d2a183861293333
-7c6348385463f0be
-5549e13e7d4a1a14
-3d400f0f7d295214
-7d295038614a0f0f
-7d2a4a14552ac23e
-7c634a145523843e
-4e800020786306a0
+3920000028030002
+4182002c39401040
+3920000028030003
+4182001c39401058
+3920000028030001
+4182000c39401028
+3940101039200000
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
 2803000200000000
-3940104039200000
+3940103c39200000
 280300034182002c
-3940105839200000
+3940105439200000
 280300014182001c
-3940102839200000
+3940102439200000
 392000004182000c
-654ac80039401010
+654ac8003940100c
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-3920000028030002
-4182002c3940103c
-3920000028030003
-4182001c39401054
-3920000028030001
-4182000c39401024
-3940100c39200000
-7c0004ac654ac800
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-7c0802a63842a554
-f821ff4148001f2d
-3f02ffff23a30001
-3b40100c3ae00003
-3ac010743b201010
-3bc0000020630003
-3b187e503b600000
-675ac80066f78020
-66d6c8006739c800
-7c7f07b47fbd07b4
-3a8100207bc91764
-3aa000047e87a378
-7e9ca3787d58482e
+3842a5883c4c0001
+48001f2d7c0802a6
+3ee2fffff821ff31
+3b20100c3ec0e008
+3aa010743b001010
+236300033b800830
+3ba000003bc00000
+7ad610203af77fac
+6718c8006739c800
+679cc80066b5c800
+687f00017f7b07b4
+3a4100207bc91764
+3a8000047e479378
+7e5a93787d57482e
 4800004439000000
 794a07e07949f862
-7d4ab8387d4a00d0
+7d4ab0387d4a00d0
 7d2a4b787d494a78
 7d293030552907fe
 7d292b7838c60001
@@ -812,253 +838,252 @@ f821ff4148001f2d
 4182001828280004
 38a0000039200008
 38c000007d2903a6
-3ab5ffff4bffffb0
-2c15000038e70004
+3a94ffff4bffffb0
+2c14000038e70004
 7c0004ac4082ff98
-7c0004ac7ea0d72a
-386000097ea0cf2a
-3860000f4bfffd41
-392010144bfffd1d
+7c0004ac7e80cf2a
+386000097e80c72a
+3860000f4bfffd3d
+392010144bfffd19
 38e000046529c800
-7ce903a63914ffff
-8ce8000139400000
+7ce903a63912ffff
+394000003a600004
+3a73ffff8ce80001
 7cea3b787947400c
-7c0004ac4200fff4
+7c0004ac4200fff0
 392900187ce04f2a
-7c29b0003a940004
-3a8008304082ffcc
-7c0004ac6694c800
-5463063e7c60a62a
-7c0004ac4bfffe61
-5463063e7c60a62a
-7c0004ac4bfffdfd
-388000177c60a62a
-4bfffcf95463063e
-3860000f3a80082c
-6694c8004bfffc95
-7c60a62a7c0004ac
-4bfffe1d5463063e
-7c60a62a7c0004ac
-4bfffdb95463063e
-7c60a62a7c0004ac
+7c29a8003a520004
+7c0004ac4082ffc4
+5463063e7c60e62a
+7c0004ac4bfffe5d
+5463063e7c60e62a
+7c0004ac4bfffdf9
+388000177c60e62a
+4bfffcf55463063e
+3860000f3a40082c
+6652c8004bfffc91
+7c60962a7c0004ac
+4bfffe195463063e
+7c60962a7c0004ac
+4bfffdb55463063e
+7c60962a7c0004ac
 5463063e38800025
-3860000f4bfffcb5
-392000004bfffc55
-7d20d72a7c0004ac
+3860000f4bfffcb1
+392000004bfffc51
 7d20cf2a7c0004ac
-7e9cea143860000b
-3860000f4bfffc51
-4bfffc293a601018
-6673c8003a001078
-7e91a3787f9cfa14
-7c0004ac6610c800
-390000047d209e2a
+7d20c72a7c0004ac
+39c010183860000b
+3860000f4bfffc4d
+4bfffc2565cec800
+7e5afa147dfada14
+7e7107b41d330018
+7c0004ac7d297214
+390000047d204e2a
 7d0903a679290020
 9d2affff39410034
 4200fff87929c202
-3a7300187d3da050
-7c69f8ae3a940004
-7c634a78893c0010
-4bfffcb55463063e
-7c721b7889310010
-7c634a788874fffc
-4bfffc9d5463063e
-7c6392147c338000
-4082ff987eb51a14
-7f7baa143bde0001
-4082fddc283e0003
-7f6307b4382100c0
-0000000048001d04
-0000108001000000
-3842a2c03c4c0001
-388000007c0802a6
-f821ff6148001cb5
-3b1864ec3f02ffff
-3bc000007c7d1b78
-7f05c3783b800000
-600000004800084d
-4bfffd397fa3eb78
-7c7f00342c030000
-4082006857ffd97e
-418200602c1c0000
-7ff9fb783bfeffff
-7fdbf3787ffcfb78
-3b5b00017fa3eb78
-2c0300004bfffd05
-7d39d85040820070
-7c0950007d5fe050
-2c1a001f41810068
-3ca2ffff4181006c
-3880000038a564a4
-7f5bd3787fa3eb78
-60000000480007d5
-3bde00014bffffb8
-418200242c1e0020
-38a564a43ca2ffff
+7a3117647a691764
+3a7300017e3a8a14
+892f00107c6f48ae
+5463063e7c634a78
+893200104bfffcad
+7c71f8ae7c701b78
+5463063e7c634a78
+283300044bfffc95
+7e941a147c638214
+3bde00014082ff88
+283e00037fbda214
+382100d04082fdd8
+48001cfc7fa307b4
+0100000000000000
+3c4c000100001280
+7c0802a63842a2ec
+48001cb538800000
+3f02fffff821ff61
+7c7d1b783b1864b4
+3b8000003bc00000
+480008417f05c378
+7fa3eb7860000000
+2c0300004bfffd31
+57ffd97e7c7f0034
+2c1c000040820068
+3bfeffff41820060
+7ffcfb787ff9fb78
+7fa3eb787fdbf378
+4bfffcfd3b5b0001
+408200702c030000
+7d5fe0507d39d850
+418100687c095000
+4181006c2c1a001f
+38a5646c3ca2ffff
 7fa3eb7838800000
-480007a97ffcfb78
-4bffff5c60000000
-4bffff783be0ffff
-4bffffa07f59d378
-7f3fcb787f7cdb78
-2c1c00004bffff94
-7fc907b440800024
-2129001f3b800000
-418000082c290000
-3bde0001239e001f
-2c1f00007f9cf214
-3c62ffff4080001c
-4bfff3cd38637d70
-382100a060000000
-7cbfe05048001bd4
-7ca50e707c9cfa14
-789bfee27ca50194
-7ca507b43c62ffff
-38637d807f64db78
-4bfff3953be00008
-7f05c37860000000
+480007c97f5bd378
+4bffffb860000000
+2c1e00203bde0001
+3ca2ffff41820024
+3880000038a5646c
+7ffcfb787fa3eb78
+600000004800079d
+3be0ffff4bffff5c
+7f59d3784bffff78
+7f7cdb784bffffa0
+4bffff947f3fcb78
+4080001c2c1c0000
+3b8000002c1e0020
+239e001f41820008
+7f9cf2143bde0001
+4080001c2c1f0000
+38637d603c62ffff
+600000004bfff379
+48001bdc382100a0
+7c9fe2147cbfe050
+7ca501947ca50e70
+3c62ffff789bfee2
+7f64db787ca507b4
+3be0000838637d70
+600000004bfff341
+388000007f05c378
+3bc000007fa3eb78
+60000000480006f5
+4bfff9ed38600064
+418100247c1bf000
+4bfffbd57fa3eb78
+4182ff942c030000
+2c1f00003bffffff
+4bffff844082ffc0
+38a5646c3ca2ffff
 7fa3eb7838800000
-480006f93bc00000
+480006a93bde0001
 3860006460000000
-7c1bf0004bfff9ed
-7fa3eb7841810024
-2c0300004bfffbd5
-3bffffff4182ff94
-4082ffc02c1f0000
-3ca2ffff4bffff84
-3880000038a564a4
-3bde00017fa3eb78
-60000000480006ad
-4bfff9a138600064
-000000004bffffb4
-0000088001000000
-3842a0d03c4c0001
-6529c80039201000
-7d404e2a7c0004ac
-4d820020280a000e
-3940000e7c0802a6
-f821ffa1f8010010
-7d404f2a7c0004ac
-38637d983c62ffff
-600000004bfff2d1
-e801001038210060
-4e8000207c0803a6
+4bffffb44bfff9a1
 0100000000000000
-3c4c000100000080
-392010003842a06c
+3c4c000100000880
+392010003842a104
 7c0004ac6529c800
-280a00017d404e2a
+280a000e7d404e2a
 7c0802a64d820020
-f801001039400001
+f80100103940000e
 7c0004acf821ffa1
 3c62ffff7d404f2a
-4bfff26d38637dc0
+4bfff27d38637d88
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-3842a0083c4c0001
-480019ed7c0802a6
-3f02fffff821ff31
-3ec2ffff3b186574
-3e82ffff3ea2ffff
-3e62ffff3ee2ffff
-3ad67de83b400000
-3a947e003ab57df8
-3a737e083af77b30
-7f05c3787f5f07b4
+3842a0a03c4c0001
+6529c80039201000
+7d404e2a7c0004ac
+4d820020280a0001
+394000017c0802a6
+f821ffa1f8010010
+7d404f2a7c0004ac
+38637db03c62ffff
+600000004bfff219
+e801001038210060
+4e8000207c0803a6
+0100000000000000
+3c4c000100000080
+7c0802a63842a03c
+f821ff31480019f5
+3b18653c3f02ffff
+3ea2ffff3ec2ffff
+3ee2ffff3e82ffff
+3b4000003e62ffff
+3ab57de83ad67dd8
+3af77b003a947df0
+7f5f07b43a737df8
+388000007f05c378
+480005697fe3fb78
+3b60000060000000
+3bc000003b800000
+7fdbf37848000030
+418200e42c1e0007
+38a564f43ca2ffff
 7fe3fb7838800000
-600000004800056d
-3b8000003b600000
-480000303bc00000
-2c1e00077fdbf378
-3ca2ffff418200e4
-3880000038a5652c
-3bde00017fe3fb78
-480005317fbceb78
-7fc507b460000000
-7ec3b3787fe4fb78
-4bfff19d3b200020
-3ca2ffff60000000
-3880000038a564ec
-3ba000007fe3fb78
-60000000480004fd
-4bfff9e97fe3fb78
-7c64003439400000
-5484d97e212300c0
+7fbceb783bde0001
+600000004800052d
+7fe4fb787fc507b4
+3b2000207ec3b378
+600000004bfff149
+38a564b43ca2ffff
+7fe3fb7838800000
+480004f93ba00000
+7fe3fb7860000000
+392000004bfff9e9
+5484d97e7c640034
 418200082c040000
-7d29521439401800
-7ea3ab78788407e0
-4bfff1457fbd4a14
-3ca2ffff60000000
-3880000038a564a4
-480004a97fe3fb78
-3739ffff60000000
-7e83a3784082ffa8
-600000004bfff119
-4bfffc157fe3fb78
-4bfff1057ee3bb78
-7c1ce84060000000
-7f9de3784180ff20
-7f6507b44bffff1c
-7e639b787fe4fb78
-4bfff0dd3bc00000
-7f05c37860000000
+206300c039201800
+7d291a14788407e0
+7fbd4a147ea3ab78
+600000004bfff0f1
+38a5646c3ca2ffff
+7fe3fb7838800000
+60000000480004a5
+4082ffa83739ffff
+4bfff0c57e83a378
+7fe3fb7860000000
+7ee3bb784bfffc1d
+600000004bfff0b1
+4180ff207c1ce840
+4bffff1c7f9de378
+7fe4fb787f6507b4
+3bc000007e639b78
+600000004bfff089
+388000007f05c378
+480004417fe3fb78
+7c1ed80060000000
+7fe3fb7840820030
+7ee3bb784bfffbc5
+600000004bfff059
+3b400001393a0001
+4082fe982c090002
+48001898382100d0
+38a564f43ca2ffff
 7fe3fb7838800000
-6000000048000445
-418000287c1ed800
-4bfffbbd7fe3fb78
-4bfff0ad7ee3bb78
-2c1a000060000000
-3b4000014082002c
-3ca2ffff4bfffe98
-3880000038a5652c
-3bde00017fe3fb78
-60000000480003fd
-382100d04bffffb8
-0000000048001870
-00000d8001000000
-38429e203c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-4bfffd3df821ff91
-3bde64ec3fc2ffff
+480003f13bde0001
+4bffffb060000000
+0100000000000000
+3c4c000100000d80
+7c0802a638429e54
+fbe1fff8fbc1fff0
+f821ff91f8010010
+3fc2ffff4bfffd3d
+388000003bde64b4
+7fc5f37838600000
+60000000480003a5
+3bff653c3fe2ffff
 3860000038800000
-480003a97fc5f378
-3fe2ffff60000000
-388000003bff6574
-7fe5fb7838600000
-600000004800038d
-388000007fc5f378
-4800037938600001
-7fe5fb7860000000
+480003897fe5fb78
+7fc5f37860000000
 3860000138800000
-6000000048000365
-38637e203c62ffff
-600000004bffefd9
-4bfffd294bfffd91
-3860000138210070
-0000000048001800
-0000028001000000
-38429d703c4c0001
-3920082c7c0802a6
-4800175d6529c800
+6000000048000375
+388000007fe5fb78
+4800036138600001
+3c62ffff60000000
+4bffef8538637e10
+4bfffd9160000000
+382100704bfffd29
+4800180838600001
+0100000000000000
+3c4c000100000280
+7c0802a638429da4
+3b80082c4800176d
 3b000002f821ff51
-7f004f2a7c0004ac
-3b20000339200830
-7c0004ac6529c800
-3c62ffff7f204f2a
-38637e303c804000
-4bffef653bc00800
-3b80000160000000
-67dec8004bfffc51
-7f80f72a7c0004ac
-3be00000386003e8
-7c0004ac4bfff5bd
-386003e87fe0f72a
-4bfff5a93f60c800
-7c0004ac7b7b0020
-3b4000047fe0df2a
+7c0004ac679cc800
+392008307f00e72a
+6529c8003b200003
+7f204f2a7c0004ac
+3c8040003c62ffff
+3bc0080038637e20
+600000004bffef11
+4bfffc513b600001
+7c0004ac67dec800
+386003e87f60f72a
+4bfff5bd3be00000
+7fe0f72a7c0004ac
+3b9cf7d4386003e8
+7c0004ac4bfff5a9
+3b4000047fe0e72a
 7c0004ac675ac800
 3ba0100c7fe0d72a
 7c0004ac67bdc800
@@ -1068,47 +1093,47 @@ f8010010fbe1fff8
 66f7c8003920000c
 7d20bf2a7c0004ac
 6063c35038600000
-7c0004ac4bfff54d
+7c0004ac4bfff551
 7c0004ac7fe0ef2a
 3920000e7fe0f72a
 7d20bf2a7c0004ac
-4bfff52938602710
+4bfff52d38602710
 7c0004ac39200200
 7c0004ac7d20ef2a
 3860000f7f00f72a
-7c0004ac4bfff529
+7c0004ac4bfff52d
 7c0004ac7fe0ef2a
 3860000f7f20f72a
-392000064bfff511
+392000064bfff515
 7d20ef2a7c0004ac
-7f80f72a7c0004ac
-4bfff4f53860000f
+7f60f72a7c0004ac
+4bfff4f93860000f
 7c0004ac39200930
 7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff4d9
-392004004bfff4b5
+386000c84bfff4dd
+392004004bfff4b9
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bfff4b538600003
-4bfff491386000c8
-4bfffb694bfffdb9
+4bfff4b938600003
+4bfff495386000c8
+4bfffb6d4bfffdbd
 3c6040003c800020
 600000004800085d
 408200242c030000
 7c0004ac7c691b78
-7c0004ac7f80d72a
-382100b07f80df2a
-480015e47d2307b4
+7c0004ac7f60d72a
+382100b07f60e72a
+480015f07d2307b4
 38a0000038c00000
 3c6040003c800020
 60000000480005e5
-7f80df2a7c0004ac
+7f60e72a7c0004ac
 4bffffd039200001
 0100000000000000
 3c4c000100000980
-6000000038429b5c
-3942802078631764
+6000000038429b94
+3942800878631764
 392900017d2a182e
 7d2a192e552906fe
 3920000139400818
@@ -1116,16 +1141,16 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429b14
-3922802078631764
+6000000038429b4c
+3922800878631764
 7d49192e39400000
 3920000139400814
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429ad4
-3942801878631764
+6000000038429b0c
+3942800078631764
 392900017d2a182e
 7d2a192e5529077e
 3920000139400820
@@ -1133,15 +1158,15 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429a8c
-3922801878631764
+6000000038429ac4
+3922800078631764
 7d49192e39400000
 392000013940081c
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-7c0802a638429a4c
+7c0802a638429a84
 39200001fbe1fff8
 7cac2b783be00804
 67ffc8007d291830
@@ -1151,46 +1176,46 @@ f84100187ca903a6
 e84100184e800421
 7c0004ac39200000
 382100307d20ff2a
-000000004800147c
+0000000048001488
 0000018001000000
-384299e83c4c0001
+38429a203c4c0001
 282303ff7c0802a6
 f821ffa1f8010010
 7c641b7841810028
-38637e603c62ffff
-600000004bffec01
+38637e403c62ffff
+600000004bffebb1
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffebc538637e68
+4bffeb7538637e48
 4bffffc460000000
 786465023d204000
 408000247c234840
 788955647863b282
 38a000667d291850
 7ca92b923c62ffff
-4bffffc838637e78
+4bffffc838637e58
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637e887ca54b92
+38637e687ca54b92
 000000004bffffa4
 0000008001000000
-384299183c4c0001
+384299503c4c0001
 fbe1fff87c0802a6
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-f801001038637e98
-4bffeb25f821ff91
+f801001038637e78
+4bffead5f821ff91
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffeb0d38637ea8
+4bffeabd38637e88
 3821007060000000
-0000000048001344
+0000000048001350
 0000018001000000
 418200242c240000
 786307e07869f842
@@ -1200,14 +1225,14 @@ f801001038637e98
 4bfffff438630001
 0000000000000000
 3c4c000100000000
-7c0802a638429874
+7c0802a6384298ac
 3d40aaaa78840764
 614aaaaa7c691b78
-7f8322144800126d
+7f83221448001279
 f821ffc17884f082
 7c7f1b7839040001
 7c7d1b787d0903a6
-4bffeae142000080
+4bffea9142000080
 7d3fe05060000000
 7929f0823d00aaaa
 392900017feafb78
@@ -1217,12 +1242,12 @@ f821ffc17884f082
 7feafb787929f082
 6108555539290001
 420000587d2903a6
-4bffea917fffe050
+4bffea417fffe050
 7bfff08260000000
 395f00013d205555
 7d4903a661295555
 3821004042000040
-480012207fc307b4
+4800122c7fc307b4
 3929000491490000
 812a00004bffff78
 418200087c094000
@@ -1234,44 +1259,44 @@ f821ffc17884f082
 4bffffac3bbd0004
 0100000000000000
 3c4c000100000480
-7d60002638429764
+7d6000263842979c
 916100087c0802a6
-480011452e260000
+480011512e260000
 7c7f1b78f821ff41
 7cde33787cba2b78
-419200c0789cf082
+419200e4789cf082
 82e6000081260004
-408200442c090000
-3ba000003f02ffff
-7bf900203b600001
-7c3ce8403b187eb0
-3c62ffff4082009c
-38637eb07b851028
-4bfffde57be40020
-38637b303c62ffff
-600000004bffe929
-600000004bffe98d
+418200d82c090000
+600000004bffe97d
 7ffbfb782d970000
 3ac000013ba00000
 7bf500203b200000
-7fb8eb787c3de040
-2c17000040820084
+7fb8eb787c3ce840
+2c170000408200c4
 3c62ffff41820028
-38637ec07b051028
-4bfffd8d7be40020
-38637b303c62ffff
-600000004bffe8d1
+38637ea07b051028
+4bfffdcd7be40020
+38637b003c62ffff
+600000004bffe8c1
 7f2307b4382100c0
 7d61812081610008
-3ae00001480010c0
-7b6300204bffff50
-4bfffdb57f44d378
+7b6300204800110c
+4bfffdfd7f44d378
 7c7f492e7ba91764
 7c7b1b7873a97fff
 7ba5102840820014
 7f03c3787f24cb78
-3bbd00014bfffd31
-7f44d3784bffff2c
+3bbd00014bfffd79
+4082ffc87c3ce840
+7b8510283c62ffff
+7be4002038637e90
+3c62ffff4bfffd59
+4bffe84d38637b00
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187e907bf90020
+7f44d3784bffffb8
 4bfffd7d7ac30020
 7c651b78809b0000
 7c0320407c761b78
@@ -1282,29 +1307,29 @@ e8de00107d8903a6
 f841001878840020
 4e8004217b630020
 2c030000e8410018
-73187fff4082ff58
+73187fff4082ff18
 418e00184082001c
 7ba510283c62ffff
-38637ec07ea4ab78
+38637ea07ea4ab78
 3bbd00014bfffcb1
-4bfffef43b7b0004
+4bfffeb43b7b0004
 0300000000000000
 3c4c000100000b80
-7d708026384295a4
+7d708026384295dc
 916100087c0802a6
-f821ff7148000f9d
+f821ff7148000fa9
 3ba4ffe07cdb3378
 7c7f1b782e3b0000
 7fa3ea147c9e2378
 3c62ffff7c641b78
-7cbc2b7838637ed0
-600000004bffe7a1
-38637ee83c62ffff
+7cbc2b7838637eb0
+600000004bffe751
+38637ec83c62ffff
 3c62ffff4092000c
-4bffe78538637ef8
+4bffe73538637ed8
 7fc3f37860000000
 3c62ffff4bfffb59
-4bffe76d38637f08
+4bffe71d38637ee8
 2c3c000060000000
 7cf602a6408200a8
 38bd002038df0020
@@ -1320,14 +1345,14 @@ f90a0018f90a0010
 639ce10078ea0020
 7f9ee1d279290020
 3c62ffff7d295050
-7f9c4b9238637f10
-600000004bffe6e9
+7f9c4b9238637ef0
+600000004bffe699
 4bfffabd7f83e378
-38637f203c62ffff
-600000004bffe6d1
-38637b303c62ffff
-600000004bffe6c1
-600000004bffe725
+38637f003c62ffff
+600000004bffe681
+38637b003c62ffff
+600000004bffe671
+600000004bffe6d5
 409200487f9602a6
 395f00207d3fe850
 7929d9423bbd0020
@@ -1344,16 +1369,16 @@ e95f0018e95f0010
 7b9c00203d4005f5
 79290020614ae100
 7d29e0507fde51d2
-38637f283c62ffff
-4bffe6257fde4b92
+38637f083c62ffff
+4bffe5d57fde4b92
 7fc3f37860000000
 3c62ffff4bfff9f9
-4bffe60d38637f20
+4bffe5bd38637f00
 3c62ffff60000000
-4bffe5fd38637b30
+4bffe5ad38637b00
 3821009060000000
 7d70812081610008
-7fa407b448000e04
+7fa407b448000e10
 4bfffaed79430020
 7d23db963bbd0001
 7d29d9d67c6a1b78
@@ -1361,16 +1386,16 @@ e95f0018e95f0010
 4bffff687d3f482a
 0300000000000000
 3c4c000100000680
-7c0802a63842936c
-48000d7128240200
+7c0802a6384293a4
+48000d7d28240200
 7c7e1b78f821ff81
 3b8002007c9f2378
 7c9c237841810008
 7fc4f3783c62ffff
-4bffe57538637f38
+4bffe52538637f18
 7fe3fb7860000000
 3c62ffff4bfff949
-4bffe55d38637f08
+4bffe50d38637ee8
 7f84e37860000000
 4bfffaa17fc3f378
 38a0000138c00000
@@ -1379,55 +1404,55 @@ e95f0018e95f0010
 7c7e1b787d23ea14
 418200802c090000
 7b85f8823c62ffff
-38637f487fa4eb78
-600000004bffe511
+38637f287fa4eb78
+600000004bffe4c1
 7fe5fb78283f8000
 38a0ffff4081000c
 3c62ffff54a50420
 3880000078a5f082
-4bffe4e538637f60
+4bffe49538637f40
 3c62ffff60000000
 7fc4f3787be5f082
-4bffe4cd38637f78
+4bffe47d38637f58
 3c62ffff60000000
-4bffe4bd38637f90
+4bffe46d38637f70
 3860000060000000
 786307e038210080
-3c62ffff48000ccc
-4bffe49d38637fa0
+3c62ffff48000cd8
+4bffe44d38637f80
 3860000160000000
 000000004bffffe0
 0000048001000000
-384292403c4c0001
-8922803060000000
-3942802860000000
+384292783c4c0001
+8922801860000000
+3942801060000000
 418200302c090000
 39290014e92a0000
 7d204eaa7c0004ac
 4182ffec71290020
-e922802860000000
+e922801060000000
 7c604faa7c0004ac
 e92a00004e800020
 7c0004ac39290010
 712900087d204eea
 5469063e4082ffec
-e942802860000000
+e942801060000000
 7d2057ea7c0004ac
 000000004e800020
 0000000000000000
-384291b83c4c0001
+384291f03c4c0001
 fbe1fff87c0802a6
 3be3fffffbc1fff0
 f821ffd1f8010010
 2c1e00008fdf0001
 3821003040820010
-48000c0438600000
+48000c1038600000
 4082000c2c1e000a
 4bffff3d3860000d
-4bffff3557c3063e
+4bffff357bc30020
 000000004bffffd0
 0000028001000000
-384291583c4c0001
+384291903c4c0001
 654ac00039400020
 7d4056ea7c0004ac
 794a060039200008
@@ -1438,377 +1463,378 @@ f821ffd1f8010010
 7929f8047d204eea
 79290fc339002000
 600000006508c000
-3d00001cf9028028
+3d00001cf9028010
 7d4a439261082000
 6000000041820080
-9922803039200001
+9922801839200001
 3920ff803900200c
 7c0004ac6508c000
-e92280287d2047aa
+e92280107d2047aa
 7d404faa7c0004ac
-794ac202e9228028
+794ac202e9228010
 7c0004ac39290004
-e92280287d404faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e9228028
+39290010e9228010
 7d404faa7c0004ac
-39400007e9228028
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
 394affff60000000
-3920201899228030
+3920201899228018
 7c0004ac6529c000
 4e8000207d404fea
 0000000000000000
 78a9e8c200000000
 3929000139400000
-420000287d2903a6
-78a5076078a90724
-7d434a1439050001
-7c844a147d0903a6
-4200001839200000
-7d24502a4e800020
-394a00087d23512a
-7d0448ae4bffffcc
-392900017d0a49ae
-000000004bffffdc
-0000000000000000
-386000007c691b78
-2c0a00007d4918ae
-386300014d820020
-000000004bfffff0
-0000000000000000
-408200082c240000
+4200002c7d2903a6
+3940000078a9e8c2
+7ca54a141d29fff8
+390500017c892050
+7d0903a67d291850
+4e80002042000018
+7d23512a7d24502a
+4bffffc8394a0008
+7d0951ae7d0450ae
+4bffffdc394a0001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
+0000000000000000
+2c24000000000000
+408200087c691b78
 280500243881fff0
-38600000f8640000
-3d2000014d810020
-612a2600792983e4
-89090000e9240000
-4181004028080020
-70e700017d474436
-2c25000040820028
-2c050010418200e0
-2c08003040820010
-38a0001041820048
-4800008038600000
-f924000039290001
-2c2500004bffffb8
-2c0800304082ffd4
-4082ffdc38a0000a
-2c0a007889490001
-392900024082ffd0
-4bffffc0f9240000
-2c0a007889490001
-4bffffe84082ffb4
-54e7063e38eaffd0
-4181003c28070009
-7d2a07343929ffd0
-4c8000207c0a2800
-7c6519d239080001
-f90400007d290734
-e90400007c691a14
-714900ff89480000
-4e8000204082ffc0
-54e7063e38eaff9f
-4181000c28070019
-4bffffb83929ffa9
-554a063e394affbf
-4d810020280a0019
-4bffffa03929ffc9
-4bffff3438a0000a
-0000000000000000
-3923ff9f00000000
-4181000828090019
-7c6307b43863ffe0
-000000004e800020
+38600000f9240000
+3d4000014d810020
+614a2600794a83e4
+2808002089090000
+7d47443641810038
+4082002070e70001
+418200d02c250000
+418200282c050010
+386000003929ffff
+3929000148000078
+4bffffc4f9240000
+4082ffdc2c250000
+2c08003038a0000a
+894900014082ffd8
+4082ffcc2c0a0078
+38a0001039290002
+4bffffbcf9240000
+54e7063e38e8ffd0
+4181004028070009
+7d480734394affd0
+4c8000207c082800
+392900027c6519d2
+f92400007d4a0734
+7c6a1a147cc93378
+38c9000189090001
+4082ffbc710a00ff
+38e8ff9f4e800020
+2807001954e7063e
+394affa94181000c
+3908ffbf4bffffb4
+280800195508063e
+394affc94d810020
+38a0000a4bffff9c
+000000004bffff38
+0000000000000000
+280900193923ff9f
+3863ffe041810008
+4e8000207c6307b4
 0000000000000000
-38428e583c4c0001
-480008557c0802a6
-7c7e1b78f821ffa1
-7ca32b787cfd3b78
-38a0000a7c9c2378
-eb3e000038800000
-7d1b43787cdf3378
-4bfffe657d3a4b78
-2b9d001060000000
-2c3f000039400000
-2c0a00004082005c
-3940000140820008
-7c0350007d4ad214
-7d2350504081003c
-792900207d2948f8
-7d2903a639290001
-7d594850e93e0000
-408000187c2ae040
-e93e00009b690000
-f93e000039290001
-382100604200ffe0
-409e001048000808
-394a00017bffe102
-7fffeb924bffff94
-000000004bfffff4
-0000078001000000
-38428d883c4c0001
-4800078d7c0802a6
-eb630000f821ffb1
-7c9c23787c7f1b78
-3bc000007cbd2b78
-4bfffd7d7fa3eb78
-7c3e184060000000
-e93f000040800014
-7c2ae0407d5b4850
-382100504180000c
-7d5df0ae48000798
-994900003bde0001
-39290001e93f0000
-4bffffbcf93f0000
+3c4c000100000000
+7c0802a638428e9c
+f821ffa14800086d
+7cfd3b787c7e1b78
+7c9c23787ca32b78
+3880000038a0000a
+7cdf3378eb3e0000
+7d3a4b787d1b4378
+600000004bfffe75
+394000002b9d0010
+4082005c2c3f0000
+418100082c0a0000
+7d4ad21439400001
+4081003c7c035000
+394affff7d4a1850
+392a0001794a0020
+e93e00007d2903a6
+7c2ae0407d594850
+9b69000040800018
+39290001e93e0000
+4200ffe0f93e0000
+4800082038210060
+7bffe102409e0010
+4bffff94394a0001
+4bfffff47fffeb92
 0100000000000000
-3c4c000100000580
-7c0802a638428d0c
-e9297fb03d22ffff
-7d7080262b860010
-916100087caa2b78
-f821ffa1480006f5
+3c4c000100000780
+7c0802a638428dcc
+f821ffb1480007a5
+7c7f1b78eb630000
+7cbd2b787c9c2378
+7fa3eb783bc00000
+600000004bfffd8d
+408000147c3e1840
+7d5b4850e93f0000
+4180000c7c2ae040
+480007b038210050
+3bde00017d5df0ae
+e93f000099490000
+f93f000039290001
+000000004bffffbc
+0000058001000000
+38428d503c4c0001
+3d22ffff7c0802a6
+2b860010e9297f90
+916100087d708026
+f821ffa148000711
 7cbe2b787c7c1b78
 3be000007cdd3378
 3d22fffff9210020
-f9210028e9297fb8
-408200342c2a0000
-408200082c1f0000
-7fff07b43be00001
-7c3f20402e270000
-408100303b7fffff
-8161000838210060
-480006e87d708120
-794ae102409e0010
-4bffffbc3bff0001
-4bfffff47d4aeb92
-7f5eeb927f5ed378
-7d29f0507d3ae9d2
-886900207d214a14
-5463063e41920010
-600000004bfffdd5
-e93c00007c3df040
-3b7bffff7c69d9ae
-e93c00004081ffc8
-f93c00007d29fa14
-000000004bffff90
-0000068003000000
-38428c183c4c0001
-480005e97c0802a6
-7c761b79f821fef1
-38600000f8610060
-2c2400004182003c
-3b04ffff41820034
-3a8000003aa10040
-ebc1006089250000
-7c76f050712a00ff
-7c23c0404182000c
-3920000041800018
-38210110993e0000
-480005e07c6307b4
-390500012c0a0025
-3920000040820564
-7cb32b7889450000
-7d49a9ae8ce50001
-280a007854ea063e
-280a006241810024
-2c0a004f41810024
-2c0a0058418200a0
-2c0a002541820098
-3929000141820090
-3907ff9d4bffffc0
-280400155504063e
-3c82ffff4181ffec
-790815a8388474d0
-7d0822147d0442aa
-4e8004207d0903a6
-0000005800000058
-ffffffccffffffcc
-ffffffccffffffcc
-ffffffcc00000058
-ffffffccffffffcc
-ffffffccffffffcc
-0000005800000058
-ffffffccffffffcc
-ffffffcc00000058
-ffffffcc00000058
-00000058ffffffcc
-2c0a002539090001
-38a1002039290002
-7d2907b47d0807b4
-7d254a147d054214
-9a89002098e80020
+f9210028e9297f98
+2c2900007ca92b78
+2c1f000040820034
+3be0000141810008
+2e2700007fff07b4
+3b7fffff7c3f2040
+3821006040810030
+7d70812081610008
+409e001048000700
+3bff00017929e102
+7d29eb924bffffbc
+7f5ed3784bfffff4
+7d3ae9d27f5eeb92
+7d214a147d29f050
+4192001088690020
+4bfffdd55463063e
+7c3df04060000000
+7c69d9aee93c0000
+4081ffc83b7bffff
+7d29fa14e93c0000
+4bffff90f93c0000
+0300000000000000
+3c4c000100000680
+7c0802a638428c5c
+f821fef148000601
+f86100607c751b79
+4182004438600000
+4182003c2c240000
+3ae4ffff7cbd2b78
+3b2100203a610040
+895d00003a400000
+714900ffebc10060
+4182000c7c75f050
+418000187c23b840
+993e000039200000
+7c6307b438210110
+2c090025480005f0
+40820574391d0001
+7d4999ae39200000
+389d0001895d0001
+280800785548063e
+2808006241810024
+2c08004f41810028
+2c080058418200a4
+2c0800254182009c
+3929000141820094
+4bffffc07c9d2378
+54e5063e38eaff9d
+4181ffe828050015
+38a574943ca2ffff
+7ce53aaa78e715a8
+7ce903a67ce72a14
+000000584e800420
+ffffffc800000058
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc800000058
+00000058ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+38e9000100000058
+392900022c080025
+7d2907b47ce707b4
+7d394a147cf93a14
+9a49002099470020
 393e000140820018
-f9210060995e0000
-4bfffebc38b30002
+995e0000f9210060
+4bfffec03bbd0002
 eb86000089210041
-3a2600087fe3c050
-3b4100423a400030
+3a2600087fe3b850
+3b4100423a800030
 712900fd3929ffd2
-5649063e40820428
-3ae000003de2ffff
-f92100683b200004
+5689063e4082043c
+3ac000003de2ffff
+f92100683b000004
 3a0000003b600000
-4800017039ef7fd0
-38da00012c07004f
-390affa8418201dc
-280500225505063e
-3ca2ffff418103bc
-790815a838a575e8
-7d082a147d0542aa
-4e8004207d0903a6
-0000039c00000158
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-000002680000039c
-0000039c0000008c
-0000039c0000039c
-0000008c00000380
-0000039c0000039c
-0000039c00000368
-000001ac0000039c
-0000039c00000204
-000002ac0000039c
-0000008c0000039c
-0000039c0000039c
-0000039c0000015c
-2c070075000003c0
+4800016c39ef7fb8
+38ba00012c06004f
+38e8ffa8418201e0
+2804002254e4063e
+3c82ffff418103d0
+78e715a8388475a8
+7ce722147ce43aaa
+4e8004207ce903a6
+000003b000000154
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+00000270000003b0
+000003b00000008c
+000003b0000003b0
+0000008c00000394
+000003b0000003b0
+000003b00000037c
+000001b0000003b0
+000003b00000020c
+000002b4000003b0
+0000008c000003b0
+000003b0000003b0
+000003b000000158
+2c060075000003d4
 7d4152147b6a0020
-7f9de37839000000
+7f8ee37839000000
 41820044990a0020
-3940000157281838
-7d4a40363908ffff
-4182002c7f8a5039
+3900000157071838
+7d08383638e7ffff
+4182002c7f884039
 392900013940002d
-9949ffff7fbc00d0
-f92100603d42ffff
-394a7fd07b291e68
-7fbd48387d2a482a
-38e0000ae8810060
-38a100207fa6eb78
-5648063e39200000
-7c9e205038610060
-4bfffabd7c84f850
-7ae707e0e8810060
-7fa5eb7838c0000a
-7c84f8507c9e2050
-4bfffbe938610060
-895a00003b5a0001
-714700ffe9210060
-7fbe485041820010
-4181fe7c7c3fe840
-4bfffe247e268b78
-7b6900203ae00001
-38e00010e9010068
-7c9df8507d214a14
-3861006038a10020
-7b291e689a090020
-392000007d4f482a
-7dc673787f8e5038
-e88100604bfffa39
-38c000107ae707e0
-7dc573787c9e2050
-7b6900204bffff7c
-7d214a1439400000
-7c9df85038e00008
-994900205648063e
-7b291e683d42ffff
-38a10020394a7fd0
-7d4a482a38610060
-7f8e503839200000
-4bfff9dd7dc67378
-7ae707e0e8810060
+7b081e683ce2ffff
+9949ffff38e77fb8
+7d5c00d0f9210060
+7d4e40387d07402a
+38e0000a7c9e4850
+7f25cb787dc67378
+392000007c84f850
+386100605688063e
+e88100604bfffabd
+38c0000a7ac707e0
+7c9e20507dc57378
+386100607c84f850
+3b5a00014bfffbe9
+e9210060891a0000
+41820010710600ff
+7c3f70407dde4850
+7e268b784181fe80
+3ac000014bfffe28
+e90100687b690020
+7d214a1438e00010
+7f25cb787c8ef850
+9a09002038610060
+7d6f482a7b091e68
+7f8b583839200000
+f96100707d665b78
+e88100604bfffa35
+38c000107ac707e0
+e96100707c9e2050
+4bffff747d655b78
+390000007b690020
+38e000087d214a14
+7f25cb787c8ef850
+3d02ffff99090020
+39087fb87b091e68
+7d68482a38610060
+5688063e39200000
+7d665b787f8b5838
+4bfff9d1f9610070
+7ac707e0e8810060
 7c9e205038c00008
-7b6900204bffffa4
-7d214a1439400000
+7b6900204bffff9c
+7d214a1439000000
 7f86e37838e00010
-9949002039000020
-3920000238a10020
-386100607c9df850
-e88100604bfff999
+990900207f25cb78
+392000027c8ef850
+3861006039000020
+e88100604bfff98d
 386100603ca2ffff
-7c9e205038a57fc8
-4bfffa4d7c84f850
-7ae707e0e8810060
+7c9e205038a57fa8
+4bfffa417c84f850
+7ac707e0e8810060
 7f85e37838c00010
-4bfffec07c9e2050
-394000007b690020
-390000207d214a14
-38c0000138e0000a
-38a1002099490020
-7c9df85039200000
-4bfff93538610060
+4bfffeb47c9e2050
+390000007b690020
+38e0000a7d214a14
+7f25cb7838c00001
+7c8ef85099090020
+3900002039200000
+4bfff92938610060
 9b890000e9210060
 f921006039290001
-7b6a00204bfffe88
-f921007039000000
-38a0000a7d415214
-3861002038800000
-4bfff795990a0020
-7c6e1b7860000000
-4bfff75d7f83e378
-7c2e184060000000
-e921007040810048
-7c6370507fbdf850
-38e0002039400000
-7d09f0503bbd0001
-7d08fa147c691a14
-408200082c280000
-2c3d00013ba00001
-408200283bbdffff
-40820034714a0001
-7f85e378e8810060
-7c9e205038610060
-4bfff9557c84f850
-98e900004bfffde8
-3940000139290001
-4082ffc07c291840
-4bffffccf9210060
-3b200008893a0001
-4082fdbc2c09006c
-4bfffdb47cda3378
-3b200002893a0001
-4082fda42c090068
-3b2000017cda3378
-392affd04bfffd98
-280900095529063e
-7b6900204181fd88
-7d214a143b7b0001
-4bfffd7499490020
-4bfffd6c3b200008
-3b4100413a400020
-993e00004bfffbd4
-7d0543783bde0001
-4bfffa54fbc10060
-0100000000000000
-f9c1ff7000001280
-fa01ff80f9e1ff78
-fa41ff90fa21ff88
-fa81ffa0fa61ff98
-fac1ffb0faa1ffa8
-fb01ffc0fae1ffb8
-fb41ffd0fb21ffc8
-fb81ffe0fb61ffd8
-fbc1fff0fba1ffe8
-f8010010fbe1fff8
-e9c1ff704e800020
-ea01ff80e9e1ff78
-ea41ff90ea21ff88
-ea81ffa0ea61ff98
-eac1ffb0eaa1ffa8
-eb01ffc0eae1ffb8
-eb41ffd0eb21ffc8
-eb81ffe0eb61ffd8
-eba1ffe8e8010010
-ebc1fff07c0803a6
-4e800020ebe1fff8
-e8010010ebc1fff0
-7c0803a6ebe1fff8
-600000004e800020
+7b6800204bfffe7c
+f921007838e00000
+38a0000a7d014214
+7f23cb7838800000
+4bfff79998e80020
+f861007060000000
+4bfff7617f83e378
+e901007060000000
+7c281840e9210078
+7d244b7841810020
+7f85e3787c9e2050
+386100607c84f850
+4bfffe184bfff985
+7c6340507ce9f050
+7d4ef8507ce7fa14
+7c691a142c270000
+390000007d244b78
+394a000138c00020
+3940000140820008
+394affff2c2a0001
+7108000140820010
+4bffffa04082001c
+3884000198c40000
+7c24184039000001
+f88100604082ffd8
+893a00014bffff88
+2c09006c3b000008
+7cba2b784082fda4
+893a00014bfffd9c
+2c0900683b000002
+7cba2b784082fd8c
+4bfffd803b000001
+5529063e3928ffd0
+4181fd7028090009
+3b7b00017b690020
+990900207d214a14
+3b0000084bfffd5c
+3a8000204bfffd54
+4bfffbc03b410041
+3bde0001995e0000
+fbc100607d1d4378
+000000004bfffa44
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
+eb21ffc8eb01ffc0
+eb61ffd8eb41ffd0
+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1853,14 +1879,18 @@ e8010010ebc1fff0
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1921,15 +1951,13 @@ e8010010ebc1fff0
 000000000000207c
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
@@ -1971,11 +1999,12 @@ e8010010ebc1fff0
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index 21cfb28..b70854e 100644
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:05
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:38
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -79,19 +79,19 @@ LiteDRAMCore
 └─── cpu (CPUNone)
 └─── crg (LiteDRAMS7DDRPHYCRG)
 │    └─── pll (S7PLL)
-│    │    └─── [BUFG]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [PLLE2_ADV]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
 │    └─── idelayctrl (S7IDELAYCTRL)
 │    │    └─── [IDELAYCTRL]
 └─── ddrphy (A7DDRPHY)
@@ -136,85 +136,72 @@ LiteDRAMCore
 │    └─── bitslip_35* (BitSlip)
 │    └─── tappeddelayline_2* (TappedDelayLine)
 │    └─── tappeddelayline_3* (TappedDelayLine)
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
-│    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [IOBUFDS]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
@@ -222,16 +209,29 @@ LiteDRAMCore
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
 │    └─── [OBUFDS]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
 │    │    └─── pi0 (PhaseInjector)
@@ -543,6 +543,7 @@ wire   [29:0] builder_interface0_adr;
 wire   [13:0] builder_interface0_bank_bus_adr;
 reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_re;
 wire          builder_interface0_bank_bus_we;
 wire    [1:0] builder_interface0_bte;
 wire    [2:0] builder_interface0_cti;
@@ -559,17 +560,22 @@ reg           builder_interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] builder_interface1_bank_bus_adr;
 reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_re;
 wire          builder_interface1_bank_bus_we;
 wire   [31:0] builder_interface1_dat_r;
 reg    [31:0] builder_interface1_dat_w = 32'd0;
 reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
 reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_re = 1'd0;
+reg           builder_interface1_re_next_value2 = 1'd0;
+reg           builder_interface1_re_next_value_ce2 = 1'd0;
 reg           builder_interface1_we = 1'd0;
-reg           builder_interface1_we_next_value2 = 1'd0;
-reg           builder_interface1_we_next_value_ce2 = 1'd0;
+reg           builder_interface1_we_next_value3 = 1'd0;
+reg           builder_interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] builder_interface2_bank_bus_adr;
 reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_re;
 wire          builder_interface2_bank_bus_we;
 reg           builder_locked0 = 1'd0;
 reg           builder_locked1 = 1'd0;
@@ -594,6 +600,7 @@ reg           builder_new_master_wdata_ready0 = 1'd0;
 reg           builder_new_master_wdata_ready1 = 1'd0;
 reg     [1:0] builder_next_state = 2'd0;
 wire          builder_pll_fb;
+wire          builder_re;
 reg     [1:0] builder_refresher_next_state = 2'd0;
 reg     [1:0] builder_refresher_state = 2'd0;
 wire          builder_reset0;
@@ -700,14 +707,14 @@ reg           builder_t_self3 = 1'd0;
 reg           builder_t_self4 = 1'd0;
 reg           builder_t_self5 = 1'd0;
 wire          builder_we;
-wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0;
 wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1;
 wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2;
 wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3;
 wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
@@ -1895,9 +1902,9 @@ reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p0_address;
 wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
 reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_cke;
 reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_odt;
 reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p0_rddata_en;
@@ -1911,9 +1918,9 @@ reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p1_address;
 wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
 reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_cke;
 reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_odt;
 reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p1_rddata_en;
@@ -1927,9 +1934,9 @@ reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p2_address;
 wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
 reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_cke;
 reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_odt;
 reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p2_rddata_en;
@@ -1943,9 +1950,9 @@ reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p3_address;
 wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
 reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_cke;
 reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_odt;
 reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p3_rddata_en;
@@ -4763,42 +4770,26 @@ always @(*) begin
         main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
-end
+assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt;
 assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4831,20 +4822,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector0_command_issue_re) begin
-        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
 assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
 assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4877,20 +4868,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector1_command_issue_re) begin
-        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
 assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
 assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4923,20 +4914,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
 assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
 assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4969,14 +4960,6 @@ always @(*) begin
         main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector3_command_issue_re) begin
-        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
 assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
@@ -5085,82 +5068,82 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_cmd_valid <= 1'd0;
+    main_litedramcore_zqcs_executer_start <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
-            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_cmd_valid <= 1'd1;
             if (main_litedramcore_sequencer_done0) begin
                 if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
-                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            main_litedramcore_cmd_valid <= 1'd1;
-            if (main_litedramcore_zqcs_executer_done) begin
-                main_litedramcore_cmd_valid <= 1'd0;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_zqcs_executer_start <= 1'd0;
+    main_litedramcore_cmd_last <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
             if (main_litedramcore_sequencer_done0) begin
                 if (main_litedramcore_wants_zqcs) begin
-                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
+                    main_litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_cmd_last <= 1'd0;
+    main_litedramcore_sequencer_start0 <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
         end
         2'd2: begin
-            if (main_litedramcore_sequencer_done0) begin
-                if (main_litedramcore_wants_zqcs) begin
-                end else begin
-                    main_litedramcore_cmd_last <= 1'd1;
-                end
-            end
         end
         2'd3: begin
-            if (main_litedramcore_zqcs_executer_done) begin
-                main_litedramcore_cmd_last <= 1'd1;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_sequencer_start0 <= 1'd0;
+    main_litedramcore_cmd_valid <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
-            if (main_litedramcore_cmd_ready) begin
-                main_litedramcore_sequencer_start0 <= 1'd1;
-            end
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                end else begin
+                    main_litedramcore_cmd_valid <= 1'd0;
+                end
+            end
         end
         2'd3: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
+            end
         end
         default: begin
         end
@@ -5306,7 +5289,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
@@ -5331,8 +5314,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine0_row_opened) begin
                         if (main_litedramcore_bankmachine0_row_hit) begin
                             if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -5344,7 +5327,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
@@ -5353,6 +5336,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5363,32 +5349,20 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine0_source_source_valid) begin
-                    if (main_litedramcore_bankmachine0_row_opened) begin
-                        if (main_litedramcore_bankmachine0_row_hit) begin
-                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5401,78 +5375,11 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine0_source_source_valid) begin
-                    if (main_litedramcore_bankmachine0_row_opened) begin
-                        if (main_litedramcore_bankmachine0_row_hit) begin
-                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_row_open <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine0_trccon_ready) begin
-                main_litedramcore_bankmachine0_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
@@ -5737,6 +5644,82 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
 assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
@@ -5876,125 +5859,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_row_open <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine1_trccon_ready) begin
-                main_litedramcore_bankmachine1_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine1_trccon_ready) begin
-                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine1_source_source_valid) begin
-                    if (main_litedramcore_bankmachine1_row_opened) begin
-                        if (main_litedramcore_bankmachine1_row_hit) begin
-                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_row_close <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-            main_litedramcore_bankmachine1_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine1_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine1_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine1_state)
@@ -6308,17 +6172,136 @@ always @(*) begin
         end
     endcase
 end
-assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
-assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
-assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
-assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
-assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
-assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
-assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
-assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+always @(*) begin
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
@@ -6447,32 +6430,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (builder_bankmachine2_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine2_state)
@@ -6879,6 +6836,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
 assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
 assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
@@ -7018,76 +7001,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine3_source_source_valid) begin
-                    if (main_litedramcore_bankmachine3_row_opened) begin
-                        if (main_litedramcore_bankmachine3_row_hit) begin
-                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
-                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine3_state)
@@ -7297,33 +7210,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine3_row_open <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
     case (builder_bankmachine3_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
@@ -7389,6 +7276,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine3_state)
@@ -7450,6 +7363,76 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
 assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
@@ -7589,82 +7572,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine4_source_source_valid) begin
-                    if (main_litedramcore_bankmachine4_row_opened) begin
-                        if (main_litedramcore_bankmachine4_row_hit) begin
-                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
-                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine4_source_source_valid) begin
-                    if (main_litedramcore_bankmachine4_row_opened) begin
-                        if (main_litedramcore_bankmachine4_row_hit) begin
-                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
-                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
     case (builder_bankmachine4_state)
@@ -8021,6 +7928,82 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
 assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
@@ -8105,180 +8088,61 @@ always @(*) begin
     case (builder_bankmachine5_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                if (main_litedramcore_bankmachine5_cmd_ready) begin
-                    builder_bankmachine5_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                builder_bankmachine5_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                if (main_litedramcore_bankmachine5_cmd_ready) begin
-                    builder_bankmachine5_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-                builder_bankmachine5_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            builder_bankmachine5_next_state <= 3'd6;
-        end
-        3'd6: begin
-            builder_bankmachine5_next_state <= 2'd3;
-        end
-        3'd7: begin
-            builder_bankmachine5_next_state <= 4'd8;
-        end
-        4'd8: begin
-            builder_bankmachine5_next_state <= 1'd0;
-        end
-        default: begin
-            if (main_litedramcore_bankmachine5_refresh_req) begin
-                builder_bankmachine5_next_state <= 3'd4;
-            end else begin
-                if (main_litedramcore_bankmachine5_source_source_valid) begin
-                    if (main_litedramcore_bankmachine5_row_opened) begin
-                        if (main_litedramcore_bankmachine5_row_hit) begin
-                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-                                builder_bankmachine5_next_state <= 2'd2;
-                            end
-                        end else begin
-                            builder_bankmachine5_next_state <= 1'd1;
-                        end
-                    end else begin
-                        builder_bankmachine5_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_row_open <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
             if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
             if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
                 if (main_litedramcore_bankmachine5_source_source_valid) begin
                     if (main_litedramcore_bankmachine5_row_opened) begin
                         if (main_litedramcore_bankmachine5_row_hit) begin
-                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine5_row_close <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-            main_litedramcore_bankmachine5_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine5_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine5_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine5_state)
@@ -8592,6 +8456,125 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
 assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
@@ -8731,32 +8714,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (builder_bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine6_state)
@@ -9163,6 +9120,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
 assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
@@ -9303,21 +9286,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9332,12 +9316,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -9360,8 +9341,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9373,22 +9354,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9399,11 +9373,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9428,8 +9417,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
-                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9441,7 +9430,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9466,8 +9455,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9479,7 +9468,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9488,6 +9477,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9498,32 +9490,23 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -9541,10 +9524,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine7_source_source_valid) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
-                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9555,18 +9535,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9607,18 +9587,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9632,34 +9609,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9670,19 +9632,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -9700,9 +9677,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -9724,7 +9704,10 @@ always @(*) begin
                 if (main_litedramcore_bankmachine7_source_source_valid) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -10328,10 +10311,14 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_en1 <= 1'd0;
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            main_litedramcore_en1 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -10352,18 +10339,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    main_litedramcore_en1 <= 1'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-            end
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -10384,11 +10372,6 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-            end
         end
     endcase
 end
@@ -10493,64 +10476,82 @@ always @(*) begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
+                builder_interface1_adr_next_value1 <= builder_interface0_adr;
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface0_ack <= 1'd0;
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
     case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            builder_interface0_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    builder_interface1_re_next_value2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_adr_next_value_ce1 <= 1'd1;
+            builder_interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value_ce1 <= 1'd1;
+                builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0));
+            end
+        end
+    endcase
+end
+always @(*) begin
+    builder_interface1_re_next_value_ce2 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_re_next_value_ce2 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_re_next_value_ce2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value2 <= 1'd0;
+    builder_interface1_we_next_value3 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value2 <= 1'd0;
+            builder_interface1_we_next_value3 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+                builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value_ce2 <= 1'd0;
+    builder_interface1_we_next_value_ce3 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value_ce2 <= 1'd1;
+            builder_interface1_we_next_value_ce3 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value_ce2 <= 1'd1;
+                builder_interface1_we_next_value_ce3 <= 1'd1;
             end
         end
     endcase
@@ -10579,6 +10580,18 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+        end
+        2'd2: begin
+            builder_interface0_ack <= 1'd1;
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     builder_interface1_dat_w_next_value_ce0 <= 1'd0;
     case (builder_state)
@@ -10596,7 +10609,7 @@ assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
     builder_csrbank0_init_done0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10607,15 +10620,15 @@ always @(*) begin
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_error0_we <= 1'd0;
+    builder_csrbank0_init_error0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_error0_re <= 1'd0;
+    builder_csrbank0_init_error0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re;
     end
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
@@ -10623,41 +10636,41 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage;
 assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_rst0_we <= 1'd0;
+    builder_csrbank1_rst0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_rst0_re <= 1'd0;
+    builder_csrbank1_rst0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_dly_sel0_re <= 1'd0;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_dly_sel0_we <= 1'd0;
+    builder_csrbank1_dly_sel0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
@@ -10670,53 +10683,53 @@ end
 always @(*) begin
     builder_csrbank1_wlevel_en0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10727,75 +10740,75 @@ always @(*) begin
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_rdphase0_re <= 1'd0;
+    builder_csrbank1_rdphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_rdphase0_we <= 1'd0;
+    builder_csrbank1_rdphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_wrphase0_we <= 1'd0;
+    builder_csrbank1_wrphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_wrphase0_re <= 1'd0;
+    builder_csrbank1_wrphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage;
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage;
 assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage;
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage;
 assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
@@ -10807,14 +10820,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_control0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10825,15 +10838,15 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
@@ -10846,14 +10859,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10862,11 +10875,11 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10875,7 +10888,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
@@ -10885,14 +10898,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10903,22 +10916,22 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10937,14 +10950,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10953,7 +10966,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
@@ -10963,7 +10976,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
@@ -10976,27 +10989,27 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
     builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11015,10 +11028,10 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
@@ -11028,14 +11041,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11054,7 +11067,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
@@ -11067,7 +11080,7 @@ end
 always @(*) begin
     main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
@@ -11080,14 +11093,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11096,7 +11109,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
@@ -11106,14 +11119,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11126,7 +11139,7 @@ assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
 assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage;
 assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
 assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
 assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
@@ -11135,11 +11148,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
 assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
 assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage;
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage;
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage;
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status;
 assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
 assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
@@ -11149,11 +11162,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
 assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
 assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage;
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage;
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage;
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status;
 assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
 assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
@@ -11163,11 +11176,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
 assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
 assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage;
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage;
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage;
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status;
 assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
 assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
@@ -11177,19 +11190,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
 assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
 assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage;
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage;
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage;
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status;
 assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_adr = builder_interface1_adr;
+assign builder_re = builder_interface1_re;
 assign builder_we = builder_interface1_we;
 assign builder_dat_w = builder_interface1_dat_w;
 assign builder_interface1_dat_r = builder_dat_r;
 assign builder_interface0_bank_bus_adr = builder_adr;
 assign builder_interface1_bank_bus_adr = builder_adr;
 assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_re = builder_re;
+assign builder_interface1_bank_bus_re = builder_re;
+assign builder_interface2_bank_bus_re = builder_re;
 assign builder_interface0_bank_bus_we = builder_we;
 assign builder_interface1_bank_bus_we = builder_we;
 assign builder_interface2_bank_bus_we = builder_we;
@@ -11915,16 +11932,16 @@ always @(*) begin
     builder_self0 <= 3'd0;
     case (main_litedramcore_steerer0)
         1'd0: begin
-            builder_self0 <= main_litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12034,16 +12051,16 @@ always @(*) begin
     builder_self7 <= 3'd0;
     case (main_litedramcore_steerer1)
         1'd0: begin
-            builder_self7 <= main_litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12153,16 +12170,16 @@ always @(*) begin
     builder_self14 <= 3'd0;
     case (main_litedramcore_steerer2)
         1'd0: begin
-            builder_self14 <= main_litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12272,16 +12289,16 @@ always @(*) begin
     builder_self21 <= 3'd0;
     case (main_litedramcore_steerer3)
         1'd0: begin
-            builder_self21 <= main_litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12387,10 +12404,10 @@ always @(*) begin
         end
     endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -13989,8 +14006,11 @@ always @(posedge sys_clk) begin
     if (builder_interface1_adr_next_value_ce1) begin
         builder_interface1_adr <= builder_interface1_adr_next_value1;
     end
-    if (builder_interface1_we_next_value_ce2) begin
-        builder_interface1_we <= builder_interface1_we_next_value2;
+    if (builder_interface1_re_next_value_ce2) begin
+        builder_interface1_re <= builder_interface1_re_next_value2;
+    end
+    if (builder_interface1_we_next_value_ce3) begin
+        builder_interface1_we <= builder_interface1_we_next_value3;
     end
     builder_interface0_bank_bus_dat_r <= 1'd0;
     if (builder_csrbank0_sel) begin
@@ -14060,11 +14080,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
     if (builder_csrbank1_dly_sel0_re) begin
-        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+        main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r;
     end
     main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
     if (builder_csrbank1_half_sys8x_taps0_re) begin
-        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+        main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r;
     end
     main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
     if (builder_csrbank1_wlevel_en0_re) begin
@@ -14072,11 +14092,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
     if (builder_csrbank1_rdphase0_re) begin
-        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+        main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r;
     end
     main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
     if (builder_csrbank1_wrphase0_re) begin
-        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+        main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r;
     end
     main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
     builder_interface2_bank_bus_dat_r <= 1'd0;
@@ -14160,74 +14180,74 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (builder_csrbank2_dfii_control0_re) begin
-        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+        main_litedramcore_storage <= builder_csrbank2_dfii_control0_r;
     end
     main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
     if (builder_csrbank2_dfii_pi0_command0_re) begin
-        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
+        main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r;
     end
     main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
     if (builder_csrbank2_dfii_pi0_address0_re) begin
-        main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
+        main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r;
     end
     main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
     if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+        main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
     main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
     if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+        main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
     main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
     main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
     if (builder_csrbank2_dfii_pi1_command0_re) begin
-        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
+        main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r;
     end
     main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
     if (builder_csrbank2_dfii_pi1_address0_re) begin
-        main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
+        main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r;
     end
     main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
     if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+        main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
     main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
     if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+        main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
     main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
     main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
     if (builder_csrbank2_dfii_pi2_command0_re) begin
-        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
+        main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r;
     end
     main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
     if (builder_csrbank2_dfii_pi2_address0_re) begin
-        main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
+        main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r;
     end
     main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
     if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+        main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
     main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
     if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+        main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
     main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
     main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
     if (builder_csrbank2_dfii_pi3_command0_re) begin
-        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
+        main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r;
     end
     main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
     if (builder_csrbank2_dfii_pi3_address0_re) begin
-        main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
+        main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r;
     end
     main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
     if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+        main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
     main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
     if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+        main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
     main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
     main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
@@ -14500,6 +14520,7 @@ always @(posedge sys_clk) begin
         main_init_done_re <= 1'd0;
         main_init_error_storage <= 1'd0;
         main_init_error_re <= 1'd0;
+        builder_interface1_re <= 1'd0;
         builder_interface1_we <= 1'd0;
         builder_refresher_state <= 2'd0;
         builder_bankmachine0_state <= 4'd0;
@@ -17453,7 +17474,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
@@ -17471,7 +17492,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (iodelay_rst)
@@ -17489,7 +17510,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
@@ -17507,7 +17528,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (sys_rst)
@@ -17525,7 +17546,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
@@ -17543,7 +17564,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
@@ -17561,7 +17582,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
@@ -17579,7 +17600,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
@@ -17588,5 +17609,5 @@ FDPE #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:06.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:38.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/ecpix-5/litedram_core.init b/litedram/generated/ecpix-5/litedram_core.init
index ecf50a2..130d4d6 100644
--- a/litedram/generated/ecpix-5/litedram_core.init
+++ b/litedram/generated/ecpix-5/litedram_core.init
@@ -523,14 +523,14 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
 7c0802a63842ada4
-f821ffc148002809
+f821ffc148002815
 3ba000053bc06000
 4bffff8567dec000
 7fa0f7aa7c0004ac
 7fe0f6aa7c0004ac
 73ff00014bffff95
 382100404082ffe4
-0000000048002820
+000000004800282c
 0000038001000000
 3842ad503c4c0001
 fbe1fff87c0802a6
@@ -540,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48002155f9410108
+48002149f9410108
 7c7f1b7860000000
 48001ba538610020
 382100b060000000
-480027c87fe3fb78
+480027d47fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -553,54 +553,54 @@ f9210100f90100f8
 0000000000000000
 3c4c000100000000
 7c0802a63842acb4
-480026fd7d600026
+480027097d600026
 f821fec191610008
 6000000048001ba1
-38637af03c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+38637af83c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637b103be00008
+38637b183be00008
 4bffff1d67ffc000
-38637b303c62ffff
+38637b383c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637b48
+4bfffef538637b50
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637b50
+4bfffedd38637b58
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b58
+4bfffec538637b60
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b60
+4bfffead38637b68
 4182001073e90010
-38637b703c62ffff
+38637b783c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637b80
-3b397b883f22ffff
+4bfffe8538637b88
+3b397b903f22ffff
 4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637b907884b582
+38637b987884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637ba8
+4bfffe2d38637bb0
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637bc0
+4bfffe0d38637bc8
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637bd87c892392
+38637be07c892392
 3b8000003be00000
 418a04204bfffdd9
 675ac0003b400038
@@ -613,7 +613,7 @@ f821fec191610008
 7fa0f6aa7c0004ac
 3c62ffff4bfffcfd
 5785063e57a6063e
-38637bf857e4063e
+38637c0057e4063e
 4bfffd75579b063e
 57b7063e7fe9e378
 57f8063e7d29eb78
@@ -633,9 +633,9 @@ f821fec191610008
 7c0004ac7fc0ffaa
 4bfffc597fc0feaa
 57c4063e3c62ffff
-4bfffcdd38637c18
+4bfffcdd38637c20
 4082006473c90002
-38637c383c62ffff
+38637c403c62ffff
 4bfffc0d4bfffcc9
 7c0004ac39200006
 4bfffc217d20ffaa
@@ -652,46 +652,46 @@ f821fec191610008
 2c1b00ba408201c8
 2c17001840820284
 3c62ffff4082027c
-4bfffc4538637c48
+4bfffc4538637c50
 73ff00014bffffd0
 3c62ffff418200a4
-4bfffc2d38637ce8
+4bfffc2d38637cf0
 38a000403c9cf000
 3861007078840020
 6000000048001975
 3d200002e9410070
 6129464c3c62ffff
-792983e438637d00
+792983e438637d08
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637d203c62ffff
+38637d283c62ffff
 892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d8088810070
+38637d8888810070
 89210075f9210060
 3c62ffff4bfffb99
-4bfffb8d38637db0
-3880600038a00000
-6484ff0060a5a000
+4bfffb8d38637db8
+3880f80338a00000
+7884682860a5a000
 480018d13c604000
 3c62ffff60000000
-4bfffb6538637dd0
+4bfffb6538637dd8
 480002184bfffbdd
 3f22ffffebe10090
-3b397d383ba00000
+3b397d403ba00000
 a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffb2d38637d60
+4bfffb2d38637d68
 e86100884bfffba5
 4182ff882c23ffff
 8161000838210140
-480022fc7d638120
+480023087d638120
 38a000383c9ff000
 386100b078840020
 6000000048001855
@@ -710,13 +710,13 @@ ebc100b8eb6100c0
 2c1b0060577b0734
 2c170019408200b4
 3c62ffff408200ac
-4bfffa7538637c50
+4bfffa7538637c58
 392000054bfff9b9
 7d20f7aa7c0004ac
 7fe0f6aa7c0004ac
 73e900404bfff9c5
 3c62ffff40820048
-4bfffa4538637c58
+4bfffa4538637c60
 392000064bfff989
 7d20f7aa7c0004ac
 4bfff9754bfff99d
@@ -725,29 +725,29 @@ ebc100b8eb6100c0
 7fe0f7aa7c0004ac
 4bfff9b94bfff97d
 63ff3f6c3fe02000
-38637c703c62ffff
+38637c783c62ffff
 394060084bfff9f9
 7c0004ac654ac000
 5529021e7d20562a
 7c0004ac7d29fb78
 7f23cb787d20572a
 3c62ffff4bfff9d1
-38637c807b440020
+38637c887b440020
 4bfff9bd7f5cd378
 7f23cb783be00001
 419200384bfff9b1
-792900203d20c800
+7929d80039200019
 7d204e2a7c0004ac
 408200202c090000
 3c62ffff3c82ffff
-38637cb038847ca0
+38637cb838847ca8
 480009ad4bfff981
 3940002860000000
 7c0004ac654ac000
 7929e0427d2056ea
 7c0004ac79292000
 418efd187d2057ea
-38637cd03c62ffff
+38637cd83c62ffff
 386000004bfff949
 000000004bfffe28
 0000098003000000
@@ -775,18 +775,17 @@ ebc100b8eb6100c0
 0000000000000000
 3c4c000100000000
 7c0802a63842a5c4
-f821ff3148001fed
-23a300073b400001
-3ec2ffff7f5a1830
-3b20100c3aa00003
-3a8010143b001010
-206300033a601018
-3b6000003bc00000
-66b580203ad67ec8
-6739c8003ae00001
-6694c8006718c800
-7fbd07b46673c800
-7bc917647c7f07b4
+f821ff3148001ffd
+23a300033b400001
+600000007f5a1830
+3b20100c3ea0e008
+206300073b001010
+3bc000003a80103c
+3ac2803c3b600000
+3ae000017ab51020
+6718c8006739c800
+7c7f07b47fbd07b4
+7bc917646694c800
 38a0000238e10020
 7d56482e7cfc3b78
 4800004439000000
@@ -806,19 +805,21 @@ f821ff3148001fed
 7c0004ac39200000
 7c0004ac7d20cf2a
 386000097d20c72a
-3860000f4bfffe65
-38e000044bfffe41
+3860000f4bfffe6d
+38e000044bfffe49
 7ce903a63901001f
 3940000039200004
 3929ffff8ce80001
 7cea3b787947400c
-7c0004ac4200fff0
-38e000047ce0a72a
+390010144200fff0
+7c0004ac6508c800
+38e000047ce0472a
 7ce903a639010023
 8ce8000139400004
 7927400c394affff
 4200fff07ce93b78
-7ce09f2a7c0004ac
+6508c80039001018
+7ce0472a7c0004ac
 3901002738e00004
 392000047ce903a6
 3929ffff8ce80001
@@ -831,100 +832,99 @@ f821ff3148001fed
 4200fff47d094378
 654ac80039401038
 7d00572a7c0004ac
-3a4000003920102c
+3a6000003920102c
 7c0004ac6529c800
-392010307e404f2a
+392010307e604f2a
 7c0004ac6529c800
-394010247e404f2a
+394010247e604f2a
 654ac80039200017
 7d20572a7c0004ac
 6529c80039201028
 7ee04f2a7c0004ac
-4bfffd353860000f
+4bfffd2d3860000f
 6529c80039200814
 7ee04f2a7c0004ac
-7e40cf2a7c0004ac
-7e40c72a7c0004ac
-4bfffd2938600025
-4bfffd053860000f
-7e40cf2a7c0004ac
-7e40c72a7c0004ac
-7e3cea143860000b
-3860000f4bfffd05
-4bfffcdd39c00000
-7f9cfa147e2f8b78
-6529c8003920101c
+7e60cf2a7c0004ac
+7e60c72a7c0004ac
+4bfffd2138600025
+4bfffcfd3860000f
+7e60cf2a7c0004ac
+7e60c72a7c0004ac
+7e5cea143860000b
+3860000f4bfffcfd
+4bfffcd539e00000
+7f9cfa143920101c
+7e5193786529c800
 7d404e2a7c0004ac
 794a002038e00004
 390100347ce903a6
 794ac2029d48ffff
 392900044200fff8
 7d204e2a7c0004ac
-8871000039410034
-892f00107d20552c
-5463063e7c634a78
-7d3d88504bfffcd1
-7c701b783a310008
+7d20552c39410034
+3a5200087d3d9050
 893c00107c69f8ae
 5463063e7c634a78
-2c0e00004bfffcb1
-7e521a147c638214
-3920081841820040
-7c0004ac6529c800
-7f4948387d204e2a
-408200082c090000
-3bde00013a520001
-283e00037f7b9214
-382100d04082fd3c
-48001d107f6307b4
-3920103c39c00001
-000000004bffff3c
-0000128001000000
-3842a2703c4c0001
+893100104bfffcc1
+8872fff87c701b78
+5463063e7c634a78
+2c0f00014bfffca9
+7c6382147e89a378
+408200407e731a14
+6529c80039200818
+7d204e2a7c0004ac
+2c0900007f494838
+3a73000140820008
+7f7b9a143bde0001
+4082fd28283e0003
+7f6307b4382100d0
+39e0000148001d14
+000000004bffff40
+0000118001000000
+3842a2683c4c0001
 388000007c0802a6
-f821ff6148001cbd
+f821ff6148001cc1
 3b1864f43f02ffff
 3bc000007c7d1b78
 7f05c3783b800000
-600000004800083d
-4bfffc797fa3eb78
+6000000048000835
+4bfffc717fa3eb78
 7c7f00342c030000
 4082006857ffd97e
 418200602c1c0000
 7ff9fb783bfeffff
 7fdbf3787ffcfb78
 3b5b00017fa3eb78
-2c0300004bfffc45
+2c0300004bfffc3d
 7d39d85040820070
 7c0950007d5fe050
 2c1a000741810068
 3ca2ffff4181006c
 3880000038a564ac
 7f5bd3787fa3eb78
-60000000480007c5
+60000000480007bd
 3bde00014bffffb8
 418200242c1e0008
 38a564ac3ca2ffff
 7fa3eb7838800000
-480007997ffcfb78
+480007917ffcfb78
 4bffff5c60000000
 4bffff783be0ffff
 4bffffa07f59d378
 7f3fcb787f7cdb78
 2c1c00004bffff94
-7fc907b440800024
-212900073b800000
-418000082c290000
+2c1e00084080001c
+418200083b800000
 3bde0001239e0007
 2c1f00007f9cf214
 3c62ffff4080001c
-4bfff3f538637de8
+4bfff3f538637df0
 382100a060000000
-7cbfe05048001bdc
-7ca50e707c9cfa14
+7cbfe05048001be8
+7ca50e707c9fe214
 789bff627ca50194
 7ca507b43c62ffff
-38637df87f64db78
+38637e007f64db78
 4bfff3bd3be00008
 7f05c37860000000
 7fa3eb7838800000
@@ -949,7 +949,7 @@ f821ff6148001cbd
 3940000e7c0802a6
 f821ffa1f8010010
 7d404f2a7c0004ac
-38637e103c62ffff
+38637e183c62ffff
 600000004bfff2f9
 e801001038210060
 4e8000207c0803a6
@@ -962,20 +962,20 @@ e801001038210060
 f801001039400001
 7c0004acf821ffa1
 3c62ffff7d404f2a
-4bfff29538637e38
+4bfff29538637e40
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
 38429fb83c4c0001
-480019f57c0802a6
+48001a017c0802a6
 3f02fffff821ff31
 3ec2ffff3b18657c
 3e82ffff3ea2ffff
 3e62ffff3ee2ffff
-3ad67e603b400000
-3a947e783ab57e70
-3a737e803af77b88
+3ad67e683b400000
+3a947e803ab57e78
+3a737e883af77b90
 7f05c3787f5f07b4
 7fe3fb7838800000
 600000004800055d
@@ -994,11 +994,11 @@ f801001039400001
 3ba000007fe3fb78
 60000000480004ed
 4bfff9297fe3fb78
-7c64003439400000
-5484d97e212300c0
-418200082c040000
-7d29521439400600
-7ea3ab78788407e0
+7c64003439200000
+2c0400005484d97e
+3920060041820008
+788407e0206300c0
+7ea3ab787d291a14
 4bfff16d7fbd4a14
 3ca2ffff60000000
 3880000038a564ac
@@ -1006,7 +1006,7 @@ f801001039400001
 3739ffff60000000
 7e83a3784082ffa8
 600000004bfff141
-4bfffc157fe3fb78
+4bfffc1d7fe3fb78
 4bfff12d7ee3bb78
 7c1ce84060000000
 7f9de3784180ff20
@@ -1016,17 +1016,17 @@ f801001039400001
 7f05c37860000000
 7fe3fb7838800000
 6000000048000435
-418000287c1ed800
-4bfffbbd7fe3fb78
+408200307c1ed800
+4bfffbc57fe3fb78
 4bfff0d57ee3bb78
-2c1a000060000000
-3b4000014082002c
-3ca2ffff4bfffe98
+393a000160000000
+2c0900023b400001
+382100d04082fe98
+3ca2ffff480018a4
 3880000038a56534
 3bde00017fe3fb78
-60000000480003ed
-382100d04bffffb8
-0000000048001878
+60000000480003e5
+000000004bffffb0
 00000d8001000000
 38429dd03c4c0001
 fbc1fff07c0802a6
@@ -1044,18 +1044,18 @@ f8010010fbe1fff8
 7fe5fb7860000000
 3860000138800000
 6000000048000355
-38637e983c62ffff
+38637ea03c62ffff
 600000004bfff001
 4bfffd294bfffd91
 3860000138210070
-0000000048001808
+0000000048001814
 0000028001000000
 38429d203c4c0001
 3c62ffff7c0802a6
-38637ea83c804000
-f821ff714800176d
-3be000003f60c800
-4bffefad7b7b0020
+38637eb03c804000
+f821ff7148001779
+3be000003b600019
+4bffefad7b7bd800
 4bfffc7560000000
 7fe0df2a7c0004ac
 675ac8003b400004
@@ -1100,7 +1100,7 @@ f821ff714800176d
 7c0004ac7c691b78
 7c0004ac7f80d72a
 382100907f80df2a
-480016407d2307b4
+4800164c7d2307b4
 38a0000038c00000
 3c6040003c800020
 6000000048000635
@@ -1168,7 +1168,7 @@ ebc1fff0e8010010
 282303ff7c0802a6
 f821ffa1f8010010
 7c641b7841810028
-38637ed83c62ffff
+38637ed03c62ffff
 600000004bffec21
 e801001038210060
 4e8000207c0803a6
@@ -1176,18 +1176,18 @@ e801001038210060
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffebe538637ee0
+4bffebe538637ed8
 4bffffc460000000
 786465023d204000
 408000247c234840
 788955647863b282
 38a000667d291850
 7ca92b923c62ffff
-4bffffc838637ef0
+4bffffc838637ee8
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637f007ca54b92
+38637ef87ca54b92
 000000004bffffa4
 0000008001000000
 384298c03c4c0001
@@ -1195,13 +1195,13 @@ fbe1fff87c0802a6
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-f801001038637f10
+f801001038637f08
 4bffeb45f821ff91
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffeb2d38637f20
+4bffeb2d38637f18
 3821007060000000
-0000000048001344
+0000000048001350
 0000018001000000
 418200242c240000
 786307e07869f842
@@ -1214,7 +1214,7 @@ f801001038637f10
 7c0802a63842981c
 3d40aaaa78840764
 614aaaaa7c691b78
-7f8322144800126d
+7f83221448001279
 f821ffc17884f082
 7c7f1b7839040001
 7c7d1b787d0903a6
@@ -1233,7 +1233,7 @@ f821ffc17884f082
 395f00013d205555
 7d4903a661295555
 3821004042000040
-480012207fc307b4
+4800122c7fc307b4
 3929000491490000
 812a00004bffff78
 418200087c094000
@@ -1247,42 +1247,42 @@ f821ffc17884f082
 3c4c000100000480
 7d6000263842970c
 916100087c0802a6
-480011452e260000
+480011512e260000
 7c7f1b78f821ff41
 7cde33787cba2b78
-419200c0789cf082
+419200e4789cf082
 82e6000081260004
-408200442c090000
-3ba000003f02ffff
-7bf900203b600001
-7c3ce8403b187f28
-3c62ffff4082009c
-38637f287b851028
-4bfffde57be40020
-38637b883c62ffff
-600000004bffe949
-600000004bffe9ad
+418200d82c090000
+600000004bffe9ed
 7ffbfb782d970000
 3ac000013ba00000
 7bf500203b200000
-7fb8eb787c3de040
-2c17000040820084
+7fb8eb787c3ce840
+2c170000408200c4
 3c62ffff41820028
-38637f387b051028
-4bfffd8d7be40020
-38637b883c62ffff
-600000004bffe8f1
+38637f307b051028
+4bfffdcd7be40020
+38637b903c62ffff
+600000004bffe931
 7f2307b4382100c0
 7d61812081610008
-3ae00001480010c0
-7b6300204bffff50
-4bfffdb57f44d378
+7b6300204800110c
+4bfffdfd7f44d378
 7c7f492e7ba91764
 7c7b1b7873a97fff
 7ba5102840820014
 7f03c3787f24cb78
-3bbd00014bfffd31
-7f44d3784bffff2c
+3bbd00014bfffd79
+4082ffc87c3ce840
+7b8510283c62ffff
+7be4002038637f20
+3c62ffff4bfffd59
+4bffe8bd38637b90
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187f207bf90020
+7f44d3784bffffb8
 4bfffd7d7ac30020
 7c651b78809b0000
 7c0320407c761b78
@@ -1293,29 +1293,29 @@ e8de00107d8903a6
 f841001878840020
 4e8004217b630020
 2c030000e8410018
-73187fff4082ff58
+73187fff4082ff18
 418e00184082001c
 7ba510283c62ffff
-38637f387ea4ab78
+38637f307ea4ab78
 3bbd00014bfffcb1
-4bfffef43b7b0004
+4bfffeb43b7b0004
 0300000000000000
 3c4c000100000b80
 7d7080263842954c
 916100087c0802a6
-f821ff7148000f9d
+f821ff7148000fa9
 3ba4ffe07cdb3378
 7c7f1b782e3b0000
 7fa3ea147c9e2378
 3c62ffff7c641b78
-7cbc2b7838637f48
+7cbc2b7838637f40
 600000004bffe7c1
-38637f603c62ffff
+38637f583c62ffff
 3c62ffff4092000c
-4bffe7a538637f70
+4bffe7a538637f68
 7fc3f37860000000
 3c62ffff4bfffb59
-4bffe78d38637f80
+4bffe78d38637f78
 2c3c000060000000
 7cf602a6408200a8
 38bd002038df0020
@@ -1331,12 +1331,12 @@ f90a0018f90a0010
 639cf08078ea0020
 7f9ee1d279290020
 3c62ffff7d295050
-7f9c4b9238637f88
+7f9c4b9238637f80
 600000004bffe709
 4bfffabd7f83e378
-38637f983c62ffff
+38637f903c62ffff
 600000004bffe6f1
-38637b883c62ffff
+38637b903c62ffff
 600000004bffe6e1
 600000004bffe745
 409200487f9602a6
@@ -1355,16 +1355,16 @@ e95f0018e95f0010
 7b9c00203d4002fa
 79290020614af080
 7d29e0507fde51d2
-38637fa03c62ffff
+38637f983c62ffff
 4bffe6457fde4b92
 7fc3f37860000000
 3c62ffff4bfff9f9
-4bffe62d38637f98
+4bffe62d38637f90
 3c62ffff60000000
-4bffe61d38637b88
+4bffe61d38637b90
 3821009060000000
 7d70812081610008
-7fa407b448000e04
+7fa407b448000e10
 4bfffaed79430020
 7d23db963bbd0001
 7d29d9d67c6a1b78
@@ -1373,15 +1373,15 @@ e95f0018e95f0010
 0300000000000000
 3c4c000100000680
 7c0802a638429314
-48000d7128240200
+48000d7d28240200
 7c7e1b78f821ff81
 3b8002007c9f2378
 7c9c237841810008
 7fc4f3783c62ffff
-4bffe59538637fb0
+4bffe59538637fa8
 7fe3fb7860000000
 3c62ffff4bfff949
-4bffe57d38637f80
+4bffe57d38637f78
 7f84e37860000000
 4bfffaa17fc3f378
 38a0000138c00000
@@ -1390,22 +1390,22 @@ e95f0018e95f0010
 7c7e1b787d23ea14
 418200802c090000
 7b85f8823c62ffff
-38637fc07fa4eb78
+38637fb87fa4eb78
 600000004bffe531
 7fe5fb78283f8000
 38a0ffff4081000c
 3c62ffff54a50420
 3880000078a5f082
-4bffe50538637fd8
+4bffe50538637fd0
 3c62ffff60000000
 7fc4f3787be5f082
-4bffe4ed38637ff0
+4bffe4ed38637fe8
 6000000060000000
-4bffe4dd38628008
+4bffe4dd38628000
 3860000060000000
 786307e038210080
-6000000048000ccc
-4bffe4bd38628018
+6000000048000cd8
+4bffe4bd38628010
 3860000160000000
 000000004bffffe0
 0000048001000000
@@ -1432,10 +1432,10 @@ fbe1fff87c0802a6
 f821ffd1f8010010
 2c1e00008fdf0001
 3821003040820010
-48000c0438600000
+48000c1038600000
 4082000c2c1e000a
 4bffff3d3860000d
-4bffff3557c3063e
+4bffff357bc30020
 000000004bffffd0
 0000028001000000
 384291003c4c0001
@@ -1474,352 +1474,353 @@ e92280a07d404faa
 0000000000000000
 78a9e8c200000000
 3929000139400000
-420000287d2903a6
-78a5076078a90724
-7d434a1439050001
-7c844a147d0903a6
-4200001839200000
-7d24502a4e800020
-394a00087d23512a
-7d0448ae4bffffcc
-392900017d0a49ae
-000000004bffffdc
-0000000000000000
-386000007c691b78
-2c0a00007d4918ae
-386300014d820020
-000000004bfffff0
-0000000000000000
-408200082c240000
+4200002c7d2903a6
+3940000078a9e8c2
+7ca54a141d29fff8
+390500017c892050
+7d0903a67d291850
+4e80002042000018
+7d23512a7d24502a
+4bffffc8394a0008
+7d0951ae7d0450ae
+4bffffdc394a0001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
+0000000000000000
+2c24000000000000
+408200087c691b78
 280500243881fff0
-38600000f8640000
-3d2000014d810020
-612a2600792983e4
-89090000e9240000
-4181004028080020
-70e700017d474436
-2c25000040820028
-2c050010418200e0
-2c08003040820010
-38a0001041820048
-4800008038600000
-f924000039290001
-2c2500004bffffb8
-2c0800304082ffd4
-4082ffdc38a0000a
-2c0a007889490001
-392900024082ffd0
-4bffffc0f9240000
-2c0a007889490001
-4bffffe84082ffb4
-54e7063e38eaffd0
-4181003c28070009
-7d2a07343929ffd0
-4c8000207c0a2800
-7c6519d239080001
-f90400007d290734
-e90400007c691a14
-714900ff89480000
-4e8000204082ffc0
-54e7063e38eaff9f
-4181000c28070019
-4bffffb83929ffa9
-554a063e394affbf
-4d810020280a0019
-4bffffa03929ffc9
-4bffff3438a0000a
-0000000000000000
-3923ff9f00000000
-4181000828090019
-7c6307b43863ffe0
-000000004e800020
+38600000f9240000
+3d4000014d810020
+614a2600794a83e4
+2808002089090000
+7d47443641810038
+4082002070e70001
+418200d02c250000
+418200282c050010
+386000003929ffff
+3929000148000078
+4bffffc4f9240000
+4082ffdc2c250000
+2c08003038a0000a
+894900014082ffd8
+4082ffcc2c0a0078
+38a0001039290002
+4bffffbcf9240000
+54e7063e38e8ffd0
+4181004028070009
+7d480734394affd0
+4c8000207c082800
+392900027c6519d2
+f92400007d4a0734
+7c6a1a147cc93378
+38c9000189090001
+4082ffbc710a00ff
+38e8ff9f4e800020
+2807001954e7063e
+394affa94181000c
+3908ffbf4bffffb4
+280800195508063e
+394affc94d810020
+38a0000a4bffff9c
+000000004bffff38
+0000000000000000
+280900193923ff9f
+3863ffe041810008
+4e8000207c6307b4
 0000000000000000
-38428e003c4c0001
-480008557c0802a6
-7c7e1b78f821ffa1
-7ca32b787cfd3b78
-38a0000a7c9c2378
-eb3e000038800000
-7d1b43787cdf3378
-4bfffe657d3a4b78
-2b9d001060000000
-2c3f000039400000
-2c0a00004082005c
-3940000140820008
-7c0350007d4ad214
-7d2350504081003c
-792900207d2948f8
-7d2903a639290001
-7d594850e93e0000
-408000187c2ae040
-e93e00009b690000
-f93e000039290001
-382100604200ffe0
-409e001048000808
-394a00017bffe102
-7fffeb924bffff94
-000000004bfffff4
-0000078001000000
-38428d303c4c0001
-4800078d7c0802a6
-eb630000f821ffb1
-7c9c23787c7f1b78
-3bc000007cbd2b78
-4bfffd7d7fa3eb78
-7c3e184060000000
-e93f000040800014
-7c2ae0407d5b4850
-382100504180000c
-7d5df0ae48000798
-994900003bde0001
-39290001e93f0000
-4bffffbcf93f0000
+3c4c000100000000
+7c0802a638428e0c
+f821ffa14800086d
+7cfd3b787c7e1b78
+7c9c23787ca32b78
+3880000038a0000a
+7cdf3378eb3e0000
+7d3a4b787d1b4378
+600000004bfffe75
+394000002b9d0010
+4082005c2c3f0000
+418100082c0a0000
+7d4ad21439400001
+4081003c7c035000
+394affff7d4a1850
+392a0001794a0020
+e93e00007d2903a6
+7c2ae0407d594850
+9b69000040800018
+39290001e93e0000
+4200ffe0f93e0000
+4800082038210060
+7bffe102409e0010
+4bffff94394a0001
+4bfffff47fffeb92
 0100000000000000
-3c4c000100000580
-7c0802a638428cb4
-e922802860000000
-7d7080262b860010
-916100087caa2b78
-f821ffa1480006f5
+3c4c000100000780
+7c0802a638428d3c
+f821ffb1480007a5
+7c7f1b78eb630000
+7cbd2b787c9c2378
+7fa3eb783bc00000
+600000004bfffd8d
+408000147c3e1840
+7d5b4850e93f0000
+4180000c7c2ae040
+480007b038210050
+3bde00017d5df0ae
+e93f000099490000
+f93f000039290001
+000000004bffffbc
+0000058001000000
+38428cc03c4c0001
+600000007c0802a6
+2b860010e9228020
+916100087d708026
+f821ffa148000711
 7cbe2b787c7c1b78
 3be000007cdd3378
 60000000f9210020
-f9210028e9228030
-408200342c2a0000
-408200082c1f0000
-7fff07b43be00001
-7c3f20402e270000
-408100303b7fffff
-8161000838210060
-480006e87d708120
-794ae102409e0010
-4bffffbc3bff0001
-4bfffff47d4aeb92
-7f5eeb927f5ed378
-7d29f0507d3ae9d2
-886900207d214a14
-5463063e41920010
-600000004bfffdd5
-e93c00007c3df040
-3b7bffff7c69d9ae
-e93c00004081ffc8
-f93c00007d29fa14
-000000004bffff90
-0000068003000000
-38428bc03c4c0001
-480005e97c0802a6
-7c761b79f821fef1
-38600000f8610060
-2c2400004182003c
-3b04ffff41820034
-3a8000003aa10040
-ebc1006089250000
-7c76f050712a00ff
-7c23c0404182000c
-3920000041800018
-38210110993e0000
-480005e07c6307b4
-390500012c0a0025
-3920000040820564
-7cb32b7889450000
-7d49a9ae8ce50001
-280a007854ea063e
-280a006241810024
-2c0a004f41810024
-2c0a0058418200a0
-2c0a002541820098
-3929000141820090
-3907ff9d4bffffc0
-280400155504063e
-3c82ffff4181ffec
-790815a838847528
-7d0822147d0442aa
-4e8004207d0903a6
-0000005800000058
-ffffffccffffffcc
-ffffffccffffffcc
-ffffffcc00000058
-ffffffccffffffcc
-ffffffccffffffcc
-0000005800000058
-ffffffccffffffcc
-ffffffcc00000058
-ffffffcc00000058
-00000058ffffffcc
-2c0a002539090001
-38a1002039290002
-7d2907b47d0807b4
-7d254a147d054214
-9a89002098e80020
+f9210028e9228028
+2c2900007ca92b78
+2c1f000040820034
+3be0000141810008
+2e2700007fff07b4
+3b7fffff7c3f2040
+3821006040810030
+7d70812081610008
+409e001048000700
+3bff00017929e102
+7d29eb924bffffbc
+7f5ed3784bfffff4
+7d3ae9d27f5eeb92
+7d214a147d29f050
+4192001088690020
+4bfffdd55463063e
+7c3df04060000000
+7c69d9aee93c0000
+4081ffc83b7bffff
+7d29fa14e93c0000
+4bffff90f93c0000
+0300000000000000
+3c4c000100000680
+7c0802a638428bcc
+f821fef148000601
+f86100607c751b79
+4182004438600000
+4182003c2c240000
+3ae4ffff7cbd2b78
+3b2100203a610040
+895d00003a400000
+714900ffebc10060
+4182000c7c75f050
+418000187c23b840
+993e000039200000
+7c6307b438210110
+2c090025480005f0
+40820574391d0001
+7d4999ae39200000
+389d0001895d0001
+280800785548063e
+2808006241810024
+2c08004f41810028
+2c080058418200a4
+2c0800254182009c
+3929000141820094
+4bffffc07c9d2378
+54e5063e38eaff9d
+4181ffe828050015
+38a575243ca2ffff
+7ce53aaa78e715a8
+7ce903a67ce72a14
+000000584e800420
+ffffffc800000058
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc800000058
+00000058ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+38e9000100000058
+392900022c080025
+7d2907b47ce707b4
+7d394a147cf93a14
+9a49002099470020
 393e000140820018
-f9210060995e0000
-4bfffebc38b30002
+995e0000f9210060
+4bfffec03bbd0002
 eb86000089210041
-3a2600087fe3c050
-3b4100423a400030
+3a2600087fe3b850
+3b4100423a800030
 712900fd3929ffd2
-5649063e40820428
-3ae0000060000000
-f92100683b200004
+5689063e4082043c
+3ac0000060000000
+f92100683b000004
 3a0000003b600000
-4800017039e28048
-38da00012c07004f
-390affa8418201dc
-280500225505063e
-3ca2ffff418103bc
-790815a838a57640
-7d082a147d0542aa
-4e8004207d0903a6
-0000039c00000158
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-000002680000039c
-0000039c0000008c
-0000039c0000039c
-0000008c00000380
-0000039c0000039c
-0000039c00000368
-000001ac0000039c
-0000039c00000204
-000002ac0000039c
-0000008c0000039c
-0000039c0000039c
-0000039c0000015c
-2c070075000003c0
+4800016c39e28048
+38ba00012c06004f
+38e8ffa8418201e0
+2804002254e4063e
+3c82ffff418103d0
+78e715a838847638
+7ce722147ce43aaa
+4e8004207ce903a6
+000003b000000154
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+00000270000003b0
+000003b00000008c
+000003b0000003b0
+0000008c00000394
+000003b0000003b0
+000003b00000037c
+000001b0000003b0
+000003b00000020c
+000002b4000003b0
+0000008c000003b0
+000003b0000003b0
+000003b000000158
+2c060075000003d4
 7d4152147b6a0020
-7f9de37839000000
+7f8ee37839000000
 41820044990a0020
-3940000157281838
-7d4a40363908ffff
-4182002c7f8a5039
+3900000157071838
+7d08383638e7ffff
+4182002c7f884039
 392900013940002d
-9949ffff7fbc00d0
-f921006060000000
-394280487b291e68
-7fbd48387d2a482a
-38e0000ae8810060
-38a100207fa6eb78
-5648063e39200000
-7c9e205038610060
-4bfffabd7c84f850
-7ae707e0e8810060
-7fa5eb7838c0000a
-7c84f8507c9e2050
-4bfffbe938610060
-895a00003b5a0001
-714700ffe9210060
-7fbe485041820010
-4181fe7c7c3fe840
-4bfffe247e268b78
-7b6900203ae00001
-38e00010e9010068
-7c9df8507d214a14
-3861006038a10020
-7b291e689a090020
-392000007d4f482a
-7dc673787f8e5038
-e88100604bfffa39
-38c000107ae707e0
-7dc573787c9e2050
-7b6900204bffff7c
-7d214a1439400000
-7c9df85038e00008
-994900205648063e
-7b291e6860000000
-38a1002039428048
-7d4a482a38610060
-7f8e503839200000
-4bfff9dd7dc67378
-7ae707e0e8810060
+7b081e6860000000
+9949ffff38e28048
+7d5c00d0f9210060
+7d4e40387d07402a
+38e0000a7c9e4850
+7f25cb787dc67378
+392000007c84f850
+386100605688063e
+e88100604bfffabd
+38c0000a7ac707e0
+7c9e20507dc57378
+386100607c84f850
+3b5a00014bfffbe9
+e9210060891a0000
+41820010710600ff
+7c3f70407dde4850
+7e268b784181fe80
+3ac000014bfffe28
+e90100687b690020
+7d214a1438e00010
+7f25cb787c8ef850
+9a09002038610060
+7d6f482a7b091e68
+7f8b583839200000
+f96100707d665b78
+e88100604bfffa35
+38c000107ac707e0
+e96100707c9e2050
+4bffff747d655b78
+390000007b690020
+38e000087d214a14
+7f25cb787c8ef850
+6000000099090020
+390280487b091e68
+7d68482a38610060
+5688063e39200000
+7d665b787f8b5838
+4bfff9d1f9610070
+7ac707e0e8810060
 7c9e205038c00008
-7b6900204bffffa4
-7d214a1439400000
+7b6900204bffff9c
+7d214a1439000000
 7f86e37838e00010
-9949002039000020
-3920000238a10020
-386100607c9df850
-e88100604bfff999
+990900207f25cb78
+392000027c8ef850
+3861006039000020
+e88100604bfff98d
 3861006060000000
-7c9e205038a28040
-4bfffa4d7c84f850
-7ae707e0e8810060
+7c9e205038a28038
+4bfffa417c84f850
+7ac707e0e8810060
 7f85e37838c00010
-4bfffec07c9e2050
-394000007b690020
-390000207d214a14
-38c0000138e0000a
-38a1002099490020
-7c9df85039200000
-4bfff93538610060
+4bfffeb47c9e2050
+390000007b690020
+38e0000a7d214a14
+7f25cb7838c00001
+7c8ef85099090020
+3900002039200000
+4bfff92938610060
 9b890000e9210060
 f921006039290001
-7b6a00204bfffe88
-f921007039000000
-38a0000a7d415214
-3861002038800000
-4bfff795990a0020
-7c6e1b7860000000
-4bfff75d7f83e378
-7c2e184060000000
-e921007040810048
-7c6370507fbdf850
-38e0002039400000
-7d09f0503bbd0001
-7d08fa147c691a14
-408200082c280000
-2c3d00013ba00001
-408200283bbdffff
-40820034714a0001
-7f85e378e8810060
-7c9e205038610060
-4bfff9557c84f850
-98e900004bfffde8
-3940000139290001
-4082ffc07c291840
-4bffffccf9210060
-3b200008893a0001
-4082fdbc2c09006c
-4bfffdb47cda3378
-3b200002893a0001
-4082fda42c090068
-3b2000017cda3378
-392affd04bfffd98
-280900095529063e
-7b6900204181fd88
-7d214a143b7b0001
-4bfffd7499490020
-4bfffd6c3b200008
-3b4100413a400020
-993e00004bfffbd4
-7d0543783bde0001
-4bfffa54fbc10060
-0100000000000000
-f9c1ff7000001280
-fa01ff80f9e1ff78
-fa41ff90fa21ff88
-fa81ffa0fa61ff98
-fac1ffb0faa1ffa8
-fb01ffc0fae1ffb8
-fb41ffd0fb21ffc8
-fb81ffe0fb61ffd8
-fbc1fff0fba1ffe8
-f8010010fbe1fff8
-e9c1ff704e800020
-ea01ff80e9e1ff78
-ea41ff90ea21ff88
-ea81ffa0ea61ff98
-eac1ffb0eaa1ffa8
-eb01ffc0eae1ffb8
-eb41ffd0eb21ffc8
-eb81ffe0eb61ffd8
-eba1ffe8e8010010
-ebc1fff07c0803a6
-4e800020ebe1fff8
-e8010010ebc1fff0
-7c0803a6ebe1fff8
-600000004e800020
+7b6800204bfffe7c
+f921007838e00000
+38a0000a7d014214
+7f23cb7838800000
+4bfff79998e80020
+f861007060000000
+4bfff7617f83e378
+e901007060000000
+7c281840e9210078
+7d244b7841810020
+7f85e3787c9e2050
+386100607c84f850
+4bfffe184bfff985
+7c6340507ce9f050
+7d4ef8507ce7fa14
+7c691a142c270000
+390000007d244b78
+394a000138c00020
+3940000140820008
+394affff2c2a0001
+7108000140820010
+4bffffa04082001c
+3884000198c40000
+7c24184039000001
+f88100604082ffd8
+893a00014bffff88
+2c09006c3b000008
+7cba2b784082fda4
+893a00014bfffd9c
+2c0900683b000002
+7cba2b784082fd8c
+4bfffd803b000001
+5529063e3928ffd0
+4181fd7028090009
+3b7b00017b690020
+990900207d214a14
+3b0000084bfffd5c
+3a8000204bfffd54
+4bfffbc03b410041
+3bde0001995e0000
+fbc100607d1d4378
+000000004bfffa44
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
+eb21ffc8eb01ffc0
+eb61ffd8eb41ffd0
+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1874,8 +1875,8 @@ e8010010ebc1fff0
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1936,15 +1937,13 @@ e8010010ebc1fff0
 000000000000207c
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
@@ -1986,11 +1985,12 @@ e8010010ebc1fff0
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/ecpix-5/litedram_core.v b/litedram/generated/ecpix-5/litedram_core.v
index bc80a1b..21f8c69 100644
--- a/litedram/generated/ecpix-5/litedram_core.v
+++ b/litedram/generated/ecpix-5/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : LFE5UM5G-85F-8BG554I
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 18:06:24
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:51
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -80,9 +80,9 @@ LiteDRAMCore
 └─── crg (LiteDRAMECP5DDRPHYCRG)
 │    └─── pll (ECP5PLL)
 │    │    └─── [EHXPLLL]
+│    └─── [ECLKSYNCB]
 │    └─── [CLKDIVF]
 │    └─── [ECLKBRIDGECS]
-│    └─── [ECLKSYNCB]
 └─── ddrphy (ECP5DDRPHY)
 │    └─── init (ECP5DDRPHYInit)
 │    │    └─── [DDRDLLA]
@@ -105,128 +105,128 @@ LiteDRAMCore
 │    └─── tappeddelayline_0* (TappedDelayLine)
 │    └─── tappeddelayline_1* (TappedDelayLine)
 │    └─── [DELAYG]
-│    └─── [TSHX2DQA]
 │    └─── [ODDRX2F]
-│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
-│    └─── [ODDRX2DQSB]
-│    └─── [TSHX2DQA]
 │    └─── [DELAYG]
 │    └─── [DELAYG]
-│    └─── [TSHX2DQA]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
 │    └─── [ODDRX2F]
-│    └─── [TSHX2DQA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [TSHX2DQA]
-│    └─── [ODDRX2DQA]
-│    └─── [ODDRX2DQA]
 │    └─── [ODDRX2F]
+│    └─── [DELAYG]
 │    └─── [ODDRX2F]
-│    └─── [ODDRX2DQA]
-│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
-│    └─── [DQSBUFM]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [TSHX2DQA]
 │    └─── [ODDRX2F]
-│    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [DELAYG]
 │    └─── [ODDRX2F]
-│    └─── [IDDRX2DQA]
-│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [IDDRX2DQA]
-│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
+│    └─── [DQSBUFM]
+│    └─── [ODDRX2DQSB]
 │    └─── [TSHX2DQSA]
-│    └─── [IDDRX2DQA]
-│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [ODDRX2DQA]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [IDDRX2DQA]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [DQSBUFM]
-│    └─── [DELAYG]
-│    └─── [TSHX2DQSA]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [DELAYG]
 │    └─── [ODDRX2DQA]
-│    └─── [TSHX2DQA]
-│    └─── [IDDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
 │    └─── [DELAYG]
-│    └─── [ODDRX2F]
-│    └─── [DELAYG]
-│    └─── [ODDRX2F]
-│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
-│    └─── [DELAYG]
 │    └─── [ODDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [TSHX2DQA]
-│    └─── [DELAYG]
 │    └─── [DELAYG]
-│    └─── [ODDRX2DQA]
-│    └─── [ODDRX2F]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2DQA]
-│    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
+│    └─── [IDDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQSB]
+│    └─── [DQSBUFM]
+│    └─── [TSHX2DQSA]
 │    └─── [ODDRX2DQA]
 │    └─── [ODDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [IDDRX2DQA]
-│    └─── [IDDRX2DQA]
-│    └─── [IDDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
-│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
-│    └─── [ODDRX2F]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [ODDRX2DQSB]
-│    └─── [ODDRX2F]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [TSHX2DQA]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
@@ -364,32 +364,32 @@ LiteDRAMCore
 │    │    └─── csrstorage_8* (CSRStorage)
 │    │    └─── csrstatus_1* (CSRStatus)
 └─── csr_interconnect (InterconnectShared)
-└─── [FD1S3BX]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
 * : Generated name.
 []: BlackBox.
 */
@@ -864,6 +864,7 @@ wire   [29:0] interface0_adr;
 wire   [13:0] interface0_bank_bus_adr;
 reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface0_bank_bus_dat_w;
+wire          interface0_bank_bus_re;
 wire          interface0_bank_bus_we;
 wire    [1:0] interface0_bte;
 wire    [2:0] interface0_cti;
@@ -880,17 +881,22 @@ reg           interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] interface1_bank_bus_adr;
 reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface1_bank_bus_dat_w;
+wire          interface1_bank_bus_re;
 wire          interface1_bank_bus_we;
 wire   [31:0] interface1_dat_r;
 reg    [31:0] interface1_dat_w = 32'd0;
 reg    [31:0] interface1_dat_w_next_value0 = 32'd0;
 reg           interface1_dat_w_next_value_ce0 = 1'd0;
+reg           interface1_re = 1'd0;
+reg           interface1_re_next_value2 = 1'd0;
+reg           interface1_re_next_value_ce2 = 1'd0;
 reg           interface1_we = 1'd0;
-reg           interface1_we_next_value2 = 1'd0;
-reg           interface1_we_next_value_ce2 = 1'd0;
+reg           interface1_we_next_value3 = 1'd0;
+reg           interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] interface2_bank_bus_adr;
 reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface2_bank_bus_dat_w;
+wire          interface2_bank_bus_re;
 wire          interface2_bank_bus_we;
 wire          latticeecp5asyncresetsynchronizerimpl0_expr;
 wire          latticeecp5asyncresetsynchronizerimpl0_rst1;
@@ -1733,9 +1739,9 @@ reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [14:0] litedramcore_csr_dfi_p0_address;
 wire    [2:0] litedramcore_csr_dfi_p0_bank;
 reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          litedramcore_csr_dfi_p0_cke;
 reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          litedramcore_csr_dfi_p0_odt;
 reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
 wire          litedramcore_csr_dfi_p0_rddata_en;
@@ -1749,9 +1755,9 @@ reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [14:0] litedramcore_csr_dfi_p1_address;
 wire    [2:0] litedramcore_csr_dfi_p1_bank;
 reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          litedramcore_csr_dfi_p1_cke;
 reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          litedramcore_csr_dfi_p1_odt;
 reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
 wire          litedramcore_csr_dfi_p1_rddata_en;
@@ -2115,6 +2121,7 @@ reg           multiregimpl0 = 1'd0;
 reg           multiregimpl1 = 1'd0;
 reg     [1:0] next_state = 2'd0;
 wire          por_clk;
+wire          re;
 reg           rhs_self0 = 1'd0;
 reg    [14:0] rhs_self1 = 15'd0;
 reg           rhs_self10 = 1'd0;
@@ -2951,59 +2958,6 @@ assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
 assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
 assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
 assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
-        end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
-            if (1'd0) begin
-                litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}};
-            end
-        end
-    end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
-        end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
-        end
-    end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
-    end
-end
-always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
-        end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
-        end
-    end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
-    end
-end
 always @(*) begin
     litedramcore_master_p0_cke <= 1'd0;
     if (litedramcore_sel) begin
@@ -3331,6 +3285,20 @@ always @(*) begin
     end else begin
     end
 end
+always @(*) begin
+    litedramcore_csr_dfi_p1_rddata <= 64'd0;
+    if (litedramcore_sel) begin
+    end else begin
+        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    end
+end
+always @(*) begin
+    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (litedramcore_sel) begin
+    end else begin
+        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    end
+end
 always @(*) begin
     litedramcore_csr_dfi_p0_rddata <= 64'd0;
     if (litedramcore_sel) begin
@@ -3402,23 +3370,58 @@ always @(*) begin
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cke <= 1'd0;
-    litedramcore_csr_dfi_p0_cke <= litedramcore_cke;
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_cke <= 1'd0;
-    litedramcore_csr_dfi_p1_cke <= litedramcore_cke;
+    litedramcore_master_p0_cs_n <= 1'd1;
+    if (litedramcore_sel) begin
+        if (litedramcore_ext_dfi_sel) begin
+            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+        end else begin
+            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}};
+            end
+        end
+    end else begin
+        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+    end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_odt <= 1'd0;
-    litedramcore_csr_dfi_p0_odt <= litedramcore_odt;
+    litedramcore_master_p0_ras_n <= 1'd1;
+    if (litedramcore_sel) begin
+        if (litedramcore_ext_dfi_sel) begin
+            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+        end else begin
+            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+        end
+    end else begin
+        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+    end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_odt <= 1'd0;
-    litedramcore_csr_dfi_p1_odt <= litedramcore_odt;
+    litedramcore_master_p0_we_n <= 1'd1;
+    if (litedramcore_sel) begin
+        if (litedramcore_ext_dfi_sel) begin
+            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+        end else begin
+            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+        end
+    end else begin
+        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+    end
 end
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
 assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
 assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+always @(*) begin
+    litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (litedramcore_phaseinjector0_command_issue_re) begin
+        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    end else begin
+        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     if (litedramcore_phaseinjector0_command_issue_re) begin
@@ -3451,20 +3454,20 @@ always @(*) begin
         litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
-    end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    end
-end
 assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
 assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
 assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
 assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
 assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
 assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (litedramcore_phaseinjector1_command_issue_re) begin
+        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    end else begin
+        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     if (litedramcore_phaseinjector1_command_issue_re) begin
@@ -3497,14 +3500,6 @@ always @(*) begin
         litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
-    end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    end
-end
 assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
 assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
 assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
@@ -3612,22 +3607,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
-        1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_cmd_valid <= 1'd0;
     case (litedramcore_refresher_state)
@@ -3694,6 +3673,22 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_sequencer_start0 <= 1'd0;
+    case (litedramcore_refresher_state)
+        1'd1: begin
+            if (litedramcore_cmd_ready) begin
+                litedramcore_sequencer_start0 <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
 assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
 assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
@@ -3827,66 +3822,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
     case (litedramcore_bankmachine0_state)
@@ -4207,6 +4142,66 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine0_trccon_ready) begin
+                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine0_source_source_valid) begin
+                    if (litedramcore_bankmachine0_row_opened) begin
+                        if (litedramcore_bankmachine0_row_hit) begin
+                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
 assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
 assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
@@ -4340,40 +4335,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine1_refresh_gnt <= 1'd0;
     case (litedramcore_bankmachine1_state)
@@ -4396,28 +4357,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine1_cmd_valid <= 1'd0;
     case (litedramcore_bankmachine1_state)
@@ -4477,6 +4416,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine1_row_open <= 1'd0;
+    case (litedramcore_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine1_trccon_ready) begin
+                litedramcore_bankmachine1_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
     case (litedramcore_bankmachine1_state)
@@ -4720,6 +4681,40 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine1_source_source_valid) begin
+                    if (litedramcore_bankmachine1_row_opened) begin
+                        if (litedramcore_bankmachine1_row_hit) begin
+                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
 assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
 assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
@@ -4853,28 +4848,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
     case (litedramcore_bankmachine2_state)
@@ -5233,6 +5206,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine2_row_close <= 1'd0;
+    case (litedramcore_bankmachine2_state)
+        1'd1: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        2'd2: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
 assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
 assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
@@ -5366,37 +5361,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
     case (litedramcore_bankmachine3_state)
@@ -5746,6 +5710,37 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine3_source_source_valid) begin
+                    if (litedramcore_bankmachine3_row_opened) begin
+                        if (litedramcore_bankmachine3_row_hit) begin
+                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
 assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
 assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
@@ -5879,66 +5874,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
     case (litedramcore_bankmachine4_state)
@@ -6187,7 +6122,69 @@ always @(*) begin
                 if (litedramcore_bankmachine4_source_source_valid) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine4_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine4_trccon_ready) begin
+                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine4_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine4_source_source_valid) begin
+                    if (litedramcore_bankmachine4_row_opened) begin
+                        if (litedramcore_bankmachine4_row_hit) begin
+                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -6198,21 +6195,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
     case (litedramcore_bankmachine4_state)
         1'd1: begin
             if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6223,12 +6221,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
     case (litedramcore_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -6247,8 +6242,8 @@ always @(*) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
                             if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                             end else begin
+                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6392,40 +6387,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine5_refresh_gnt <= 1'd0;
     case (litedramcore_bankmachine5_state)
@@ -6772,6 +6733,40 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine5_source_source_valid) begin
+                    if (litedramcore_bankmachine5_row_opened) begin
+                        if (litedramcore_bankmachine5_row_hit) begin
+                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
 assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
 assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
@@ -6905,28 +6900,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
     case (litedramcore_bankmachine6_state)
@@ -7042,28 +7015,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
     case (litedramcore_bankmachine6_state)
@@ -7248,6 +7199,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine6_row_open <= 1'd0;
+    case (litedramcore_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine6_trccon_ready) begin
+                litedramcore_bankmachine6_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     litedramcore_bankmachine6_cmd_valid <= 1'd0;
     case (litedramcore_bankmachine6_state)
@@ -7285,6 +7258,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine6_row_close <= 1'd0;
+    case (litedramcore_bankmachine6_state)
+        1'd1: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd2: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
 assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
 assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
@@ -7418,37 +7413,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
     case (litedramcore_bankmachine7_state)
@@ -7798,6 +7762,37 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine7_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine7_source_source_valid) begin
+                    if (litedramcore_bankmachine7_row_opened) begin
+                        if (litedramcore_bankmachine7_row_hit) begin
+                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
 assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
 assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
@@ -8048,19 +8043,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer0 <= 2'd0;
+    litedramcore_choose_cmd_want_activates <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                litedramcore_steerer0 <= 2'd2;
-            end
-            if (1'd1) begin
-                litedramcore_steerer0 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
             end
         end
         2'd2: begin
-            litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -8086,29 +8077,23 @@ always @(*) begin
         end
         4'd14: begin
         end
-        4'd15: begin
-        end
-        default: begin
-            litedramcore_steerer0 <= 1'd0;
-            if (1'd1) begin
-                litedramcore_steerer0 <= 2'd2;
-            end
+        4'd15: begin
+        end
+        default: begin
             if (1'd0) begin
-                litedramcore_steerer0 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer1 <= 2'd0;
+    litedramcore_choose_cmd_cmd_ready <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer1 <= 1'd0;
-            if (1'd1) begin
-                litedramcore_steerer1 <= 2'd2;
-            end
             if (1'd0) begin
-                litedramcore_steerer1 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -8140,24 +8125,17 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_steerer1 <= 1'd0;
             if (1'd0) begin
-                litedramcore_steerer1 <= 2'd2;
-            end
-            if (1'd1) begin
-                litedramcore_steerer1 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
+    litedramcore_choose_req_want_reads <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
-            end
         end
         2'd2: begin
         end
@@ -8188,10 +8166,7 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
-            end
+            litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
@@ -8234,13 +8209,10 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    litedramcore_choose_req_want_writes <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
-            end
+            litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -8271,15 +8243,11 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
+    litedramcore_en0 <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
         end
@@ -8312,15 +8280,19 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
+    litedramcore_choose_req_cmd_ready <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            if (1'd0) begin
+                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+            end else begin
+                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -8351,13 +8323,19 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            if (1'd0) begin
+                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+            end else begin
+                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
+    litedramcore_en1 <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
+            litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -8388,21 +8366,23 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
+    litedramcore_steerer0 <= 2'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
+            litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                litedramcore_steerer0 <= 2'd2;
+            end
+            if (1'd1) begin
+                litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
+            litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -8431,19 +8411,27 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_steerer0 <= 1'd0;
+            if (1'd1) begin
+                litedramcore_steerer0 <= 2'd2;
+            end
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
+    litedramcore_steerer1 <= 2'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
+            litedramcore_steerer1 <= 1'd0;
+            if (1'd1) begin
+                litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd0) begin
+                litedramcore_steerer1 <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -8474,6 +8462,13 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_steerer1 <= 1'd0;
+            if (1'd0) begin
+                litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd1) begin
+                litedramcore_steerer1 <= 1'd1;
+            end
         end
     endcase
 end
@@ -8569,138 +8564,168 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    interface0_ack <= 1'd0;
+    interface1_adr_next_value1 <= 14'd0;
     case (state)
         1'd1: begin
+            interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
-            interface0_ack <= 1'd1;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value1 <= interface0_adr;
+            end
         end
     endcase
 end
 always @(*) begin
-    interface0_dat_r <= 32'd0;
+    interface1_adr_next_value_ce1 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            interface0_dat_r <= interface1_dat_r;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    interface1_dat_w_next_value0 <= 32'd0;
+    interface1_re_next_value2 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            interface1_dat_w_next_value0 <= interface0_dat_w;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    interface1_dat_w_next_value_ce0 <= 1'd0;
+    interface1_re_next_value_ce2 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_re_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            interface1_dat_w_next_value_ce0 <= 1'd1;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_re_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    interface1_adr_next_value1 <= 14'd0;
+    interface1_we_next_value3 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_adr_next_value1 <= 1'd0;
+            interface1_we_next_value3 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((interface0_cyc & interface0_stb)) begin
-                interface1_adr_next_value1 <= interface0_adr[29:0];
+                interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    interface1_adr_next_value_ce1 <= 1'd0;
+    interface1_we_next_value_ce3 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_adr_next_value_ce1 <= 1'd1;
+            interface1_we_next_value_ce3 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((interface0_cyc & interface0_stb)) begin
-                interface1_adr_next_value_ce1 <= 1'd1;
+                interface1_we_next_value_ce3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    interface1_we_next_value2 <= 1'd0;
+    interface0_dat_r <= 32'd0;
+    case (state)
+        1'd1: begin
+        end
+        2'd2: begin
+            interface0_dat_r <= interface1_dat_r;
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    interface0_ack <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
+            interface0_ack <= 1'd1;
         end
         default: begin
-            if ((interface0_cyc & interface0_stb)) begin
-                interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0));
-            end
         end
     endcase
 end
 always @(*) begin
-    interface1_we_next_value_ce2 <= 1'd0;
+    interface1_dat_w_next_value0 <= 32'd0;
+    case (state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        default: begin
+            interface1_dat_w_next_value0 <= interface0_dat_w;
+        end
+    endcase
+end
+always @(*) begin
+    interface1_dat_w_next_value_ce0 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((interface0_cyc & interface0_stb)) begin
-                interface1_we_next_value_ce2 <= 1'd1;
-            end
+            interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
+    csrbank0_init_done0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+        csrbank0_init_done0_we <= interface0_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
+    csrbank0_init_done0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_done0_re <= interface0_bank_bus_we;
     end
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
+    csrbank0_init_error0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_error0_re <= interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
+    csrbank0_init_error0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+        csrbank0_init_error0_we <= interface0_bank_bus_re;
     end
 end
 assign csrbank0_init_done0_w = init_done_storage;
@@ -8708,54 +8733,54 @@ assign csrbank0_init_error0_w = init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
+    csrbank1_dly_sel0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
+    csrbank1_dly_sel0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+        csrbank1_dly_sel0_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_rdly_dq_rst_we <= 1'd0;
+    ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    ddrphy_rdly_dq_rst_re <= 1'd0;
+    ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+        ddrphy_rdly_dq_rst_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_rdly_dq_inc_we <= 1'd0;
+    ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    ddrphy_rdly_dq_inc_re <= 1'd0;
+    ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+        ddrphy_rdly_dq_inc_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+        ddrphy_rdly_dq_bitslip_rst_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
@@ -8768,20 +8793,20 @@ end
 always @(*) begin
     ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_bitslip_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_burstdet_clr_re <= 1'd0;
+    ddrphy_burstdet_clr_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
+        ddrphy_burstdet_clr_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    ddrphy_burstdet_clr_we <= 1'd0;
+    ddrphy_burstdet_clr_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we);
+        ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0];
@@ -8794,11 +8819,11 @@ end
 always @(*) begin
     csrbank1_burstdet_seen_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
+        csrbank1_burstdet_seen_we <= interface1_bank_bus_re;
     end
 end
-assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0];
-assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0];
+assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage;
+assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status;
 assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we;
 assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
 assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
@@ -8811,46 +8836,46 @@ end
 always @(*) begin
     csrbank2_dfii_control0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_control0_we <= interface2_bank_bus_re;
     end
 end
 assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
+    csrbank2_dfii_pi0_command0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
+    csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_command0_we <= interface2_bank_bus_re;
     end
 end
 assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+        litedramcore_phaseinjector0_command_issue_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
+    csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_address0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
+    csrbank2_dfii_pi0_address0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
@@ -8863,14 +8888,14 @@ end
 always @(*) begin
     csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_baddress0_we <= interface2_bank_bus_re;
     end
 end
-assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
     csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_wrdata1_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8879,37 +8904,37 @@ always @(*) begin
         csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_wrdata0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_rddata1_we <= interface2_bank_bus_re;
     end
 end
-assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
     csrbank2_dfii_pi0_rddata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_rddata0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8920,22 +8945,22 @@ always @(*) begin
 end
 assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
+    csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_command0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
+    csrbank2_dfii_pi1_command0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
     end
 end
 assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
     litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+        litedramcore_phaseinjector1_command_issue_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8954,14 +8979,14 @@ end
 always @(*) begin
     csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_address0_we <= interface2_bank_bus_re;
     end
 end
 assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_baddress0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8970,37 +8995,37 @@ always @(*) begin
         csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_wrdata1_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_wrdata0_we <= interface2_bank_bus_re;
     end
 end
-assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
     csrbank2_dfii_pi1_rddata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_rddata1_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -9009,24 +9034,24 @@ always @(*) begin
         csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_rddata0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
     end
 end
 assign litedramcore_sel = litedramcore_storage[0];
 assign litedramcore_cke = litedramcore_storage[1];
 assign litedramcore_odt = litedramcore_storage[2];
 assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign csrbank2_dfii_control0_w = litedramcore_storage;
 assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
 assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
 assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
@@ -9035,9 +9060,9 @@ assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_c
 assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
 assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6];
 assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage;
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage;
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage;
 assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
 assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
 assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
@@ -9051,21 +9076,25 @@ assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_c
 assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
 assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6];
 assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage;
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage;
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage;
 assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
 assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
 assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
 assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
 assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
 assign adr = interface1_adr;
+assign re = interface1_re;
 assign we = interface1_we;
 assign dat_w = interface1_dat_w;
 assign interface1_dat_r = dat_r;
 assign interface0_bank_bus_adr = adr;
 assign interface1_bank_bus_adr = adr;
 assign interface2_bank_bus_adr = adr;
+assign interface0_bank_bus_re = re;
+assign interface1_bank_bus_re = re;
+assign interface2_bank_bus_re = re;
 assign interface0_bank_bus_we = we;
 assign interface1_bank_bus_we = we;
 assign interface2_bank_bus_we = we;
@@ -9791,16 +9820,16 @@ always @(*) begin
     self0 <= 3'd0;
     case (litedramcore_steerer0)
         1'd0: begin
-            self0 <= litedramcore_nop_ba[2:0];
+            self0 <= litedramcore_nop_ba;
         end
         1'd1: begin
-            self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self0 <= litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            self0 <= litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self0 <= litedramcore_cmd_payload_ba[2:0];
+            self0 <= litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -9910,16 +9939,16 @@ always @(*) begin
     self7 <= 3'd0;
     case (litedramcore_steerer1)
         1'd0: begin
-            self7 <= litedramcore_nop_ba[2:0];
+            self7 <= litedramcore_nop_ba;
         end
         1'd1: begin
-            self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self7 <= litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            self7 <= litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self7 <= litedramcore_cmd_payload_ba[2:0];
+            self7 <= litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -11727,8 +11756,11 @@ always @(posedge sys_clk) begin
     if (interface1_adr_next_value_ce1) begin
         interface1_adr <= interface1_adr_next_value1;
     end
-    if (interface1_we_next_value_ce2) begin
-        interface1_we <= interface1_we_next_value2;
+    if (interface1_re_next_value_ce2) begin
+        interface1_re <= interface1_re_next_value2;
+    end
+    if (interface1_we_next_value_ce3) begin
+        interface1_we <= interface1_we_next_value3;
     end
     interface0_bank_bus_dat_r <= 1'd0;
     if (csrbank0_sel) begin
@@ -11776,7 +11808,7 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (csrbank1_dly_sel0_re) begin
-        ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+        ddrphy_dly_sel_storage <= csrbank1_dly_sel0_r;
     end
     ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
     ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re;
@@ -11837,19 +11869,19 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+        litedramcore_storage <= csrbank2_dfii_control0_r;
     end
     litedramcore_re <= csrbank2_dfii_control0_re;
     if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r;
+        litedramcore_phaseinjector0_command_storage <= csrbank2_dfii_pi0_command0_r;
     end
     litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
     if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+        litedramcore_phaseinjector0_address_storage <= csrbank2_dfii_pi0_address0_r;
     end
     litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
     if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+        litedramcore_phaseinjector0_baddress_storage <= csrbank2_dfii_pi0_baddress0_r;
     end
     litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
     if (csrbank2_dfii_pi0_wrdata1_re) begin
@@ -11861,15 +11893,15 @@ always @(posedge sys_clk) begin
     litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
     litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
     if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r;
+        litedramcore_phaseinjector1_command_storage <= csrbank2_dfii_pi1_command0_r;
     end
     litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
     if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+        litedramcore_phaseinjector1_address_storage <= csrbank2_dfii_pi1_address0_r;
     end
     litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
     if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+        litedramcore_phaseinjector1_baddress_storage <= csrbank2_dfii_pi1_baddress0_r;
     end
     litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
     if (csrbank2_dfii_pi1_wrdata1_re) begin
@@ -12151,6 +12183,7 @@ always @(posedge sys_clk) begin
         init_done_re <= 1'd0;
         init_error_storage <= 1'd0;
         init_error_re <= 1'd0;
+        interface1_re <= 1'd0;
         interface1_we <= 1'd0;
         litedramcore_refresher_state <= 2'd0;
         litedramcore_bankmachine0_state <= 3'd0;
@@ -14965,5 +14998,5 @@ TRELLIS_IO #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 18:06:24.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:52.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init
index 33ac9e8..f7d487f 100644
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842bdc83c4c0001
+3c4c000100000000
+7c0802a63842bea4
+f821ffc148003751
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+0000000048003768
+0000038001000000
+3842be503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48003041f9410108
+48003085f9410108
 7c7f1b7860000000
-48002a9138610020
+48002ae138610020
 382100b060000000
-480036b47fe3fb78
+480037107fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,538 +552,549 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842bd2c
-480035ed7d600026
-f821fed191610008
-6000000048002a8d
-386379603c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842bdb4
+480036457d600026
+f821fec191610008
+6000000048002add
+386379383c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-386379803be00008
+386379583be00008
 4bffff1d67ffc000
-386379a03c62ffff
+386379783c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef5386379b8
+4bfffef538637990
 4e00000073e90002
 3c62ffff41820010
-4bfffedd386379c0
+4bfffedd38637998
 4d80000073e90004
 3c62ffff41820010
-4bfffec5386379c8
+4bfffec5386379a0
 4d00000073e90008
 3c62ffff41820010
-4bfffead386379d0
+4bfffead386379a8
 4182001073e90010
-386379e03c62ffff
+386379b83c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe85386379f0
-3b7b79f83f62ffff
-4bfffe757f63db78
+4bfffe85386379c8
+3b3979d03f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637a007884b582
+386379d87884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637a18
+4bfffe2d386379f0
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637a30
+4bfffe0d38637a08
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637a487c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637a6857c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637a207c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637a4057e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637a88
-4082009073a90002
-38637aa83c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637a60
+4082006473c90002
+38637a803c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637ac0
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637ad07b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637b0038847af0
-480017114bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637b203c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637a90
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637b38
-38a000403c9af000
+4bfffc2d38637b30
+38a000403c9cf000
 3861007078840020
-6000000048002781
+60000000480028b1
 3d200002e9410070
 6129464c3c62ffff
-792983e438637b50
+792983e438637b48
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637b703c62ffff
-892100774bfffae9
+38637b683c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637bd088810070
+38637bc888810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637c00
-3880600038a00000
-6484ff0060a5a000
-480026dd3c604000
+3c62ffff4bfffb99
+4bfffb8d38637bf8
+3880f80338a00000
+7884682860a5a000
+4800280d3c604000
 3c62ffff60000000
-4bfffa8538637c20
-4bffff184bfffafd
+4bfffb6538637c18
+480002184bfffbdd
 3f22ffffebe10090
-3b397b883ba00000
-a12100a87ffafa14
+3b397b803ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637bb0
-e86100884bfffac5
+4bfffb2d38637ba8
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-4800310c7d638120
+8161000838210140
+480032447d638120
 38a000383c9ff000
 386100b078840020
-6000000048002661
+6000000048002791
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-6000000048002619
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+6000000048002749
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637a98
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637aa0
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
 38637ab83c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637ac87b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637af838847ae8
+480015454bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637b183c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920100400000000
+7c0004ac6529c800
+394010087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-6529c80039201004
-7c604f2a7c0004ac
-3920000139401008
+3842b7283c4c0001
+4182004428030002
+4182001428030003
+4182005028030001
+4bffffa87c8307b4
+6529c80039201064
+7c804f2a7c0004ac
+3940106839200001
 7c0004ac654ac800
 4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842b6f4
-2803000341820044
-2803000141820014
-7c8307b441820050
-392010644bffffa8
-7c0004ac6529c800
-392000017c804f2a
-654ac80039401068
-7d20572a7c0004ac
-392010444e800020
+6529c80039201044
+7c804f2a7c0004ac
+3940104839200001
+392010244bffffd8
 7c0004ac6529c800
 392000017c804f2a
-4bffffd839401048
-6529c80039201024
-7c804f2a7c0004ac
-3940102839200001
-000000004bffffbc
-0000000000000000
-5469f87e3d405555
-7d295038614a5555
-3d2033337c691850
-7d2a183861293333
-7c6348385463f0be
-5549e13e7d4a1a14
-3d400f0f7d295214
-7d295038614a0f0f
-7d2a4a14552ac23e
-7c634a145523843e
-4e800020786306a0
-0000000000000000
-2803000200000000
-3940105039200000
-280300034182002c
-3940107039200000
-280300014182001c
-3940103039200000
-392000004182000c
-654ac80039401010
-7d20572a7c0004ac
+4bffffbc39401028
+0000000000000000
+3d40555500000000
+614a55555469f87e
+7c6918507d295038
+612933333d203333
+5463f0be7d2a1838
+7d4a1a147c634838
+7d2952145549e13e
+614a0f0f3d400f0f
+552ac23e7d295038
+5523843e7d2a4a14
+786306a07c634a14
 000000004e800020
 0000000000000000
 3920000028030002
-4182002c3940104c
+4182002c39401050
 3920000028030003
-4182001c3940106c
+4182001c39401070
 3920000028030001
-4182000c3940102c
-3940100c39200000
+4182000c39401030
+3940101039200000
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
-7c0004ac00000000
-390000047d201e2a
-7d0903a679290020
-9d2affff39440004
-4200fff87929c202
-7c0004ac38630004
-7869c2227c601e2a
-9924000698640007
-7863462278698422
-9864000499240005
+2803000200000000
+3940104c39200000
+280300034182002c
+3940106c39200000
+280300014182001c
+3940102c39200000
+392000004182000c
+654ac8003940100c
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-3842b4f83c4c0001
-48002d9d7c0802a6
-23a30003f821ff31
-3ae000033f02ffff
-3b2010103b40100c
-206300073ac01094
-3b6000003bc00000
-66f780203b187e40
-6739c800675ac800
-7fbd07b466d6c800
-7bc917647c7f07b4
-7e87a3783a810020
-7d58482e3aa00004
-390000007e9ca378
-7949f86248000044
-7d4a00d0794a07e0
-7d494a787d4ab838
-552907fe7d2a4b78
-38c600017d293030
-7d254b787d292b78
-7d2741ae4200ffd4
-2828000839080001
-3920000841820018
-7d2903a638a00000
-4bffffb038c00000
-38e700083ab5ffff
-4082ff982c150000
-7ea0d72a7c0004ac
-7ea0cf2a7c0004ac
-4bfffce538600009
-4bfffcc13860000f
-6529c80039201014
-38f4ffff38c00004
-394000047cc903a6
-8cc7000139000000
-7906400c394affff
-4200fff07cc83378
-7cc04f2a7c0004ac
-38e9000438c00004
-391400037cc903a6
-7946400c8cc80001
-4200fff47cca3378
-7cc03f2a7c0004ac
-3a94000839290020
-4082ff9c7c29b000
-6694c8003a800848
-7c60a62a7c0004ac
-4bfffdd55463063e
-7c60a62a7c0004ac
-4bfffd715463063e
-7c60a62a7c0004ac
-5463063e38800017
-3a8008444bfffc6d
-4bfffc093860000f
+7d201e2a7c0004ac
+7929002039000004
+394400047d0903a6
+7929c2029d2affff
+386300044200fff8
+7c601e2a7c0004ac
+986400077869c222
+7869842299240006
+9924000578634622
+4e80002098640004
+0000000000000000
+3c4c000100000000
+7c0802a63842b52c
+f821ff3148002da5
+3f02ffff23a30007
+3b40100c3ee0e008
+3ac010943b201010
+3bc0000020630003
+3b187fec3b600000
+675ac8007af71020
+66d6c8006739c800
+7c7f07b47fbd07b4
+3a8100207bc91764
+3aa000047e87a378
+7e9ca3787d58482e
+4800004439000000
+794a07e07949f862
+7d4ab8387d4a00d0
+7d2a4b787d494a78
+7d293030552907fe
+7d292b7838c60001
+4200ffd47d254b78
+390800017d2741ae
+4182001828280008
+38a0000039200008
+38c000007d2903a6
+3ab5ffff4bffffb0
+2c15000038e70008
+7c0004ac4082ff98
+7c0004ac7ea0d72a
+386000097ea0cf2a
+3860000f4bfffce5
+392010144bfffcc1
+38c000046529c800
+7cc903a638f4ffff
+3900000039400004
+394affff8cc70001
+7cc833787906400c
+7c0004ac4200fff0
+38c000047cc04f2a
+7cc903a638e90004
+8cc8000139140003
+7cca33787946400c
+7c0004ac4200fff4
+392900207cc03f2a
+7c29b0003a940008
+3a8008484082ff9c
 7c0004ac6694c800
 5463063e7c60a62a
-7c0004ac4bfffd91
+7c0004ac4bfffdd5
 5463063e7c60a62a
-7c0004ac4bfffd2d
-388000257c60a62a
+7c0004ac4bfffd71
+388000177c60a62a
+4bfffc6d5463063e
+3860000f3a800844
+6694c8004bfffc09
+7c60a62a7c0004ac
+4bfffd915463063e
+7c60a62a7c0004ac
+4bfffd2d5463063e
+7c60a62a7c0004ac
+5463063e38800025
+3860000f4bfffc29
+392000004bfffbc9
+7d20d72a7c0004ac
+7d20cf2a7c0004ac
+7e9cea143860000b
+3860000f4bfffbc5
+4bfffb9d3a60101c
+6673c8003a00109c
+7f9cfa147e91a378
+388100406610c800
+4bfffd6d7e639b78
+8874000089310020
+7c634a783a730020
+4bfffc495463063e
+3a9400087d3da050
+7c69f8ae7c721b78
+7c634a78893c0020
 4bfffc295463063e
-4bfffbc93860000f
-7c0004ac39200000
-7c0004ac7d20d72a
-3860000b7d20cf2a
-4bfffbc57e9cea14
-3a60101c3860000f
-3a00109c4bfffb9d
-7f9cfa146673c800
-6610c8007e91a378
-7e639b7838810040
-7d3da0504bfffd6d
-3a9400083a730020
-893c00207c69f8ae
-5463063e7c634a78
-893100204bfffc41
-8874fff87c721b78
-5463063e7c634a78
-7c3380004bfffc29
-7eb51a147c639214
-3bde00014082ffb0
-283e00037f7baa14
-382100d04082fdc4
-48002b5c7f6307b4
-0100000000000000
-3c4c000100001080
-7d7080263842b24c
+7c6392147c338000
+4082ffb07eb51a14
+7f7baa143bde0001
+4082fdc4283e0003
+7f6307b4382100d0
+0000000048002b64
+0000108001000000
+3842b2803c4c0001
+7c0802a67d708026
+2e25000091610008
+f821ff8148002b1d
+4192001c7c7f1b78
+7c641b787c852378
+38637c303c62ffff
+600000004bfff401
+38a5603c3ca2ffff
+7fe3fb7838800000
+3ba000203f82ffff
+3b9c7c403bc00000
+60000000480015b1
+4bfffcf17fe3fb78
+7c64003439200000
+2c0400005484d97e
+3920180041820008
+7d291a14206300c0
+419200147fde4a14
+7f83e378788407e0
+600000004bfff399
+38a55ff43ca2ffff
+7fe3fb7838800000
+6000000048001559
+4082ffa437bdffff
+3c62ffff41920014
+4bfff36538637c48
+3821008060000000
+816100087bc30020
+48002a987d708120
+0300000000000000
+3c4c000100000480
+7d6000263842b184
 916100087c0802a6
-48002b152e250000
-7c7f1b78f821ff81
-7c8523784192001c
+48002a012e250000
+7c7e1b78f821ff41
+7cda33787c972378
+419200187cfb3b78
 3c62ffff7c641b78
-4bfff45538637c38
-3ca2ffff60000000
-3880000038a56074
-3f82ffff7fe3fb78
-3bc000003ba00020
-480015b53b9c7c48
-7fe3fb7860000000
-394000004bfffcf1
-212300c07c640034
-2c0400005484d97e
-3940180041820008
-7fde4a147d295214
-788407e041920014
-4bfff3ed7f83e378
-3ca2ffff60000000
-3880000038a5602c
-4800155d7fe3fb78
-37bdffff60000000
-419200144082ffa4
-38637c503c62ffff
-600000004bfff3b9
-7bc3002038210080
-7d70812081610008
-0000000048002a90
-0000048003000000
-3842b1503c4c0001
-7c0802a67d600026
-2e25000091610008
-f821ff41480029f9
-7c9723787c7e1b78
-7cfb3b787cda3378
-7c641b7841920018
+4bfff2fd38637c50
+7f45d37860000000
+7fc3f37838800000
+480014bd3f02ffff
+3ba0000060000000
+3b187c403b200000
+4bfffbf17fc3f378
+7c7c1b787c7f0034
+4192001457ffd97e
+7f03c3787be407e0
+600000004bfff2b1
+408200882c1c0000
+418200802c190000
+3e82ffff3bfdffff
+7ffcfb787ff5fb78
+3a947c407fb9eb78
+4bfffba17fc3f378
+419200187c781b78
+7e83a3787c640034
+4bfff2655484d97e
+2c18000060000000
+408200683ad90001
+7d5fe0507d35c850
+418100607c095000
+418100642c16001f
+388000007f65db78
+7ed9b3787fc3f378
+6000000048001401
+3bbd00014bffffa0
+418200202c1d0020
+388000007f65db78
+7ff9fb787fc3f378
+60000000480013d9
+3be0ffff4bffff28
+7ed5b3784bffff5c
+7f3ccb784bffffa8
+4bffff9c7ebfab78
+4080001c2c1c0000
+3b8000002c1d0020
+239d001f41820008
+7f9cea143bbd0001
+3c62ffff41920014
+4bfff1ad38637c48
+7d3fe21460000000
+7d290e702c370000
+2d9f00007d290194
+7fbd01947d3d2e70
+7fbd485057bd2834
+408c003c418200b4
 38637c583c62ffff
-600000004bfff351
-388000007f45d378
-3f02ffff7fc3f378
-60000000480014c1
-3b2000003ba00000
-7fc3f3783b187c48
-7c7f00344bfffbf1
-57ffd97e7c7c1b78
-7be407e041920014
-4bfff3057f03c378
-2c1c000060000000
-2c19000040820088
-3bfdffff41820080
-7ff5fb783e82ffff
-7fb9eb787ffcfb78
-7fc3f3783a947c48
-7c781b784bfffba1
-7c64003441920018
-5484d97e7e83a378
-600000004bfff2b9
-3ad900012c180000
-7d35c85040820068
-7c0950007d5fe050
-2c16001f41810060
-7f65db7841810064
+600000004bfff171
+3c62ffff41920018
+4bfff15d386379d0
+408c003c60000000
+81610008382100c0
+480028707d618120
+3c62ffff7fffe050
+7ca501947fe50e70
+38637c687fa407b4
+4bfff1257ca507b4
+4092ffb860000000
+7f45d3783be00008
 7fc3f37838800000
-480014057ed9b378
-4bffffa060000000
-2c1d00203bbd0001
-7f65db7841820020
+480012dd3b800000
+3860006460000000
+7c1de0004bfff7c9
+7fc3f3784181002c
+2c0300004bfffa0d
+3bffffff4182ff90
+4082ffc02c1f0000
+4192ff784bffff80
+7f65db784bffff64
 7fc3f37838800000
-480013dd7ff9fb78
-4bffff2860000000
-4bffff5c3be0ffff
-4bffffa87ed5b378
-7ebfab787f3ccb78
-2c1c00004bffff9c
-7fa907b440800024
-2129001f3b800000
-418000082c290000
-3bbd0001239d001f
-419200147f9cea14
-38637c503c62ffff
-600000004bfff1f9
-2c3700007d3cfa14
-7d2901947d290e70
-7d3d2e702d9f0000
-57bd28347fbd0194
-418200b47fbd4850
-3c62ffff408c003c
-4bfff1bd38637c60
-4192001860000000
-386379f83c62ffff
-600000004bfff1a9
-382100c0408c003c
-7d61812081610008
-7fffe05048002860
-7fe50e703c62ffff
-7fa407b47ca50194
-7ca507b438637c70
-600000004bfff171
-3be000084092ffb8
-388000007f45d378
-3b8000007fc3f378
-60000000480012d9
-4bfff7c138600064
-4181002c7c1de000
-4bfffa057fc3f378
-4182ff902c030000
-2c1f00003bffffff
-4bffff804082ffc0
-4bffff644192ff78
-388000007f65db78
-3b9c00017fc3f378
-6000000048001289
-4bfff77138600064
-000000004bffffb0
-00000c8003000000
-3842aea03c4c0001
+4800128d3b9c0001
+3860006460000000
+4bffffb04bfff779
+0300000000000000
+3c4c000100000c80
+392010003842aedc
+7c0004ac6529c800
+280a000e7d404e2a
+7c0802a64d820020
+f80100103940000e
+7c0004acf821ffa1
+3c62ffff7d404f2a
+4bfff05538637c80
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+3842ae783c4c0001
 6529c80039201000
 7d404e2a7c0004ac
-4d820020280a000e
-3940000e7c0802a6
+4d820020280a0001
+394000017c0802a6
 f821ffa1f8010010
 7d404f2a7c0004ac
-38637c883c62ffff
-600000004bfff0a1
+38637ca83c62ffff
+600000004bffeff1
 e801001038210060
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-392010003842ae3c
+3920100c3842ae14
 7c0004ac6529c800
-280a00017d404e2a
-7c0802a64d820020
-f801001039400001
-7c0004acf821ffa1
-3c62ffff7d404f2a
-4bfff03d38637cb0
-3821006060000000
-7c0803a6e8010010
-000000004e800020
-0000008001000000
-3842add83c4c0001
-6529c8003920100c
-7c804f2a7c0004ac
-6529c80039201010
-7c604f2a7c0004ac
-4bfff6843860000f
+392010107c804f2a
+7c0004ac6529c800
+3860000f7c604f2a
+000000004bfff68c
 0000000000000000
-3c4c000100000000
-7c0802a63842ad9c
-916100087d708026
-f821fec148002631
-83a2806460000000
-7c9823787c7f1b78
-3880008638600001
-7fbd16707cbc2b78
-4bffff8d7fbd0194
-23bd00203940080c
-654ac80039200001
-7d20572a7c0004ac
-3ac0081038600064
-3d22ffff4bfff5f5
-39297cd860000000
-3de2ffff3e02ffff
-f92100982e3c0000
-3b4100803d22ffff
-3bc0000039297c48
-66d6c8003b600000
-3d22fffff9210090
-39297ce83aa10060
-3a107d003a228064
-f92100a039ef7cf0
+3842add83c4c0001
+7d7080267c0802a6
+4800264191610008
+60000000f821fec1
+7c7f1b7883a28054
+386000017c982378
+7cbc2b7838800086
+7fbd01947fbd1670
+3940080c4bffff8d
+3920000123bd0020
+7c0004ac654ac800
+386000647d20572a
+4bfff5fd3ac00810
+600000003d22ffff
+3e02ffff39297cd0
+2e3c00003de2ffff
+3920101cf92100a0
+6529c8003b410080
+3b6000003bc00000
+f921009066d6c800
+3aa100603d22ffff
+3a22805439297c40
+39ef7ce83a107cf8
+3d22fffff9210098
+f92100a839297ce0
 419200147f7c07b4
-7f84e378e8610098
-600000004bffef11
-3af7626c3ee2ffff
+7f84e378e86100a0
+600000004bffeeb9
+3af762343ee2ffff
 7f83e37838800000
 39c000013b200000
-480010757ee5bb78
+4800106d7ee5bb78
 3860006460000000
-7c1dc8004bfff55d
+7c1dc8004bfff559
 4192001041810110
-4bffeecde86100a0
+4bffee75e86100a8
 38bd000160000000
 2c0500003920ffff
 7d3ff12e38e10060
@@ -1078,350 +1104,349 @@ f92100a039ef7cf0
 4080000839290001
 2c29000139200001
 3929ffff7e8ae800
-7ee5bb7840820150
+7ee5bb784082014c
 7f83e37838800000
-6000000048000ff9
-4bfff4e138600064
-392280a860000000
+6000000048000ff1
+4bfff4dd38600064
+3922809860000000
 2c0900007d29f02e
-7d3ff12e418001a8
+7d3ff12e418001a4
 7d3ff02e3b200000
-4181016c7c09c800
-3b7b0001409201f8
+418101687c09c800
+3b7b0001409201f4
 2c1b00043b5affff
 4082ff043bde0004
 3860000138800006
-3940080c4bfffe09
+3940080c4bfffdfd
 654ac80039200000
 7d20572a7c0004ac
 3bff001039200004
 386000017d2903a6
-2c090000853ffffc
-3860000040800008
+7d2948f8853ffffc
+7c63483855290ffe
 382101404200fff0
 81610008786307e0
-480024847d708120
+480024887d708120
 3a8000007f12c378
 7c0004ac3a600000
 386000647dc0b72a
-3860101c4bfff42d
-6463c80038810080
-88fa00034bfff60d
-4182005c2c070000
-3652ffff3a940001
-7e6a07b44082ffcc
-7c8450507e8407b4
-7c99a9ae78840fe0
-e861009041920010
-600000004bffed69
-38a562283ca2ffff
-7f83e37838800000
-48000ed53b390001
-3860006460000000
-4bfffe604bfff3bd
-4bffffa83a730001
-419e00282f880000
-88a7000041960010
-408200282c050000
-7c1940007d065050
-3900000041800028
-4196001048000014
+e86100904bfff429
+4bfff60d38810080
+2c07000088fa0003
+3a9400014182005c
+4082ffd03652ffff
+7e8407b47e6a07b4
+78840fe07c845050
+419200107c99a9ae
+4bffed15e8610098
+3ca2ffff60000000
+3880000038a561f0
+3b3900017f83e378
+6000000048000ed1
+4bfff3bd38600064
+3a7300014bfffe64
+2f8800004bffffa8
+41960010419e0028
 2c05000088a70000
-394a00014082001c
-4bfffe6038e70001
-7cce33787d194378
-7d4653784bffffd4
-4bffffe039000001
-38a562283ca2ffff
+7d06505040820028
+418000287c194000
+4800001439000000
+88a7000041960010
+4082001c2c050000
+38e70001394a0001
+7d1943784bfffe64
+4bffffd47cce3378
+390000017d465378
+3ca2ffff4bffffe0
+3880000038a561f0
+3b3900017f83e378
+6000000048000e41
+4bfff32d38600064
+2c0e00004bfffe6c
+2c19000040810048
+7ddff12e4081fe68
+7d3ff02e3b200000
+4081fe547c09c800
+38a561f03ca2ffff
 7f83e37838800000
-48000e453b390001
+48000df53b390001
 3860006460000000
-4bfffe684bfff32d
-408100482c0e0000
-4081fe642c190000
-3b2000007ddff12e
-7c09c8007d3ff02e
-3ca2ffff4081fe50
-3880000038a56228
-3b3900017f83e378
-6000000048000df9
-4bfff2e138600064
-4082fe244bffffd0
-7d29167081310000
-7c09c8007d290194
-4bffffac4080fe10
-2c04ffff7c9ff02e
-7de37b7840820014
-600000004bffec31
-7c8407b44bfffdf4
-4bffec1d7e038378
-4bfffde060000000
-0300000000000000
-3c4c000100001280
-7c0802a63842a9c4
-6484c80038800808
-f821ff5148002281
-7c80262a7c0004ac
-5484103a60000000
-908280643c62ffff
-7c8407b438637d10
+4bffffd04bfff2e1
+813100004082fe28
+7d2901947d291670
+4080fe147c09c800
+7c9ff02e4bffffac
+408200142c04ffff
+4bffebdd7de37b78
+4bfffdf860000000
+7e0383787c8407b4
 600000004bffebc9
-8122805860000000
-418201b82c090000
-83c2805460000000
-408200082c1effff
-600000003bc00000
-2c1dffff83a28050
-6000000040820014
-7fbd0e7083a28064
-3c62ffff7fbd0194
-7fc407b47fa507b4
-6000000038637d30
-600000004bffeb69
-3f22ffff3c62ffff
-3be0ffff38637d48
-600000004bffeb51
-6000000048000a05
-3b80ffff3b600000
-3b397c483b428064
-408100c87c1df000
-3b02811860000000
-480009994800000c
-8138000060000000
-4180fff07c09f000
-38a0000038800008
-4bfffb2938610060
-815a000039200004
-7d2903a638c1005c
-7c641b7839000000
-8526000438e00000
-418200182c09ffff
-390800015529103a
-552930327d295214
-4200ffe07ce74a14
-418200082c080000
-214a00807ce743d6
-7d275050554a2834
-408000082c090000
-7c08d8407d2a3850
-7c09e04041800018
-7fdff37840800010
-7d3c4b787d1b4378
-4bffea757f23cb78
-3bde000160000000
-3c62ffff4bffff38
-38637d507fe407b4
-600000004bffea59
+000000004bfffde4
+0000128003000000
+3842a9f83c4c0001
+388008087c0802a6
+480022896484c800
+7c0004acf821ff51
+600000007c80262a
+3c62ffff5484103a
+38637d0890828054
+4bffeb757c8407b4
+6000000060000000
+2c09000081228048
+60000000418201b8
+2c1effff83c28044
+3bc0000040820008
+83a2804060000000
+408200142c1dffff
+83a2805460000000
+7fbd01947fbd0e70
+7fa507b43c62ffff
+38637d287fc407b4
+4bffeb1560000000
+3c62ffff60000000
+38637d403f22ffff
+4bffeafd3be0ffff
+48000a0160000000
+3b60000060000000
+3b4280543b80ffff
+7c1df0003b397c40
+60000000408100c8
+4800000c3b028108
+6000000048000995
+7c09f00081380000
+388000084180fff0
+3861006038a00000
+394000044bfffb21
+38c1005c80fa0000
+390000007d4903a6
+392000007c641b78
+2c0affff85460004
+554a103a41820018
+7d4a3a1439080001
+7d295214554a3032
+2c0800004200ffe0
+7d2943d641820008
+418000307c08d840
+54e7283420e70080
+7d2afe707d293850
+7d2a48507d494a78
+408000107c09e040
+7d1b43787fdff378
+7f23cb787d3c4b78
+600000004bffea21
+4bffff383bde0001
 7fe407b43c62ffff
-4bffea4538637d60
-2c1f000060000000
-3c62ffff40800048
-4bffea2d38637d88
+4bffea0538637d48
+3c62ffff60000000
+38637d587fe407b4
+600000004bffe9f1
+408000482c1f0000
+38637d803c62ffff
+600000004bffe9d9
+3880008038a00001
+4bfffa3d38610060
+7c691b782c030000
+382100b040820040
+480020e87d2307b4
+83e2805060000000
+480008a94bffffa4
+3bc0000060000000
+4182ffac7c1ef800
+6000000048000855
+4bffffec3bde0001
+57e90ffe7ffff8f8
+000000004bffffbc
+0000088001000000
+3842a7a83c4c0001
+480020317c0802a6
+3f22fffff821ff41
+3f02ffff3b3962c0
+3ba000003e82ffff
+3a947d903b1879d0
+7f25cb787fbf07b4
+7fe3fb7838800000
+6000000048000af9
+3b6000003b400000
+480000303bc00000
+2c1e00077fdaf378
+3ca2ffff41820080
+3880000038a56278
+3bde00017fe3fb78
+48000abd7ebbab78
 38a0000160000000
-3861006038800080
-2c0300004bfffa45
-408200407c691b78
-7d2307b4382100b0
-60000000480020e0
-4bffffa483e28060
-60000000480008ad
-7c1ef8003bc00000
-480008594182ffac
-3bde000160000000
-7ffff8f84bffffec
-4bffffbc57e90ffe
-0100000000000000
-3c4c000100000880
-7c0802a63842a774
-f821ff4148002029
-3b3962f83f22ffff
-3e82ffff3f02ffff
-3b1879f83ba00000
-7fbf07b43a947d98
+7fe3fb787fc407b4
+3ec2ffff4bfff4a1
+3ee2ffff3ad65ff4
+38a000003af7603c
+7c7c1b7838800001
+7ec7b3787c751b78
+7fe3fb787ee6bb78
+7f03c3784bfff56d
+600000004bffe899
+4180ff847c1be040
+4bffff807f75db78
+7fe4fb787f4507b4
+3bc000007e83a378
+600000004bffe871
 388000007f25cb78
-48000afd7fe3fb78
-3b40000060000000
-3bc000003b600000
-7fdaf37848000030
-418200802c1e0007
-38a562b03ca2ffff
+48000a357fe3fb78
+7c1ed00060000000
+7ec7b3784082003c
+38a000007ee6bb78
+7fe3fb7838800001
+4bfff5013bbd0001
+4bffe82d7f03c378
+2c1d000460000000
+382100c04082fef0
+3ca2ffff48001f44
+3880000038a56278
+3bde00017fe3fb78
+60000000480009d9
+000000004bffffa4
+00000c8001000000
+3842a6303c4c0001
+48001eb57c0802a6
+3be00000f821ff31
+3fa2ffff4bfff745
+7ffe07b43bbd6234
+388000007fa5eb78
+4800098d7fc3f378
+3ec2ffff60000000
+388000003ad66348
+3bff00017fc3f378
+4800096d7ec5b378
+3f22ffff60000000
+388000003b39603c
+7f25cb787fc3f378
+6000000048000951
+3b9c62c03f82ffff
+7fc3f37838800000
+480009357f85e378
+2c1f000460000000
+3c62ffff4082ff8c
+38637da83e82ffff
+4bffe73d3e62ffff
+4bfffb8d60000000
+3bc000003c62ffff
+3a947de838637dc0
+600000004bffe721
+3ae0ffff3a737de0
+3ba000003aa00000
+7ec5b3787fdf07b4
 7fe3fb7838800000
-7ebbab783bde0001
-6000000048000ac1
-7fc407b438a00001
-4bfff4a17fe3fb78
-3ad6602c3ec2ffff
-3af760743ee2ffff
-3880000138a00000
-7c751b787c7c1b78
-7ee6bb787ec7b378
-4bfff56d7fe3fb78
-4bffe8ed7f03c378
-7c1be04060000000
-7f75db784180ff84
-7f4507b44bffff80
-7e83a3787fe4fb78
-4bffe8c53bc00000
-7f25cb7860000000
+480008cd3b600000
+7c1dd80060000000
+7f85e3784082012c
 7fe3fb7838800000
-6000000048000a39
-4180003c7c1ed000
-7ee6bb787ec7b378
-3880000138a00000
-3bbd00017fe3fb78
-7f03c3784bfff501
-600000004bffe881
-4082fef02c1d0004
-48001f3c382100c0
-38a562b03ca2ffff
+480008ad3b600000
+3b40000060000000
+7f4407b438a00000
+4bfff28d7fe3fb78
+408000087c1b1840
+3f02ffff7c7b1b78
+388000003b186278
+3b5a00017fe3fb78
+4800086d7f05c378
+2c1a000860000000
+7c1ba8404082ffc0
+7fb7eb784081000c
+3bbd00027f75db78
+4082ff682c1d0008
+3942805860000000
+7faa482e7bc91764
+408000bc2c1d0000
+408200b02c17ffff
+7e639b787fe4fb78
+600000004bffe641
+7ec5b3783ba0ffff
 7fe3fb7838800000
-480009dd3bde0001
-4bffffa460000000
-0100000000000000
-3c4c000100000c80
-7c0802a63842a5fc
-f821ff3148001ead
-4bfff74d3be00000
-3bbd626c3fa2ffff
-7fa5eb787ffe07b4
-7fc3f37838800000
-6000000048000991
-3ad663803ec2ffff
-7fc3f37838800000
-7ec5b3783bff0001
-6000000048000971
-3b3960743f22ffff
-7fc3f37838800000
-480009557f25cb78
-3f82ffff60000000
-388000003b9c62f8
-7f85e3787fc3f378
-6000000048000939
-4082ff8c2c1f0004
-3e82ffff3c62ffff
-3e62ffff38637db0
-600000004bffe791
-3c62ffff4bfffb8d
-38637dc83bc00000
-4bffe7753a947df0
-3a737de860000000
-3aa000003ae0ffff
-7fdf07b43ba00000
-388000007ec5b378
-3b6000007fe3fb78
-60000000480008d1
-4082012c7c1dd800
+480007fd3b600000
+7c1be80060000000
+3bde000141800098
+4082fef8283e0004
+3ba000003c62ffff
+4bffe5fd386379d0
+3c62ffff60000000
+4bffe5ed38637df0
+7fbf07b460000000
 388000007f85e378
-3b6000007fe3fb78
-60000000480008b1
-38a000003b400000
-7fe3fb787f4407b4
-7c1b18404bfff28d
-7c7b1b7840800008
-3b1862b03f02ffff
-7fe3fb7838800000
-7f05c3783b5a0001
-6000000048000871
-4082ffc02c1a0008
-4081000c7c1ba840
-7f75db787fb7eb78
-2c1d00083bbd0002
-600000004082ff68
-7bc9176439428068
-2c1d00007faa482e
-2c17ffff408000bc
-7fe4fb78408200b0
-4bffe6957e639b78
-3ba0ffff60000000
-388000007ec5b378
-3b6000007fe3fb78
-6000000048000801
-418000987c1be800
-283e00043bde0001
-3c62ffff4082fef8
-386379f83ba00000
-600000004bffe651
-38637df83c62ffff
-600000004bffe641
-7f85e3787fbf07b4
+480007ad7fe3fb78
+3b40000060000000
+3bc000003ae00000
+3ca2ffff48000088
+3880000038a56300
+3b7b00017fe3fb78
+6000000048000781
+7efdbb784bfffeb4
+7fe4fb787fa507b4
+4bffe58d7e83a378
+4bffff5060000000
+38a563003ca2ffff
 7fe3fb7838800000
-60000000480007b1
-3ae000003b400000
-480000883bc00000
-38a563383ca2ffff
+480007453b7b0001
+4bffff4860000000
+2c1e00077fd7f378
+7f05c37841820068
 7fe3fb7838800000
-480007853b7b0001
-4bfffeb460000000
-7fa507b47efdbb78
-7e83a3787fe4fb78
-600000004bffe5e1
-3ca2ffff4bffff50
-3880000038a56338
-3b7b00017fe3fb78
-6000000048000749
-7fd7f3784bffff48
-418200682c1e0007
+4800071d3bde0001
+7ebaab7860000000
+7fc407b438a00000
+4bfff0fd7fe3fb78
+3ad65ff43ec2ffff
+38a000007f26cb78
+7c7b1b7838800000
+7ec7b3787c751b78
+4bfff1d17fe3fb78
+4181ff9c7c1bd040
+4bffff987f55d378
+388000007f85e378
+3bc000007fe3fb78
+60000000480006b9
+4082006c7c1eb800
+7f26cb787ec7b378
+3880000038a00000
+3bbd00017fe3fb78
+3ce2ffff4bfff185
+3cc2ffff38e760f4
+38a0000138c6613c
+7fe3fb7838800001
+2c1d00044bfff165
+3c62ffff4082feac
+4bffe48538637e08
+4bfffb2560000000
+382100d04bfff451
+48001b9438600001
 388000007f05c378
 3bde00017fe3fb78
-6000000048000721
-38a000007ebaab78
-7fe3fb787fc407b4
-3ec2ffff4bfff0fd
-7f26cb783ad6602c
-3880000038a00000
-7c751b787c7b1b78
-7fe3fb787ec7b378
-7c1bd0404bfff1d1
-7f55d3784181ff9c
-7f85e3784bffff98
-7fe3fb7838800000
-480006bd3bc00000
-7c1eb80060000000
-7ec7b3784180006c
-38a000007f26cb78
-7fe3fb7838800000
-4bfff1853bbd0001
-38e7612c3ce2ffff
-38c661743cc2ffff
-3880000138a00001
-4bfff1657fe3fb78
-4082feac2c1d0004
-38637e103c62ffff
-600000004bffe4d9
-4bfff4594bfffb25
-38600001382100d0
-7f05c37848001b8c
-7fe3fb7838800000
-480006353bde0001
-4bffff7860000000
-0100000000000000
-3c4c000100000d80
-7c0802a63842a254
-6000000039200001
-48001b0d91228058
-3be00000f821ff61
-388000007fe307b4
-480006513bff0001
-2c1f001060000000
-3be000004082ffe8
-388000007fe307b4
-480006913bff0001
-2c1f001060000000
-392008444082ffe8
-6529c8003b800001
-7f804f2a7c0004ac
-3b20000239200848
-7c0004ac6529c800
-3c62ffff7f204f2a
-38637e203c804000
-4bffe3fd3bc00800
-67dec80060000000
-7c0004ac4bfff319
-386003e87f80f72a
-4bffea593be00000
-7fe0f72a7c0004ac
-3f60c800386003e8
-7b7b00204bffea45
+6000000048000631
+000000004bffff78
+00000d8001000000
+3842a2883c4c0001
+392000017c0802a6
+48001b1960000000
+91228048f821ff61
+7fe307b43be00000
+3bff000138800000
+600000004800064d
+4082ffe82c1f0010
+7fe307b43be00000
+3bff000138800000
+600000004800068d
+4082ffe82c1f0010
+3b8000013b600844
+7c0004ac677bc800
+392008487f80df2a
+6529c8003b200002
+7f204f2a7c0004ac
+3c8040003c62ffff
+3bc0080038637e18
+600000004bffe3a9
+4bfff31167dec800
+7f80f72a7c0004ac
+3be00000386003e8
+7c0004ac4bffea59
+386003e87fe0f72a
+4bffea453b7bf7bc
 7fe0df2a7c0004ac
 675ac8003b400004
 7fe0d72a7c0004ac
@@ -1432,39 +1457,39 @@ f821ff3148001ead
 3920000c3b001000
 7c0004ac6718c800
 386000007d20c72a
-4bffe9e96063c350
+4bffe9ed6063c350
 7fe0ef2a7c0004ac
 7fe0f72a7c0004ac
 7c0004ac3920000e
 386027107d20c72a
-392002004bffe9c5
+392002004bffe9c9
 7d20ef2a7c0004ac
 7f20f72a7c0004ac
-4bffe9c53860000f
+4bffe9c93860000f
 7fe0ef2a7c0004ac
 7c0004ac39200003
 3860000f7d20f72a
-392000064bffe9a9
+392000064bffe9ad
 7d20ef2a7c0004ac
 7f80f72a7c0004ac
-4bffe98d3860000f
+4bffe9913860000f
 7c0004ac39200920
 7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bffe971
-392004004bffe94d
+386000c84bffe975
+392004004bffe951
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bffe94d38600003
-4bffe929386000c8
-4bfff2314bfffa75
+4bffe95138600003
+4bffe92d386000c8
+4bfff22d4bfffa79
 3c6040003c800020
 6000000048000bc1
 7c691b782c030000
 7c0004ac40820020
 7c0004ac7f80d72a
 382100a07f80df2a
-4800194c7d2307b4
+480019587d2307b4
 38a0000038c00000
 3c6040003c800020
 6000000048000949
@@ -1476,8 +1501,8 @@ f821ff3148001ead
 4e8000204200fffc
 0000000000000000
 3c4c000100000000
-6000000038429fd4
-3942811c78631764
+600000003842a00c
+3942810c78631764
 392900017d2a182e
 7d2a192e552906fe
 3920000139400820
@@ -1485,31 +1510,31 @@ f821ff3148001ead
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429f8c
-3922811c78631764
+6000000038429fc4
+3922810c78631764
 7d49192e39400000
 392000013940081c
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429f4c
-3929000181228118
-91228118552906fe
+6000000038429f84
+3929000181228108
+91228108552906fe
 3920000139400818
 7c0004ac654ac800
 4bffff287d20572a
 0000000000000000
 3c4c000100000000
-6000000038429f0c
-9122811839200000
+6000000038429f44
+9122810839200000
 3920000139400814
 7c0004ac654ac800
 4bfffef07d20572a
 0000000000000000
 3c4c000100000000
-6000000038429ed4
-3942810878631764
+6000000038429f0c
+394280f878631764
 392900017d2a182e
 7d2a192e552906fe
 3920000139400830
@@ -1517,29 +1542,29 @@ f821ff3148001ead
 4bfffea87d20572a
 0000000000000000
 3c4c000100000000
-7c0802a638429e8c
+7c0802a638429ec4
 fbe1fff83940082c
 7c7f1b7839200001
 f8010010654ac800
 7c0004acf821ffd1
 4bfffe697d20572a
 7be3176460000000
-3940000039228108
+39400000392280f8
 7d49192e38210030
-0000000048001790
+000000004800179c
 0000018001000000
-38429e303c4c0001
+38429e683c4c0001
 3920000139400838
 7c0004ac654ac800
 4bfffe207d20572a
 0000000000000000
 3c4c000100000000
-3940083438429e04
+3940083438429e3c
 654ac80039200001
 7d20572a7c0004ac
 000000004bfffdf4
 0000000000000000
-38429dd83c4c0001
+38429e103c4c0001
 fbe1fff87c0802a6
 f80100107c7f1b78
 4bfffef1f821ffd1
@@ -1548,7 +1573,7 @@ ebe1fff8e8010010
 4bffff7c7c0803a6
 0100000000000000
 3c4c000100000180
-7c0802a638429d94
+7c0802a638429dcc
 7c7f1b78fbe1fff8
 f821ffd1f8010010
 382100304bfffef5
@@ -1556,41 +1581,41 @@ e80100107fe3fb78
 7c0803a6ebe1fff8
 000000004bffff64
 0000018001000000
-38429d503c4c0001
+38429d883c4c0001
 7863176460000000
-7d2a182e394280f8
+7d2a182e394280e8
 5529077e39290001
 394008287d2a192e
 654ac80039200001
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-38429d083c4c0001
+38429d403c4c0001
 7863176460000000
-39400000392280f8
+39400000392280e8
 394008247d49192e
 654ac80039200001
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-38429cc83c4c0001
+38429d003c4c0001
 7863176460000000
-7d2a182e394280e8
+7d2a182e394280d8
 5529077e39290001
 394008407d2a192e
 654ac80039200001
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-38429c803c4c0001
+38429cb83c4c0001
 7863176460000000
-39400000392280e8
+39400000392280d8
 3940083c7d49192e
 654ac80039200001
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-38429c403c4c0001
+38429c783c4c0001
 fbe1fff87c0802a6
 3be0080439200001
 7d2918307cac2b78
@@ -1600,70 +1625,70 @@ f801001067ffc800
 4e800421f8410018
 39200000e8410018
 7d20ff2a7c0004ac
-4800153c38210030
+4800154838210030
 0100000000000000
 3c4c000100000180
-2c24000038429bdc
+2c24000038429c14
 7869176460000000
-3900ffff394280a8
+3900ffff39428098
 4d8200207d0a492e
 7c641b787c0802a6
-38637e503c62ffff
+38637e383c62ffff
 f821ffa1f8010010
-600000004bffdde1
+600000004bffdd91
 e801001038210060
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-2c24000038429b7c
+2c24000038429bb4
 7869176460000000
-3900ffff39428068
+3900ffff39428058
 4d8200207d0a492e
 7c641b787c0802a6
-38637e783c62ffff
+38637e603c62ffff
 f821ffa1f8010010
-600000004bffdd81
+600000004bffdd31
 e801001038210060
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429b1c
+7c0802a638429b54
 f8010010282303ff
 41810028f821ffa1
 3c62ffff7c641b78
-4bffdd3538637e98
+4bffdce538637e80
 3821006060000000
 7c0803a6e8010010
 3d2000104e800020
 408000287c234840
 39200066786505a0
 7864b2827ca54b92
-38637ea03c62ffff
-600000004bffdcf9
+38637e883c62ffff
+600000004bffdca9
 3d2040004bffffc4
 7c23484078646502
 7863b28240800024
 7d29185078895564
 3c62ffff38a00066
-38637eb07ca92b92
+38637e987ca92b92
 786317824bffffc8
 7865556439200066
 7c641b787ca52050
 7ca54b923c62ffff
-4bffffa438637ec0
+4bffffa438637ea8
 0100000000000000
 3c4c000100000080
-7c0802a638429a4c
+7c0802a638429a84
 7cc42a14fbe1fff8
 7c8523787cbf2b78
 3c62ffff7c641b78
-38637ed078c60020
+38637eb878c60020
 f821ff91f8010010
-600000004bffdc59
+600000004bffdc09
 4bfffef97fe3fb78
-38637ee03c62ffff
-600000004bffdc41
-4800134438210070
+38637ec83c62ffff
+600000004bffdbf1
+4800135038210070
 0100000000000000
 2c24000000000180
 7869f84241820024
@@ -1673,15 +1698,15 @@ f821ff91f8010010
 386300014e800020
 000000004bfffff4
 0000000000000000
-384299a83c4c0001
+384299e03c4c0001
 788407647c0802a6
 7c691b783d40aaaa
-4800126d614aaaaa
+48001279614aaaaa
 7884f0827f832214
 39040001f821ffc1
 7d0903a67c7f1b78
 420000807c7d1b78
-600000004bffdc15
+600000004bffdbc5
 3d00aaaa7d3fe050
 7feafb787929f082
 3bc0000039290001
@@ -1691,12 +1716,12 @@ f821ff91f8010010
 392900017feafb78
 7d2903a661085555
 7fffe05042000058
-600000004bffdbc5
+600000004bffdb75
 3d2055557bfff082
 61295555395f0001
 420000407d4903a6
 7fc307b438210040
-9149000048001220
+914900004800122c
 4bffff7839290004
 7c094000812a0000
 3bde000141820008
@@ -1707,44 +1732,44 @@ f821ff91f8010010
 3bbd00043bde0001
 000000004bffffac
 0000048001000000
-384298983c4c0001
+384298d03c4c0001
 7c0802a67d600026
 2e26000091610008
-f821ff4148001145
+f821ff4148001151
 7cba2b787c7f1b78
 789cf0827cde3378
-81260004419200c0
+81260004419200e4
 2c09000082e60000
-3f02ffff40820044
-3b6000013ba00000
-3b187ee87bf90020
-4082009c7c3ce840
-7b8510283c62ffff
-7be4002038637ee8
-3c62ffff4bfffde5
-4bffda5d386379f8
-4bffdac160000000
+4bffdab1418200d8
 2d97000060000000
 3ba000007ffbfb78
 3b2000003ac00001
-7c3de0407bf50020
-408200847fb8eb78
+7c3ce8407bf50020
+408200c47fb8eb78
 418200282c170000
 7b0510283c62ffff
-7be4002038637ef8
-3c62ffff4bfffd8d
-4bffda05386379f8
+7be4002038637ee0
+3c62ffff4bfffdcd
+4bffd9f5386379d0
 382100c060000000
 816100087f2307b4
-480010c07d618120
-4bffff503ae00001
+4800110c7d618120
 7f44d3787b630020
-7ba917644bfffdb5
+7ba917644bfffdfd
 73a97fff7c7f492e
 408200147c7b1b78
 7f24cb787ba51028
-4bfffd317f03c378
-4bffff2c3bbd0001
+4bfffd797f03c378
+7c3ce8403bbd0001
+3c62ffff4082ffc8
+38637ed07b851028
+4bfffd597be40020
+386379d03c62ffff
+600000004bffd981
+3ae000014bffff34
+3ba000003f02ffff
+7bf900203b600001
+4bffffb83b187ed0
 7ac300207f44d378
 809b00004bfffd7d
 7c761b787c651b78
@@ -1755,30 +1780,30 @@ f821ff4148001145
 78840020e8de0010
 7b630020f8410018
 e84100184e800421
-4082ff582c030000
+4082ff182c030000
 4082001c73187fff
 3c62ffff418e0018
 7ea4ab787ba51028
-4bfffcb138637ef8
+4bfffcb138637ee0
 3b7b00043bbd0001
-000000004bfffef4
+000000004bfffeb4
 00000b8003000000
-384296d83c4c0001
+384297103c4c0001
 7c0802a67d708026
-48000f9d91610008
+48000fa991610008
 7cdb3378f821ff71
 2e3b00003ba4ffe0
 7c9e23787c7f1b78
 7c641b787fa3ea14
-38637f083c62ffff
-4bffd8d57cbc2b78
+38637ef03c62ffff
+4bffd8857cbc2b78
 3c62ffff60000000
-4092000c38637f20
-38637f303c62ffff
-600000004bffd8b9
+4092000c38637f08
+38637f183c62ffff
+600000004bffd869
 4bfffb597fc3f378
-38637f403c62ffff
-600000004bffd8a1
+38637f283c62ffff
+600000004bffd851
 408200a82c3c0000
 38df00207cf602a6
 7c26284038bd0020
@@ -1793,14 +1818,14 @@ f90a0010f90a0008
 78ea00203f8005f5
 79290020639ce100
 7d2950507f9ee1d2
-38637f483c62ffff
-4bffd81d7f9c4b92
+38637f303c62ffff
+4bffd7cd7f9c4b92
 7f83e37860000000
 3c62ffff4bfffabd
-4bffd80538637f58
+4bffd7b538637f40
 3c62ffff60000000
-4bffd7f5386379f8
-4bffd85960000000
+4bffd7a5386379d0
+4bffd80960000000
 7f9602a660000000
 7d3fe85040920048
 3bbd0020395f0020
@@ -1818,15 +1843,15 @@ e95f0010e95f0008
 614ae1007b9c0020
 7fde51d279290020
 3c62ffff7d29e050
-7fde4b9238637f60
-600000004bffd759
+7fde4b9238637f48
+600000004bffd709
 4bfff9f97fc3f378
-38637f583c62ffff
-600000004bffd741
-386379f83c62ffff
-600000004bffd731
+38637f403c62ffff
+600000004bffd6f1
+386379d03c62ffff
+600000004bffd6e1
 8161000838210090
-48000e047d708120
+48000e107d708120
 794300207fa407b4
 3bbd00014bfffaed
 7c6a1b787d23db96
@@ -1834,17 +1859,17 @@ e95f0010e95f0008
 7d3f482a79291f48
 000000004bffff68
 0000068003000000
-384294a03c4c0001
+384294d83c4c0001
 282402007c0802a6
-f821ff8148000d71
+f821ff8148000d7d
 7c9f23787c7e1b78
 418100083b800200
 3c62ffff7c9c2378
-38637f707fc4f378
-600000004bffd6a9
+38637f587fc4f378
+600000004bffd659
 4bfff9497fe3fb78
-38637f403c62ffff
-600000004bffd691
+38637f283c62ffff
+600000004bffd641
 7fc3f3787f84e378
 38c000004bfffaa1
 7fe4fb7838a00001
@@ -1853,55 +1878,55 @@ f821ff8148000d71
 2c0900007c7e1b78
 3c62ffff41820080
 7fa4eb787b85f882
-4bffd64538637f80
+4bffd5f538637f68
 283f800060000000
 4081000c7fe5fb78
 54a5042038a0ffff
 78a5f0823c62ffff
-38637f9838800000
-600000004bffd619
+38637f8038800000
+600000004bffd5c9
 7be5f0823c62ffff
-38637fb07fc4f378
-600000004bffd601
-38637fc83c62ffff
-600000004bffd5f1
+38637f987fc4f378
+600000004bffd5b1
+38637fb03c62ffff
+600000004bffd5a1
 3821008038600000
-48000ccc786307e0
-38637fd83c62ffff
-600000004bffd5d1
+48000cd8786307e0
+38637fc03c62ffff
+600000004bffd581
 4bffffe038600001
 0100000000000000
 3c4c000100000480
-6000000038429374
-6000000089228138
-2c09000039428130
+60000000384293ac
+6000000089228128
+2c09000039428120
 e92a000041820030
 7c0004ac39290014
 712900207d204eaa
 600000004182ffec
-7c0004ace9228130
+7c0004ace9228120
 4e8000207c604faa
 39290010e92a0000
 7d204eea7c0004ac
 4082ffec71290008
 600000005469063e
-7c0004ace9428130
+7c0004ace9428120
 4e8000207d2057ea
 0000000000000000
 3c4c000100000000
-7c0802a6384292ec
+7c0802a638429324
 fbc1fff0fbe1fff8
 f80100103be3ffff
 8fdf0001f821ffd1
 408200102c1e0000
 3860000038210030
-2c1e000a48000c04
+2c1e000a48000c10
 3860000d4082000c
-57c3063e4bffff3d
+7bc300204bffff3d
 4bffffd04bffff35
 0100000000000000
 3c4c000100000280
-394000203842928c
+39400020384292c4
 7c0004ac654ac000
 392000087d4056ea
 6529c000794a0600
@@ -1911,377 +1936,379 @@ f80100103be3ffff
 7d204eea7c0004ac
 390020007929f804
 6508c00079290fc3
-f902813060000000
+f902812060000000
 610820003d00001c
 418200807d4a4392
 3920000160000000
-3900200c99228138
+3900200c99228128
 6508c0003920ff80
 7d2047aa7c0004ac
-7c0004ace9228130
-e92281307d404faa
+7c0004ace9228120
+e92281207d404faa
 39290004794ac202
 7d404faa7c0004ac
-39400003e9228130
+39400003e9228120
 7c0004ac3929000c
-e92281307d404faa
+e92281207d404faa
 7c0004ac39290010
-e92281307d404faa
+e92281207d404faa
 3929000839400007
 7d404faa7c0004ac
 600000004e800020
-99228138394affff
+99228128394affff
 6529c00039202018
 7d404fea7c0004ac
 000000004e800020
 0000000000000000
 3940000078a9e8c2
 7d2903a639290001
-78a9072442000028
-3905000178a50760
-7d0903a67d434a14
-392000007c844a14
-4e80002042000018
-7d23512a7d24502a
-4bffffcc394a0008
-7d0a49ae7d0448ae
-4bffffdc39290001
-0000000000000000
-7c691b7800000000
-7d4918ae38600000
-4d8200202c0a0000
-4bfffff038630001
-0000000000000000
-2c24000000000000
+78a9e8c24200002c
+1d29fff839400000
+7c8920507ca54a14
+7d29185039050001
+420000187d0903a6
+7d24502a4e800020
+394a00087d23512a
+7d0450ae4bffffc8
+394a00017d0951ae
+000000004bffffdc
+0000000000000000
+386000007c691b78
+2c0a00007d4918ae
+386300014d820020
+000000004bfffff0
+0000000000000000
+7c691b782c240000
 3881fff040820008
-f864000028050024
+f924000028050024
 4d81002038600000
-792983e43d200001
-e9240000612a2600
-2808002089090000
-7d47443641810040
-4082002870e70001
-418200e02c250000
-408200102c050010
-418200482c080030
-3860000038a00010
-3929000148000080
-4bffffb8f9240000
-4082ffd42c250000
-38a0000a2c080030
-894900014082ffdc
-4082ffd02c0a0078
-f924000039290002
-894900014bffffc0
-4082ffb42c0a0078
-38eaffd04bffffe8
+794a83e43d400001
+89090000614a2600
+4181003828080020
+70e700017d474436
+2c25000040820020
+2c050010418200d0
+3929ffff41820028
+4800007838600000
+f924000039290001
+2c2500004bffffc4
+38a0000a4082ffdc
+4082ffd82c080030
+2c0a007889490001
+392900024082ffcc
+f924000038a00010
+38e8ffd04bffffbc
 2807000954e7063e
-3929ffd04181003c
-7c0a28007d2a0734
-390800014c800020
-7d2907347c6519d2
-7c691a14f9040000
-89480000e9040000
-4082ffc0714900ff
-38eaff9f4e800020
-2807001954e7063e
-3929ffa94181000c
-394affbf4bffffb8
-280a0019554a063e
-3929ffc94d810020
-38a0000a4bffffa0
-000000004bffff34
-0000000000000000
-280900193923ff9f
-3863ffe041810008
-4e8000207c6307b4
+394affd041810040
+7c0828007d480734
+7c6519d24c800020
+7d4a073439290002
+7cc93378f9240000
+890900017c6a1a14
+710a00ff38c90001
+4e8000204082ffbc
+54e7063e38e8ff9f
+4181000c28070019
+4bffffb4394affa9
+5508063e3908ffbf
+4d81002028080019
+4bffff9c394affc9
+4bffff3838a0000a
+0000000000000000
+3923ff9f00000000
+4181000828090019
+7c6307b43863ffe0
+000000004e800020
 0000000000000000
-3c4c000100000000
-7c0802a638428f8c
-f821ffa148000855
-7cfd3b787c7e1b78
-7c9c23787ca32b78
-3880000038a0000a
-7cdf3378eb3e0000
-7d3a4b787d1b4378
-600000004bfffe65
-394000002b9d0010
-4082005c2c3f0000
-408200082c0a0000
-7d4ad21439400001
-4081003c7c035000
-7d2948f87d235050
-3929000179290020
-e93e00007d2903a6
-7c2ae0407d594850
-9b69000040800018
-39290001e93e0000
-4200ffe0f93e0000
-4800080838210060
-7bffe102409e0010
-4bffff94394a0001
-4bfffff47fffeb92
+38428fd03c4c0001
+4800086d7c0802a6
+7c7e1b78f821ffa1
+7ca32b787cfd3b78
+38a0000a7c9c2378
+eb3e000038800000
+7d1b43787cdf3378
+4bfffe757d3a4b78
+2b9d001060000000
+2c3f000039400000
+2c0a00004082005c
+3940000141810008
+7c0350007d4ad214
+7d4a18504081003c
+794a0020394affff
+7d2903a6392a0001
+7d594850e93e0000
+408000187c2ae040
+e93e00009b690000
+f93e000039290001
+382100604200ffe0
+409e001048000820
+394a00017bffe102
+7fffeb924bffff94
+000000004bfffff4
+0000078001000000
+38428f003c4c0001
+480007a57c0802a6
+eb630000f821ffb1
+7c9c23787c7f1b78
+3bc000007cbd2b78
+4bfffd8d7fa3eb78
+7c3e184060000000
+e93f000040800014
+7c2ae0407d5b4850
+382100504180000c
+7d5df0ae480007b0
+994900003bde0001
+39290001e93f0000
+4bffffbcf93f0000
 0100000000000000
-3c4c000100000780
-7c0802a638428ebc
-f821ffb14800078d
-7c7f1b78eb630000
-7cbd2b787c9c2378
-7fa3eb783bc00000
-600000004bfffd7d
-408000147c3e1840
-7d5b4850e93f0000
-4180000c7c2ae040
-4800079838210050
-3bde00017d5df0ae
-e93f000099490000
-f93f000039290001
-000000004bffffbc
-0000058001000000
-38428e403c4c0001
-3d22ffff7c0802a6
-2b860010e9297fe8
-7caa2b787d708026
-480006f591610008
+3c4c000100000580
+7c0802a638428e84
+e9297fd03d22ffff
+7d7080262b860010
+4800071191610008
 7c7c1b78f821ffa1
 7cdd33787cbe2b78
 f92100203be00000
-e9297ff03d22ffff
-2c2a0000f9210028
-2c1f000040820034
-3be0000140820008
-2e2700007fff07b4
-3b7fffff7c3f2040
-3821006040810030
-7d70812081610008
-409e0010480006e8
-3bff0001794ae102
-7d4aeb924bffffbc
-7f5ed3784bfffff4
-7d3ae9d27f5eeb92
-7d214a147d29f050
-4192001088690020
-4bfffdd55463063e
-7c3df04060000000
-7c69d9aee93c0000
-4081ffc83b7bffff
-7d29fa14e93c0000
-4bffff90f93c0000
-0300000000000000
-3c4c000100000680
-7c0802a638428d4c
-f821fef1480005e9
-f86100607c761b79
-4182003c38600000
-418200342c240000
-3aa100403b04ffff
-892500003a800000
-712a00ffebc10060
-4182000c7c76f050
-418000187c23c040
-993e000039200000
-7c6307b438210110
-2c0a0025480005e0
-4082056439050001
-8945000039200000
-8ce500017cb32b78
-54ea063e7d49a9ae
-41810024280a0078
-41810024280a0062
-418200a02c0a004f
-418200982c0a0058
-418200902c0a0025
-4bffffc039290001
-5504063e3907ff9d
-4181ffec28040015
-3884739c3c82ffff
-7d0442aa790815a8
-7d0903a67d082214
-000000584e800420
-ffffffcc00000058
-ffffffccffffffcc
-00000058ffffffcc
-ffffffccffffffcc
-ffffffccffffffcc
-00000058ffffffcc
-ffffffcc00000058
-00000058ffffffcc
-00000058ffffffcc
-ffffffccffffffcc
-3909000100000058
-392900022c0a0025
-7d0807b438a10020
-7d0542147d2907b4
-98e800207d254a14
-408200189a890020
-995e0000393e0001
-38b30002f9210060
-892100414bfffebc
-7fe3c050eb860000
-3a4000303a260008
+e9297fd83d22ffff
+7ca92b78f9210028
+408200342c290000
+418100082c1f0000
+7fff07b43be00001
+7c3f20402e270000
+408100303b7fffff
+8161000838210060
+480007007d708120
+7929e102409e0010
+4bffffbc3bff0001
+4bfffff47d29eb92
+7f5eeb927f5ed378
+7d29f0507d3ae9d2
+886900207d214a14
+5463063e41920010
+600000004bfffdd5
+e93c00007c3df040
+3b7bffff7c69d9ae
+e93c00004081ffc8
+f93c00007d29fa14
+000000004bffff90
+0000068003000000
+38428d903c4c0001
+480006017c0802a6
+7c751b79f821fef1
+38600000f8610060
+2c24000041820044
+7cbd2b784182003c
+3a6100403ae4ffff
+3a4000003b210020
+ebc10060895d0000
+7c75f050714900ff
+7c23b8404182000c
+3920000041800018
+38210110993e0000
+480005f07c6307b4
+391d00012c090025
+3920000040820574
+895d00017d4999ae
+5548063e389d0001
+4181002428080078
+4181002828080062
+418200a42c08004f
+4182009c2c080058
+418200942c080025
+7c9d237839290001
+38eaff9d4bffffc0
+2805001554e5063e
+3ca2ffff4181ffe8
+78e715a838a57360
+7ce72a147ce53aaa
+4e8004207ce903a6
+0000005800000058
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+ffffffc800000058
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+0000005800000058
+ffffffc8ffffffc8
+ffffffc800000058
+ffffffc800000058
+00000058ffffffc8
+2c08002538e90001
+7ce707b439290002
+7cf93a147d2907b4
+994700207d394a14
+408200189a490020
+f9210060393e0001
+3bbd0002995e0000
+892100414bfffec0
+7fe3b850eb860000
+3a8000303a260008
 3929ffd23b410042
-40820428712900fd
-600000005649063e
-3b2000043ae00000
+4082043c712900fd
+3de2ffff5689063e
+3b0000043ac00000
 3b600000f9210068
-39e280083a000000
-2c07004f48000170
-418201dc38da0001
-5505063e390affa8
-418103bc28050022
-38a574b43ca2ffff
-7d0542aa790815a8
-7d0903a67d082a14
-000001584e800420
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000008c00000268
-0000039c0000039c
-000003800000039c
-0000039c0000008c
-000003680000039c
-0000039c0000039c
-00000204000001ac
-0000039c0000039c
-0000039c000002ac
-0000039c0000008c
-0000015c0000039c
-000003c00000039c
-7b6a00202c070075
+39ef7ff83a000000
+2c06004f4800016c
+418201e038ba0001
+54e4063e38e8ffa8
+418103d028040022
+388474743c82ffff
+7ce43aaa78e715a8
+7ce903a67ce72214
+000001544e800420
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+0000008c00000270
+000003b0000003b0
+00000394000003b0
+000003b00000008c
+0000037c000003b0
+000003b0000003b0
+0000020c000001b0
+000003b0000003b0
+000003b0000002b4
+000003b00000008c
+00000158000003b0
+000003d4000003b0
+7b6a00202c060075
 390000007d415214
-990a00207f9de378
-5728183841820044
-3908ffff39400001
-7f8a50397d4a4036
+990a00207f8ee378
+5707183841820044
+38e7ffff39000001
+7f8840397d083836
 3940002d4182002c
-7fbc00d039290001
-600000009949ffff
-7b291e68f9210060
-7d2a482a39428008
-e88100607fbd4838
-7fa6eb7838e0000a
-3920000038a10020
-386100605648063e
+3ce2ffff39290001
+38e77ff87b081e68
+f92100609949ffff
+7d07402a7d5c00d0
+7c9e48507d4e4038
+7dc6737838e0000a
+7c84f8507f25cb78
+5688063e39200000
+4bfffabd38610060
+7ac707e0e8810060
+7dc5737838c0000a
 7c84f8507c9e2050
-e88100604bfffabd
-38c0000a7ae707e0
-7c9e20507fa5eb78
-386100607c84f850
-3b5a00014bfffbe9
-e9210060895a0000
-41820010714700ff
-7c3fe8407fbe4850
-7e268b784181fe7c
-3ae000014bfffe24
-e90100687b690020
-7d214a1438e00010
-38a100207c9df850
-9a09002038610060
-7d4f482a7b291e68
-7f8e503839200000
-4bfffa397dc67378
-7ae707e0e8810060
+4bfffbe938610060
+891a00003b5a0001
+710600ffe9210060
+7dde485041820010
+4181fe807c3f7040
+4bfffe287e268b78
+7b6900203ac00001
+38e00010e9010068
+7c8ef8507d214a14
+386100607f25cb78
+7b091e689a090020
+392000007d6f482a
+7d665b787f8b5838
+4bfffa35f9610070
+7ac707e0e8810060
 7c9e205038c00010
-4bffff7c7dc57378
-394000007b690020
-38e000087d214a14
-5648063e7c9df850
-6000000099490020
-394280087b291e68
-3861006038a10020
-392000007d4a482a
-7dc673787f8e5038
-e88100604bfff9dd
-38c000087ae707e0
-4bffffa47c9e2050
-394000007b690020
+7d655b78e9610070
+7b6900204bffff74
+7d214a1439000000
+7c8ef85038e00008
+990900207f25cb78
+7b091e683d02ffff
+3861006039087ff8
+392000007d68482a
+7f8b58385688063e
+f96100707d665b78
+e88100604bfff9d1
+38c000087ac707e0
+4bffff9c7c9e2050
+390000007b690020
 38e000107d214a14
-390000207f86e378
-38a1002099490020
-7c9df85039200002
-4bfff99938610060
-60000000e8810060
-38a2800038610060
+7f25cb787f86e378
+7c8ef85099090020
+3900002039200002
+4bfff98d38610060
+3ca2ffffe8810060
+38a57fe838610060
 7c84f8507c9e2050
-e88100604bfffa4d
-38c000107ae707e0
+e88100604bfffa41
+38c000107ac707e0
 7c9e20507f85e378
-7b6900204bfffec0
-7d214a1439400000
-38e0000a39000020
-9949002038c00001
-3920000038a10020
-386100607c9df850
-e92100604bfff935
+7b6900204bfffeb4
+7d214a1439000000
+38c0000138e0000a
+990900207f25cb78
+392000007c8ef850
+3861006039000020
+e92100604bfff929
 392900019b890000
-4bfffe88f9210060
-390000007b6a0020
-7d415214f9210070
+4bfffe7cf9210060
+38e000007b680020
+7d014214f9210078
 3880000038a0000a
-990a002038610020
-600000004bfff795
-7f83e3787c6e1b78
-600000004bfff75d
-408100487c2e1840
-7fbdf850e9210070
-394000007c637050
-3bbd000138e00020
-7c691a147d09f050
-2c2800007d08fa14
-3ba0000140820008
-3bbdffff2c3d0001
-714a000140820028
-e881006040820034
-386100607f85e378
-7c84f8507c9e2050
-4bfffde84bfff955
-3929000198e90000
-7c29184039400001
-f92100604082ffc0
-893a00014bffffcc
-2c09006c3b200008
-7cda33784082fdbc
-893a00014bfffdb4
-2c0900683b200002
-7cda33784082fda4
-4bfffd983b200001
-5529063e392affd0
-4181fd8828090009
-3b7b00017b690020
-994900207d214a14
-3b2000084bfffd74
-3a4000204bfffd6c
-4bfffbd43b410041
-3bde0001993e0000
-fbc100607d054378
-000000004bfffa54
-0000128001000000
-f9e1ff78f9c1ff70
-fa21ff88fa01ff80
-fa61ff98fa41ff90
-faa1ffa8fa81ffa0
-fae1ffb8fac1ffb0
-fb21ffc8fb01ffc0
-fb61ffd8fb41ffd0
-fba1ffe8fb81ffe0
-fbe1fff8fbc1fff0
-4e800020f8010010
-e9e1ff78e9c1ff70
-ea21ff88ea01ff80
-ea61ff98ea41ff90
-eaa1ffa8ea81ffa0
-eae1ffb8eac1ffb0
-eb21ffc8eb01ffc0
-eb61ffd8eb41ffd0
-e8010010eb81ffe0
-7c0803a6eba1ffe8
-ebe1fff8ebc1fff0
-ebc1fff04e800020
-ebe1fff8e8010010
-4e8000207c0803a6
+98e800207f23cb78
+600000004bfff799
+7f83e378f8610070
+600000004bfff761
+e9210078e9010070
+418100207c281840
+7c9e20507d244b78
+7c84f8507f85e378
+4bfff98538610060
+7ce9f0504bfffe18
+7ce7fa147c634050
+2c2700007d4ef850
+7d244b787c691a14
+38c0002039000000
+40820008394a0001
+2c2a000139400001
+40820010394affff
+4082001c71080001
+98c400004bffffa0
+3900000138840001
+4082ffd87c241840
+4bffff88f8810060
+3b000008893a0001
+4082fda42c09006c
+4bfffd9c7cba2b78
+3b000002893a0001
+4082fd8c2c090068
+3b0000017cba2b78
+3928ffd04bfffd80
+280900095529063e
+7b6900204181fd70
+7d214a143b7b0001
+4bfffd5c99090020
+4bfffd543b000008
+3b4100413a800020
+995e00004bfffbc0
+7d1d43783bde0001
+4bfffa44fbc10060
+0100000000000000
+f9c1ff7000001280
+fa01ff80f9e1ff78
+fa41ff90fa21ff88
+fa81ffa0fa61ff98
+fac1ffb0faa1ffa8
+fb01ffc0fae1ffb8
+fb41ffd0fb21ffc8
+fb81ffe0fb61ffd8
+fbc1fff0fba1ffe8
+f8010010fbe1fff8
+e9c1ff704e800020
+ea01ff80e9e1ff78
+ea41ff90ea21ff88
+ea81ffa0ea61ff98
+eac1ffb0eaa1ffa8
+eb01ffc0eae1ffb8
+eb41ffd0eb21ffc8
+eb81ffe0eb61ffd8
+eba1ffe8e8010010
+ebc1fff07c0803a6
+4e800020ebe1fff8
+e8010010ebc1fff0
+7c0803a6ebe1fff8
+600000004e800020
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -2326,14 +2353,18 @@ ebe1fff8e8010010
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -2419,7 +2450,7 @@ ebe1fff8e8010010
 0000000a3a6e6163
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 656c206574697257
 0a3a676e696c6576
 0000000000000000
@@ -2438,8 +2469,6 @@ ebe1fff8e8010010
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 676e697465736552
 6c65642074614420
 6f6d20666f207961
@@ -2490,11 +2519,12 @@ ebe1fff8e8010010
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v
index b6d2e37..fd058f4 100644
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:08
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:43
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -80,18 +80,18 @@ LiteDRAMCore
 └─── crg (LiteDRAMS7DDRPHYCRG)
 │    └─── pll (S7PLL)
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [PLLE2_ADV]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
 │    └─── idelayctrl (S7IDELAYCTRL)
 │    │    └─── [IDELAYCTRL]
 └─── ddrphy (K7DDRPHY)
@@ -172,239 +172,239 @@ LiteDRAMCore
 │    └─── bitslip_71* (BitSlip)
 │    └─── tappeddelayline_2* (TappedDelayLine)
 │    └─── tappeddelayline_3* (TappedDelayLine)
-│    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [ODELAYE2]
 │    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [OSERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [ODELAYE2]
+│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [IOBUFDS]
-│    └─── [IDELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [IOBUF]
-│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
 │    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [OSERDESE2]
-│    └─── [IOBUF]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [IOBUFDS]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
-│    └─── [ODELAYE2]
 │    └─── [ISERDESE2]
-│    └─── [OBUFDS]
-│    └─── [ODELAYE2]
 │    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [IOBUF]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [ODELAYE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUFDS]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [ODELAYE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
 │    └─── [ODELAYE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
 │    └─── [ODELAYE2]
-│    └─── [IOBUF]
+│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [ODELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
 │    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUFDS]
+│    └─── [ODELAYE2]
+│    └─── [OBUFDS]
+│    └─── [ODELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
 │    │    └─── pi0 (PhaseInjector)
@@ -748,6 +748,7 @@ wire   [29:0] builder_interface0_adr;
 wire   [13:0] builder_interface0_bank_bus_adr;
 reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_re;
 wire          builder_interface0_bank_bus_we;
 wire    [1:0] builder_interface0_bte;
 wire    [2:0] builder_interface0_cti;
@@ -764,17 +765,22 @@ reg           builder_interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] builder_interface1_bank_bus_adr;
 reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_re;
 wire          builder_interface1_bank_bus_we;
 wire   [31:0] builder_interface1_dat_r;
 reg    [31:0] builder_interface1_dat_w = 32'd0;
 reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
 reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_re = 1'd0;
+reg           builder_interface1_re_next_value2 = 1'd0;
+reg           builder_interface1_re_next_value_ce2 = 1'd0;
 reg           builder_interface1_we = 1'd0;
-reg           builder_interface1_we_next_value2 = 1'd0;
-reg           builder_interface1_we_next_value_ce2 = 1'd0;
+reg           builder_interface1_we_next_value3 = 1'd0;
+reg           builder_interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] builder_interface2_bank_bus_adr;
 reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_re;
 wire          builder_interface2_bank_bus_we;
 reg           builder_locked0 = 1'd0;
 reg           builder_locked1 = 1'd0;
@@ -799,6 +805,7 @@ reg           builder_new_master_wdata_ready0 = 1'd0;
 reg           builder_new_master_wdata_ready1 = 1'd0;
 reg     [1:0] builder_next_state = 2'd0;
 wire          builder_pll_fb;
+wire          builder_re;
 reg     [1:0] builder_refresher_next_state = 2'd0;
 reg     [1:0] builder_refresher_state = 2'd0;
 wire          builder_reset0;
@@ -905,14 +912,14 @@ reg           builder_t_self3 = 1'd0;
 reg           builder_t_self4 = 1'd0;
 reg           builder_t_self5 = 1'd0;
 wire          builder_we;
-wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0;
 wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1;
 wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2;
 wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3;
 wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
@@ -2383,9 +2390,9 @@ reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p0_address;
 wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
 reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_cke;
 reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_odt;
 reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [63:0] main_litedramcore_csr_dfi_p0_rddata = 64'd0;
 wire          main_litedramcore_csr_dfi_p0_rddata_en;
@@ -2399,9 +2406,9 @@ reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p1_address;
 wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
 reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_cke;
 reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_odt;
 reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [63:0] main_litedramcore_csr_dfi_p1_rddata = 64'd0;
 wire          main_litedramcore_csr_dfi_p1_rddata_en;
@@ -2415,9 +2422,9 @@ reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p2_address;
 wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
 reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_cke;
 reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_odt;
 reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
 reg    [63:0] main_litedramcore_csr_dfi_p2_rddata = 64'd0;
 wire          main_litedramcore_csr_dfi_p2_rddata_en;
@@ -2431,9 +2438,9 @@ reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p3_address;
 wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
 reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_cke;
 reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_odt;
 reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
 reg    [63:0] main_litedramcore_csr_dfi_p3_rddata = 64'd0;
 wire          main_litedramcore_csr_dfi_p3_rddata_en;
@@ -6423,42 +6430,26 @@ always @(*) begin
         main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
-end
+assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt;
 assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
+    end else begin
+        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
     if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -6491,20 +6482,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (main_litedramcore_phaseinjector0_command_issue_re) begin
-        main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas);
-    end else begin
-        main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
 assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
 assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
+    end else begin
+        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
     if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -6537,14 +6528,6 @@ always @(*) begin
         main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (main_litedramcore_phaseinjector1_command_issue_re) begin
-        main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas);
-    end else begin
-        main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
@@ -6552,10 +6535,18 @@ assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector
 assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
-            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
+        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
+    end else begin
+        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin
+            main_litedramcore_csr_dfi_p2_cs_n <= 2'd2;
         end else begin
             if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin
                 main_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
@@ -6583,20 +6574,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas);
-    end else begin
-        main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
 assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
 assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
+    end else begin
+        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
     if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -6629,14 +6620,6 @@ always @(*) begin
         main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (main_litedramcore_phaseinjector3_command_issue_re) begin
-        main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas);
-    end else begin
-        main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
 assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
@@ -6744,22 +6727,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_sequencer_start0 <= 1'd0;
-    case (builder_refresher_state)
-        1'd1: begin
-            if (main_litedramcore_cmd_ready) begin
-                main_litedramcore_sequencer_start0 <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_cmd_valid <= 1'd0;
     case (builder_refresher_state)
@@ -6826,6 +6793,22 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_sequencer_start0 <= 1'd0;
+    case (builder_refresher_state)
+        1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid;
 assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready;
 assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we;
@@ -6965,74 +6948,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine0_trccon_ready) begin
-                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine0_source_source_valid) begin
-                    if (main_litedramcore_bankmachine0_row_opened) begin
-                        if (main_litedramcore_bankmachine0_row_hit) begin
-                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine0_state)
@@ -7397,6 +7312,74 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
 assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
@@ -7537,7 +7520,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
     case (builder_bankmachine1_state)
         1'd1: begin
         end
@@ -7546,6 +7529,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -7556,37 +7542,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine1_source_source_valid) begin
-                    if (main_litedramcore_bankmachine1_row_opened) begin
-                        if (main_litedramcore_bankmachine1_row_hit) begin
-                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
     case (builder_bankmachine1_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -7667,32 +7638,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine1_row_open <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine1_trccon_ready) begin
-                main_litedramcore_bankmachine1_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine1_state)
@@ -7968,6 +7913,44 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            if (main_litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
 assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
@@ -8107,32 +8090,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine2_row_close <= 1'd0;
-    case (builder_bankmachine2_state)
-        1'd1: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine2_state)
@@ -8294,6 +8251,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine2_state)
@@ -8447,18 +8430,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -8473,15 +8456,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_open <= 1'd1;
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -8495,25 +8481,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8524,18 +8519,6 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine2_source_source_valid) begin
-                    if (main_litedramcore_bankmachine2_row_opened) begin
-                        if (main_litedramcore_bankmachine2_row_hit) begin
-                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
@@ -8665,48 +8648,13 @@ always @(*) begin
                     if (main_litedramcore_bankmachine3_row_opened) begin
                         if (main_litedramcore_bankmachine3_row_hit) begin
                             if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-                                builder_bankmachine3_next_state <= 2'd2;
-                            end
-                        end else begin
-                            builder_bankmachine3_next_state <= 1'd1;
-                        end
-                    end else begin
-                        builder_bankmachine3_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine3_source_source_valid) begin
-                    if (main_litedramcore_bankmachine3_row_opened) begin
-                        if (main_litedramcore_bankmachine3_row_hit) begin
-                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                                builder_bankmachine3_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
                     end
                 end
             end
@@ -9110,6 +9058,41 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
 assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
@@ -9249,74 +9232,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine4_trccon_ready) begin
-                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine4_source_source_valid) begin
-                    if (main_litedramcore_bankmachine4_row_opened) begin
-                        if (main_litedramcore_bankmachine4_row_hit) begin
-                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine4_state)
@@ -9681,6 +9596,74 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine4_trccon_ready) begin
+                main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
 assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
@@ -9821,7 +9804,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
     case (builder_bankmachine5_state)
         1'd1: begin
         end
@@ -9830,6 +9813,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9840,37 +9826,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine5_source_source_valid) begin
-                    if (main_litedramcore_bankmachine5_row_opened) begin
-                        if (main_litedramcore_bankmachine5_row_hit) begin
-                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
     case (builder_bankmachine5_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -9951,32 +9922,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine5_row_open <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine5_state)
@@ -10119,12 +10064,35 @@ always @(*) begin
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-            end
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
         end
         3'd4: begin
-            main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -10135,11 +10103,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine5_state)
         1'd1: begin
         end
@@ -10164,8 +10147,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine5_row_opened) begin
                         if (main_litedramcore_bankmachine5_row_hit) begin
                             if (main_litedramcore_bankmachine5_source_source_payload_we) begin
+                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                             end else begin
-                                main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -10177,7 +10160,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
     case (builder_bankmachine5_state)
         1'd1: begin
         end
@@ -10202,7 +10185,7 @@ always @(*) begin
                     if (main_litedramcore_bankmachine5_row_opened) begin
                         if (main_litedramcore_bankmachine5_row_hit) begin
                             if (main_litedramcore_bankmachine5_source_source_payload_we) begin
-                                main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
                             end else begin
                             end
                         end else begin
@@ -10215,7 +10198,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
     case (builder_bankmachine5_state)
         1'd1: begin
         end
@@ -10240,8 +10223,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine5_row_opened) begin
                         if (main_litedramcore_bankmachine5_row_hit) begin
                             if (main_litedramcore_bankmachine5_source_source_payload_we) begin
-                                main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
                             end else begin
+                                main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
                             end
                         end else begin
                         end
@@ -10391,32 +10374,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine6_row_close <= 1'd0;
-    case (builder_bankmachine6_state)
-        1'd1: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine6_state)
@@ -10757,15 +10714,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_open <= 1'd1;
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
             end
         end
         3'd4: begin
@@ -10779,22 +10739,57 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
             end
         end
         3'd4: begin
@@ -10808,18 +10803,6 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine6_source_source_valid) begin
-                    if (main_litedramcore_bankmachine6_row_opened) begin
-                        if (main_litedramcore_bankmachine6_row_hit) begin
-                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
@@ -10962,41 +10945,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (builder_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine7_state)
@@ -11394,6 +11342,41 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine7_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_nphases = (main_k7ddrphy_rdphase_storage - 1'd1);
 assign main_litedramcore_rdphase = (main_k7ddrphy_wrphase_storage - 1'd1);
 assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
@@ -11640,34 +11623,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_en1 <= 1'd0;
-    case (builder_multiplexer_state)
-        1'd1: begin
-            main_litedramcore_en1 <= 1'd1;
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        4'd9: begin
-        end
-        4'd10: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_steerer0 <= 2'd0;
     case (builder_multiplexer_state)
@@ -11987,6 +11942,34 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_en1 <= 1'd0;
+    case (builder_multiplexer_state)
+        1'd1: begin
+            main_litedramcore_en1 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     main_litedramcore_choose_req_want_writes <= 1'd0;
     case (builder_multiplexer_state)
@@ -12096,24 +12079,24 @@ assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant ==
 assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
 assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
 always @(*) begin
-    main_litedramcore_interface_wdata_we <= 32'd0;
+    main_litedramcore_interface_wdata <= 256'd0;
     case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
         end
         default: begin
-            main_litedramcore_interface_wdata_we <= 1'd0;
+            main_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_interface_wdata <= 256'd0;
+    main_litedramcore_interface_wdata_we <= 32'd0;
     case ({builder_new_master_wdata_ready1})
         1'd1: begin
-            main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+            main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
         end
         default: begin
-            main_litedramcore_interface_wdata <= 1'd0;
+            main_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
@@ -12144,97 +12127,112 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value2 <= 1'd0;
+    builder_interface0_ack <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
-            end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value_ce2 <= 1'd0;
+    builder_interface1_dat_w_next_value0 <= 32'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value_ce2 <= 1'd1;
-            end
+            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
         end
     endcase
 end
 always @(*) begin
-    builder_interface0_ack <= 1'd0;
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
     case (builder_state)
         1'd1: begin
         end
         2'd2: begin
-            builder_interface0_ack <= 1'd1;
         end
         default: begin
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_dat_w_next_value0 <= 32'd0;
+    builder_interface1_adr_next_value1 <= 14'd0;
     case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr;
+            end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
     case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_adr_next_value1 <= 14'd0;
+    builder_interface1_re_next_value2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_adr_next_value1 <= 1'd0;
+            builder_interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
+                builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    builder_interface1_re_next_value_ce2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_adr_next_value_ce1 <= 1'd1;
+            builder_interface1_re_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value_ce1 <= 1'd1;
+                builder_interface1_re_next_value_ce2 <= 1'd1;
+            end
+        end
+    endcase
+end
+always @(*) begin
+    builder_interface1_we_next_value3 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_we_next_value3 <= 1'd0;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
@@ -12251,6 +12249,21 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    builder_interface1_we_next_value_ce3 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_we_next_value_ce3 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce3 <= 1'd1;
+            end
+        end
+    endcase
+end
 assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
@@ -12262,20 +12275,20 @@ end
 always @(*) begin
     builder_csrbank0_init_done0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re;
     end
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_error0_re <= 1'd0;
+    builder_csrbank0_init_error0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_error0_we <= 1'd0;
+    builder_csrbank0_init_error0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
@@ -12283,48 +12296,48 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage;
 assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_rst0_re <= 1'd0;
+    builder_csrbank1_rst0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_rst0_we <= 1'd0;
+    builder_csrbank1_rst0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0];
 always @(*) begin
-    builder_csrbank1_dly_sel0_we <= 1'd0;
+    builder_csrbank1_dly_sel0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_dly_sel0_re <= 1'd0;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     builder_csrbank1_wlevel_en0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12335,22 +12348,22 @@ always @(*) begin
 end
 assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_wlevel_strobe_re <= 1'd0;
+    main_k7ddrphy_wlevel_strobe_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_k7ddrphy_wlevel_strobe_we <= 1'd0;
+    main_k7ddrphy_wlevel_strobe_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     main_k7ddrphy_cdly_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_cdly_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12361,41 +12374,41 @@ always @(*) begin
 end
 assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_cdly_inc_we <= 1'd0;
+    main_k7ddrphy_cdly_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_k7ddrphy_cdly_inc_re <= 1'd0;
+    main_k7ddrphy_cdly_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_cdly_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
+    main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
+    main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_rdly_dq_inc_we <= 1'd0;
+    main_k7ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_k7ddrphy_rdly_dq_inc_re <= 1'd0;
+    main_k7ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
@@ -12408,53 +12421,53 @@ end
 always @(*) begin
     main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
+    main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_wdly_dq_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
+    main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_wdly_dq_inc_re <= 1'd0;
+    main_k7ddrphy_wdly_dq_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_wdly_dq_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_k7ddrphy_wdly_dq_inc_we <= 1'd0;
+    main_k7ddrphy_wdly_dq_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     main_k7ddrphy_wdly_dqs_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wdly_dqs_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12465,75 +12478,75 @@ always @(*) begin
 end
 assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_wdly_dqs_inc_we <= 1'd0;
+    main_k7ddrphy_wdly_dqs_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
-        main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_k7ddrphy_wdly_dqs_inc_re <= 1'd0;
+    main_k7ddrphy_wdly_dqs_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin
-        main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_wdly_dqs_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
-        main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
-        main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
-        main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin
-        main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_k7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_rdphase0_we <= 1'd0;
+    builder_csrbank1_rdphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_rdphase0_re <= 1'd0;
+    builder_csrbank1_rdphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_wrphase0_re <= 1'd0;
+    builder_csrbank1_wrphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_wrphase0_we <= 1'd0;
+    builder_csrbank1_wrphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage;
-assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0];
-assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage;
+assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage;
 assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage;
+assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage;
 assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
@@ -12545,14 +12558,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_control0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12563,48 +12576,48 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+    builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+    builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_wrdata1_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12613,7 +12626,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
@@ -12623,27 +12636,27 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+    builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi0_rddata1_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+    builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_rddata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12654,48 +12667,48 @@ always @(*) begin
 end
 assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+    builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+    builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12704,7 +12717,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
@@ -12714,36 +12727,36 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_wrdata1_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+    builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+    builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi1_rddata1_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
@@ -12753,40 +12766,40 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_rddata0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+    builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
     end
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
     builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12805,36 +12818,36 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+    builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi2_wrdata1_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+    builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+    builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
@@ -12844,27 +12857,27 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_rddata1_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+    builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi2_rddata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+    builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12877,7 +12890,7 @@ assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_ban
 always @(*) begin
     main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12896,36 +12909,36 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+    builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+    builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-        builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+    builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-        builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi3_wrdata1_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
@@ -12935,14 +12948,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
-        builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_rddata1_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -12951,24 +12964,24 @@ always @(*) begin
         builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
-    builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+    builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-        builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+    builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-        builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+        builder_csrbank2_dfii_pi3_rddata0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
 assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage;
 assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
 assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
 assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
@@ -12977,9 +12990,9 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
 assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
 assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage;
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage;
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage;
 assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32];
 assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
 assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32];
@@ -12993,9 +13006,9 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
 assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
 assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage;
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage;
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage;
 assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32];
 assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
 assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32];
@@ -13009,9 +13022,9 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
 assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
 assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage;
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage;
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage;
 assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32];
 assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
 assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32];
@@ -13025,21 +13038,25 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
 assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
 assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage;
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage;
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage;
 assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32];
 assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
 assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32];
 assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
 assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
 assign builder_adr = builder_interface1_adr;
+assign builder_re = builder_interface1_re;
 assign builder_we = builder_interface1_we;
 assign builder_dat_w = builder_interface1_dat_w;
 assign builder_interface1_dat_r = builder_dat_r;
 assign builder_interface0_bank_bus_adr = builder_adr;
 assign builder_interface1_bank_bus_adr = builder_adr;
 assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_re = builder_re;
+assign builder_interface1_bank_bus_re = builder_re;
+assign builder_interface2_bank_bus_re = builder_re;
 assign builder_interface0_bank_bus_we = builder_we;
 assign builder_interface1_bank_bus_we = builder_we;
 assign builder_interface2_bank_bus_we = builder_we;
@@ -13765,16 +13782,16 @@ always @(*) begin
     builder_self0 <= 3'd0;
     case (main_litedramcore_steerer0)
         1'd0: begin
-            builder_self0 <= main_litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -13884,16 +13901,16 @@ always @(*) begin
     builder_self7 <= 3'd0;
     case (main_litedramcore_steerer1)
         1'd0: begin
-            builder_self7 <= main_litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -14003,16 +14020,16 @@ always @(*) begin
     builder_self14 <= 3'd0;
     case (main_litedramcore_steerer2)
         1'd0: begin
-            builder_self14 <= main_litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -14122,16 +14139,16 @@ always @(*) begin
     builder_self21 <= 3'd0;
     case (main_litedramcore_steerer3)
         1'd0: begin
-            builder_self21 <= main_litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -14237,10 +14254,10 @@ always @(*) begin
         end
     endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -16090,8 +16107,11 @@ always @(posedge sys_clk) begin
     if (builder_interface1_adr_next_value_ce1) begin
         builder_interface1_adr <= builder_interface1_adr_next_value1;
     end
-    if (builder_interface1_we_next_value_ce2) begin
-        builder_interface1_we <= builder_interface1_we_next_value2;
+    if (builder_interface1_re_next_value_ce2) begin
+        builder_interface1_re <= builder_interface1_re_next_value2;
+    end
+    if (builder_interface1_we_next_value_ce3) begin
+        builder_interface1_we <= builder_interface1_we_next_value3;
     end
     builder_interface0_bank_bus_dat_r <= 1'd0;
     if (builder_csrbank0_sel) begin
@@ -16179,11 +16199,11 @@ always @(posedge sys_clk) begin
     end
     main_k7ddrphy_rst_re <= builder_csrbank1_rst0_re;
     if (builder_csrbank1_dly_sel0_re) begin
-        main_k7ddrphy_dly_sel_storage[3:0] <= builder_csrbank1_dly_sel0_r;
+        main_k7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r;
     end
     main_k7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
     if (builder_csrbank1_half_sys8x_taps0_re) begin
-        main_k7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+        main_k7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r;
     end
     main_k7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
     if (builder_csrbank1_wlevel_en0_re) begin
@@ -16191,11 +16211,11 @@ always @(posedge sys_clk) begin
     end
     main_k7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
     if (builder_csrbank1_rdphase0_re) begin
-        main_k7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+        main_k7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r;
     end
     main_k7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
     if (builder_csrbank1_wrphase0_re) begin
-        main_k7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+        main_k7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r;
     end
     main_k7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
     builder_interface2_bank_bus_dat_r <= 1'd0;
@@ -16303,19 +16323,19 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (builder_csrbank2_dfii_control0_re) begin
-        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+        main_litedramcore_storage <= builder_csrbank2_dfii_control0_r;
     end
     main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
     if (builder_csrbank2_dfii_pi0_command0_re) begin
-        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
+        main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r;
     end
     main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
     if (builder_csrbank2_dfii_pi0_address0_re) begin
-        main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
+        main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r;
     end
     main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
     if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+        main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
     main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
     if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
@@ -16327,15 +16347,15 @@ always @(posedge sys_clk) begin
     main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
     main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
     if (builder_csrbank2_dfii_pi1_command0_re) begin
-        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
+        main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r;
     end
     main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
     if (builder_csrbank2_dfii_pi1_address0_re) begin
-        main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
+        main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r;
     end
     main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
     if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+        main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
     main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
     if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
@@ -16347,15 +16367,15 @@ always @(posedge sys_clk) begin
     main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
     main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
     if (builder_csrbank2_dfii_pi2_command0_re) begin
-        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
+        main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r;
     end
     main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
     if (builder_csrbank2_dfii_pi2_address0_re) begin
-        main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
+        main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r;
     end
     main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
     if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+        main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
     main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
     if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
@@ -16367,15 +16387,15 @@ always @(posedge sys_clk) begin
     main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
     main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
     if (builder_csrbank2_dfii_pi3_command0_re) begin
-        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
+        main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r;
     end
     main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
     if (builder_csrbank2_dfii_pi3_address0_re) begin
-        main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
+        main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r;
     end
     main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
     if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+        main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
     main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
     if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
@@ -16690,6 +16710,7 @@ always @(posedge sys_clk) begin
         main_init_done_re <= 1'd0;
         main_init_error_storage <= 1'd0;
         main_init_error_re <= 1'd0;
+        builder_interface1_re <= 1'd0;
         builder_interface1_we <= 1'd0;
         builder_refresher_state <= 2'd0;
         builder_bankmachine0_state <= 4'd0;
@@ -23218,7 +23239,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
@@ -23236,7 +23257,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (iodelay_rst)
@@ -23254,7 +23275,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
@@ -23272,7 +23293,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (sys_rst)
@@ -23290,7 +23311,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
@@ -23308,7 +23329,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
@@ -23326,7 +23347,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
@@ -23344,7 +23365,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
@@ -23353,5 +23374,5 @@ FDPE #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:08.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:43.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index 0573632..843a495 100644
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842adc83c4c0001
+3c4c000100000000
+7c0802a63842aea4
+f821ffc148002885
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+000000004800289c
+0000038001000000
+3842ae503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48002175f9410108
+480021b9f9410108
 7c7f1b7860000000
-48001bc538610020
+48001c1538610020
 382100b060000000
-480027e87fe3fb78
+480028447fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,273 +552,284 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842ad2c
-480027217d600026
-f821fed191610008
-6000000048001bc1
-38637a983c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842adb4
+480027797d600026
+f821fec191610008
+6000000048001c11
+38637a683c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637ab83be00008
+38637a883be00008
 4bffff1d67ffc000
-38637ad83c62ffff
+38637aa83c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637af0
+4bfffef538637ac0
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637af8
+4bfffedd38637ac8
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b00
+4bfffec538637ad0
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b08
+4bfffead38637ad8
 4182001073e90010
-38637b183c62ffff
+38637ae83c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637b28
-3b7b7b303f62ffff
-4bfffe757f63db78
+4bfffe8538637af8
+3b397b003f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637b387884b582
+38637b087884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637b50
+4bfffe2d38637b20
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637b68
+4bfffe0d38637b38
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637b807c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637ba057c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637b507c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637b7057e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637bc0
-4082009073a90002
-38637be03c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637b90
+4082006473c90002
+38637bb03c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637bf8
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637c087b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637c3838847c28
-48000bf54bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637c583c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637bc0
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637c70
-38a000403c9af000
+4bfffc2d38637c60
+38a000403c9cf000
 3861007078840020
-60000000480018b5
+60000000480019e5
 3d200002e9410070
 6129464c3c62ffff
-792983e438637c88
+792983e438637c78
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637ca83c62ffff
-892100774bfffae9
+38637c983c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d0888810070
+38637cf888810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637d38
-3880600038a00000
-6484ff0060a5a000
-480018113c604000
+3c62ffff4bfffb99
+4bfffb8d38637d28
+3880f80338a00000
+7884682860a5a000
+480019413c604000
 3c62ffff60000000
-4bfffa8538637d58
-4bffff184bfffafd
+4bfffb6538637d48
+480002184bfffbdd
 3f22ffffebe10090
-3b397cc03ba00000
-a12100a87ffafa14
+3b397cb03ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637ce8
-e86100884bfffac5
+4bfffb2d38637cd8
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-480022407d638120
+8161000838210140
+480023787d638120
 38a000383c9ff000
 386100b078840020
-6000000048001795
+60000000480018c5
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-600000004800174d
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+600000004800187d
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
-38637bf03c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637bc8
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637bd0
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
+38637be83c62ffff
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637bf87b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637c2838847c18
+48000a294bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637c483c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920100400000000
+7c0004ac6529c800
+394010087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-6529c80039201004
-7c604f2a7c0004ac
-3920000139401008
+3842a7283c4c0001
+4182004428030002
+4182001428030003
+4182005028030001
+4bffffa87c8307b4
+6529c8003920104c
+7c804f2a7c0004ac
+3940105039200001
 7c0004ac654ac800
 4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a6f4
-2803000341820044
-2803000141820014
-7c8307b441820050
-3920104c4bffffa8
-7c0004ac6529c800
-392000017c804f2a
-654ac80039401050
-7d20572a7c0004ac
-392010344e800020
+6529c80039201034
+7c804f2a7c0004ac
+3940103839200001
+3920101c4bffffd8
 7c0004ac6529c800
 392000017c804f2a
-4bffffd839401038
-6529c8003920101c
-7c804f2a7c0004ac
-3940102039200001
-000000004bffffbc
+4bffffbc39401020
+0000000000000000
+3d40555500000000
+614a55555469f87e
+7c6918507d295038
+612933333d203333
+5463f0be7d2a1838
+7d4a1a147c634838
+7d2952145549e13e
+614a0f0f3d400f0f
+552ac23e7d295038
+5523843e7d2a4a14
+786306a07c634a14
+000000004e800020
 0000000000000000
-5469f87e3d405555
-7d295038614a5555
-3d2033337c691850
-7d2a183861293333
-7c6348385463f0be
-5549e13e7d4a1a14
-3d400f0f7d295214
-7d295038614a0f0f
-7d2a4a14552ac23e
-7c634a145523843e
-4e800020786306a0
+3920000028030002
+4182002c39401040
+3920000028030003
+4182001c39401058
+3920000028030001
+4182000c39401028
+3940101039200000
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
 2803000200000000
-3940104039200000
+3940103c39200000
 280300034182002c
-3940105839200000
+3940105439200000
 280300014182001c
-3940102839200000
+3940102439200000
 392000004182000c
-654ac80039401010
+654ac8003940100c
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-3920000028030002
-4182002c3940103c
-3920000028030003
-4182001c39401054
-3920000028030001
-4182000c39401024
-3940100c39200000
-7c0004ac654ac800
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-7c0802a63842a554
-f821ff4148001f2d
-3f02ffff23a30001
-3b40100c3ae00003
-3ac010743b201010
-3bc0000020630003
-3b187e503b600000
-675ac80066f78020
-66d6c8006739c800
-7c7f07b47fbd07b4
-3a8100207bc91764
-3aa000047e87a378
-7e9ca3787d58482e
+3842a5883c4c0001
+48001f2d7c0802a6
+3ee2fffff821ff31
+3b20100c3ec0e008
+3aa010743b001010
+236300033b800830
+3ba000003bc00000
+7ad610203af77fac
+6718c8006739c800
+679cc80066b5c800
+687f00017f7b07b4
+3a4100207bc91764
+3a8000047e479378
+7e5a93787d57482e
 4800004439000000
 794a07e07949f862
-7d4ab8387d4a00d0
+7d4ab0387d4a00d0
 7d2a4b787d494a78
 7d293030552907fe
 7d292b7838c60001
@@ -812,253 +838,252 @@ f821ff4148001f2d
 4182001828280004
 38a0000039200008
 38c000007d2903a6
-3ab5ffff4bffffb0
-2c15000038e70004
+3a94ffff4bffffb0
+2c14000038e70004
 7c0004ac4082ff98
-7c0004ac7ea0d72a
-386000097ea0cf2a
-3860000f4bfffd41
-392010144bfffd1d
+7c0004ac7e80cf2a
+386000097e80c72a
+3860000f4bfffd3d
+392010144bfffd19
 38e000046529c800
-7ce903a63914ffff
-8ce8000139400000
+7ce903a63912ffff
+394000003a600004
+3a73ffff8ce80001
 7cea3b787947400c
-7c0004ac4200fff4
+7c0004ac4200fff0
 392900187ce04f2a
-7c29b0003a940004
-3a8008304082ffcc
-7c0004ac6694c800
-5463063e7c60a62a
-7c0004ac4bfffe61
-5463063e7c60a62a
-7c0004ac4bfffdfd
-388000177c60a62a
-4bfffcf95463063e
-3860000f3a80082c
-6694c8004bfffc95
-7c60a62a7c0004ac
-4bfffe1d5463063e
-7c60a62a7c0004ac
-4bfffdb95463063e
-7c60a62a7c0004ac
+7c29a8003a520004
+7c0004ac4082ffc4
+5463063e7c60e62a
+7c0004ac4bfffe5d
+5463063e7c60e62a
+7c0004ac4bfffdf9
+388000177c60e62a
+4bfffcf55463063e
+3860000f3a40082c
+6652c8004bfffc91
+7c60962a7c0004ac
+4bfffe195463063e
+7c60962a7c0004ac
+4bfffdb55463063e
+7c60962a7c0004ac
 5463063e38800025
-3860000f4bfffcb5
-392000004bfffc55
-7d20d72a7c0004ac
+3860000f4bfffcb1
+392000004bfffc51
 7d20cf2a7c0004ac
-7e9cea143860000b
-3860000f4bfffc51
-4bfffc293a601018
-6673c8003a001078
-7e91a3787f9cfa14
-7c0004ac6610c800
-390000047d209e2a
+7d20c72a7c0004ac
+39c010183860000b
+3860000f4bfffc4d
+4bfffc2565cec800
+7e5afa147dfada14
+7e7107b41d330018
+7c0004ac7d297214
+390000047d204e2a
 7d0903a679290020
 9d2affff39410034
 4200fff87929c202
-3a7300187d3da050
-7c69f8ae3a940004
-7c634a78893c0010
-4bfffcb55463063e
-7c721b7889310010
-7c634a788874fffc
-4bfffc9d5463063e
-7c6392147c338000
-4082ff987eb51a14
-7f7baa143bde0001
-4082fddc283e0003
-7f6307b4382100c0
-0000000048001d04
-0000108001000000
-3842a2c03c4c0001
-388000007c0802a6
-f821ff6148001cb5
-3b1864ec3f02ffff
-3bc000007c7d1b78
-7f05c3783b800000
-600000004800084d
-4bfffd397fa3eb78
-7c7f00342c030000
-4082006857ffd97e
-418200602c1c0000
-7ff9fb783bfeffff
-7fdbf3787ffcfb78
-3b5b00017fa3eb78
-2c0300004bfffd05
-7d39d85040820070
-7c0950007d5fe050
-2c1a001f41810068
-3ca2ffff4181006c
-3880000038a564a4
-7f5bd3787fa3eb78
-60000000480007d5
-3bde00014bffffb8
-418200242c1e0020
-38a564a43ca2ffff
+7a3117647a691764
+3a7300017e3a8a14
+892f00107c6f48ae
+5463063e7c634a78
+893200104bfffcad
+7c71f8ae7c701b78
+5463063e7c634a78
+283300044bfffc95
+7e941a147c638214
+3bde00014082ff88
+283e00037fbda214
+382100d04082fdd8
+48001cfc7fa307b4
+0100000000000000
+3c4c000100001280
+7c0802a63842a2ec
+48001cb538800000
+3f02fffff821ff61
+7c7d1b783b1864b4
+3b8000003bc00000
+480008417f05c378
+7fa3eb7860000000
+2c0300004bfffd31
+57ffd97e7c7f0034
+2c1c000040820068
+3bfeffff41820060
+7ffcfb787ff9fb78
+7fa3eb787fdbf378
+4bfffcfd3b5b0001
+408200702c030000
+7d5fe0507d39d850
+418100687c095000
+4181006c2c1a001f
+38a5646c3ca2ffff
 7fa3eb7838800000
-480007a97ffcfb78
-4bffff5c60000000
-4bffff783be0ffff
-4bffffa07f59d378
-7f3fcb787f7cdb78
-2c1c00004bffff94
-7fc907b440800024
-2129001f3b800000
-418000082c290000
-3bde0001239e001f
-2c1f00007f9cf214
-3c62ffff4080001c
-4bfff3cd38637d70
-382100a060000000
-7cbfe05048001bd4
-7ca50e707c9cfa14
-789bfee27ca50194
-7ca507b43c62ffff
-38637d807f64db78
-4bfff3953be00008
-7f05c37860000000
+480007c97f5bd378
+4bffffb860000000
+2c1e00203bde0001
+3ca2ffff41820024
+3880000038a5646c
+7ffcfb787fa3eb78
+600000004800079d
+3be0ffff4bffff5c
+7f59d3784bffff78
+7f7cdb784bffffa0
+4bffff947f3fcb78
+4080001c2c1c0000
+3b8000002c1e0020
+239e001f41820008
+7f9cf2143bde0001
+4080001c2c1f0000
+38637d603c62ffff
+600000004bfff379
+48001bdc382100a0
+7c9fe2147cbfe050
+7ca501947ca50e70
+3c62ffff789bfee2
+7f64db787ca507b4
+3be0000838637d70
+600000004bfff341
+388000007f05c378
+3bc000007fa3eb78
+60000000480006f5
+4bfff9ed38600064
+418100247c1bf000
+4bfffbd57fa3eb78
+4182ff942c030000
+2c1f00003bffffff
+4bffff844082ffc0
+38a5646c3ca2ffff
 7fa3eb7838800000
-480006f93bc00000
+480006a93bde0001
 3860006460000000
-7c1bf0004bfff9ed
-7fa3eb7841810024
-2c0300004bfffbd5
-3bffffff4182ff94
-4082ffc02c1f0000
-3ca2ffff4bffff84
-3880000038a564a4
-3bde00017fa3eb78
-60000000480006ad
-4bfff9a138600064
-000000004bffffb4
-0000088001000000
-3842a0d03c4c0001
-6529c80039201000
-7d404e2a7c0004ac
-4d820020280a000e
-3940000e7c0802a6
-f821ffa1f8010010
-7d404f2a7c0004ac
-38637d983c62ffff
-600000004bfff2d1
-e801001038210060
-4e8000207c0803a6
+4bffffb44bfff9a1
 0100000000000000
-3c4c000100000080
-392010003842a06c
+3c4c000100000880
+392010003842a104
 7c0004ac6529c800
-280a00017d404e2a
+280a000e7d404e2a
 7c0802a64d820020
-f801001039400001
+f80100103940000e
 7c0004acf821ffa1
 3c62ffff7d404f2a
-4bfff26d38637dc0
+4bfff27d38637d88
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-3842a0083c4c0001
-480019ed7c0802a6
-3f02fffff821ff31
-3ec2ffff3b186574
-3e82ffff3ea2ffff
-3e62ffff3ee2ffff
-3ad67de83b400000
-3a947e003ab57df8
-3a737e083af77b30
-7f05c3787f5f07b4
+3842a0a03c4c0001
+6529c80039201000
+7d404e2a7c0004ac
+4d820020280a0001
+394000017c0802a6
+f821ffa1f8010010
+7d404f2a7c0004ac
+38637db03c62ffff
+600000004bfff219
+e801001038210060
+4e8000207c0803a6
+0100000000000000
+3c4c000100000080
+7c0802a63842a03c
+f821ff31480019f5
+3b18653c3f02ffff
+3ea2ffff3ec2ffff
+3ee2ffff3e82ffff
+3b4000003e62ffff
+3ab57de83ad67dd8
+3af77b003a947df0
+7f5f07b43a737df8
+388000007f05c378
+480005697fe3fb78
+3b60000060000000
+3bc000003b800000
+7fdbf37848000030
+418200e42c1e0007
+38a564f43ca2ffff
 7fe3fb7838800000
-600000004800056d
-3b8000003b600000
-480000303bc00000
-2c1e00077fdbf378
-3ca2ffff418200e4
-3880000038a5652c
-3bde00017fe3fb78
-480005317fbceb78
-7fc507b460000000
-7ec3b3787fe4fb78
-4bfff19d3b200020
-3ca2ffff60000000
-3880000038a564ec
-3ba000007fe3fb78
-60000000480004fd
-4bfff9e97fe3fb78
-7c64003439400000
-5484d97e212300c0
+7fbceb783bde0001
+600000004800052d
+7fe4fb787fc507b4
+3b2000207ec3b378
+600000004bfff149
+38a564b43ca2ffff
+7fe3fb7838800000
+480004f93ba00000
+7fe3fb7860000000
+392000004bfff9e9
+5484d97e7c640034
 418200082c040000
-7d29521439401800
-7ea3ab78788407e0
-4bfff1457fbd4a14
-3ca2ffff60000000
-3880000038a564a4
-480004a97fe3fb78
-3739ffff60000000
-7e83a3784082ffa8
-600000004bfff119
-4bfffc157fe3fb78
-4bfff1057ee3bb78
-7c1ce84060000000
-7f9de3784180ff20
-7f6507b44bffff1c
-7e639b787fe4fb78
-4bfff0dd3bc00000
-7f05c37860000000
+206300c039201800
+7d291a14788407e0
+7fbd4a147ea3ab78
+600000004bfff0f1
+38a5646c3ca2ffff
+7fe3fb7838800000
+60000000480004a5
+4082ffa83739ffff
+4bfff0c57e83a378
+7fe3fb7860000000
+7ee3bb784bfffc1d
+600000004bfff0b1
+4180ff207c1ce840
+4bffff1c7f9de378
+7fe4fb787f6507b4
+3bc000007e639b78
+600000004bfff089
+388000007f05c378
+480004417fe3fb78
+7c1ed80060000000
+7fe3fb7840820030
+7ee3bb784bfffbc5
+600000004bfff059
+3b400001393a0001
+4082fe982c090002
+48001898382100d0
+38a564f43ca2ffff
 7fe3fb7838800000
-6000000048000445
-418000287c1ed800
-4bfffbbd7fe3fb78
-4bfff0ad7ee3bb78
-2c1a000060000000
-3b4000014082002c
-3ca2ffff4bfffe98
-3880000038a5652c
-3bde00017fe3fb78
-60000000480003fd
-382100d04bffffb8
-0000000048001870
-00000d8001000000
-38429e203c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-4bfffd3df821ff91
-3bde64ec3fc2ffff
+480003f13bde0001
+4bffffb060000000
+0100000000000000
+3c4c000100000d80
+7c0802a638429e54
+fbe1fff8fbc1fff0
+f821ff91f8010010
+3fc2ffff4bfffd3d
+388000003bde64b4
+7fc5f37838600000
+60000000480003a5
+3bff653c3fe2ffff
 3860000038800000
-480003a97fc5f378
-3fe2ffff60000000
-388000003bff6574
-7fe5fb7838600000
-600000004800038d
-388000007fc5f378
-4800037938600001
-7fe5fb7860000000
+480003897fe5fb78
+7fc5f37860000000
 3860000138800000
-6000000048000365
-38637e203c62ffff
-600000004bffefd9
-4bfffd294bfffd91
-3860000138210070
-0000000048001800
-0000028001000000
-38429d703c4c0001
-3920082c7c0802a6
-4800175d6529c800
+6000000048000375
+388000007fe5fb78
+4800036138600001
+3c62ffff60000000
+4bffef8538637e10
+4bfffd9160000000
+382100704bfffd29
+4800180838600001
+0100000000000000
+3c4c000100000280
+7c0802a638429da4
+3b80082c4800176d
 3b000002f821ff51
-7f004f2a7c0004ac
-3b20000339200830
-7c0004ac6529c800
-3c62ffff7f204f2a
-38637e303c804000
-4bffef653bc00800
-3b80000160000000
-67dec8004bfffc51
-7f80f72a7c0004ac
-3be00000386003e8
-7c0004ac4bfff5bd
-386003e87fe0f72a
-4bfff5a93f60c800
-7c0004ac7b7b0020
-3b4000047fe0df2a
+7c0004ac679cc800
+392008307f00e72a
+6529c8003b200003
+7f204f2a7c0004ac
+3c8040003c62ffff
+3bc0080038637e20
+600000004bffef11
+4bfffc513b600001
+7c0004ac67dec800
+386003e87f60f72a
+4bfff5bd3be00000
+7fe0f72a7c0004ac
+3b9cf7d4386003e8
+7c0004ac4bfff5a9
+3b4000047fe0e72a
 7c0004ac675ac800
 3ba0100c7fe0d72a
 7c0004ac67bdc800
@@ -1068,47 +1093,47 @@ f8010010fbe1fff8
 66f7c8003920000c
 7d20bf2a7c0004ac
 6063c35038600000
-7c0004ac4bfff54d
+7c0004ac4bfff551
 7c0004ac7fe0ef2a
 3920000e7fe0f72a
 7d20bf2a7c0004ac
-4bfff52938602710
+4bfff52d38602710
 7c0004ac39200200
 7c0004ac7d20ef2a
 3860000f7f00f72a
-7c0004ac4bfff529
+7c0004ac4bfff52d
 7c0004ac7fe0ef2a
 3860000f7f20f72a
-392000064bfff511
+392000064bfff515
 7d20ef2a7c0004ac
-7f80f72a7c0004ac
-4bfff4f53860000f
+7f60f72a7c0004ac
+4bfff4f93860000f
 7c0004ac39200930
 7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff4d9
-392004004bfff4b5
+386000c84bfff4dd
+392004004bfff4b9
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bfff4b538600003
-4bfff491386000c8
-4bfffb694bfffdb9
+4bfff4b938600003
+4bfff495386000c8
+4bfffb6d4bfffdbd
 3c6040003c800020
 600000004800085d
 408200242c030000
 7c0004ac7c691b78
-7c0004ac7f80d72a
-382100b07f80df2a
-480015e47d2307b4
+7c0004ac7f60d72a
+382100b07f60e72a
+480015f07d2307b4
 38a0000038c00000
 3c6040003c800020
 60000000480005e5
-7f80df2a7c0004ac
+7f60e72a7c0004ac
 4bffffd039200001
 0100000000000000
 3c4c000100000980
-6000000038429b5c
-3942802078631764
+6000000038429b94
+3942800878631764
 392900017d2a182e
 7d2a192e552906fe
 3920000139400818
@@ -1116,16 +1141,16 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429b14
-3922802078631764
+6000000038429b4c
+3922800878631764
 7d49192e39400000
 3920000139400814
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429ad4
-3942801878631764
+6000000038429b0c
+3942800078631764
 392900017d2a182e
 7d2a192e5529077e
 3920000139400820
@@ -1133,15 +1158,15 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429a8c
-3922801878631764
+6000000038429ac4
+3922800078631764
 7d49192e39400000
 392000013940081c
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-7c0802a638429a4c
+7c0802a638429a84
 39200001fbe1fff8
 7cac2b783be00804
 67ffc8007d291830
@@ -1151,46 +1176,46 @@ f84100187ca903a6
 e84100184e800421
 7c0004ac39200000
 382100307d20ff2a
-000000004800147c
+0000000048001488
 0000018001000000
-384299e83c4c0001
+38429a203c4c0001
 282303ff7c0802a6
 f821ffa1f8010010
 7c641b7841810028
-38637e603c62ffff
-600000004bffec01
+38637e403c62ffff
+600000004bffebb1
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffebc538637e68
+4bffeb7538637e48
 4bffffc460000000
 786465023d204000
 408000247c234840
 788955647863b282
 38a000667d291850
 7ca92b923c62ffff
-4bffffc838637e78
+4bffffc838637e58
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637e887ca54b92
+38637e687ca54b92
 000000004bffffa4
 0000008001000000
-384299183c4c0001
+384299503c4c0001
 fbe1fff87c0802a6
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-f801001038637e98
-4bffeb25f821ff91
+f801001038637e78
+4bffead5f821ff91
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffeb0d38637ea8
+4bffeabd38637e88
 3821007060000000
-0000000048001344
+0000000048001350
 0000018001000000
 418200242c240000
 786307e07869f842
@@ -1200,14 +1225,14 @@ f801001038637e98
 4bfffff438630001
 0000000000000000
 3c4c000100000000
-7c0802a638429874
+7c0802a6384298ac
 3d40aaaa78840764
 614aaaaa7c691b78
-7f8322144800126d
+7f83221448001279
 f821ffc17884f082
 7c7f1b7839040001
 7c7d1b787d0903a6
-4bffeae142000080
+4bffea9142000080
 7d3fe05060000000
 7929f0823d00aaaa
 392900017feafb78
@@ -1217,12 +1242,12 @@ f821ffc17884f082
 7feafb787929f082
 6108555539290001
 420000587d2903a6
-4bffea917fffe050
+4bffea417fffe050
 7bfff08260000000
 395f00013d205555
 7d4903a661295555
 3821004042000040
-480012207fc307b4
+4800122c7fc307b4
 3929000491490000
 812a00004bffff78
 418200087c094000
@@ -1234,44 +1259,44 @@ f821ffc17884f082
 4bffffac3bbd0004
 0100000000000000
 3c4c000100000480
-7d60002638429764
+7d6000263842979c
 916100087c0802a6
-480011452e260000
+480011512e260000
 7c7f1b78f821ff41
 7cde33787cba2b78
-419200c0789cf082
+419200e4789cf082
 82e6000081260004
-408200442c090000
-3ba000003f02ffff
-7bf900203b600001
-7c3ce8403b187eb0
-3c62ffff4082009c
-38637eb07b851028
-4bfffde57be40020
-38637b303c62ffff
-600000004bffe929
-600000004bffe98d
+418200d82c090000
+600000004bffe97d
 7ffbfb782d970000
 3ac000013ba00000
 7bf500203b200000
-7fb8eb787c3de040
-2c17000040820084
+7fb8eb787c3ce840
+2c170000408200c4
 3c62ffff41820028
-38637ec07b051028
-4bfffd8d7be40020
-38637b303c62ffff
-600000004bffe8d1
+38637ea07b051028
+4bfffdcd7be40020
+38637b003c62ffff
+600000004bffe8c1
 7f2307b4382100c0
 7d61812081610008
-3ae00001480010c0
-7b6300204bffff50
-4bfffdb57f44d378
+7b6300204800110c
+4bfffdfd7f44d378
 7c7f492e7ba91764
 7c7b1b7873a97fff
 7ba5102840820014
 7f03c3787f24cb78
-3bbd00014bfffd31
-7f44d3784bffff2c
+3bbd00014bfffd79
+4082ffc87c3ce840
+7b8510283c62ffff
+7be4002038637e90
+3c62ffff4bfffd59
+4bffe84d38637b00
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187e907bf90020
+7f44d3784bffffb8
 4bfffd7d7ac30020
 7c651b78809b0000
 7c0320407c761b78
@@ -1282,29 +1307,29 @@ e8de00107d8903a6
 f841001878840020
 4e8004217b630020
 2c030000e8410018
-73187fff4082ff58
+73187fff4082ff18
 418e00184082001c
 7ba510283c62ffff
-38637ec07ea4ab78
+38637ea07ea4ab78
 3bbd00014bfffcb1
-4bfffef43b7b0004
+4bfffeb43b7b0004
 0300000000000000
 3c4c000100000b80
-7d708026384295a4
+7d708026384295dc
 916100087c0802a6
-f821ff7148000f9d
+f821ff7148000fa9
 3ba4ffe07cdb3378
 7c7f1b782e3b0000
 7fa3ea147c9e2378
 3c62ffff7c641b78
-7cbc2b7838637ed0
-600000004bffe7a1
-38637ee83c62ffff
+7cbc2b7838637eb0
+600000004bffe751
+38637ec83c62ffff
 3c62ffff4092000c
-4bffe78538637ef8
+4bffe73538637ed8
 7fc3f37860000000
 3c62ffff4bfffb59
-4bffe76d38637f08
+4bffe71d38637ee8
 2c3c000060000000
 7cf602a6408200a8
 38bd002038df0020
@@ -1320,14 +1345,14 @@ f90a0018f90a0010
 639ce10078ea0020
 7f9ee1d279290020
 3c62ffff7d295050
-7f9c4b9238637f10
-600000004bffe6e9
+7f9c4b9238637ef0
+600000004bffe699
 4bfffabd7f83e378
-38637f203c62ffff
-600000004bffe6d1
-38637b303c62ffff
-600000004bffe6c1
-600000004bffe725
+38637f003c62ffff
+600000004bffe681
+38637b003c62ffff
+600000004bffe671
+600000004bffe6d5
 409200487f9602a6
 395f00207d3fe850
 7929d9423bbd0020
@@ -1344,16 +1369,16 @@ e95f0018e95f0010
 7b9c00203d4005f5
 79290020614ae100
 7d29e0507fde51d2
-38637f283c62ffff
-4bffe6257fde4b92
+38637f083c62ffff
+4bffe5d57fde4b92
 7fc3f37860000000
 3c62ffff4bfff9f9
-4bffe60d38637f20
+4bffe5bd38637f00
 3c62ffff60000000
-4bffe5fd38637b30
+4bffe5ad38637b00
 3821009060000000
 7d70812081610008
-7fa407b448000e04
+7fa407b448000e10
 4bfffaed79430020
 7d23db963bbd0001
 7d29d9d67c6a1b78
@@ -1361,16 +1386,16 @@ e95f0018e95f0010
 4bffff687d3f482a
 0300000000000000
 3c4c000100000680
-7c0802a63842936c
-48000d7128240200
+7c0802a6384293a4
+48000d7d28240200
 7c7e1b78f821ff81
 3b8002007c9f2378
 7c9c237841810008
 7fc4f3783c62ffff
-4bffe57538637f38
+4bffe52538637f18
 7fe3fb7860000000
 3c62ffff4bfff949
-4bffe55d38637f08
+4bffe50d38637ee8
 7f84e37860000000
 4bfffaa17fc3f378
 38a0000138c00000
@@ -1379,55 +1404,55 @@ e95f0018e95f0010
 7c7e1b787d23ea14
 418200802c090000
 7b85f8823c62ffff
-38637f487fa4eb78
-600000004bffe511
+38637f287fa4eb78
+600000004bffe4c1
 7fe5fb78283f8000
 38a0ffff4081000c
 3c62ffff54a50420
 3880000078a5f082
-4bffe4e538637f60
+4bffe49538637f40
 3c62ffff60000000
 7fc4f3787be5f082
-4bffe4cd38637f78
+4bffe47d38637f58
 3c62ffff60000000
-4bffe4bd38637f90
+4bffe46d38637f70
 3860000060000000
 786307e038210080
-3c62ffff48000ccc
-4bffe49d38637fa0
+3c62ffff48000cd8
+4bffe44d38637f80
 3860000160000000
 000000004bffffe0
 0000048001000000
-384292403c4c0001
-8922803060000000
-3942802860000000
+384292783c4c0001
+8922801860000000
+3942801060000000
 418200302c090000
 39290014e92a0000
 7d204eaa7c0004ac
 4182ffec71290020
-e922802860000000
+e922801060000000
 7c604faa7c0004ac
 e92a00004e800020
 7c0004ac39290010
 712900087d204eea
 5469063e4082ffec
-e942802860000000
+e942801060000000
 7d2057ea7c0004ac
 000000004e800020
 0000000000000000
-384291b83c4c0001
+384291f03c4c0001
 fbe1fff87c0802a6
 3be3fffffbc1fff0
 f821ffd1f8010010
 2c1e00008fdf0001
 3821003040820010
-48000c0438600000
+48000c1038600000
 4082000c2c1e000a
 4bffff3d3860000d
-4bffff3557c3063e
+4bffff357bc30020
 000000004bffffd0
 0000028001000000
-384291583c4c0001
+384291903c4c0001
 654ac00039400020
 7d4056ea7c0004ac
 794a060039200008
@@ -1438,377 +1463,378 @@ f821ffd1f8010010
 7929f8047d204eea
 79290fc339002000
 600000006508c000
-3d00001cf9028028
+3d00001cf9028010
 7d4a439261082000
 6000000041820080
-9922803039200001
+9922801839200001
 3920ff803900200c
 7c0004ac6508c000
-e92280287d2047aa
+e92280107d2047aa
 7d404faa7c0004ac
-794ac202e9228028
+794ac202e9228010
 7c0004ac39290004
-e92280287d404faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e9228028
+39290010e9228010
 7d404faa7c0004ac
-39400007e9228028
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
 394affff60000000
-3920201899228030
+3920201899228018
 7c0004ac6529c000
 4e8000207d404fea
 0000000000000000
 78a9e8c200000000
 3929000139400000
-420000287d2903a6
-78a5076078a90724
-7d434a1439050001
-7c844a147d0903a6
-4200001839200000
-7d24502a4e800020
-394a00087d23512a
-7d0448ae4bffffcc
-392900017d0a49ae
-000000004bffffdc
-0000000000000000
-386000007c691b78
-2c0a00007d4918ae
-386300014d820020
-000000004bfffff0
-0000000000000000
-408200082c240000
+4200002c7d2903a6
+3940000078a9e8c2
+7ca54a141d29fff8
+390500017c892050
+7d0903a67d291850
+4e80002042000018
+7d23512a7d24502a
+4bffffc8394a0008
+7d0951ae7d0450ae
+4bffffdc394a0001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
+0000000000000000
+2c24000000000000
+408200087c691b78
 280500243881fff0
-38600000f8640000
-3d2000014d810020
-612a2600792983e4
-89090000e9240000
-4181004028080020
-70e700017d474436
-2c25000040820028
-2c050010418200e0
-2c08003040820010
-38a0001041820048
-4800008038600000
-f924000039290001
-2c2500004bffffb8
-2c0800304082ffd4
-4082ffdc38a0000a
-2c0a007889490001
-392900024082ffd0
-4bffffc0f9240000
-2c0a007889490001
-4bffffe84082ffb4
-54e7063e38eaffd0
-4181003c28070009
-7d2a07343929ffd0
-4c8000207c0a2800
-7c6519d239080001
-f90400007d290734
-e90400007c691a14
-714900ff89480000
-4e8000204082ffc0
-54e7063e38eaff9f
-4181000c28070019
-4bffffb83929ffa9
-554a063e394affbf
-4d810020280a0019
-4bffffa03929ffc9
-4bffff3438a0000a
-0000000000000000
-3923ff9f00000000
-4181000828090019
-7c6307b43863ffe0
-000000004e800020
+38600000f9240000
+3d4000014d810020
+614a2600794a83e4
+2808002089090000
+7d47443641810038
+4082002070e70001
+418200d02c250000
+418200282c050010
+386000003929ffff
+3929000148000078
+4bffffc4f9240000
+4082ffdc2c250000
+2c08003038a0000a
+894900014082ffd8
+4082ffcc2c0a0078
+38a0001039290002
+4bffffbcf9240000
+54e7063e38e8ffd0
+4181004028070009
+7d480734394affd0
+4c8000207c082800
+392900027c6519d2
+f92400007d4a0734
+7c6a1a147cc93378
+38c9000189090001
+4082ffbc710a00ff
+38e8ff9f4e800020
+2807001954e7063e
+394affa94181000c
+3908ffbf4bffffb4
+280800195508063e
+394affc94d810020
+38a0000a4bffff9c
+000000004bffff38
+0000000000000000
+280900193923ff9f
+3863ffe041810008
+4e8000207c6307b4
 0000000000000000
-38428e583c4c0001
-480008557c0802a6
-7c7e1b78f821ffa1
-7ca32b787cfd3b78
-38a0000a7c9c2378
-eb3e000038800000
-7d1b43787cdf3378
-4bfffe657d3a4b78
-2b9d001060000000
-2c3f000039400000
-2c0a00004082005c
-3940000140820008
-7c0350007d4ad214
-7d2350504081003c
-792900207d2948f8
-7d2903a639290001
-7d594850e93e0000
-408000187c2ae040
-e93e00009b690000
-f93e000039290001
-382100604200ffe0
-409e001048000808
-394a00017bffe102
-7fffeb924bffff94
-000000004bfffff4
-0000078001000000
-38428d883c4c0001
-4800078d7c0802a6
-eb630000f821ffb1
-7c9c23787c7f1b78
-3bc000007cbd2b78
-4bfffd7d7fa3eb78
-7c3e184060000000
-e93f000040800014
-7c2ae0407d5b4850
-382100504180000c
-7d5df0ae48000798
-994900003bde0001
-39290001e93f0000
-4bffffbcf93f0000
+3c4c000100000000
+7c0802a638428e9c
+f821ffa14800086d
+7cfd3b787c7e1b78
+7c9c23787ca32b78
+3880000038a0000a
+7cdf3378eb3e0000
+7d3a4b787d1b4378
+600000004bfffe75
+394000002b9d0010
+4082005c2c3f0000
+418100082c0a0000
+7d4ad21439400001
+4081003c7c035000
+394affff7d4a1850
+392a0001794a0020
+e93e00007d2903a6
+7c2ae0407d594850
+9b69000040800018
+39290001e93e0000
+4200ffe0f93e0000
+4800082038210060
+7bffe102409e0010
+4bffff94394a0001
+4bfffff47fffeb92
 0100000000000000
-3c4c000100000580
-7c0802a638428d0c
-e9297fb03d22ffff
-7d7080262b860010
-916100087caa2b78
-f821ffa1480006f5
+3c4c000100000780
+7c0802a638428dcc
+f821ffb1480007a5
+7c7f1b78eb630000
+7cbd2b787c9c2378
+7fa3eb783bc00000
+600000004bfffd8d
+408000147c3e1840
+7d5b4850e93f0000
+4180000c7c2ae040
+480007b038210050
+3bde00017d5df0ae
+e93f000099490000
+f93f000039290001
+000000004bffffbc
+0000058001000000
+38428d503c4c0001
+3d22ffff7c0802a6
+2b860010e9297f90
+916100087d708026
+f821ffa148000711
 7cbe2b787c7c1b78
 3be000007cdd3378
 3d22fffff9210020
-f9210028e9297fb8
-408200342c2a0000
-408200082c1f0000
-7fff07b43be00001
-7c3f20402e270000
-408100303b7fffff
-8161000838210060
-480006e87d708120
-794ae102409e0010
-4bffffbc3bff0001
-4bfffff47d4aeb92
-7f5eeb927f5ed378
-7d29f0507d3ae9d2
-886900207d214a14
-5463063e41920010
-600000004bfffdd5
-e93c00007c3df040
-3b7bffff7c69d9ae
-e93c00004081ffc8
-f93c00007d29fa14
-000000004bffff90
-0000068003000000
-38428c183c4c0001
-480005e97c0802a6
-7c761b79f821fef1
-38600000f8610060
-2c2400004182003c
-3b04ffff41820034
-3a8000003aa10040
-ebc1006089250000
-7c76f050712a00ff
-7c23c0404182000c
-3920000041800018
-38210110993e0000
-480005e07c6307b4
-390500012c0a0025
-3920000040820564
-7cb32b7889450000
-7d49a9ae8ce50001
-280a007854ea063e
-280a006241810024
-2c0a004f41810024
-2c0a0058418200a0
-2c0a002541820098
-3929000141820090
-3907ff9d4bffffc0
-280400155504063e
-3c82ffff4181ffec
-790815a8388474d0
-7d0822147d0442aa
-4e8004207d0903a6
-0000005800000058
-ffffffccffffffcc
-ffffffccffffffcc
-ffffffcc00000058
-ffffffccffffffcc
-ffffffccffffffcc
-0000005800000058
-ffffffccffffffcc
-ffffffcc00000058
-ffffffcc00000058
-00000058ffffffcc
-2c0a002539090001
-38a1002039290002
-7d2907b47d0807b4
-7d254a147d054214
-9a89002098e80020
+f9210028e9297f98
+2c2900007ca92b78
+2c1f000040820034
+3be0000141810008
+2e2700007fff07b4
+3b7fffff7c3f2040
+3821006040810030
+7d70812081610008
+409e001048000700
+3bff00017929e102
+7d29eb924bffffbc
+7f5ed3784bfffff4
+7d3ae9d27f5eeb92
+7d214a147d29f050
+4192001088690020
+4bfffdd55463063e
+7c3df04060000000
+7c69d9aee93c0000
+4081ffc83b7bffff
+7d29fa14e93c0000
+4bffff90f93c0000
+0300000000000000
+3c4c000100000680
+7c0802a638428c5c
+f821fef148000601
+f86100607c751b79
+4182004438600000
+4182003c2c240000
+3ae4ffff7cbd2b78
+3b2100203a610040
+895d00003a400000
+714900ffebc10060
+4182000c7c75f050
+418000187c23b840
+993e000039200000
+7c6307b438210110
+2c090025480005f0
+40820574391d0001
+7d4999ae39200000
+389d0001895d0001
+280800785548063e
+2808006241810024
+2c08004f41810028
+2c080058418200a4
+2c0800254182009c
+3929000141820094
+4bffffc07c9d2378
+54e5063e38eaff9d
+4181ffe828050015
+38a574943ca2ffff
+7ce53aaa78e715a8
+7ce903a67ce72a14
+000000584e800420
+ffffffc800000058
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc800000058
+00000058ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+38e9000100000058
+392900022c080025
+7d2907b47ce707b4
+7d394a147cf93a14
+9a49002099470020
 393e000140820018
-f9210060995e0000
-4bfffebc38b30002
+995e0000f9210060
+4bfffec03bbd0002
 eb86000089210041
-3a2600087fe3c050
-3b4100423a400030
+3a2600087fe3b850
+3b4100423a800030
 712900fd3929ffd2
-5649063e40820428
-3ae000003de2ffff
-f92100683b200004
+5689063e4082043c
+3ac000003de2ffff
+f92100683b000004
 3a0000003b600000
-4800017039ef7fd0
-38da00012c07004f
-390affa8418201dc
-280500225505063e
-3ca2ffff418103bc
-790815a838a575e8
-7d082a147d0542aa
-4e8004207d0903a6
-0000039c00000158
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-000002680000039c
-0000039c0000008c
-0000039c0000039c
-0000008c00000380
-0000039c0000039c
-0000039c00000368
-000001ac0000039c
-0000039c00000204
-000002ac0000039c
-0000008c0000039c
-0000039c0000039c
-0000039c0000015c
-2c070075000003c0
+4800016c39ef7fb8
+38ba00012c06004f
+38e8ffa8418201e0
+2804002254e4063e
+3c82ffff418103d0
+78e715a8388475a8
+7ce722147ce43aaa
+4e8004207ce903a6
+000003b000000154
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+00000270000003b0
+000003b00000008c
+000003b0000003b0
+0000008c00000394
+000003b0000003b0
+000003b00000037c
+000001b0000003b0
+000003b00000020c
+000002b4000003b0
+0000008c000003b0
+000003b0000003b0
+000003b000000158
+2c060075000003d4
 7d4152147b6a0020
-7f9de37839000000
+7f8ee37839000000
 41820044990a0020
-3940000157281838
-7d4a40363908ffff
-4182002c7f8a5039
+3900000157071838
+7d08383638e7ffff
+4182002c7f884039
 392900013940002d
-9949ffff7fbc00d0
-f92100603d42ffff
-394a7fd07b291e68
-7fbd48387d2a482a
-38e0000ae8810060
-38a100207fa6eb78
-5648063e39200000
-7c9e205038610060
-4bfffabd7c84f850
-7ae707e0e8810060
-7fa5eb7838c0000a
-7c84f8507c9e2050
-4bfffbe938610060
-895a00003b5a0001
-714700ffe9210060
-7fbe485041820010
-4181fe7c7c3fe840
-4bfffe247e268b78
-7b6900203ae00001
-38e00010e9010068
-7c9df8507d214a14
-3861006038a10020
-7b291e689a090020
-392000007d4f482a
-7dc673787f8e5038
-e88100604bfffa39
-38c000107ae707e0
-7dc573787c9e2050
-7b6900204bffff7c
-7d214a1439400000
-7c9df85038e00008
-994900205648063e
-7b291e683d42ffff
-38a10020394a7fd0
-7d4a482a38610060
-7f8e503839200000
-4bfff9dd7dc67378
-7ae707e0e8810060
+7b081e683ce2ffff
+9949ffff38e77fb8
+7d5c00d0f9210060
+7d4e40387d07402a
+38e0000a7c9e4850
+7f25cb787dc67378
+392000007c84f850
+386100605688063e
+e88100604bfffabd
+38c0000a7ac707e0
+7c9e20507dc57378
+386100607c84f850
+3b5a00014bfffbe9
+e9210060891a0000
+41820010710600ff
+7c3f70407dde4850
+7e268b784181fe80
+3ac000014bfffe28
+e90100687b690020
+7d214a1438e00010
+7f25cb787c8ef850
+9a09002038610060
+7d6f482a7b091e68
+7f8b583839200000
+f96100707d665b78
+e88100604bfffa35
+38c000107ac707e0
+e96100707c9e2050
+4bffff747d655b78
+390000007b690020
+38e000087d214a14
+7f25cb787c8ef850
+3d02ffff99090020
+39087fb87b091e68
+7d68482a38610060
+5688063e39200000
+7d665b787f8b5838
+4bfff9d1f9610070
+7ac707e0e8810060
 7c9e205038c00008
-7b6900204bffffa4
-7d214a1439400000
+7b6900204bffff9c
+7d214a1439000000
 7f86e37838e00010
-9949002039000020
-3920000238a10020
-386100607c9df850
-e88100604bfff999
+990900207f25cb78
+392000027c8ef850
+3861006039000020
+e88100604bfff98d
 386100603ca2ffff
-7c9e205038a57fc8
-4bfffa4d7c84f850
-7ae707e0e8810060
+7c9e205038a57fa8
+4bfffa417c84f850
+7ac707e0e8810060
 7f85e37838c00010
-4bfffec07c9e2050
-394000007b690020
-390000207d214a14
-38c0000138e0000a
-38a1002099490020
-7c9df85039200000
-4bfff93538610060
+4bfffeb47c9e2050
+390000007b690020
+38e0000a7d214a14
+7f25cb7838c00001
+7c8ef85099090020
+3900002039200000
+4bfff92938610060
 9b890000e9210060
 f921006039290001
-7b6a00204bfffe88
-f921007039000000
-38a0000a7d415214
-3861002038800000
-4bfff795990a0020
-7c6e1b7860000000
-4bfff75d7f83e378
-7c2e184060000000
-e921007040810048
-7c6370507fbdf850
-38e0002039400000
-7d09f0503bbd0001
-7d08fa147c691a14
-408200082c280000
-2c3d00013ba00001
-408200283bbdffff
-40820034714a0001
-7f85e378e8810060
-7c9e205038610060
-4bfff9557c84f850
-98e900004bfffde8
-3940000139290001
-4082ffc07c291840
-4bffffccf9210060
-3b200008893a0001
-4082fdbc2c09006c
-4bfffdb47cda3378
-3b200002893a0001
-4082fda42c090068
-3b2000017cda3378
-392affd04bfffd98
-280900095529063e
-7b6900204181fd88
-7d214a143b7b0001
-4bfffd7499490020
-4bfffd6c3b200008
-3b4100413a400020
-993e00004bfffbd4
-7d0543783bde0001
-4bfffa54fbc10060
-0100000000000000
-f9c1ff7000001280
-fa01ff80f9e1ff78
-fa41ff90fa21ff88
-fa81ffa0fa61ff98
-fac1ffb0faa1ffa8
-fb01ffc0fae1ffb8
-fb41ffd0fb21ffc8
-fb81ffe0fb61ffd8
-fbc1fff0fba1ffe8
-f8010010fbe1fff8
-e9c1ff704e800020
-ea01ff80e9e1ff78
-ea41ff90ea21ff88
-ea81ffa0ea61ff98
-eac1ffb0eaa1ffa8
-eb01ffc0eae1ffb8
-eb41ffd0eb21ffc8
-eb81ffe0eb61ffd8
-eba1ffe8e8010010
-ebc1fff07c0803a6
-4e800020ebe1fff8
-e8010010ebc1fff0
-7c0803a6ebe1fff8
-600000004e800020
+7b6800204bfffe7c
+f921007838e00000
+38a0000a7d014214
+7f23cb7838800000
+4bfff79998e80020
+f861007060000000
+4bfff7617f83e378
+e901007060000000
+7c281840e9210078
+7d244b7841810020
+7f85e3787c9e2050
+386100607c84f850
+4bfffe184bfff985
+7c6340507ce9f050
+7d4ef8507ce7fa14
+7c691a142c270000
+390000007d244b78
+394a000138c00020
+3940000140820008
+394affff2c2a0001
+7108000140820010
+4bffffa04082001c
+3884000198c40000
+7c24184039000001
+f88100604082ffd8
+893a00014bffff88
+2c09006c3b000008
+7cba2b784082fda4
+893a00014bfffd9c
+2c0900683b000002
+7cba2b784082fd8c
+4bfffd803b000001
+5529063e3928ffd0
+4181fd7028090009
+3b7b00017b690020
+990900207d214a14
+3b0000084bfffd5c
+3a8000204bfffd54
+4bfffbc03b410041
+3bde0001995e0000
+fbc100607d1d4378
+000000004bfffa44
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
+eb21ffc8eb01ffc0
+eb61ffd8eb41ffd0
+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1853,14 +1879,18 @@ e8010010ebc1fff0
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1921,15 +1951,13 @@ e8010010ebc1fff0
 000000000000207c
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
@@ -1971,11 +1999,12 @@ e8010010ebc1fff0
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index bab09c2..f8000fe 100644
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:06
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:40
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -81,17 +81,17 @@ LiteDRAMCore
 │    └─── pll (S7PLL)
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [PLLE2_ADV]
 │    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
 │    └─── idelayctrl (S7IDELAYCTRL)
 │    │    └─── [IDELAYCTRL]
 └─── ddrphy (A7DDRPHY)
@@ -136,103 +136,103 @@ LiteDRAMCore
 │    └─── bitslip_35* (BitSlip)
 │    └─── tappeddelayline_2* (TappedDelayLine)
 │    └─── tappeddelayline_3* (TappedDelayLine)
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [IDELAYE2]
-│    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OBUFDS]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [IOBUFDS]
-│    └─── [IOBUF]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
+│    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [ISERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [IOBUF]
+│    └─── [IDELAYE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [ISERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OBUFDS]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
+│    └─── [OSERDESE2]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
 │    │    └─── pi0 (PhaseInjector)
@@ -544,6 +544,7 @@ wire   [29:0] builder_interface0_adr;
 wire   [13:0] builder_interface0_bank_bus_adr;
 reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_re;
 wire          builder_interface0_bank_bus_we;
 wire    [1:0] builder_interface0_bte;
 wire    [2:0] builder_interface0_cti;
@@ -560,17 +561,22 @@ reg           builder_interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] builder_interface1_bank_bus_adr;
 reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_re;
 wire          builder_interface1_bank_bus_we;
 wire   [31:0] builder_interface1_dat_r;
 reg    [31:0] builder_interface1_dat_w = 32'd0;
 reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
 reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_re = 1'd0;
+reg           builder_interface1_re_next_value2 = 1'd0;
+reg           builder_interface1_re_next_value_ce2 = 1'd0;
 reg           builder_interface1_we = 1'd0;
-reg           builder_interface1_we_next_value2 = 1'd0;
-reg           builder_interface1_we_next_value_ce2 = 1'd0;
+reg           builder_interface1_we_next_value3 = 1'd0;
+reg           builder_interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] builder_interface2_bank_bus_adr;
 reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_re;
 wire          builder_interface2_bank_bus_we;
 reg           builder_locked0 = 1'd0;
 reg           builder_locked1 = 1'd0;
@@ -595,6 +601,7 @@ reg           builder_new_master_wdata_ready0 = 1'd0;
 reg           builder_new_master_wdata_ready1 = 1'd0;
 reg     [1:0] builder_next_state = 2'd0;
 wire          builder_pll_fb;
+wire          builder_re;
 reg     [1:0] builder_refresher_next_state = 2'd0;
 reg     [1:0] builder_refresher_state = 2'd0;
 wire          builder_reset0;
@@ -701,14 +708,14 @@ reg           builder_t_self3 = 1'd0;
 reg           builder_t_self4 = 1'd0;
 reg           builder_t_self5 = 1'd0;
 wire          builder_we;
-wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0;
 wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1;
 wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2;
 wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3;
 wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
@@ -1896,9 +1903,9 @@ reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p0_address;
 wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
 reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_cke;
 reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_odt;
 reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p0_rddata_en;
@@ -1912,9 +1919,9 @@ reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p1_address;
 wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
 reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_cke;
 reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_odt;
 reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p1_rddata_en;
@@ -1928,9 +1935,9 @@ reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p2_address;
 wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
 reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_cke;
 reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_odt;
 reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p2_rddata_en;
@@ -1944,9 +1951,9 @@ reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
 wire   [14:0] main_litedramcore_csr_dfi_p3_address;
 wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
 reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_cke;
 reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_odt;
 reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p3_rddata_en;
@@ -4764,58 +4771,18 @@ always @(*) begin
         main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
-end
+assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt;
 assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector0_command_issue_re) begin
-        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    end
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector0_command_issue_re) begin
-        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
-    end else begin
-        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    end
-end
 always @(*) begin
     main_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4840,28 +4807,28 @@ always @(*) begin
         main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
-assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
-assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
-assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
-assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
-assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
-assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
-    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector1_command_issue_re) begin
-        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
     end else begin
-        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector1_command_issue_re) begin
-        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
+    main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we);
     end else begin
-        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
+assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
+assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
 always @(*) begin
     main_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4886,28 +4853,28 @@ always @(*) begin
         main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
-assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
-assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
-assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
-assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
-assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
-assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
-    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
     end else begin
-        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
+    main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we);
     end else begin
-        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
+assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
+assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
 always @(*) begin
     main_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4932,28 +4899,28 @@ always @(*) begin
         main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
-assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
-assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
-assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
-assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
-assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
-assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
-    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector3_command_issue_re) begin
-        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
     end else begin
-        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
     end
 end
 always @(*) begin
-    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
-    if (main_litedramcore_phaseinjector3_command_issue_re) begin
-        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
+    main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we);
     end else begin
-        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+        main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
+assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
+assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
+assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
 always @(*) begin
     main_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
     if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4978,6 +4945,22 @@ always @(*) begin
         main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    end
+end
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we);
+    end else begin
+        main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+    end
+end
 assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
 assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
@@ -5306,32 +5289,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine0_row_close <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-            main_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine0_state)
@@ -5738,23 +5695,49 @@ always @(*) begin
         end
     endcase
 end
-assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
-assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
-assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
-assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
-assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
-assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
-assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
-assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
-assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
-assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
-assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
-assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
-assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]);
-assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
 always @(*) begin
-    main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
-    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+    main_litedramcore_bankmachine0_row_close <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine0_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
+assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid;
+assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready;
+assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first;
+assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last;
+assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we;
+assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr;
+assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+    if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
         main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7];
     end else begin
         main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
@@ -5877,70 +5860,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine1_source_source_valid) begin
-                    if (main_litedramcore_bankmachine1_row_opened) begin
-                        if (main_litedramcore_bankmachine1_row_hit) begin
-                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine1_trccon_ready) begin
-                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
     case (builder_bankmachine1_state)
@@ -6309,6 +6228,70 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
 assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
 assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
@@ -6449,22 +6432,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6475,11 +6451,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6505,7 +6496,7 @@ always @(*) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
                             if (main_litedramcore_bankmachine2_source_source_payload_we) begin
                             end else begin
-                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
                             end
                         end else begin
                         end
@@ -6517,7 +6508,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6526,6 +6517,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -6536,32 +6530,20 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine2_source_source_valid) begin
-                    if (main_litedramcore_bankmachine2_row_opened) begin
-                        if (main_litedramcore_bankmachine2_row_hit) begin
-                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine2_row_open <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6574,32 +6556,23 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine2_source_source_valid) begin
-                    if (main_litedramcore_bankmachine2_row_opened) begin
-                        if (main_litedramcore_bankmachine2_row_hit) begin
-                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                                main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -6617,10 +6590,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine2_source_source_valid) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
-                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6631,18 +6601,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine2_row_close <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine2_twtpcon_ready) begin
-                main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6657,7 +6627,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_row_open <= 1'd0;
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
         end
@@ -6665,7 +6635,7 @@ always @(*) begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_open <= 1'd1;
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -6683,19 +6653,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6713,7 +6677,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine2_source_source_valid) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
-                            main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -6724,18 +6688,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_row_close <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine2_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -6750,16 +6717,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6772,19 +6739,41 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6795,35 +6784,17 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine2_source_source_valid) begin
-                    if (main_litedramcore_bankmachine2_row_opened) begin
-                        if (main_litedramcore_bankmachine2_row_hit) begin
-                            main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -6836,16 +6807,28 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine2_source_source_valid) begin
+                    if (main_litedramcore_bankmachine2_row_opened) begin
+                        if (main_litedramcore_bankmachine2_row_hit) begin
+                            if (main_litedramcore_bankmachine2_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine2_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -6868,7 +6851,7 @@ always @(*) begin
                     if (main_litedramcore_bankmachine2_row_opened) begin
                         if (main_litedramcore_bankmachine2_row_hit) begin
                             if (main_litedramcore_bankmachine2_source_source_payload_we) begin
-                                main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                                main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -6952,160 +6935,70 @@ assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_
 assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last;
 assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we;
 assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr;
-assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
-assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
-assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
-assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
-assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
-assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
-always @(*) begin
-    builder_bankmachine3_next_state <= 4'd0;
-    builder_bankmachine3_next_state <= builder_bankmachine3_state;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                if (main_litedramcore_bankmachine3_cmd_ready) begin
-                    builder_bankmachine3_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                builder_bankmachine3_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine3_trccon_ready) begin
-                if (main_litedramcore_bankmachine3_cmd_ready) begin
-                    builder_bankmachine3_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
-                builder_bankmachine3_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            builder_bankmachine3_next_state <= 3'd6;
-        end
-        3'd6: begin
-            builder_bankmachine3_next_state <= 2'd3;
-        end
-        3'd7: begin
-            builder_bankmachine3_next_state <= 4'd8;
-        end
-        4'd8: begin
-            builder_bankmachine3_next_state <= 1'd0;
-        end
-        default: begin
-            if (main_litedramcore_bankmachine3_refresh_req) begin
-                builder_bankmachine3_next_state <= 3'd4;
-            end else begin
-                if (main_litedramcore_bankmachine3_source_source_valid) begin
-                    if (main_litedramcore_bankmachine3_row_opened) begin
-                        if (main_litedramcore_bankmachine3_row_hit) begin
-                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
-                                builder_bankmachine3_next_state <= 2'd2;
-                            end
-                        end else begin
-                            builder_bankmachine3_next_state <= 1'd1;
-                        end
-                    end else begin
-                        builder_bankmachine3_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine3_source_source_valid) begin
-                    if (main_litedramcore_bankmachine3_row_opened) begin
-                        if (main_litedramcore_bankmachine3_row_hit) begin
-                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
+assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready;
+assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first;
+assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last;
+assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
 always @(*) begin
-    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    builder_bankmachine3_next_state <= 4'd0;
+    builder_bankmachine3_next_state <= builder_bankmachine3_state;
     case (builder_bankmachine3_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd5;
+                end
+            end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                builder_bankmachine3_next_state <= 3'd5;
+            end
         end
         2'd3: begin
             if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_row_open <= 1'd1;
+                if (main_litedramcore_bankmachine3_cmd_ready) begin
+                    builder_bankmachine3_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+                builder_bankmachine3_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine3_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine3_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine3_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine3_next_state <= 1'd0;
         end
         default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+                builder_bankmachine3_next_state <= 3'd4;
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+                                builder_bankmachine3_next_state <= 2'd2;
+                            end
+                        end else begin
+                            builder_bankmachine3_next_state <= 1'd1;
+                        end
+                    end else begin
+                        builder_bankmachine3_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
@@ -7176,6 +7069,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine3_state)
@@ -7451,6 +7370,70 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+                main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
 assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
@@ -7651,32 +7634,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine4_row_close <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-            main_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine4_state)
@@ -8022,6 +7979,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
 assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
@@ -8153,75 +8136,11 @@ always @(*) begin
                         end else begin
                             builder_bankmachine5_next_state <= 1'd1;
                         end
-                    end else begin
-                        builder_bankmachine5_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine5_source_source_valid) begin
-                    if (main_litedramcore_bankmachine5_row_opened) begin
-                        if (main_litedramcore_bankmachine5_row_hit) begin
-                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
+                    end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
+                    end
+                end
+            end
         end
     endcase
 end
@@ -8593,6 +8512,70 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
 assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
@@ -8733,22 +8716,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -8759,11 +8735,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
@@ -8789,7 +8780,7 @@ always @(*) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
                             if (main_litedramcore_bankmachine6_source_source_payload_we) begin
                             end else begin
-                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
                             end
                         end else begin
                         end
@@ -8801,7 +8792,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
@@ -8810,6 +8801,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -8820,32 +8814,20 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine6_source_source_valid) begin
-                    if (main_litedramcore_bankmachine6_row_opened) begin
-                        if (main_litedramcore_bankmachine6_row_hit) begin
-                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine6_row_open <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -8858,32 +8840,23 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine6_source_source_valid) begin
-                    if (main_litedramcore_bankmachine6_row_opened) begin
-                        if (main_litedramcore_bankmachine6_row_hit) begin
-                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                                main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -8901,10 +8874,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine6_source_source_valid) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
-                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -8915,18 +8885,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine6_row_close <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-                main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -8941,7 +8911,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_row_open <= 1'd0;
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
         end
@@ -8949,7 +8919,7 @@ always @(*) begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_open <= 1'd1;
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -8967,19 +8937,13 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -8997,7 +8961,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine6_source_source_valid) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
-                            main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9008,18 +8972,21 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_row_close <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine6_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9034,16 +9001,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -9056,19 +9023,41 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
         end
         3'd4: begin
+            main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9079,35 +9068,17 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine6_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine6_source_source_valid) begin
-                    if (main_litedramcore_bankmachine6_row_opened) begin
-                        if (main_litedramcore_bankmachine6_row_hit) begin
-                            main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-            end
         end
         3'd4: begin
         end
@@ -9120,16 +9091,28 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine6_source_source_valid) begin
+                    if (main_litedramcore_bankmachine6_row_opened) begin
+                        if (main_litedramcore_bankmachine6_row_hit) begin
+                            if (main_litedramcore_bankmachine6_source_source_payload_we) begin
+                            end else begin
+                                main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine6_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -9152,7 +9135,7 @@ always @(*) begin
                     if (main_litedramcore_bankmachine6_row_opened) begin
                         if (main_litedramcore_bankmachine6_row_hit) begin
                             if (main_litedramcore_bankmachine6_source_source_payload_we) begin
-                                main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                                main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                             end else begin
                             end
                         end else begin
@@ -9304,13 +9287,19 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -9328,10 +9317,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine7_source_source_valid) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
-                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9342,18 +9328,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9394,18 +9380,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9419,34 +9402,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9457,19 +9425,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -9487,9 +9470,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -9511,7 +9497,10 @@ always @(*) begin
                 if (main_litedramcore_bankmachine7_source_source_valid) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -9522,21 +9511,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9551,12 +9541,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -9579,8 +9566,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9592,22 +9579,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9618,11 +9598,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9647,8 +9642,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
-                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9660,7 +9655,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9685,8 +9680,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9698,7 +9693,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9707,6 +9702,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9717,21 +9715,6 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
@@ -9981,97 +9964,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_en0 <= 1'd0;
-    case (builder_multiplexer_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        4'd9: begin
-        end
-        4'd10: begin
-        end
-        default: begin
-            main_litedramcore_en0 <= 1'd1;
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
-    case (builder_multiplexer_state)
-        1'd1: begin
-            if (1'd0) begin
-            end else begin
-                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        4'd9: begin
-        end
-        4'd10: begin
-        end
-        default: begin
-            if (1'd0) begin
-            end else begin
-                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_choose_req_want_reads <= 1'd0;
-    case (builder_multiplexer_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        4'd9: begin
-        end
-        4'd10: begin
-        end
-        default: begin
-            main_litedramcore_choose_req_want_reads <= 1'd1;
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_choose_req_want_writes <= 1'd0;
     case (builder_multiplexer_state)
@@ -10101,13 +9993,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    main_litedramcore_steerer3 <= 2'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
+            end
+            if ((main_litedramcore_rdphase == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
         2'd2: begin
@@ -10129,19 +10023,25 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            main_litedramcore_steerer3 <= 1'd0;
+            if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+                main_litedramcore_steerer3 <= 2'd2;
+            end
+            if ((main_litedramcore_nphases == 2'd3)) begin
+                main_litedramcore_steerer3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_en1 <= 1'd0;
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            main_litedramcore_en1 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -10162,20 +10062,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_steerer3 <= 2'd0;
+    main_litedramcore_en1 <= 1'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            main_litedramcore_steerer3 <= 1'd0;
-            if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-                main_litedramcore_steerer3 <= 2'd2;
-            end
-            if ((main_litedramcore_rdphase == 2'd3)) begin
-                main_litedramcore_steerer3 <= 1'd1;
-            end
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -10196,13 +10095,6 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            main_litedramcore_steerer3 <= 1'd0;
-            if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-                main_litedramcore_steerer3 <= 2'd2;
-            end
-            if ((main_litedramcore_nphases == 2'd3)) begin
-                main_litedramcore_steerer3 <= 1'd1;
-            end
         end
     endcase
 end
@@ -10393,6 +10285,97 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_en0 <= 1'd0;
+    case (builder_multiplexer_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+            main_litedramcore_en0 <= 1'd1;
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    case (builder_multiplexer_state)
+        1'd1: begin
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+            if (1'd0) begin
+            end else begin
+                main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_choose_req_want_reads <= 1'd0;
+    case (builder_multiplexer_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+            main_litedramcore_choose_req_want_reads <= 1'd1;
+        end
+    endcase
+end
 assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
 assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
 assign main_litedramcore_interface_bank0_addr = builder_rhs_self12;
@@ -10484,6 +10467,36 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    builder_interface1_we_next_value3 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_we_next_value3 <= 1'd0;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+            end
+        end
+    endcase
+end
+always @(*) begin
+    builder_interface1_we_next_value_ce3 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_we_next_value_ce3 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_we_next_value_ce3 <= 1'd1;
+            end
+        end
+    endcase
+end
 always @(*) begin
     builder_interface0_dat_r <= 32'd0;
     case (builder_state)
@@ -10509,41 +10522,41 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
+    builder_interface0_ack <= 1'd0;
     case (builder_state)
         1'd1: begin
         end
         2'd2: begin
+            builder_interface0_ack <= 1'd1;
         end
         default: begin
-            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_adr_next_value1 <= 14'd0;
+    builder_interface1_dat_w_next_value_ce0 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
-            end
+            builder_interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    builder_interface0_ack <= 1'd0;
+    builder_interface1_adr_next_value1 <= 14'd0;
     case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
-            builder_interface0_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value1 <= builder_interface0_adr;
+            end
         end
     endcase
 end
@@ -10563,31 +10576,31 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value2 <= 1'd0;
+    builder_interface1_re_next_value2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value2 <= 1'd0;
+            builder_interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+                builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value_ce2 <= 1'd0;
+    builder_interface1_re_next_value_ce2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value_ce2 <= 1'd1;
+            builder_interface1_re_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value_ce2 <= 1'd1;
+                builder_interface1_re_next_value_ce2 <= 1'd1;
             end
         end
     endcase
@@ -10595,28 +10608,28 @@ end
 assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_done0_we <= 1'd0;
+    builder_csrbank0_init_done0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_done0_re <= 1'd0;
+    builder_csrbank0_init_done0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re;
     end
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_error0_re <= 1'd0;
+    builder_csrbank0_init_error0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_error0_we <= 1'd0;
+    builder_csrbank0_init_error0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
@@ -10624,28 +10637,28 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage;
 assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_rst0_re <= 1'd0;
+    builder_csrbank1_rst0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_rst0_we <= 1'd0;
+    builder_csrbank1_rst0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_dly_sel0_we <= 1'd0;
+    builder_csrbank1_dly_sel0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_dly_sel0_re <= 1'd0;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
@@ -10658,66 +10671,66 @@ end
 always @(*) begin
     builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_wlevel_en0_re <= 1'd0;
+    builder_csrbank1_wlevel_en0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_wlevel_en0_we <= 1'd0;
+    builder_csrbank1_wlevel_en0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10728,81 +10741,81 @@ always @(*) begin
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_rdphase0_we <= 1'd0;
+    builder_csrbank1_rdphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_rdphase0_re <= 1'd0;
+    builder_csrbank1_rdphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_wrphase0_re <= 1'd0;
+    builder_csrbank1_wrphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_wrphase0_we <= 1'd0;
+    builder_csrbank1_wrphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage;
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage;
 assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage;
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage;
 assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
     builder_csrbank2_dfii_control0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10821,27 +10834,27 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10854,7 +10867,7 @@ assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w
 always @(*) begin
     builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10863,7 +10876,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
@@ -10873,14 +10886,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10893,7 +10906,7 @@ assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[
 always @(*) begin
     builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10904,15 +10917,15 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0];
@@ -10925,14 +10938,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10941,7 +10954,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
@@ -10951,10 +10964,10 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
@@ -10964,14 +10977,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10990,7 +11003,7 @@ end
 always @(*) begin
     main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0];
@@ -11003,7 +11016,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
@@ -11016,14 +11029,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11032,7 +11045,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
@@ -11042,7 +11055,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0];
@@ -11055,27 +11068,27 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0];
 always @(*) begin
     builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11094,14 +11107,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11110,11 +11123,11 @@ always @(*) begin
         builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11127,7 +11140,7 @@ assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
 assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage;
 assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
 assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
 assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
@@ -11136,11 +11149,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
 assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
 assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage;
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage;
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage;
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status;
 assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
 assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
@@ -11150,11 +11163,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
 assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
 assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage;
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage;
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage;
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status;
 assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
 assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
@@ -11164,11 +11177,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
 assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
 assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage;
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage;
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage;
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status;
 assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
 assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
@@ -11178,19 +11191,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
 assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
 assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage;
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage;
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage;
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status;
 assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_adr = builder_interface1_adr;
+assign builder_re = builder_interface1_re;
 assign builder_we = builder_interface1_we;
 assign builder_dat_w = builder_interface1_dat_w;
 assign builder_interface1_dat_r = builder_dat_r;
 assign builder_interface0_bank_bus_adr = builder_adr;
 assign builder_interface1_bank_bus_adr = builder_adr;
 assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_re = builder_re;
+assign builder_interface1_bank_bus_re = builder_re;
+assign builder_interface2_bank_bus_re = builder_re;
 assign builder_interface0_bank_bus_we = builder_we;
 assign builder_interface1_bank_bus_we = builder_we;
 assign builder_interface2_bank_bus_we = builder_we;
@@ -11916,16 +11933,16 @@ always @(*) begin
     builder_self0 <= 3'd0;
     case (main_litedramcore_steerer0)
         1'd0: begin
-            builder_self0 <= main_litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12035,16 +12052,16 @@ always @(*) begin
     builder_self7 <= 3'd0;
     case (main_litedramcore_steerer1)
         1'd0: begin
-            builder_self7 <= main_litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12154,16 +12171,16 @@ always @(*) begin
     builder_self14 <= 3'd0;
     case (main_litedramcore_steerer2)
         1'd0: begin
-            builder_self14 <= main_litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12273,16 +12290,16 @@ always @(*) begin
     builder_self21 <= 3'd0;
     case (main_litedramcore_steerer3)
         1'd0: begin
-            builder_self21 <= main_litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12388,10 +12405,10 @@ always @(*) begin
         end
     endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -13990,8 +14007,11 @@ always @(posedge sys_clk) begin
     if (builder_interface1_adr_next_value_ce1) begin
         builder_interface1_adr <= builder_interface1_adr_next_value1;
     end
-    if (builder_interface1_we_next_value_ce2) begin
-        builder_interface1_we <= builder_interface1_we_next_value2;
+    if (builder_interface1_re_next_value_ce2) begin
+        builder_interface1_re <= builder_interface1_re_next_value2;
+    end
+    if (builder_interface1_we_next_value_ce3) begin
+        builder_interface1_we <= builder_interface1_we_next_value3;
     end
     builder_interface0_bank_bus_dat_r <= 1'd0;
     if (builder_csrbank0_sel) begin
@@ -14061,11 +14081,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
     if (builder_csrbank1_dly_sel0_re) begin
-        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+        main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r;
     end
     main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
     if (builder_csrbank1_half_sys8x_taps0_re) begin
-        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+        main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r;
     end
     main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
     if (builder_csrbank1_wlevel_en0_re) begin
@@ -14073,11 +14093,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
     if (builder_csrbank1_rdphase0_re) begin
-        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+        main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r;
     end
     main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
     if (builder_csrbank1_wrphase0_re) begin
-        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+        main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r;
     end
     main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
     builder_interface2_bank_bus_dat_r <= 1'd0;
@@ -14161,74 +14181,74 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (builder_csrbank2_dfii_control0_re) begin
-        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+        main_litedramcore_storage <= builder_csrbank2_dfii_control0_r;
     end
     main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
     if (builder_csrbank2_dfii_pi0_command0_re) begin
-        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
+        main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r;
     end
     main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
     if (builder_csrbank2_dfii_pi0_address0_re) begin
-        main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r;
+        main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r;
     end
     main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
     if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+        main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
     main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
     if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+        main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
     main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
     main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
     if (builder_csrbank2_dfii_pi1_command0_re) begin
-        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
+        main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r;
     end
     main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
     if (builder_csrbank2_dfii_pi1_address0_re) begin
-        main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r;
+        main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r;
     end
     main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
     if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+        main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
     main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
     if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+        main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
     main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
     main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
     if (builder_csrbank2_dfii_pi2_command0_re) begin
-        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
+        main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r;
     end
     main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
     if (builder_csrbank2_dfii_pi2_address0_re) begin
-        main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r;
+        main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r;
     end
     main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
     if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+        main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
     main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
     if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+        main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
     main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
     main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
     if (builder_csrbank2_dfii_pi3_command0_re) begin
-        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
+        main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r;
     end
     main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
     if (builder_csrbank2_dfii_pi3_address0_re) begin
-        main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r;
+        main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r;
     end
     main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
     if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+        main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
     main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
     if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+        main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
     main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
     main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
@@ -14501,6 +14521,7 @@ always @(posedge sys_clk) begin
         main_init_done_re <= 1'd0;
         main_init_error_storage <= 1'd0;
         main_init_error_re <= 1'd0;
+        builder_interface1_re <= 1'd0;
         builder_interface1_we <= 1'd0;
         builder_refresher_state <= 2'd0;
         builder_bankmachine0_state <= 4'd0;
@@ -17483,7 +17504,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
@@ -17501,7 +17522,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (iodelay_rst)
@@ -17519,7 +17540,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
@@ -17537,7 +17558,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (sys_rst)
@@ -17555,7 +17576,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
@@ -17573,7 +17594,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
@@ -17591,7 +17612,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
@@ -17609,7 +17630,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
@@ -17618,5 +17639,5 @@ FDPE #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:07.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:41.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init
index 51e4b9f..e9bf793 100644
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.init
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842acc83c4c0001
+3c4c000100000000
+7c0802a63842ada4
+f821ffc148002815
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+000000004800282c
+0000038001000000
+3842ad503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48002101f9410108
+48002149f9410108
 7c7f1b7860000000
-48001b5138610020
+48001ba538610020
 382100b060000000
-480027747fe3fb78
+480027d47fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,927 +552,938 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842ac2c
-480026ad7d600026
-f821fed191610008
-6000000048001b4d
-38637b203c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842acb4
+480027097d600026
+f821fec191610008
+6000000048001ba1
+38637af83c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637b403be00008
+38637b183be00008
 4bffff1d67ffc000
-38637b603c62ffff
+38637b383c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637b78
+4bfffef538637b50
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637b80
+4bfffedd38637b58
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b88
+4bfffec538637b60
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b90
+4bfffead38637b68
 4182001073e90010
-38637ba03c62ffff
+38637b783c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637bb0
-3b7b7bb83f62ffff
-4bfffe757f63db78
+4bfffe8538637b88
+3b397b903f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637bc07884b582
+38637b987884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637bd8
+4bfffe2d38637bb0
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637bf0
+4bfffe0d38637bc8
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637c087c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637c2857c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637be07c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637c0057e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637c48
-4082009073a90002
-38637c683c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637c20
+4082006473c90002
+38637c403c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637c80
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637c907b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637cc038847cb0
-48000b794bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637ce03c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637c50
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637cf8
-38a000403c9af000
+4bfffc2d38637cf0
+38a000403c9cf000
 3861007078840020
-6000000048001841
+6000000048001975
 3d200002e9410070
 6129464c3c62ffff
-792983e438637d10
+792983e438637d08
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637d303c62ffff
-892100774bfffae9
+38637d283c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d9088810070
+38637d8888810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637dc0
-3880600038a00000
-6484ff0060a5a000
-4800179d3c604000
+3c62ffff4bfffb99
+4bfffb8d38637db8
+3880f80338a00000
+7884682860a5a000
+480018d13c604000
 3c62ffff60000000
-4bfffa8538637de0
-4bffff184bfffafd
+4bfffb6538637dd8
+480002184bfffbdd
 3f22ffffebe10090
-3b397d483ba00000
-a12100a87ffafa14
+3b397d403ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637d70
-e86100884bfffac5
+4bfffb2d38637d68
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-480021cc7d638120
+8161000838210140
+480023087d638120
 38a000383c9ff000
 386100b078840020
-6000000048001721
+6000000048001855
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-60000000480016d9
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+600000004800180d
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637c58
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637c60
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
 38637c783c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637c887b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637cb838847ca8
+480009ad4bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637cd83c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920100400000000
+7c0004ac6529c800
+394010087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-6529c80039201004
-7c604f2a7c0004ac
-3920000139401008
-7c0004ac654ac800
-4e8000207d20572a
-0000000000000000
-3d40555500000000
-614a55555469f87e
-7c6918507d295038
-612933333d203333
-5463f0be7d2a1838
-7d4a1a147c634838
-7d2952145549e13e
-614a0f0f3d400f0f
-552ac23e7d295038
-5523843e7d2a4a14
-786306a07c634a14
-000000004e800020
+5469f87e3d405555
+7d295038614a5555
+3d2033337c691850
+7d2a183861293333
+7c6348385463f0be
+5549e13e7d4a1a14
+3d400f0f7d295214
+7d295038614a0f0f
+7d2a4a14552ac23e
+7c634a145523843e
+4e800020786306a0
 0000000000000000
-3842a5903c4c0001
-48001fed7c0802a6
-3b400001f821ff31
-7f5a183023a30007
-3aa000033ec2ffff
-3b0010103b20100c
-3a6010183a801014
-3bc0000020630003
-3ad67ed83b600000
-3ae0000166b58020
+3c4c000100000000
+7c0802a63842a5c4
+f821ff3148001ffd
+23a300033b400001
+600000007f5a1830
+3b20100c3ea0e008
+206300073b001010
+3bc000003a80103c
+3ac2803c3b600000
+3ae000017ab51020
 6718c8006739c800
-6673c8006694c800
 7c7f07b47fbd07b4
-38e100207bc91764
-7cfc3b7838a00002
-390000007d56482e
-7949f86248000044
-7d4a00d0794a07e0
-7d494a787d4aa838
-552907fe7d2a4b78
-38c600017d293030
-7d244b787d292378
-7d2741ae4200ffd4
-2828000839080001
-3920000841820018
-7d2903a638800000
-4bffffb038c00000
-38e7000828050001
-38a000014182000c
-392000004bffff94
-7d20cf2a7c0004ac
-7d20c72a7c0004ac
-4bfffe6538600009
-4bfffe413860000f
-3901001f38e00004
-392000047ce903a6
-8ce8000139400000
-7947400c3929ffff
-4200fff07cea3b78
-7ce0a72a7c0004ac
-3901002338e00004
-394000047ce903a6
-394affff8ce80001
-7ce93b787927400c
-7c0004ac4200fff0
-38e000047ce09f2a
-7ce903a639010027
-8ce8000139200004
-7947400c3929ffff
-4200fff07cea3b78
-6508c80039001034
+7bc917646694c800
+38a0000238e10020
+7d56482e7cfc3b78
+4800004439000000
+794a07e07949f862
+7d4aa8387d4a00d0
+7d2a4b787d494a78
+7d293030552907fe
+7d29237838c60001
+4200ffd47d244b78
+390800017d2741ae
+4182001828280008
+3880000039200008
+38c000007d2903a6
+280500014bffffb0
+4182000c38e70008
+4bffff9438a00001
+7c0004ac39200000
+7c0004ac7d20cf2a
+386000097d20c72a
+3860000f4bfffe6d
+38e000044bfffe49
+7ce903a63901001f
+3940000039200004
+3929ffff8ce80001
+7cea3b787947400c
+390010144200fff0
+7c0004ac6508c800
+38e000047ce0472a
+7ce903a639010023
+8ce8000139400004
+7927400c394affff
+4200fff07ce93b78
+6508c80039001018
 7ce0472a7c0004ac
-3941002b39000004
-8d0a00017d0903a6
-7d0943787928400c
-394010384200fff4
-7c0004ac654ac800
-3920102c7d00572a
-6529c8003a400000
-7e404f2a7c0004ac
-6529c80039201030
-7e404f2a7c0004ac
-3920001739401024
-7c0004ac654ac800
-392010287d20572a
-7c0004ac6529c800
-3860000f7ee04f2a
-392008144bfffd35
+3901002738e00004
+392000047ce903a6
+3929ffff8ce80001
+7cea3b787947400c
+390010344200fff0
+7c0004ac6508c800
+390000047ce0472a
+7d0903a63941002b
+7928400c8d0a0001
+4200fff47d094378
+654ac80039401038
+7d00572a7c0004ac
+3a6000003920102c
 7c0004ac6529c800
-7c0004ac7ee04f2a
-7c0004ac7e40cf2a
-386000257e40c72a
-3860000f4bfffd29
-7c0004ac4bfffd05
-7c0004ac7e40cf2a
-3860000b7e40c72a
-4bfffd057e3cea14
-39c000003860000f
-7e2f8b784bfffcdd
-3920101c7f9cfa14
+392010307e604f2a
 7c0004ac6529c800
-38e000047d404e2a
-7ce903a6794a0020
-9d48ffff39010034
-4200fff8794ac202
-7c0004ac39290004
-394100347d204e2a
-7d20552c88710000
-7c634a78892f0010
-4bfffcd15463063e
-3a3100087d3d8850
-7c69f8ae7c701b78
-7c634a78893c0010
-4bfffcb15463063e
-7c6382142c0e0000
-418200407e521a14
+394010247e604f2a
+654ac80039200017
+7d20572a7c0004ac
+6529c80039201028
+7ee04f2a7c0004ac
+4bfffd2d3860000f
+6529c80039200814
+7ee04f2a7c0004ac
+7e60cf2a7c0004ac
+7e60c72a7c0004ac
+4bfffd2138600025
+4bfffcfd3860000f
+7e60cf2a7c0004ac
+7e60c72a7c0004ac
+7e5cea143860000b
+3860000f4bfffcfd
+4bfffcd539e00000
+7f9cfa143920101c
+7e5193786529c800
+7d404e2a7c0004ac
+794a002038e00004
+390100347ce903a6
+794ac2029d48ffff
+392900044200fff8
+7d204e2a7c0004ac
+7d20552c39410034
+3a5200087d3d9050
+893c00107c69f8ae
+5463063e7c634a78
+893100104bfffcc1
+8872fff87c701b78
+5463063e7c634a78
+2c0f00014bfffca9
+7c6382147e89a378
+408200407e731a14
 6529c80039200818
 7d204e2a7c0004ac
 2c0900007f494838
-3a52000140820008
-7f7b92143bde0001
-4082fd3c283e0003
+3a73000140820008
+7f7b9a143bde0001
+4082fd28283e0003
 7f6307b4382100d0
-39c0000148001d10
-4bffff3c3920103c
-0100000000000000
-3c4c000100001280
-7c0802a63842a23c
-48001cbd38800000
-3f02fffff821ff61
-7c7d1b783b186528
-3b8000003bc00000
-4800083d7f05c378
-7fa3eb7860000000
-2c0300004bfffc79
-57ffd97e7c7f0034
-2c1c000040820068
-3bfeffff41820060
-7ffcfb787ff9fb78
-7fa3eb787fdbf378
-4bfffc453b5b0001
-408200702c030000
-7d5fe0507d39d850
-418100687c095000
-4181006c2c1a0007
-38a564e03ca2ffff
+39e0000148001d14
+000000004bffff40
+0000118001000000
+3842a2683c4c0001
+388000007c0802a6
+f821ff6148001cc1
+3b1864f43f02ffff
+3bc000007c7d1b78
+7f05c3783b800000
+6000000048000835
+4bfffc717fa3eb78
+7c7f00342c030000
+4082006857ffd97e
+418200602c1c0000
+7ff9fb783bfeffff
+7fdbf3787ffcfb78
+3b5b00017fa3eb78
+2c0300004bfffc3d
+7d39d85040820070
+7c0950007d5fe050
+2c1a000741810068
+3ca2ffff4181006c
+3880000038a564ac
+7f5bd3787fa3eb78
+60000000480007bd
+3bde00014bffffb8
+418200242c1e0008
+38a564ac3ca2ffff
 7fa3eb7838800000
-480007c57f5bd378
-4bffffb860000000
-2c1e00083bde0001
-3ca2ffff41820024
-3880000038a564e0
-7ffcfb787fa3eb78
-6000000048000799
-3be0ffff4bffff5c
-7f59d3784bffff78
-7f7cdb784bffffa0
-4bffff947f3fcb78
-408000242c1c0000
-3b8000007fc907b4
-2c29000021290007
-239e000741800008
-7f9cf2143bde0001
-4080001c2c1f0000
-38637df83c62ffff
-600000004bfff449
-48001bdc382100a0
-7c9cfa147cbfe050
-7ca501947ca50e70
-3c62ffff789bff62
-7f64db787ca507b4
-3be0000838637e08
-600000004bfff411
-388000007f05c378
-3bc000007fa3eb78
-60000000480006e9
-4bfffa6938600064
-418100247c1bf000
-4bfffb157fa3eb78
-4182ff942c030000
-2c1f00003bffffff
-4bffff844082ffc0
-38a564e03ca2ffff
+480007917ffcfb78
+4bffff5c60000000
+4bffff783be0ffff
+4bffffa07f59d378
+7f3fcb787f7cdb78
+2c1c00004bffff94
+2c1e00084080001c
+418200083b800000
+3bde0001239e0007
+2c1f00007f9cf214
+3c62ffff4080001c
+4bfff3f538637df0
+382100a060000000
+7cbfe05048001be8
+7ca50e707c9fe214
+789bff627ca50194
+7ca507b43c62ffff
+38637e007f64db78
+4bfff3bd3be00008
+7f05c37860000000
 7fa3eb7838800000
-4800069d3bde0001
+480006e93bc00000
 3860006460000000
-4bffffb44bfffa1d
+7c1bf0004bfffa69
+7fa3eb7841810024
+2c0300004bfffb15
+3bffffff4182ff94
+4082ffc02c1f0000
+3ca2ffff4bffff84
+3880000038a564ac
+3bde00017fa3eb78
+600000004800069d
+4bfffa1d38600064
+000000004bffffb4
+0000088001000000
+3842a0803c4c0001
+6529c80039201000
+7d404e2a7c0004ac
+4d820020280a000e
+3940000e7c0802a6
+f821ffa1f8010010
+7d404f2a7c0004ac
+38637e183c62ffff
+600000004bfff2f9
+e801001038210060
+4e8000207c0803a6
 0100000000000000
-3c4c000100000880
-392010003842a04c
+3c4c000100000080
+392010003842a01c
 7c0004ac6529c800
-280a000e7d404e2a
+280a00017d404e2a
 7c0802a64d820020
-f80100103940000e
+f801001039400001
 7c0004acf821ffa1
 3c62ffff7d404f2a
-4bfff34d38637e20
+4bfff29538637e40
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-38429fe83c4c0001
-6529c80039201000
-7d404e2a7c0004ac
-4d820020280a0001
-394000017c0802a6
-f821ffa1f8010010
-7d404f2a7c0004ac
-38637e483c62ffff
-600000004bfff2e9
-e801001038210060
-4e8000207c0803a6
-0100000000000000
-3c4c000100000080
-7c0802a638429f84
-f821ff31480019f5
-3b1865b03f02ffff
-3ea2ffff3ec2ffff
-3ee2ffff3e82ffff
-3b4000003e62ffff
-3ab57e803ad67e70
-3af77bb83a947e88
-7f5f07b43a737e90
-388000007f05c378
-4800055d7fe3fb78
-3b60000060000000
-3bc000003b800000
-7fdbf37848000030
-418200e42c1e0003
-38a565683ca2ffff
-7fe3fb7838800000
-7fbceb783bde0001
-6000000048000521
-7fe4fb787fc507b4
-3b2000087ec3b378
-600000004bfff219
-38a565283ca2ffff
+38429fb83c4c0001
+48001a017c0802a6
+3f02fffff821ff31
+3ec2ffff3b18657c
+3e82ffff3ea2ffff
+3e62ffff3ee2ffff
+3ad67e683b400000
+3a947e803ab57e78
+3a737e883af77b90
+7f05c3787f5f07b4
 7fe3fb7838800000
-480004ed3ba00000
-7fe3fb7860000000
-394000004bfff929
-212300c07c640034
+600000004800055d
+3b8000003b600000
+480000303bc00000
+2c1e00037fdbf378
+3ca2ffff418200e4
+3880000038a56534
+3bde00017fe3fb78
+480005217fbceb78
+7fc507b460000000
+7ec3b3787fe4fb78
+4bfff1c53b200008
+3ca2ffff60000000
+3880000038a564f4
+3ba000007fe3fb78
+60000000480004ed
+4bfff9297fe3fb78
+7c64003439200000
 2c0400005484d97e
-3940060041820008
-788407e07d295214
-7fbd4a147ea3ab78
-600000004bfff1c1
-38a564e03ca2ffff
-7fe3fb7838800000
-6000000048000499
-4082ffa83739ffff
-4bfff1957e83a378
-7fe3fb7860000000
-7ee3bb784bfffc15
-600000004bfff181
-4180ff207c1ce840
-4bffff1c7f9de378
-7fe4fb787f6507b4
-3bc000007e639b78
-600000004bfff159
-388000007f05c378
-480004357fe3fb78
-7c1ed80060000000
-7fe3fb7841800028
-7ee3bb784bfffbbd
-600000004bfff129
-4082002c2c1a0000
-4bfffe983b400001
-38a565683ca2ffff
+3920060041820008
+788407e0206300c0
+7ea3ab787d291a14
+4bfff16d7fbd4a14
+3ca2ffff60000000
+3880000038a564ac
+480004997fe3fb78
+3739ffff60000000
+7e83a3784082ffa8
+600000004bfff141
+4bfffc1d7fe3fb78
+4bfff12d7ee3bb78
+7c1ce84060000000
+7f9de3784180ff20
+7f6507b44bffff1c
+7e639b787fe4fb78
+4bfff1053bc00000
+7f05c37860000000
 7fe3fb7838800000
-480003ed3bde0001
-4bffffb860000000
-48001878382100d0
-0100000000000000
-3c4c000100000d80
-7c0802a638429d9c
-fbe1fff8fbc1fff0
-f821ff91f8010010
-3fc2ffff4bfffd3d
-388000003bde6528
-7fc5f37838600000
-6000000048000399
-3bff65b03fe2ffff
+6000000048000435
+408200307c1ed800
+4bfffbc57fe3fb78
+4bfff0d57ee3bb78
+393a000160000000
+2c0900023b400001
+382100d04082fe98
+3ca2ffff480018a4
+3880000038a56534
+3bde00017fe3fb78
+60000000480003e5
+000000004bffffb0
+00000d8001000000
+38429dd03c4c0001
+fbc1fff07c0802a6
+f8010010fbe1fff8
+4bfffd3df821ff91
+3bde64f43fc2ffff
 3860000038800000
-4800037d7fe5fb78
-7fc5f37860000000
+480003997fc5f378
+3fe2ffff60000000
+388000003bff657c
+7fe5fb7838600000
+600000004800037d
+388000007fc5f378
+4800036938600001
+7fe5fb7860000000
 3860000138800000
-6000000048000369
-388000007fe5fb78
-4800035538600001
-3c62ffff60000000
-4bfff05538637ea8
-4bfffd9160000000
-382100704bfffd29
-4800180838600001
-0100000000000000
-3c4c000100000280
-7c0802a638429cec
-3c8040003c62ffff
-4800176d38637eb8
-3f60c800f821ff71
-7b7b00203be00000
+6000000048000355
+38637ea03c62ffff
 600000004bfff001
-7c0004ac4bfffc75
-3b4000047fe0df2a
-7c0004ac675ac800
-3ba0100c7fe0d72a
-7c0004ac67bdc800
-3bc010107fe0ef2a
-7c0004ac67dec800
-3b8010007fe0f72a
-679cc8003920000c
-7d20e72a7c0004ac
-6063c35038600000
-7c0004ac4bfff61d
-7c0004ac7fe0ef2a
-3920000e7fe0f72a
-7d20e72a7c0004ac
-4bfff5f938602710
-7c0004ac39200200
-392000027d20ef2a
-7d20f72a7c0004ac
-4bfff5f53860000f
+4bfffd294bfffd91
+3860000138210070
+0000000048001814
+0000028001000000
+38429d203c4c0001
+3c62ffff7c0802a6
+38637eb03c804000
+f821ff7148001779
+3be000003b600019
+4bffefad7b7bd800
+4bfffc7560000000
+7fe0df2a7c0004ac
+675ac8003b400004
+7fe0d72a7c0004ac
+67bdc8003ba0100c
 7fe0ef2a7c0004ac
-7c0004ac39200003
-3860000f7d20f72a
-392000064bfff5d9
+67dec8003bc01010
+7fe0f72a7c0004ac
+3920000c3b801000
+7c0004ac679cc800
+386000007d20e72a
+4bfff61d6063c350
+7fe0ef2a7c0004ac
+7fe0f72a7c0004ac
+7c0004ac3920000e
+386027107d20e72a
+392002004bfff5f9
 7d20ef2a7c0004ac
-7c0004ac3b800001
-3860000f7f80f72a
-392003204bfff5b9
+7c0004ac39200002
+3860000f7d20f72a
+7c0004ac4bfff5f5
+392000037fe0ef2a
+7d20f72a7c0004ac
+4bfff5d93860000f
+7c0004ac39200006
+3b8000017d20ef2a
+7f80f72a7c0004ac
+4bfff5b93860000f
+7c0004ac39200320
+7c0004ac7d20ef2a
+3860000f7fe0f72a
+386000c84bfff59d
+392004004bfff579
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bfff59d3860000f
-4bfff579386000c8
-7c0004ac39200400
-7c0004ac7d20ef2a
-386000037fe0f72a
-386000c84bfff579
-4bfffe014bfff555
-3c8000204bfffbb1
-480008ad3c604000
-2c03000060000000
-7c691b7840820024
-7f80d72a7c0004ac
+4bfff57938600003
+4bfff555386000c8
+4bfffbb14bfffe01
+3c6040003c800020
+60000000480008ad
+408200242c030000
+7c0004ac7c691b78
+7c0004ac7f80d72a
+382100907f80df2a
+4800164c7d2307b4
+38a0000038c00000
+3c6040003c800020
+6000000048000635
 7f80df2a7c0004ac
-7d2307b438210090
-38c0000048001640
-3c80002038a00000
-480006353c604000
-7c0004ac60000000
-392000017f80df2a
-000000004bffffd0
-0000068001000000
-38429b203c4c0001
-7863176460000000
-7d2a182e394280a8
-5529077e39290001
-394008087d2a192e
-654ac80039200001
-7d20572a7c0004ac
-000000004e800020
+4bffffd039200001
+0100000000000000
+3c4c000100000680
+6000000038429b54
+3942809878631764
+392900017d2a182e
+7d2a192e5529077e
+3920000139400808
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
-38429ad83c4c0001
-7863176460000000
-39400000392280a8
-394008047d49192e
-654ac80039200001
-7d20572a7c0004ac
-000000004e800020
+3c4c000100000000
+6000000038429b0c
+3922809878631764
+7d49192e39400000
+3920000139400804
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
-38429a983c4c0001
-7863176460000000
-7d2a182e394280a0
-552907be39290001
-394008107d2a192e
-654ac80039200001
-7d20572a7c0004ac
-000000004e800020
+3c4c000100000000
+6000000038429acc
+3942809078631764
+392900017d2a182e
+7d2a192e552907be
+3920000139400810
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
-38429a503c4c0001
-7863176460000000
-39400000392280a0
-3940080c7d49192e
-654ac80039200001
-7d20572a7c0004ac
-000000004e800020
+3c4c000100000000
+6000000038429a84
+3922809078631764
+7d49192e39400000
+392000013940080c
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
-3940000039200800
-7c0004ac6529c800
-390000ff7d404f2a
-7d004f2a7c0004ac
+3920080000000000
+6529c80039400000
 7d404f2a7c0004ac
-000000004e800020
+7c0004ac390000ff
+7c0004ac7d004f2a
+4e8000207d404f2a
 0000000000000000
-384299d83c4c0001
-392000017c0802a6
-fbe1fff8fbc1fff0
-7c7f1b7839400800
-7cac2b787c9e2378
-654ac8007d291830
-f821ffd1f8010010
-7d20572a7c0004ac
-f84100187ca903a6
-e84100184e800421
-7fc4f37838210030
-e80100107fe3fb78
-ebe1fff8ebc1fff0
-4bffff5c7c0803a6
-0100000000000000
-3c4c000100000280
-7c0802a63842995c
-f8010010282303ff
-41810028f821ffa1
-3c62ffff7c641b78
-4bffec7538637ee8
-3821006060000000
-7c0803a6e8010010
-3d2000104e800020
-408000287c234840
-39200066786505a0
-7864b2827ca54b92
-38637ef03c62ffff
-600000004bffec39
-3d2040004bffffc4
-7c23484078646502
-7863b28240800024
-7d29185078895564
-3c62ffff38a00066
-38637f007ca92b92
-786317824bffffc8
-7865556439200066
-7c641b787ca52050
-7ca54b923c62ffff
-4bffffa438637f10
-0100000000000000
-3c4c000100000080
-7c0802a63842988c
-7cc42a14fbe1fff8
-7c8523787cbf2b78
+3c4c000100000000
+7c0802a638429a0c
+fbc1fff039200001
+39400800fbe1fff8
+7c9e23787c7f1b78
+7d2918307cac2b78
+f8010010654ac800
+7c0004acf821ffd1
+7ca903a67d20572a
+4e800421f8410018
+38210030e8410018
+7fe3fb787fc4f378
+ebc1fff0e8010010
+7c0803a6ebe1fff8
+000000004bffff5c
+0000028001000000
+384299903c4c0001
+282303ff7c0802a6
+f821ffa1f8010010
+7c641b7841810028
+38637ed03c62ffff
+600000004bffec21
+e801001038210060
+4e8000207c0803a6
+7c2348403d200010
+786505a040800028
+7ca54b9239200066
+3c62ffff7864b282
+4bffebe538637ed8
+4bffffc460000000
+786465023d204000
+408000247c234840
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637ee8
+3920006678631782
+7ca5205078655564
 3c62ffff7c641b78
-38637f2078c60020
-f821ff91f8010010
-600000004bffeb99
-4bfffef97fe3fb78
-38637f303c62ffff
-600000004bffeb81
-4800134438210070
-0100000000000000
-2c24000000000180
-7869f84241820024
-7c6300d0786307e0
-5463028054630794
-786300207c634a78
-386300014e800020
-000000004bfffff4
-0000000000000000
-384297e83c4c0001
-788407647c0802a6
-7c691b783d40aaaa
-4800126d614aaaaa
-7884f0827f832214
-39040001f821ffc1
-7d0903a67c7f1b78
-420000807c7d1b78
-600000004bffeb55
-3d00aaaa7d3fe050
-7feafb787929f082
-3bc0000039290001
-6108aaaa7d2903a6
-7d3fe05042000060
-7929f0823d005555
+38637ef87ca54b92
+000000004bffffa4
+0000008001000000
+384298c03c4c0001
+fbe1fff87c0802a6
+7cbf2b787cc42a14
+7c641b787c852378
+78c600203c62ffff
+f801001038637f08
+4bffeb45f821ff91
+7fe3fb7860000000
+3c62ffff4bfffef9
+4bffeb2d38637f18
+3821007060000000
+0000000048001350
+0000018001000000
+418200242c240000
+786307e07869f842
+546307947c6300d0
+7c634a7854630280
+4e80002078630020
+4bfffff438630001
+0000000000000000
+3c4c000100000000
+7c0802a63842981c
+3d40aaaa78840764
+614aaaaa7c691b78
+7f83221448001279
+f821ffc17884f082
+7c7f1b7839040001
+7c7d1b787d0903a6
+4bffeb0142000080
+7d3fe05060000000
+7929f0823d00aaaa
 392900017feafb78
-7d2903a661085555
-7fffe05042000058
-600000004bffeb05
-3d2055557bfff082
-61295555395f0001
-420000407d4903a6
-7fc307b438210040
-9149000048001220
-4bffff7839290004
-7c094000812a0000
+7d2903a63bc00000
+420000606108aaaa
+3d0055557d3fe050
+7feafb787929f082
+6108555539290001
+420000587d2903a6
+4bffeab17fffe050
+7bfff08260000000
+395f00013d205555
+7d4903a661295555
+3821004042000040
+4800122c7fc307b4
+3929000491490000
+812a00004bffff78
+418200087c094000
+394a00043bde0001
+910a00004bffff8c
+4bffffa0394a0004
+7c0a4800815d0000
 3bde000141820008
-4bffff8c394a0004
-394a0004910a0000
-815d00004bffffa0
-418200087c0a4800
-3bbd00043bde0001
-000000004bffffac
-0000048001000000
-384296d83c4c0001
-7c0802a67d600026
-2e26000091610008
-f821ff4148001145
-7cba2b787c7f1b78
-789cf0827cde3378
-81260004419200c0
-2c09000082e60000
-3f02ffff40820044
-3b6000013ba00000
-3b187f387bf90020
-4082009c7c3ce840
+4bffffac3bbd0004
+0100000000000000
+3c4c000100000480
+7d6000263842970c
+916100087c0802a6
+480011512e260000
+7c7f1b78f821ff41
+7cde33787cba2b78
+419200e4789cf082
+82e6000081260004
+418200d82c090000
+600000004bffe9ed
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3ce840
+2c170000408200c4
+3c62ffff41820028
+38637f307b051028
+4bfffdcd7be40020
+38637b903c62ffff
+600000004bffe931
+7f2307b4382100c0
+7d61812081610008
+7b6300204800110c
+4bfffdfd7f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7f03c3787f24cb78
+3bbd00014bfffd79
+4082ffc87c3ce840
 7b8510283c62ffff
-7be4002038637f38
-3c62ffff4bfffde5
-4bffe99d38637bb8
-4bffea0160000000
-2d97000060000000
-3ba000007ffbfb78
-3b2000003ac00001
-7c3de0407bf50020
-408200847fb8eb78
-418200282c170000
-7b0510283c62ffff
-7be4002038637f48
-3c62ffff4bfffd8d
-4bffe94538637bb8
-382100c060000000
-816100087f2307b4
-480010c07d618120
-4bffff503ae00001
-7f44d3787b630020
-7ba917644bfffdb5
-73a97fff7c7f492e
-408200147c7b1b78
-7f24cb787ba51028
-4bfffd317f03c378
-4bffff2c3bbd0001
-7ac300207f44d378
-809b00004bfffd7d
-7c761b787c651b78
-4182003c7c032040
-419200343b390001
-2c2c0000e99e0008
-7d8903a641820028
-78840020e8de0010
-7b630020f8410018
-e84100184e800421
-4082ff582c030000
-4082001c73187fff
-3c62ffff418e0018
-7ea4ab787ba51028
-4bfffcb138637f48
-3b7b00043bbd0001
-000000004bfffef4
-00000b8003000000
-384295183c4c0001
-7c0802a67d708026
-48000f9d91610008
-7cdb3378f821ff71
-2e3b00003ba4ffe0
-7c9e23787c7f1b78
-7c641b787fa3ea14
+7be4002038637f20
+3c62ffff4bfffd59
+4bffe8bd38637b90
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187f207bf90020
+7f44d3784bffffb8
+4bfffd7d7ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73187fff4082ff18
+418e00184082001c
+7ba510283c62ffff
+38637f307ea4ab78
+3bbd00014bfffcb1
+4bfffeb43b7b0004
+0300000000000000
+3c4c000100000b80
+7d7080263842954c
+916100087c0802a6
+f821ff7148000fa9
+3ba4ffe07cdb3378
+7c7f1b782e3b0000
+7fa3ea147c9e2378
+3c62ffff7c641b78
+7cbc2b7838637f40
+600000004bffe7c1
 38637f583c62ffff
-4bffe8157cbc2b78
-3c62ffff60000000
-4092000c38637f70
-38637f803c62ffff
-600000004bffe7f9
-4bfffb597fc3f378
+3c62ffff4092000c
+4bffe7a538637f68
+7fc3f37860000000
+3c62ffff4bfffb59
+4bffe78d38637f78
+2c3c000060000000
+7cf602a6408200a8
+38bd002038df0020
+7d3fe8507c262840
+7feafb787929d942
+392900013900ffff
+3920000140810008
+f90a00002c290001
+f90a00083929ffff
+f90a0018f90a0010
+4082ffe4394a0020
+3f8002dc7d3602a6
+639c6c0078ea0020
+7f9ee1d279290020
+3c62ffff7d295050
+7f9c4b9238637f80
+600000004bffe709
+4bfffabd7f83e378
 38637f903c62ffff
-600000004bffe7e1
-408200a82c3c0000
-38df00207cf602a6
-7c26284038bd0020
-7929d9427d3fe850
-3900ffff7feafb78
-4081000839290001
-2c29000139200001
-3929fffff90a0000
-f90a0010f90a0008
-394a0020f90a0018
-7d3602a64082ffe4
-78ea00203f8002dc
-79290020639c6c00
-7d2950507f9ee1d2
+600000004bffe6f1
+38637b903c62ffff
+600000004bffe6e1
+600000004bffe745
+409200487f9602a6
+395f00207d3fe850
+7929d9423bbd0020
+392900017c2ae840
+3920000140810008
+e95f00002c290001
+e95f00083929ffff
+e95f0018e95f0010
+4082ffe43bff0020
+7bdbe8c24800001c
+7f7adb7839400000
+7c1dd0003ba00000
+7d3602a64082006c
+7b9c00203d4002dc
+79290020614a6c00
+7d29e0507fde51d2
 38637f983c62ffff
-4bffe75d7f9c4b92
-7f83e37860000000
-3c62ffff4bfffabd
-4bffe74538637fa8
+4bffe6457fde4b92
+7fc3f37860000000
+3c62ffff4bfff9f9
+4bffe62d38637f90
 3c62ffff60000000
-4bffe73538637bb8
-4bffe79960000000
-7f9602a660000000
-7d3fe85040920048
-3bbd0020395f0020
-7c2ae8407929d942
-4081000839290001
-2c29000139200001
-3929ffffe95f0000
-e95f0010e95f0008
-3bff0020e95f0018
-4800001c4082ffe4
-394000007bdbe8c2
-3ba000007f7adb78
-4082006c7c1dd000
-3d4002dc7d3602a6
-614a6c007b9c0020
-7fde51d279290020
-3c62ffff7d29e050
-7fde4b9238637fb0
-600000004bffe699
-4bfff9f97fc3f378
-38637fa83c62ffff
-600000004bffe681
-38637bb83c62ffff
-600000004bffe671
-8161000838210090
-48000e047d708120
-794300207fa407b4
-3bbd00014bfffaed
-7c6a1b787d23db96
-7d2918507d29d9d6
-7d3f482a79291f48
-000000004bffff68
-0000068003000000
-384292e03c4c0001
-282402007c0802a6
-f821ff8148000d71
-7c9f23787c7e1b78
-418100083b800200
-3c62ffff7c9c2378
-38637fc07fc4f378
-600000004bffe5e9
-4bfff9497fe3fb78
-38637f903c62ffff
-600000004bffe5d1
-7fc3f3787f84e378
-38c000004bfffaa1
-7fe4fb7838a00001
-7fc3f3787c7d1b78
-7d23ea144bfffb99
-2c0900007c7e1b78
-3c62ffff41820080
-7fa4eb787b85f882
-4bffe58538637fd0
-283f800060000000
-4081000c7fe5fb78
-54a5042038a0ffff
-78a5f0823c62ffff
-38637fe838800000
-600000004bffe559
-7be5f08260000000
-386280007fc4f378
-600000004bffe541
-3862801860000000
+4bffe61d38637b90
+3821009060000000
+7d70812081610008
+7fa407b448000e10
+4bfffaed79430020
+7d23db963bbd0001
+7d29d9d67c6a1b78
+79291f487d291850
+4bffff687d3f482a
+0300000000000000
+3c4c000100000680
+7c0802a638429314
+48000d7d28240200
+7c7e1b78f821ff81
+3b8002007c9f2378
+7c9c237841810008
+7fc4f3783c62ffff
+4bffe59538637fa8
+7fe3fb7860000000
+3c62ffff4bfff949
+4bffe57d38637f78
+7f84e37860000000
+4bfffaa17fc3f378
+38a0000138c00000
+7c7d1b787fe4fb78
+4bfffb997fc3f378
+7c7e1b787d23ea14
+418200802c090000
+7b85f8823c62ffff
+38637fb87fa4eb78
 600000004bffe531
-3821008038600000
-48000ccc786307e0
-3862802860000000
-600000004bffe511
-4bffffe038600001
-0100000000000000
-3c4c000100000480
-60000000384291b4
-60000000892280b8
-2c090000394280b0
-e92a000041820030
-7c0004ac39290014
-712900207d204eaa
-600000004182ffec
-7c0004ace92280b0
-4e8000207c604faa
-39290010e92a0000
-7d204eea7c0004ac
-4082ffec71290008
-600000005469063e
-7c0004ace94280b0
-4e8000207d2057ea
-0000000000000000
-3c4c000100000000
-7c0802a63842912c
-fbc1fff0fbe1fff8
-f80100103be3ffff
-8fdf0001f821ffd1
-408200102c1e0000
-3860000038210030
-2c1e000a48000c04
-3860000d4082000c
-57c3063e4bffff3d
-4bffffd04bffff35
-0100000000000000
-3c4c000100000280
-39400020384290cc
-7c0004ac654ac000
-392000087d4056ea
-6529c000794a0600
-7d204eea7c0004ac
-4182001471290020
-6529c00039200040
-7d204eea7c0004ac
-390020007929f804
-6508c00079290fc3
-f90280b060000000
-610820003d00001c
-418200807d4a4392
-3920000160000000
-3900200c992280b8
-6508c0003920ff80
-7d2047aa7c0004ac
-7c0004ace92280b0
-e92280b07d404faa
-39290004794ac202
-7d404faa7c0004ac
-39400003e92280b0
-7c0004ac3929000c
-e92280b07d404faa
+7fe5fb78283f8000
+38a0ffff4081000c
+3c62ffff54a50420
+3880000078a5f082
+4bffe50538637fd0
+3c62ffff60000000
+7fc4f3787be5f082
+4bffe4ed38637fe8
+6000000060000000
+4bffe4dd38628000
+3860000060000000
+786307e038210080
+6000000048000cd8
+4bffe4bd38628010
+3860000160000000
+000000004bffffe0
+0000048001000000
+384291e83c4c0001
+892280a860000000
+394280a060000000
+418200302c090000
+39290014e92a0000
+7d204eaa7c0004ac
+4182ffec71290020
+e92280a060000000
+7c604faa7c0004ac
+e92a00004e800020
 7c0004ac39290010
-e92280b07d404faa
-3929000839400007
-7d404faa7c0004ac
-600000004e800020
-992280b8394affff
-6529c00039202018
-7d404fea7c0004ac
+712900087d204eea
+5469063e4082ffec
+e94280a060000000
+7d2057ea7c0004ac
 000000004e800020
 0000000000000000
+384291603c4c0001
+fbe1fff87c0802a6
+3be3fffffbc1fff0
+f821ffd1f8010010
+2c1e00008fdf0001
+3821003040820010
+48000c1038600000
+4082000c2c1e000a
+4bffff3d3860000d
+4bffff357bc30020
+000000004bffffd0
+0000028001000000
+384291003c4c0001
+654ac00039400020
+7d4056ea7c0004ac
+794a060039200008
+7c0004ac6529c000
+712900207d204eea
+3920004041820014
+7c0004ac6529c000
+7929f8047d204eea
+79290fc339002000
+600000006508c000
+3d00001cf90280a0
+7d4a439261082000
+6000000041820080
+992280a839200001
+3920ff803900200c
+7c0004ac6508c000
+e92280a07d2047aa
+7d404faa7c0004ac
+794ac202e92280a0
+7c0004ac39290004
+e92280a07d404faa
+3929000c39400003
+7d404faa7c0004ac
+39290010e92280a0
+7d404faa7c0004ac
+39400007e92280a0
+7c0004ac39290008
+4e8000207d404faa
+394affff60000000
+39202018992280a8
+7c0004ac6529c000
+4e8000207d404fea
+0000000000000000
+78a9e8c200000000
+3929000139400000
+4200002c7d2903a6
 3940000078a9e8c2
-7d2903a639290001
-78a9072442000028
-3905000178a50760
-7d0903a67d434a14
-392000007c844a14
+7ca54a141d29fff8
+390500017c892050
+7d0903a67d291850
 4e80002042000018
 7d23512a7d24502a
-4bffffcc394a0008
-7d0a49ae7d0448ae
-4bffffdc39290001
+4bffffc8394a0008
+7d0951ae7d0450ae
+4bffffdc394a0001
 0000000000000000
 7c691b7800000000
 7d4918ae38600000
@@ -1465,110 +1491,108 @@ e92280b07d404faa
 4bfffff038630001
 0000000000000000
 2c24000000000000
-3881fff040820008
-f864000028050024
-4d81002038600000
-792983e43d200001
-e9240000612a2600
+408200087c691b78
+280500243881fff0
+38600000f9240000
+3d4000014d810020
+614a2600794a83e4
 2808002089090000
-7d47443641810040
-4082002870e70001
-418200e02c250000
-408200102c050010
-418200482c080030
-3860000038a00010
-3929000148000080
-4bffffb8f9240000
-4082ffd42c250000
-38a0000a2c080030
-894900014082ffdc
-4082ffd02c0a0078
-f924000039290002
-894900014bffffc0
-4082ffb42c0a0078
-38eaffd04bffffe8
-2807000954e7063e
-3929ffd04181003c
-7c0a28007d2a0734
-390800014c800020
-7d2907347c6519d2
-7c691a14f9040000
-89480000e9040000
-4082ffc0714900ff
-38eaff9f4e800020
+7d47443641810038
+4082002070e70001
+418200d02c250000
+418200282c050010
+386000003929ffff
+3929000148000078
+4bffffc4f9240000
+4082ffdc2c250000
+2c08003038a0000a
+894900014082ffd8
+4082ffcc2c0a0078
+38a0001039290002
+4bffffbcf9240000
+54e7063e38e8ffd0
+4181004028070009
+7d480734394affd0
+4c8000207c082800
+392900027c6519d2
+f92400007d4a0734
+7c6a1a147cc93378
+38c9000189090001
+4082ffbc710a00ff
+38e8ff9f4e800020
 2807001954e7063e
-3929ffa94181000c
-394affbf4bffffb8
-280a0019554a063e
-3929ffc94d810020
-38a0000a4bffffa0
-000000004bffff34
+394affa94181000c
+3908ffbf4bffffb4
+280800195508063e
+394affc94d810020
+38a0000a4bffff9c
+000000004bffff38
 0000000000000000
 280900193923ff9f
 3863ffe041810008
 4e8000207c6307b4
 0000000000000000
 3c4c000100000000
-7c0802a638428dcc
-f821ffa148000855
+7c0802a638428e0c
+f821ffa14800086d
 7cfd3b787c7e1b78
 7c9c23787ca32b78
 3880000038a0000a
 7cdf3378eb3e0000
 7d3a4b787d1b4378
-600000004bfffe65
+600000004bfffe75
 394000002b9d0010
 4082005c2c3f0000
-408200082c0a0000
+418100082c0a0000
 7d4ad21439400001
 4081003c7c035000
-7d2948f87d235050
-3929000179290020
+394affff7d4a1850
+392a0001794a0020
 e93e00007d2903a6
 7c2ae0407d594850
 9b69000040800018
 39290001e93e0000
 4200ffe0f93e0000
-4800080838210060
+4800082038210060
 7bffe102409e0010
 4bffff94394a0001
 4bfffff47fffeb92
 0100000000000000
 3c4c000100000780
-7c0802a638428cfc
-f821ffb14800078d
+7c0802a638428d3c
+f821ffb1480007a5
 7c7f1b78eb630000
 7cbd2b787c9c2378
 7fa3eb783bc00000
-600000004bfffd7d
+600000004bfffd8d
 408000147c3e1840
 7d5b4850e93f0000
 4180000c7c2ae040
-4800079838210050
+480007b038210050
 3bde00017d5df0ae
 e93f000099490000
 f93f000039290001
 000000004bffffbc
 0000058001000000
-38428c803c4c0001
+38428cc03c4c0001
 600000007c0802a6
-2b860010e9228038
-7caa2b787d708026
-480006f591610008
-7c7c1b78f821ffa1
-7cdd33787cbe2b78
-f92100203be00000
-e922804060000000
-2c2a0000f9210028
+2b860010e9228020
+916100087d708026
+f821ffa148000711
+7cbe2b787c7c1b78
+3be000007cdd3378
+60000000f9210020
+f9210028e9228028
+2c2900007ca92b78
 2c1f000040820034
-3be0000140820008
+3be0000141810008
 2e2700007fff07b4
 3b7fffff7c3f2040
 3821006040810030
 7d70812081610008
-409e0010480006e8
-3bff0001794ae102
-7d4aeb924bffffbc
+409e001048000700
+3bff00017929e102
+7d29eb924bffffbc
 7f5ed3784bfffff4
 7d3ae9d27f5eeb92
 7d214a147d29f050
@@ -1581,195 +1605,198 @@ e922804060000000
 4bffff90f93c0000
 0300000000000000
 3c4c000100000680
-7c0802a638428b8c
-f821fef1480005e9
-f86100607c761b79
-4182003c38600000
-418200342c240000
-3aa100403b04ffff
-892500003a800000
-712a00ffebc10060
-4182000c7c76f050
-418000187c23c040
+7c0802a638428bcc
+f821fef148000601
+f86100607c751b79
+4182004438600000
+4182003c2c240000
+3ae4ffff7cbd2b78
+3b2100203a610040
+895d00003a400000
+714900ffebc10060
+4182000c7c75f050
+418000187c23b840
 993e000039200000
 7c6307b438210110
-2c0a0025480005e0
-4082056439050001
-8945000039200000
-8ce500017cb32b78
-54ea063e7d49a9ae
-41810024280a0078
-41810024280a0062
-418200a02c0a004f
-418200982c0a0058
-418200902c0a0025
-4bffffc039290001
-5504063e3907ff9d
-4181ffec28040015
-3884755c3c82ffff
-7d0442aa790815a8
-7d0903a67d082214
+2c090025480005f0
+40820574391d0001
+7d4999ae39200000
+389d0001895d0001
+280800785548063e
+2808006241810024
+2c08004f41810028
+2c080058418200a4
+2c0800254182009c
+3929000141820094
+4bffffc07c9d2378
+54e5063e38eaff9d
+4181ffe828050015
+38a575243ca2ffff
+7ce53aaa78e715a8
+7ce903a67ce72a14
 000000584e800420
-ffffffcc00000058
-ffffffccffffffcc
-00000058ffffffcc
-ffffffccffffffcc
-ffffffccffffffcc
-00000058ffffffcc
-ffffffcc00000058
-00000058ffffffcc
-00000058ffffffcc
-ffffffccffffffcc
-3909000100000058
-392900022c0a0025
-7d0807b438a10020
-7d0542147d2907b4
-98e800207d254a14
-408200189a890020
-995e0000393e0001
-38b30002f9210060
-892100414bfffebc
-7fe3c050eb860000
-3a4000303a260008
-3929ffd23b410042
-40820428712900fd
-600000005649063e
-3b2000043ae00000
-3b600000f9210068
-39e280583a000000
-2c07004f48000170
-418201dc38da0001
-5505063e390affa8
-418103bc28050022
-38a576743ca2ffff
-7d0542aa790815a8
-7d0903a67d082a14
-000001584e800420
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000008c00000268
-0000039c0000039c
-000003800000039c
-0000039c0000008c
-000003680000039c
-0000039c0000039c
-00000204000001ac
-0000039c0000039c
-0000039c000002ac
-0000039c0000008c
-0000015c0000039c
-000003c00000039c
-7b6a00202c070075
-390000007d415214
-990a00207f9de378
-5728183841820044
-3908ffff39400001
-7f8a50397d4a4036
-3940002d4182002c
-7fbc00d039290001
-600000009949ffff
-7b291e68f9210060
-7d2a482a39428058
-e88100607fbd4838
-7fa6eb7838e0000a
-3920000038a10020
-386100605648063e
-7c84f8507c9e2050
+ffffffc800000058
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc800000058
+00000058ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+38e9000100000058
+392900022c080025
+7d2907b47ce707b4
+7d394a147cf93a14
+9a49002099470020
+393e000140820018
+995e0000f9210060
+4bfffec03bbd0002
+eb86000089210041
+3a2600087fe3b850
+3b4100423a800030
+712900fd3929ffd2
+5689063e4082043c
+3ac0000060000000
+f92100683b000004
+3a0000003b600000
+4800016c39e28048
+38ba00012c06004f
+38e8ffa8418201e0
+2804002254e4063e
+3c82ffff418103d0
+78e715a838847638
+7ce722147ce43aaa
+4e8004207ce903a6
+000003b000000154
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+00000270000003b0
+000003b00000008c
+000003b0000003b0
+0000008c00000394
+000003b0000003b0
+000003b00000037c
+000001b0000003b0
+000003b00000020c
+000002b4000003b0
+0000008c000003b0
+000003b0000003b0
+000003b000000158
+2c060075000003d4
+7d4152147b6a0020
+7f8ee37839000000
+41820044990a0020
+3900000157071838
+7d08383638e7ffff
+4182002c7f884039
+392900013940002d
+7b081e6860000000
+9949ffff38e28048
+7d5c00d0f9210060
+7d4e40387d07402a
+38e0000a7c9e4850
+7f25cb787dc67378
+392000007c84f850
+386100605688063e
 e88100604bfffabd
-38c0000a7ae707e0
-7c9e20507fa5eb78
+38c0000a7ac707e0
+7c9e20507dc57378
 386100607c84f850
 3b5a00014bfffbe9
-e9210060895a0000
-41820010714700ff
-7c3fe8407fbe4850
-7e268b784181fe7c
-3ae000014bfffe24
+e9210060891a0000
+41820010710600ff
+7c3f70407dde4850
+7e268b784181fe80
+3ac000014bfffe28
 e90100687b690020
 7d214a1438e00010
-38a100207c9df850
+7f25cb787c8ef850
 9a09002038610060
-7d4f482a7b291e68
-7f8e503839200000
-4bfffa397dc67378
-7ae707e0e8810060
-7c9e205038c00010
-4bffff7c7dc57378
-394000007b690020
+7d6f482a7b091e68
+7f8b583839200000
+f96100707d665b78
+e88100604bfffa35
+38c000107ac707e0
+e96100707c9e2050
+4bffff747d655b78
+390000007b690020
 38e000087d214a14
-5648063e7c9df850
-6000000099490020
-394280587b291e68
-3861006038a10020
-392000007d4a482a
-7dc673787f8e5038
-e88100604bfff9dd
-38c000087ae707e0
-4bffffa47c9e2050
-394000007b690020
-38e000107d214a14
-390000207f86e378
-38a1002099490020
-7c9df85039200002
-4bfff99938610060
-60000000e8810060
-38a2805038610060
-7c84f8507c9e2050
-e88100604bfffa4d
-38c000107ae707e0
-7c9e20507f85e378
-7b6900204bfffec0
-7d214a1439400000
-38e0000a39000020
-9949002038c00001
-3920000038a10020
-386100607c9df850
-e92100604bfff935
-392900019b890000
-4bfffe88f9210060
-390000007b6a0020
-7d415214f9210070
-3880000038a0000a
-990a002038610020
-600000004bfff795
-7f83e3787c6e1b78
-600000004bfff75d
-408100487c2e1840
-7fbdf850e9210070
-394000007c637050
-3bbd000138e00020
-7c691a147d09f050
-2c2800007d08fa14
-3ba0000140820008
-3bbdffff2c3d0001
-714a000140820028
-e881006040820034
-386100607f85e378
-7c84f8507c9e2050
-4bfffde84bfff955
-3929000198e90000
-7c29184039400001
-f92100604082ffc0
-893a00014bffffcc
-2c09006c3b200008
-7cda33784082fdbc
-893a00014bfffdb4
-2c0900683b200002
-7cda33784082fda4
-4bfffd983b200001
-5529063e392affd0
-4181fd8828090009
+7f25cb787c8ef850
+6000000099090020
+390280487b091e68
+7d68482a38610060
+5688063e39200000
+7d665b787f8b5838
+4bfff9d1f9610070
+7ac707e0e8810060
+7c9e205038c00008
+7b6900204bffff9c
+7d214a1439000000
+7f86e37838e00010
+990900207f25cb78
+392000027c8ef850
+3861006039000020
+e88100604bfff98d
+3861006060000000
+7c9e205038a28038
+4bfffa417c84f850
+7ac707e0e8810060
+7f85e37838c00010
+4bfffeb47c9e2050
+390000007b690020
+38e0000a7d214a14
+7f25cb7838c00001
+7c8ef85099090020
+3900002039200000
+4bfff92938610060
+9b890000e9210060
+f921006039290001
+7b6800204bfffe7c
+f921007838e00000
+38a0000a7d014214
+7f23cb7838800000
+4bfff79998e80020
+f861007060000000
+4bfff7617f83e378
+e901007060000000
+7c281840e9210078
+7d244b7841810020
+7f85e3787c9e2050
+386100607c84f850
+4bfffe184bfff985
+7c6340507ce9f050
+7d4ef8507ce7fa14
+7c691a142c270000
+390000007d244b78
+394a000138c00020
+3940000140820008
+394affff2c2a0001
+7108000140820010
+4bffffa04082001c
+3884000198c40000
+7c24184039000001
+f88100604082ffd8
+893a00014bffff88
+2c09006c3b000008
+7cba2b784082fda4
+893a00014bfffd9c
+2c0900683b000002
+7cba2b784082fd8c
+4bfffd803b000001
+5529063e3928ffd0
+4181fd7028090009
 3b7b00017b690020
-994900207d214a14
-3b2000084bfffd74
-3a4000204bfffd6c
-4bfffbd43b410041
-3bde0001993e0000
-fbc100607d054378
-000000004bfffa54
+990900207d214a14
+3b0000084bfffd5c
+3a8000204bfffd54
+4bfffbc03b410041
+3bde0001995e0000
+fbc100607d1d4378
+000000004bfffa44
 0000128001000000
 f9e1ff78f9c1ff70
 fa21ff88fa01ff80
@@ -1838,14 +1865,18 @@ ebe1fff8e8010010
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1906,15 +1937,13 @@ ebe1fff8e8010010
 000000000000207c
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
@@ -1956,11 +1985,12 @@ ebe1fff8e8010010
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v
index f5dc552..7a77cab 100644
--- a/litedram/generated/orangecrab-85-0.2/litedram_core.v
+++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : LFE5U-85F-8MG285C
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:11
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:49
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -104,129 +104,129 @@ LiteDRAMCore
 │    └─── bitslip_15* (BitSlip)
 │    └─── tappeddelayline_0* (TappedDelayLine)
 │    └─── tappeddelayline_1* (TappedDelayLine)
-│    └─── [TSHX2DQA]
+│    └─── [DELAYG]
 │    └─── [ODDRX2F]
-│    └─── [TSHX2DQA]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [TSHX2DQA]
-│    └─── [TSHX2DQA]
-│    └─── [ODDRX2DQSB]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [DELAYG]
-│    └─── [TSHX2DQA]
-│    └─── [ODDRX2DQA]
 │    └─── [ODDRX2F]
-│    └─── [TSHX2DQA]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [DELAYG]
-│    └─── [TSHX2DQA]
-│    └─── [ODDRX2DQA]
 │    └─── [ODDRX2F]
-│    └─── [ODDRX2DQA]
-│    └─── [ODDRX2DQA]
-│    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [ODDRX2DQA]
-│    └─── [IDDRX2DQA]
-│    └─── [ODDRX2DQA]
 │    └─── [ODDRX2F]
+│    └─── [DELAYG]
 │    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [IDDRX2DQA]
-│    └─── [TSHX2DQSA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [IDDRX2DQA]
-│    └─── [IDDRX2DQA]
-│    └─── [ODDRX2DQA]
-│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [IDDRX2DQA]
 │    └─── [DQSBUFM]
+│    └─── [ODDRX2DQSB]
+│    └─── [TSHX2DQSA]
+│    └─── [ODDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2DQA]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [DELAYG]
 │    └─── [ODDRX2F]
+│    └─── [DELAYG]
 │    └─── [ODDRX2F]
-│    └─── [ODDRX2DQA]
-│    └─── [TSHX2DQA]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [TSHX2DQSA]
-│    └─── [DELAYG]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
-│    └─── [TSHX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [DELAYG]
-│    └─── [DELAYG]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
-│    └─── [ODDRX2F]
-│    └─── [TSHX2DQA]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [ODDRX2F]
 │    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
+│    └─── [IDDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQSB]
+│    └─── [DQSBUFM]
+│    └─── [TSHX2DQSA]
 │    └─── [ODDRX2DQA]
 │    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
 │    └─── [TSHX2DQA]
-│    └─── [ODDRX2F]
 │    └─── [ODDRX2DQA]
+│    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [ODDRX2F]
+│    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
-│    └─── [ODDRX2F]
-│    └─── [DELAYG]
-│    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [IDDRX2DQA]
-│    └─── [DELAYG]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
 │    └─── [ODDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
 │    └─── [DELAYG]
-│    └─── [ODDRX2F]
-│    └─── [DELAYG]
-│    └─── [ODDRX2DQSB]
 │    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
 │    └─── [IDDRX2DQA]
-│    └─── [ODDRX2F]
-│    └─── [ODDRX2F]
-│    └─── [DELAYG]
 │    └─── [TSHX2DQA]
-│    └─── [DQSBUFM]
-│    └─── [IDDRX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [IDDRX2DQA]
+│    └─── [TSHX2DQA]
+│    └─── [ODDRX2DQA]
 │    └─── [DELAYG]
+│    └─── [TSHX2DQA]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 │    └─── [DELAYG]
+│    └─── [ODDRX2F]
+│    └─── [ODDRX2F]
 │    └─── [DELAYG]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
@@ -364,32 +364,32 @@ LiteDRAMCore
 │    │    └─── csrstorage_8* (CSRStorage)
 │    │    └─── csrstatus_1* (CSRStatus)
 └─── csr_interconnect (InterconnectShared)
-└─── [FD1S3BX]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
-└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
 └─── [TRELLIS_IO]
+└─── [FD1S3BX]
+└─── [FD1S3BX]
 * : Generated name.
 []: BlackBox.
 */
@@ -864,6 +864,7 @@ wire   [29:0] interface0_adr;
 wire   [13:0] interface0_bank_bus_adr;
 reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface0_bank_bus_dat_w;
+wire          interface0_bank_bus_re;
 wire          interface0_bank_bus_we;
 wire    [1:0] interface0_bte;
 wire    [2:0] interface0_cti;
@@ -880,17 +881,22 @@ reg           interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] interface1_bank_bus_adr;
 reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface1_bank_bus_dat_w;
+wire          interface1_bank_bus_re;
 wire          interface1_bank_bus_we;
 wire   [31:0] interface1_dat_r;
 reg    [31:0] interface1_dat_w = 32'd0;
 reg    [31:0] interface1_dat_w_next_value0 = 32'd0;
 reg           interface1_dat_w_next_value_ce0 = 1'd0;
+reg           interface1_re = 1'd0;
+reg           interface1_re_next_value2 = 1'd0;
+reg           interface1_re_next_value_ce2 = 1'd0;
 reg           interface1_we = 1'd0;
-reg           interface1_we_next_value2 = 1'd0;
-reg           interface1_we_next_value_ce2 = 1'd0;
+reg           interface1_we_next_value3 = 1'd0;
+reg           interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] interface2_bank_bus_adr;
 reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface2_bank_bus_dat_w;
+wire          interface2_bank_bus_re;
 wire          interface2_bank_bus_we;
 wire          latticeecp5asyncresetsynchronizerimpl0_expr;
 wire          latticeecp5asyncresetsynchronizerimpl0_rst1;
@@ -1733,9 +1739,9 @@ reg           litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [14:0] litedramcore_csr_dfi_p0_address;
 wire    [2:0] litedramcore_csr_dfi_p0_bank;
 reg           litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          litedramcore_csr_dfi_p0_cke;
 reg           litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          litedramcore_csr_dfi_p0_odt;
 reg           litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
 wire          litedramcore_csr_dfi_p0_rddata_en;
@@ -1749,9 +1755,9 @@ reg           litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [14:0] litedramcore_csr_dfi_p1_address;
 wire    [2:0] litedramcore_csr_dfi_p1_bank;
 reg           litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          litedramcore_csr_dfi_p1_cke;
 reg           litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          litedramcore_csr_dfi_p1_odt;
 reg           litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
 wire          litedramcore_csr_dfi_p1_rddata_en;
@@ -2115,6 +2121,7 @@ reg           multiregimpl0 = 1'd0;
 reg           multiregimpl1 = 1'd0;
 reg     [1:0] next_state = 2'd0;
 wire          por_clk;
+wire          re;
 reg           rhs_self0 = 1'd0;
 reg    [14:0] rhs_self1 = 15'd0;
 reg           rhs_self10 = 1'd0;
@@ -2951,59 +2958,6 @@ assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
 assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
 assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
 assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
-always @(*) begin
-    litedramcore_master_p0_cs_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
-        end else begin
-            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
-            if (1'd0) begin
-                litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}};
-            end
-        end
-    end else begin
-        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata <= 64'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
-    end
-end
-always @(*) begin
-    litedramcore_master_p0_ras_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
-        end else begin
-            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
-        end
-    end else begin
-        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
-    end
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
-    if (litedramcore_sel) begin
-    end else begin
-        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
-    end
-end
-always @(*) begin
-    litedramcore_master_p0_we_n <= 1'd1;
-    if (litedramcore_sel) begin
-        if (litedramcore_ext_dfi_sel) begin
-            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
-        end else begin
-            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
-        end
-    end else begin
-        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
-    end
-end
 always @(*) begin
     litedramcore_master_p0_cke <= 1'd0;
     if (litedramcore_sel) begin
@@ -3331,6 +3285,20 @@ always @(*) begin
     end else begin
     end
 end
+always @(*) begin
+    litedramcore_csr_dfi_p1_rddata <= 64'd0;
+    if (litedramcore_sel) begin
+    end else begin
+        litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+    end
+end
+always @(*) begin
+    litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+    if (litedramcore_sel) begin
+    end else begin
+        litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+    end
+end
 always @(*) begin
     litedramcore_csr_dfi_p0_rddata <= 64'd0;
     if (litedramcore_sel) begin
@@ -3402,23 +3370,58 @@ always @(*) begin
     end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_cke <= 1'd0;
-    litedramcore_csr_dfi_p0_cke <= litedramcore_cke;
-end
-always @(*) begin
-    litedramcore_csr_dfi_p1_cke <= 1'd0;
-    litedramcore_csr_dfi_p1_cke <= litedramcore_cke;
+    litedramcore_master_p0_cs_n <= 1'd1;
+    if (litedramcore_sel) begin
+        if (litedramcore_ext_dfi_sel) begin
+            litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+        end else begin
+            litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+            if (1'd0) begin
+                litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}};
+            end
+        end
+    end else begin
+        litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+    end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p0_odt <= 1'd0;
-    litedramcore_csr_dfi_p0_odt <= litedramcore_odt;
+    litedramcore_master_p0_ras_n <= 1'd1;
+    if (litedramcore_sel) begin
+        if (litedramcore_ext_dfi_sel) begin
+            litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+        end else begin
+            litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+        end
+    end else begin
+        litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+    end
 end
 always @(*) begin
-    litedramcore_csr_dfi_p1_odt <= 1'd0;
-    litedramcore_csr_dfi_p1_odt <= litedramcore_odt;
+    litedramcore_master_p0_we_n <= 1'd1;
+    if (litedramcore_sel) begin
+        if (litedramcore_ext_dfi_sel) begin
+            litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+        end else begin
+            litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+        end
+    end else begin
+        litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+    end
 end
+assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
+assign litedramcore_csr_dfi_p0_odt = litedramcore_odt;
+assign litedramcore_csr_dfi_p1_odt = litedramcore_odt;
 assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
 assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
+always @(*) begin
+    litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    if (litedramcore_phaseinjector0_command_issue_re) begin
+        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+    end else begin
+        litedramcore_csr_dfi_p0_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     litedramcore_csr_dfi_p0_cas_n <= 1'd1;
     if (litedramcore_phaseinjector0_command_issue_re) begin
@@ -3451,20 +3454,20 @@ always @(*) begin
         litedramcore_csr_dfi_p0_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    if (litedramcore_phaseinjector0_command_issue_re) begin
-        litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
-    end else begin
-        litedramcore_csr_dfi_p0_we_n <= 1'd1;
-    end
-end
 assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
 assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
 assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren);
 assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden);
 assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
 assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    if (litedramcore_phaseinjector1_command_issue_re) begin
+        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+    end else begin
+        litedramcore_csr_dfi_p1_we_n <= 1'd1;
+    end
+end
 always @(*) begin
     litedramcore_csr_dfi_p1_cas_n <= 1'd1;
     if (litedramcore_phaseinjector1_command_issue_re) begin
@@ -3497,14 +3500,6 @@ always @(*) begin
         litedramcore_csr_dfi_p1_ras_n <= 1'd1;
     end
 end
-always @(*) begin
-    litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    if (litedramcore_phaseinjector1_command_issue_re) begin
-        litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
-    end else begin
-        litedramcore_csr_dfi_p1_we_n <= 1'd1;
-    end
-end
 assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
 assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
 assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren);
@@ -3612,22 +3607,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_sequencer_start0 <= 1'd0;
-    case (litedramcore_refresher_state)
-        1'd1: begin
-            if (litedramcore_cmd_ready) begin
-                litedramcore_sequencer_start0 <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_cmd_valid <= 1'd0;
     case (litedramcore_refresher_state)
@@ -3694,6 +3673,22 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_sequencer_start0 <= 1'd0;
+    case (litedramcore_refresher_state)
+        1'd1: begin
+            if (litedramcore_cmd_ready) begin
+                litedramcore_sequencer_start0 <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
 assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
 assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
@@ -3827,66 +3822,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine0_trccon_ready) begin
-                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine0_source_source_valid) begin
-                    if (litedramcore_bankmachine0_row_opened) begin
-                        if (litedramcore_bankmachine0_row_hit) begin
-                            if (litedramcore_bankmachine0_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
     case (litedramcore_bankmachine0_state)
@@ -4207,6 +4142,66 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine0_trccon_ready) begin
+                litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+    case (litedramcore_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine0_source_source_valid) begin
+                    if (litedramcore_bankmachine0_row_opened) begin
+                        if (litedramcore_bankmachine0_row_hit) begin
+                            if (litedramcore_bankmachine0_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
 assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
 assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
@@ -4340,40 +4335,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine1_source_source_valid) begin
-                    if (litedramcore_bankmachine1_row_opened) begin
-                        if (litedramcore_bankmachine1_row_hit) begin
-                            if (litedramcore_bankmachine1_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine1_refresh_gnt <= 1'd0;
     case (litedramcore_bankmachine1_state)
@@ -4396,28 +4357,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine1_row_open <= 1'd0;
-    case (litedramcore_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine1_trccon_ready) begin
-                litedramcore_bankmachine1_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine1_cmd_valid <= 1'd0;
     case (litedramcore_bankmachine1_state)
@@ -4477,6 +4416,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine1_row_open <= 1'd0;
+    case (litedramcore_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine1_trccon_ready) begin
+                litedramcore_bankmachine1_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
     case (litedramcore_bankmachine1_state)
@@ -4720,6 +4681,40 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine1_source_source_valid) begin
+                    if (litedramcore_bankmachine1_row_opened) begin
+                        if (litedramcore_bankmachine1_row_hit) begin
+                            if (litedramcore_bankmachine1_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
 assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
 assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
@@ -4853,28 +4848,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine2_row_close <= 1'd0;
-    case (litedramcore_bankmachine2_state)
-        1'd1: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine2_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
     case (litedramcore_bankmachine2_state)
@@ -5233,6 +5206,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine2_row_close <= 1'd0;
+    case (litedramcore_bankmachine2_state)
+        1'd1: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        2'd2: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            litedramcore_bankmachine2_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
 assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
 assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
@@ -5366,37 +5361,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine3_source_source_valid) begin
-                    if (litedramcore_bankmachine3_row_opened) begin
-                        if (litedramcore_bankmachine3_row_hit) begin
-                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
     case (litedramcore_bankmachine3_state)
@@ -5746,6 +5710,37 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine3_source_source_valid) begin
+                    if (litedramcore_bankmachine3_row_opened) begin
+                        if (litedramcore_bankmachine3_row_hit) begin
+                            litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
 assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
 assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
@@ -5879,66 +5874,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
-    case (litedramcore_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine4_source_source_valid) begin
-                    if (litedramcore_bankmachine4_row_opened) begin
-                        if (litedramcore_bankmachine4_row_hit) begin
-                            if (litedramcore_bankmachine4_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
     case (litedramcore_bankmachine4_state)
@@ -6187,7 +6122,69 @@ always @(*) begin
                 if (litedramcore_bankmachine4_source_source_valid) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
-                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                            litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    case (litedramcore_bankmachine4_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine4_trccon_ready) begin
+                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    case (litedramcore_bankmachine4_state)
+        1'd1: begin
+            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine4_source_source_valid) begin
+                    if (litedramcore_bankmachine4_row_opened) begin
+                        if (litedramcore_bankmachine4_row_hit) begin
+                            if (litedramcore_bankmachine4_source_source_payload_we) begin
+                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -6198,21 +6195,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+    litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
     case (litedramcore_bankmachine4_state)
         1'd1: begin
             if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (litedramcore_bankmachine4_trccon_ready) begin
-                litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -6223,12 +6221,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+    litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
     case (litedramcore_bankmachine4_state)
         1'd1: begin
-            if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
-                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -6247,8 +6242,8 @@ always @(*) begin
                     if (litedramcore_bankmachine4_row_opened) begin
                         if (litedramcore_bankmachine4_row_hit) begin
                             if (litedramcore_bankmachine4_source_source_payload_we) begin
-                                litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                             end else begin
+                                litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -6392,40 +6387,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
-    case (litedramcore_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine5_source_source_valid) begin
-                    if (litedramcore_bankmachine5_row_opened) begin
-                        if (litedramcore_bankmachine5_row_hit) begin
-                            if (litedramcore_bankmachine5_source_source_payload_we) begin
-                            end else begin
-                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine5_refresh_gnt <= 1'd0;
     case (litedramcore_bankmachine5_state)
@@ -6772,6 +6733,40 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+    case (litedramcore_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine5_source_source_valid) begin
+                    if (litedramcore_bankmachine5_row_opened) begin
+                        if (litedramcore_bankmachine5_row_hit) begin
+                            if (litedramcore_bankmachine5_source_source_payload_we) begin
+                            end else begin
+                                litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
 assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
 assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
@@ -6905,28 +6900,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_row_close <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd2: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            litedramcore_bankmachine6_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
     case (litedramcore_bankmachine6_state)
@@ -7042,28 +7015,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine6_row_open <= 1'd0;
-    case (litedramcore_bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (litedramcore_bankmachine6_trccon_ready) begin
-                litedramcore_bankmachine6_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
     case (litedramcore_bankmachine6_state)
@@ -7248,6 +7199,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine6_row_open <= 1'd0;
+    case (litedramcore_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (litedramcore_bankmachine6_trccon_ready) begin
+                litedramcore_bankmachine6_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     litedramcore_bankmachine6_cmd_valid <= 1'd0;
     case (litedramcore_bankmachine6_state)
@@ -7285,6 +7258,28 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine6_row_close <= 1'd0;
+    case (litedramcore_bankmachine6_state)
+        1'd1: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd2: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            litedramcore_bankmachine6_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
 assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
 assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
@@ -7418,37 +7413,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
-    case (litedramcore_bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        default: begin
-            if (litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (litedramcore_bankmachine7_source_source_valid) begin
-                    if (litedramcore_bankmachine7_row_opened) begin
-                        if (litedramcore_bankmachine7_row_hit) begin
-                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
     case (litedramcore_bankmachine7_state)
@@ -7798,6 +7762,37 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    case (litedramcore_bankmachine7_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        default: begin
+            if (litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (litedramcore_bankmachine7_source_source_valid) begin
+                    if (litedramcore_bankmachine7_row_opened) begin
+                        if (litedramcore_bankmachine7_row_hit) begin
+                            litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
 assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
 assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
@@ -8048,19 +8043,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_steerer0 <= 2'd0;
+    litedramcore_choose_cmd_want_activates <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                litedramcore_steerer0 <= 2'd2;
-            end
-            if (1'd1) begin
-                litedramcore_steerer0 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
             end
         end
         2'd2: begin
-            litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -8086,29 +8077,23 @@ always @(*) begin
         end
         4'd14: begin
         end
-        4'd15: begin
-        end
-        default: begin
-            litedramcore_steerer0 <= 1'd0;
-            if (1'd1) begin
-                litedramcore_steerer0 <= 2'd2;
-            end
+        4'd15: begin
+        end
+        default: begin
             if (1'd0) begin
-                litedramcore_steerer0 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_steerer1 <= 2'd0;
+    litedramcore_choose_cmd_cmd_ready <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_steerer1 <= 1'd0;
-            if (1'd1) begin
-                litedramcore_steerer1 <= 2'd2;
-            end
             if (1'd0) begin
-                litedramcore_steerer1 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
             end
         end
         2'd2: begin
@@ -8140,24 +8125,17 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_steerer1 <= 1'd0;
             if (1'd0) begin
-                litedramcore_steerer1 <= 2'd2;
-            end
-            if (1'd1) begin
-                litedramcore_steerer1 <= 1'd1;
+            end else begin
+                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_want_activates <= 1'd0;
+    litedramcore_choose_req_want_reads <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
-            end
         end
         2'd2: begin
         end
@@ -8188,10 +8166,7 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
-            end
+            litedramcore_choose_req_want_reads <= 1'd1;
         end
     endcase
 end
@@ -8234,13 +8209,10 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    litedramcore_choose_cmd_cmd_ready <= 1'd0;
+    litedramcore_choose_req_want_writes <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
-            end
+            litedramcore_choose_req_want_writes <= 1'd1;
         end
         2'd2: begin
         end
@@ -8271,15 +8243,11 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            if (1'd0) begin
-            end else begin
-                litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
-            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_reads <= 1'd0;
+    litedramcore_en0 <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
         end
@@ -8312,15 +8280,19 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_choose_req_want_reads <= 1'd1;
+            litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_want_writes <= 1'd0;
+    litedramcore_choose_req_cmd_ready <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_choose_req_want_writes <= 1'd1;
+            if (1'd0) begin
+                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+            end else begin
+                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -8351,13 +8323,19 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            if (1'd0) begin
+                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+            end else begin
+                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en0 <= 1'd0;
+    litedramcore_en1 <= 1'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
+            litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -8388,21 +8366,23 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
-            litedramcore_en0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    litedramcore_choose_req_cmd_ready <= 1'd0;
+    litedramcore_steerer0 <= 2'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
+            litedramcore_steerer0 <= 1'd0;
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                litedramcore_steerer0 <= 2'd2;
+            end
+            if (1'd1) begin
+                litedramcore_steerer0 <= 1'd1;
             end
         end
         2'd2: begin
+            litedramcore_steerer0 <= 2'd3;
         end
         2'd3: begin
         end
@@ -8431,19 +8411,27 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_steerer0 <= 1'd0;
+            if (1'd1) begin
+                litedramcore_steerer0 <= 2'd2;
+            end
             if (1'd0) begin
-                litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
-            end else begin
-                litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                litedramcore_steerer0 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    litedramcore_en1 <= 1'd0;
+    litedramcore_steerer1 <= 2'd0;
     case (litedramcore_multiplexer_state)
         1'd1: begin
-            litedramcore_en1 <= 1'd1;
+            litedramcore_steerer1 <= 1'd0;
+            if (1'd1) begin
+                litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd0) begin
+                litedramcore_steerer1 <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -8474,6 +8462,13 @@ always @(*) begin
         4'd15: begin
         end
         default: begin
+            litedramcore_steerer1 <= 1'd0;
+            if (1'd0) begin
+                litedramcore_steerer1 <= 2'd2;
+            end
+            if (1'd1) begin
+                litedramcore_steerer1 <= 1'd1;
+            end
         end
     endcase
 end
@@ -8569,138 +8564,168 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    interface0_ack <= 1'd0;
+    interface1_adr_next_value1 <= 14'd0;
     case (state)
         1'd1: begin
+            interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
-            interface0_ack <= 1'd1;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value1 <= interface0_adr;
+            end
         end
     endcase
 end
 always @(*) begin
-    interface0_dat_r <= 32'd0;
+    interface1_adr_next_value_ce1 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            interface0_dat_r <= interface1_dat_r;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    interface1_dat_w_next_value0 <= 32'd0;
+    interface1_re_next_value2 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            interface1_dat_w_next_value0 <= interface0_dat_w;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    interface1_dat_w_next_value_ce0 <= 1'd0;
+    interface1_re_next_value_ce2 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_re_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            interface1_dat_w_next_value_ce0 <= 1'd1;
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_re_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    interface1_adr_next_value1 <= 14'd0;
+    interface1_we_next_value3 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_adr_next_value1 <= 1'd0;
+            interface1_we_next_value3 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((interface0_cyc & interface0_stb)) begin
-                interface1_adr_next_value1 <= interface0_adr[29:0];
+                interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    interface1_adr_next_value_ce1 <= 1'd0;
+    interface1_we_next_value_ce3 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_adr_next_value_ce1 <= 1'd1;
+            interface1_we_next_value_ce3 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((interface0_cyc & interface0_stb)) begin
-                interface1_adr_next_value_ce1 <= 1'd1;
+                interface1_we_next_value_ce3 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    interface1_we_next_value2 <= 1'd0;
+    interface0_dat_r <= 32'd0;
+    case (state)
+        1'd1: begin
+        end
+        2'd2: begin
+            interface0_dat_r <= interface1_dat_r;
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    interface0_ack <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_we_next_value2 <= 1'd0;
         end
         2'd2: begin
+            interface0_ack <= 1'd1;
         end
         default: begin
-            if ((interface0_cyc & interface0_stb)) begin
-                interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0));
-            end
         end
     endcase
 end
 always @(*) begin
-    interface1_we_next_value_ce2 <= 1'd0;
+    interface1_dat_w_next_value0 <= 32'd0;
+    case (state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        default: begin
+            interface1_dat_w_next_value0 <= interface0_dat_w;
+        end
+    endcase
+end
+always @(*) begin
+    interface1_dat_w_next_value_ce0 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_we_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
-            if ((interface0_cyc & interface0_stb)) begin
-                interface1_we_next_value_ce2 <= 1'd1;
-            end
+            interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_done0_re <= 1'd0;
+    csrbank0_init_done0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_re <= interface0_bank_bus_we;
+        csrbank0_init_done0_we <= interface0_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank0_init_done0_we <= 1'd0;
+    csrbank0_init_done0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_done0_re <= interface0_bank_bus_we;
     end
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
+    csrbank0_init_error0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_error0_re <= interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
+    csrbank0_init_error0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+        csrbank0_init_error0_we <= interface0_bank_bus_re;
     end
 end
 assign csrbank0_init_done0_w = init_done_storage;
@@ -8708,54 +8733,54 @@ assign csrbank0_init_error0_w = init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    csrbank1_dly_sel0_we <= 1'd0;
+    csrbank1_dly_sel0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dly_sel0_re <= 1'd0;
+    csrbank1_dly_sel0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+        csrbank1_dly_sel0_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_rdly_dq_rst_we <= 1'd0;
+    ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    ddrphy_rdly_dq_rst_re <= 1'd0;
+    ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+        ddrphy_rdly_dq_rst_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_rdly_dq_inc_we <= 1'd0;
+    ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    ddrphy_rdly_dq_inc_re <= 1'd0;
+    ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+        ddrphy_rdly_dq_inc_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+    ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+    ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+        ddrphy_rdly_dq_bitslip_rst_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
@@ -8768,20 +8793,20 @@ end
 always @(*) begin
     ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+        ddrphy_rdly_dq_bitslip_we <= interface1_bank_bus_re;
     end
 end
 assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    ddrphy_burstdet_clr_re <= 1'd0;
+    ddrphy_burstdet_clr_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
+        ddrphy_burstdet_clr_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    ddrphy_burstdet_clr_we <= 1'd0;
+    ddrphy_burstdet_clr_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we);
+        ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0];
@@ -8794,11 +8819,11 @@ end
 always @(*) begin
     csrbank1_burstdet_seen_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
+        csrbank1_burstdet_seen_we <= interface1_bank_bus_re;
     end
 end
-assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0];
-assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0];
+assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage;
+assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status;
 assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we;
 assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
 assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
@@ -8811,46 +8836,46 @@ end
 always @(*) begin
     csrbank2_dfii_control0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_control0_we <= interface2_bank_bus_re;
     end
 end
 assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi0_command0_we <= 1'd0;
+    csrbank2_dfii_pi0_command0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_command0_re <= 1'd0;
+    csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_command0_we <= interface2_bank_bus_re;
     end
 end
 assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+        litedramcore_phaseinjector0_command_issue_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+        litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
 always @(*) begin
-    csrbank2_dfii_pi0_address0_re <= 1'd0;
+    csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_address0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_address0_we <= 1'd0;
+    csrbank2_dfii_pi0_address0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
     end
 end
 assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
@@ -8863,14 +8888,14 @@ end
 always @(*) begin
     csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_baddress0_we <= interface2_bank_bus_re;
     end
 end
-assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
     csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_wrdata1_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8879,37 +8904,37 @@ always @(*) begin
         csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_wrdata0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+    csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+    csrbank2_dfii_pi0_rddata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi0_rddata1_we <= interface2_bank_bus_re;
     end
 end
-assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
     csrbank2_dfii_pi0_rddata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi0_rddata0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8920,22 +8945,22 @@ always @(*) begin
 end
 assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank2_dfii_pi1_command0_re <= 1'd0;
+    csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_command0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_command0_we <= 1'd0;
+    csrbank2_dfii_pi1_command0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
     end
 end
 assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
 always @(*) begin
     litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+        litedramcore_phaseinjector1_command_issue_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8954,14 +8979,14 @@ end
 always @(*) begin
     csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_address0_we <= interface2_bank_bus_re;
     end
 end
 assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_baddress0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -8970,37 +8995,37 @@ always @(*) begin
         csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_wrdata1_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+    csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+    csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_wrdata0_we <= interface2_bank_bus_re;
     end
 end
-assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w;
 always @(*) begin
     csrbank2_dfii_pi1_rddata1_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_rddata1_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -9009,24 +9034,24 @@ always @(*) begin
         csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
     end
 end
-assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
+assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w;
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+        csrbank2_dfii_pi1_rddata0_we <= interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+    csrbank2_dfii_pi1_rddata0_re <= 1'd0;
     if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+        csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
     end
 end
 assign litedramcore_sel = litedramcore_storage[0];
 assign litedramcore_cke = litedramcore_storage[1];
 assign litedramcore_odt = litedramcore_storage[2];
 assign litedramcore_reset_n = litedramcore_storage[3];
-assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign csrbank2_dfii_control0_w = litedramcore_storage;
 assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0];
 assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1];
 assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2];
@@ -9035,9 +9060,9 @@ assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_c
 assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5];
 assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6];
 assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7];
-assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0];
-assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
-assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage;
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage;
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage;
 assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32];
 assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
 assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32];
@@ -9051,21 +9076,25 @@ assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_c
 assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5];
 assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6];
 assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7];
-assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0];
-assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0];
-assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage;
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage;
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage;
 assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32];
 assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
 assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32];
 assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0];
 assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we;
 assign adr = interface1_adr;
+assign re = interface1_re;
 assign we = interface1_we;
 assign dat_w = interface1_dat_w;
 assign interface1_dat_r = dat_r;
 assign interface0_bank_bus_adr = adr;
 assign interface1_bank_bus_adr = adr;
 assign interface2_bank_bus_adr = adr;
+assign interface0_bank_bus_re = re;
+assign interface1_bank_bus_re = re;
+assign interface2_bank_bus_re = re;
 assign interface0_bank_bus_we = we;
 assign interface1_bank_bus_we = we;
 assign interface2_bank_bus_we = we;
@@ -9791,16 +9820,16 @@ always @(*) begin
     self0 <= 3'd0;
     case (litedramcore_steerer0)
         1'd0: begin
-            self0 <= litedramcore_nop_ba[2:0];
+            self0 <= litedramcore_nop_ba;
         end
         1'd1: begin
-            self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self0 <= litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            self0 <= litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self0 <= litedramcore_cmd_payload_ba[2:0];
+            self0 <= litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -9910,16 +9939,16 @@ always @(*) begin
     self7 <= 3'd0;
     case (litedramcore_steerer1)
         1'd0: begin
-            self7 <= litedramcore_nop_ba[2:0];
+            self7 <= litedramcore_nop_ba;
         end
         1'd1: begin
-            self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self7 <= litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+            self7 <= litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self7 <= litedramcore_cmd_payload_ba[2:0];
+            self7 <= litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -11727,8 +11756,11 @@ always @(posedge sys_clk) begin
     if (interface1_adr_next_value_ce1) begin
         interface1_adr <= interface1_adr_next_value1;
     end
-    if (interface1_we_next_value_ce2) begin
-        interface1_we <= interface1_we_next_value2;
+    if (interface1_re_next_value_ce2) begin
+        interface1_re <= interface1_re_next_value2;
+    end
+    if (interface1_we_next_value_ce3) begin
+        interface1_we <= interface1_we_next_value3;
     end
     interface0_bank_bus_dat_r <= 1'd0;
     if (csrbank0_sel) begin
@@ -11776,7 +11808,7 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (csrbank1_dly_sel0_re) begin
-        ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+        ddrphy_dly_sel_storage <= csrbank1_dly_sel0_r;
     end
     ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
     ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re;
@@ -11837,19 +11869,19 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (csrbank2_dfii_control0_re) begin
-        litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+        litedramcore_storage <= csrbank2_dfii_control0_r;
     end
     litedramcore_re <= csrbank2_dfii_control0_re;
     if (csrbank2_dfii_pi0_command0_re) begin
-        litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r;
+        litedramcore_phaseinjector0_command_storage <= csrbank2_dfii_pi0_command0_r;
     end
     litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
     if (csrbank2_dfii_pi0_address0_re) begin
-        litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+        litedramcore_phaseinjector0_address_storage <= csrbank2_dfii_pi0_address0_r;
     end
     litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
     if (csrbank2_dfii_pi0_baddress0_re) begin
-        litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+        litedramcore_phaseinjector0_baddress_storage <= csrbank2_dfii_pi0_baddress0_r;
     end
     litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
     if (csrbank2_dfii_pi0_wrdata1_re) begin
@@ -11861,15 +11893,15 @@ always @(posedge sys_clk) begin
     litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
     litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
     if (csrbank2_dfii_pi1_command0_re) begin
-        litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r;
+        litedramcore_phaseinjector1_command_storage <= csrbank2_dfii_pi1_command0_r;
     end
     litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
     if (csrbank2_dfii_pi1_address0_re) begin
-        litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+        litedramcore_phaseinjector1_address_storage <= csrbank2_dfii_pi1_address0_r;
     end
     litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
     if (csrbank2_dfii_pi1_baddress0_re) begin
-        litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+        litedramcore_phaseinjector1_baddress_storage <= csrbank2_dfii_pi1_baddress0_r;
     end
     litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
     if (csrbank2_dfii_pi1_wrdata1_re) begin
@@ -12151,6 +12183,7 @@ always @(posedge sys_clk) begin
         init_done_re <= 1'd0;
         init_error_storage <= 1'd0;
         init_error_re <= 1'd0;
+        interface1_re <= 1'd0;
         interface1_we <= 1'd0;
         litedramcore_refresher_state <= 2'd0;
         litedramcore_bankmachine0_state <= 3'd0;
@@ -14965,5 +14998,5 @@ TRELLIS_IO #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:11.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:49.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
index 7cf9fda..7f8070d 100644
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842a2c83c4c0001
+3c4c000100000000
+7c0802a63842a3a4
+f821ffc148001e09
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+0000000048001e20
+0000038001000000
+3842a3503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-480016f5f9410108
+4800173df9410108
 7c7f1b7860000000
-4800114538610020
+4800119938610020
 382100b060000000
-48001d687fe3fb78
+48001dc87fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,605 +552,616 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842a22c
-48001ca17d600026
-f821fed191610008
-6000000048001141
-38637b183c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842a2b4
+48001cfd7d600026
+f821fec191610008
+6000000048001195
+38637af03c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637b383be00008
+38637b103be00008
 4bffff1d67ffc000
-38637b583c62ffff
+38637b303c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637b70
+4bfffef538637b48
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637b78
+4bfffedd38637b50
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b80
+4bfffec538637b58
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b88
+4bfffead38637b60
 4182001073e90010
-38637b983c62ffff
+38637b703c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637ba8
-3b7b7bb03f62ffff
-4bfffe757f63db78
+4bfffe8538637b80
+3b397b883f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637bb87884b582
+38637b907884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637bd0
+4bfffe2d38637ba8
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637be8
+4bfffe0d38637bc0
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637c007c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637c2057c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637bd87c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637bf857e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637c40
-4082009073a90002
-38637c603c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637c18
+4082006473c90002
+38637c383c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637c78
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637c887b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637cb838847ca8
-480003394bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637cd83c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637c48
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637cf0
-38a000403c9af000
+4bfffc2d38637ce8
+38a000403c9cf000
 3861007078840020
-6000000048000e35
+6000000048000f69
 3d200002e9410070
 6129464c3c62ffff
-792983e438637d08
+792983e438637d00
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637d283c62ffff
-892100774bfffae9
+38637d203c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d8888810070
+38637d8088810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637db8
-3880600038a00000
-6484ff0060a5a000
-48000d913c604000
+3c62ffff4bfffb99
+4bfffb8d38637db0
+3880f80338a00000
+7884682860a5a000
+48000ec53c604000
 3c62ffff60000000
-4bfffa8538637dd8
-4bffff184bfffafd
+4bfffb6538637dd0
+480002184bfffbdd
 3f22ffffebe10090
-3b397d403ba00000
-a12100a87ffafa14
+3b397d383ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637d68
-e86100884bfffac5
+4bfffb2d38637d60
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-480017c07d638120
+8161000838210140
+480018fc7d638120
 38a000383c9ff000
 386100b078840020
-6000000048000d15
+6000000048000e49
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-6000000048000ccd
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+6000000048000e01
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637c50
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637c58
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
 38637c703c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
-000000004e800020
-0000000000000000
-6529c80039200804
-7c604f2a7c0004ac
-3920000139400808
-7c0004ac654ac800
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-3920080038429bf4
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637c807b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637cb038847ca0
+4800016d4bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637cd03c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920080400000000
 7c0004ac6529c800
-280a000e7d404e2a
-7c0802a64d820020
-f80100103940000e
-7c0004acf821ffa1
-3c62ffff7d404f2a
-4bfff8f538637df0
-3821006060000000
-7c0803a6e8010010
+394008087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
-0000008001000000
-38429b903c4c0001
+0000000000000000
+38429c283c4c0001
 6529c80039200800
 7d404e2a7c0004ac
-4d820020280a0001
-394000017c0802a6
+4d820020280a000e
+3940000e7c0802a6
 f821ffa1f8010010
 7d404f2a7c0004ac
-38637e183c62ffff
-600000004bfff891
+38637de83c62ffff
+600000004bfff8a1
 e801001038210060
 4e8000207c0803a6
 0100000000000000
 3c4c000100000080
-7c0802a638429b2c
-3c8040003c62ffff
-480015a138637e40
-3f60c800f821ff71
-7b7b00203be00000
-600000004bfff841
-7c0004ac4bffff0d
-3b4000047fe0df2a
-7c0004ac675ac800
-3ba0080c7fe0d72a
-7c0004ac67bdc800
-3bc008107fe0ef2a
-7c0004ac67dec800
-3b8008007fe0f72a
-679cc8003920000c
-7d20e72a7c0004ac
-6063c35038600000
-7c0004ac4bfffe5d
-7c0004ac7fe0ef2a
-3920000e7fe0f72a
-7d20e72a7c0004ac
-4bfffe3938602710
-7c0004ac39200200
-392000027d20ef2a
-7d20f72a7c0004ac
-4bfffe353860000f
+3920080038429bc4
+7c0004ac6529c800
+280a00017d404e2a
+7c0802a64d820020
+f801001039400001
+7c0004acf821ffa1
+3c62ffff7d404f2a
+4bfff83d38637e10
+3821006060000000
+7c0803a6e8010010
+000000004e800020
+0000008001000000
+38429b603c4c0001
+3c62ffff7c0802a6
+38637e383c804000
+f821ff71480015ad
+3be000003b600019
+4bfff7ed7b7bd800
+4bffff0d60000000
+7fe0df2a7c0004ac
+675ac8003b400004
+7fe0d72a7c0004ac
+67bdc8003ba0080c
 7fe0ef2a7c0004ac
-7c0004ac39200003
-3860000f7d20f72a
-392000064bfffe19
+67dec8003bc00810
+7fe0f72a7c0004ac
+3920000c3b800800
+7c0004ac679cc800
+386000007d20e72a
+4bfffe5d6063c350
+7fe0ef2a7c0004ac
+7fe0f72a7c0004ac
+7c0004ac3920000e
+386027107d20e72a
+392002004bfffe39
 7d20ef2a7c0004ac
-7c0004ac3b800001
-3860000f7f80f72a
-392009204bfffdf9
+7c0004ac39200002
+3860000f7d20f72a
+7c0004ac4bfffe35
+392000037fe0ef2a
+7d20f72a7c0004ac
+4bfffe193860000f
+7c0004ac39200006
+3b8000017d20ef2a
+7f80f72a7c0004ac
+4bfffdf93860000f
+7c0004ac39200920
+7c0004ac7d20ef2a
+3860000f7fe0f72a
+386000c84bfffddd
+392004004bfffdb9
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bfffddd3860000f
-4bfffdb9386000c8
-7c0004ac39200400
-7c0004ac7d20ef2a
-386000037fe0f72a
-386000c84bfffdb9
-4bfffe4d4bfffd95
-3c60400038800400
-60000000480006e9
-408200242c030000
-7c0004ac7c691b78
-7c0004ac7f80d72a
-382100907f80df2a
-480014787d2307b4
-38a0000038c00000
-3c60400038800400
-6000000048000471
+4bfffdb938600003
+4bfffd95386000c8
+388004004bfffe4d
+480006e93c604000
+2c03000060000000
+7c691b7840820024
+7f80d72a7c0004ac
 7f80df2a7c0004ac
-4bffffd039200001
-0100000000000000
-3c4c000100000680
-7c0802a638429964
-f8010010282303ff
-41810028f821ffa1
-3c62ffff7c641b78
-4bfff67d38637e60
-3821006060000000
-7c0803a6e8010010
-3d2000104e800020
-408000287c234840
-39200066786505a0
-7864b2827ca54b92
-38637e683c62ffff
-600000004bfff641
-3d2040004bffffc4
-7c23484078646502
-7863b28240800024
-7d29185078895564
-3c62ffff38a00066
-38637e787ca92b92
-786317824bffffc8
-7865556439200066
-7c641b787ca52050
-7ca54b923c62ffff
-4bffffa438637e88
-0100000000000000
-3c4c000100000080
-7c0802a638429894
-7cc42a14fbe1fff8
-7c8523787cbf2b78
+7d2307b438210090
+38c0000048001484
+3880040038a00000
+480004713c604000
+7c0004ac60000000
+392000017f80df2a
+000000004bffffd0
+0000068001000000
+384299983c4c0001
+282303ff7c0802a6
+f821ffa1f8010010
+7c641b7841810028
+38637e583c62ffff
+600000004bfff629
+e801001038210060
+4e8000207c0803a6
+7c2348403d200010
+786505a040800028
+7ca54b9239200066
+3c62ffff7864b282
+4bfff5ed38637e60
+4bffffc460000000
+786465023d204000
+408000247c234840
+788955647863b282
+38a000667d291850
+7ca92b923c62ffff
+4bffffc838637e70
+3920006678631782
+7ca5205078655564
 3c62ffff7c641b78
-38637e9878c60020
-f821ff91f8010010
-600000004bfff5a1
-4bfffef97fe3fb78
-38637ea83c62ffff
-600000004bfff589
-4800134038210070
-0100000000000000
-2c24000000000180
-7869f84241820024
-7c6300d0786307e0
-5463028054630794
-786300207c634a78
-386300014e800020
-000000004bfffff4
+38637e807ca54b92
+000000004bffffa4
+0000008001000000
+384298c83c4c0001
+fbe1fff87c0802a6
+7cbf2b787cc42a14
+7c641b787c852378
+78c600203c62ffff
+f801001038637e90
+4bfff54df821ff91
+7fe3fb7860000000
+3c62ffff4bfffef9
+4bfff53538637ea0
+3821007060000000
+000000004800134c
+0000018001000000
+418200242c240000
+786307e07869f842
+546307947c6300d0
+7c634a7854630280
+4e80002078630020
+4bfffff438630001
 0000000000000000
-384297f03c4c0001
-788407647c0802a6
-7c691b783d40aaaa
-48001269614aaaaa
-7884f0827f832214
-39040001f821ffc1
-7d0903a67c7f1b78
-420000807c7d1b78
-600000004bfff55d
-3d00aaaa7d3fe050
-7feafb787929f082
-3bc0000039290001
-6108aaaa7d2903a6
-7d3fe05042000060
-7929f0823d005555
+3c4c000100000000
+7c0802a638429824
+3d40aaaa78840764
+614aaaaa7c691b78
+7f83221448001275
+f821ffc17884f082
+7c7f1b7839040001
+7c7d1b787d0903a6
+4bfff50942000080
+7d3fe05060000000
+7929f0823d00aaaa
 392900017feafb78
-7d2903a661085555
-7fffe05042000058
-600000004bfff50d
-3d2055557bfff082
-61295555395f0001
-420000407d4903a6
-7fc307b438210040
-914900004800121c
-4bffff7839290004
-7c094000812a0000
+7d2903a63bc00000
+420000606108aaaa
+3d0055557d3fe050
+7feafb787929f082
+6108555539290001
+420000587d2903a6
+4bfff4b97fffe050
+7bfff08260000000
+395f00013d205555
+7d4903a661295555
+3821004042000040
+480012287fc307b4
+3929000491490000
+812a00004bffff78
+418200087c094000
+394a00043bde0001
+910a00004bffff8c
+4bffffa0394a0004
+7c0a4800815d0000
 3bde000141820008
-4bffff8c394a0004
-394a0004910a0000
-815d00004bffffa0
-418200087c0a4800
-3bbd00043bde0001
-000000004bffffac
-0000048001000000
-384296e03c4c0001
-7c0802a67d600026
-2e26000091610008
-f821ff4148001141
-7cba2b787c7f1b78
-789cf0827cde3378
-81260004419200c0
-2c09000082e60000
-3f02ffff40820044
-3b6000013ba00000
-3b187eb07bf90020
-4082009c7c3ce840
+4bffffac3bbd0004
+0100000000000000
+3c4c000100000480
+7d60002638429714
+916100087c0802a6
+4800114d2e260000
+7c7f1b78f821ff41
+7cde33787cba2b78
+419200e4789cf082
+82e6000081260004
+418200d82c090000
+600000004bfff3f5
+7ffbfb782d970000
+3ac000013ba00000
+7bf500203b200000
+7fb8eb787c3ce840
+2c170000408200c4
+3c62ffff41820028
+38637eb87b051028
+4bfffdcd7be40020
+38637b883c62ffff
+600000004bfff339
+7f2307b4382100c0
+7d61812081610008
+7b63002048001108
+4bfffdfd7f44d378
+7c7f492e7ba91764
+7c7b1b7873a97fff
+7ba5102840820014
+7f03c3787f24cb78
+3bbd00014bfffd79
+4082ffc87c3ce840
 7b8510283c62ffff
-7be4002038637eb0
-3c62ffff4bfffde5
-4bfff3a538637bb0
-4bfff40960000000
-2d97000060000000
-3ba000007ffbfb78
-3b2000003ac00001
-7c3de0407bf50020
-408200847fb8eb78
-418200282c170000
-7b0510283c62ffff
-7be4002038637ec0
-3c62ffff4bfffd8d
-4bfff34d38637bb0
-382100c060000000
-816100087f2307b4
-480010bc7d618120
-4bffff503ae00001
-7f44d3787b630020
-7ba917644bfffdb5
-73a97fff7c7f492e
-408200147c7b1b78
-7f24cb787ba51028
-4bfffd317f03c378
-4bffff2c3bbd0001
-7ac300207f44d378
-809b00004bfffd7d
-7c761b787c651b78
-4182003c7c032040
-419200343b390001
-2c2c0000e99e0008
-7d8903a641820028
-78840020e8de0010
-7b630020f8410018
-e84100184e800421
-4082ff582c030000
-4082001c73187fff
-3c62ffff418e0018
-7ea4ab787ba51028
-4bfffcb138637ec0
-3b7b00043bbd0001
-000000004bfffef4
-00000b8003000000
-384295203c4c0001
-7c0802a67d708026
-48000f9991610008
-7cdb3378f821ff71
-2e3b00003ba4ffe0
-7c9e23787c7f1b78
-7c641b787fa3ea14
-38637ed03c62ffff
-4bfff21d7cbc2b78
-3c62ffff60000000
-4092000c38637ee8
-38637ef83c62ffff
-600000004bfff201
-4bfffb597fc3f378
-38637f083c62ffff
-600000004bfff1e9
-408200a82c3c0000
-38df00207cf602a6
-7c26284038bd0020
-7929d9427d3fe850
-3900ffff7feafb78
-4081000839290001
-2c29000139200001
-3929fffff90a0000
-f90a0010f90a0008
-394a0020f90a0018
-7d3602a64082ffe4
-78ea00203f8005f5
-79290020639ce100
-7d2950507f9ee1d2
-38637f103c62ffff
-4bfff1657f9c4b92
-7f83e37860000000
-3c62ffff4bfffabd
-4bfff14d38637f20
-3c62ffff60000000
-4bfff13d38637bb0
-4bfff1a160000000
-7f9602a660000000
-7d3fe85040920048
-3bbd0020395f0020
-7c2ae8407929d942
-4081000839290001
-2c29000139200001
-3929ffffe95f0000
-e95f0010e95f0008
-3bff0020e95f0018
-4800001c4082ffe4
-394000007bdbe8c2
-3ba000007f7adb78
-4082006c7c1dd000
-3d4005f57d3602a6
-614ae1007b9c0020
-7fde51d279290020
-3c62ffff7d29e050
-7fde4b9238637f28
-600000004bfff0a1
-4bfff9f97fc3f378
+7be4002038637ea8
+3c62ffff4bfffd59
+4bfff2c538637b88
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187ea87bf90020
+7f44d3784bffffb8
+4bfffd7d7ac30020
+7c651b78809b0000
+7c0320407c761b78
+3b3900014182003c
+e99e000841920034
+418200282c2c0000
+e8de00107d8903a6
+f841001878840020
+4e8004217b630020
+2c030000e8410018
+73187fff4082ff18
+418e00184082001c
+7ba510283c62ffff
+38637eb87ea4ab78
+3bbd00014bfffcb1
+4bfffeb43b7b0004
+0300000000000000
+3c4c000100000b80
+7d70802638429554
+916100087c0802a6
+f821ff7148000fa5
+3ba4ffe07cdb3378
+7c7f1b782e3b0000
+7fa3ea147c9e2378
+3c62ffff7c641b78
+7cbc2b7838637ec8
+600000004bfff1c9
+38637ee03c62ffff
+3c62ffff4092000c
+4bfff1ad38637ef0
+7fc3f37860000000
+3c62ffff4bfffb59
+4bfff19538637f00
+2c3c000060000000
+7cf602a6408200a8
+38bd002038df0020
+7d3fe8507c262840
+7feafb787929d942
+392900013900ffff
+3920000140810008
+f90a00002c290001
+f90a00083929ffff
+f90a0018f90a0010
+4082ffe4394a0020
+3f8005f57d3602a6
+639ce10078ea0020
+7f9ee1d279290020
+3c62ffff7d295050
+7f9c4b9238637f08
+600000004bfff111
+4bfffabd7f83e378
+38637f183c62ffff
+600000004bfff0f9
+38637b883c62ffff
+600000004bfff0e9
+600000004bfff14d
+409200487f9602a6
+395f00207d3fe850
+7929d9423bbd0020
+392900017c2ae840
+3920000140810008
+e95f00002c290001
+e95f00083929ffff
+e95f0018e95f0010
+4082ffe43bff0020
+7bdbe8c24800001c
+7f7adb7839400000
+7c1dd0003ba00000
+7d3602a64082006c
+7b9c00203d4005f5
+79290020614ae100
+7d29e0507fde51d2
 38637f203c62ffff
-600000004bfff089
-38637bb03c62ffff
-600000004bfff079
-8161000838210090
-48000e007d708120
-794300207fa407b4
-3bbd00014bfffaed
-7c6a1b787d23db96
-7d2918507d29d9d6
-7d3f482a79291f48
-000000004bffff68
-0000068003000000
-384292e83c4c0001
-282402007c0802a6
-f821ff8148000d6d
-7c9f23787c7e1b78
-418100083b800200
-3c62ffff7c9c2378
-38637f387fc4f378
-600000004bffeff1
-4bfff9497fe3fb78
-38637f083c62ffff
-600000004bffefd9
-7fc3f3787f84e378
-38c000004bfffaa1
-7fe4fb7838a00001
-7fc3f3787c7d1b78
-7d23ea144bfffb99
-2c0900007c7e1b78
-3c62ffff4182007c
-7fa4eb787b85f882
-4bffef8d38637f48
-283f008060000000
-408100087fe5fb78
-3c62ffff38a00080
-3880000078a5f082
-4bffef6538637f60
+4bfff04d7fde4b92
+7fc3f37860000000
+3c62ffff4bfff9f9
+4bfff03538637f18
 3c62ffff60000000
-7fc4f3787be5f082
-4bffef4d38637f78
-3c62ffff60000000
-4bffef3d38637f90
-3860000060000000
-786307e038210080
-3c62ffff48000ccc
-4bffef1d38637fa0
-3860000160000000
-000000004bffffe0
-0000048001000000
-384291c03c4c0001
-8922802060000000
-3942801860000000
-418200302c090000
-39290014e92a0000
-7d204eaa7c0004ac
-4182ffec71290020
-e922801860000000
-7c604faa7c0004ac
-e92a00004e800020
-7c0004ac39290010
-712900087d204eea
-5469063e4082ffec
-e942801860000000
-7d2057ea7c0004ac
-000000004e800020
+4bfff02538637b88
+3821009060000000
+7d70812081610008
+7fa407b448000e0c
+4bfffaed79430020
+7d23db963bbd0001
+7d29d9d67c6a1b78
+79291f487d291850
+4bffff687d3f482a
+0300000000000000
+3c4c000100000680
+7c0802a63842931c
+48000d7928240200
+7c7e1b78f821ff81
+3b8002007c9f2378
+7c9c237841810008
+7fc4f3783c62ffff
+4bffef9d38637f30
+7fe3fb7860000000
+3c62ffff4bfff949
+4bffef8538637f00
+7f84e37860000000
+4bfffaa17fc3f378
+38a0000138c00000
+7c7d1b787fe4fb78
+4bfffb997fc3f378
+7c7e1b787d23ea14
+4182007c2c090000
+7b85f8823c62ffff
+38637f407fa4eb78
+600000004bffef39
+7fe5fb78283f0080
+38a0008040810008
+78a5f0823c62ffff
+38637f5838800000
+600000004bffef11
+7be5f0823c62ffff
+38637f707fc4f378
+600000004bffeef9
+38637f883c62ffff
+600000004bffeee9
+3821008038600000
+48000cd8786307e0
+38637f983c62ffff
+600000004bffeec9
+4bffffe038600001
+0100000000000000
+3c4c000100000480
+60000000384291f4
+6000000089228018
+2c09000039428010
+e92a000041820030
+7c0004ac39290014
+712900207d204eaa
+600000004182ffec
+7c0004ace9228010
+4e8000207c604faa
+39290010e92a0000
+7d204eea7c0004ac
+4082ffec71290008
+600000005469063e
+7c0004ace9428010
+4e8000207d2057ea
 0000000000000000
-384291383c4c0001
-fbe1fff87c0802a6
-3be3fffffbc1fff0
-f821ffd1f8010010
-2c1e00008fdf0001
-3821003040820010
-48000c0438600000
-4082000c2c1e000a
-4bffff3d3860000d
-4bffff3557c3063e
-000000004bffffd0
-0000028001000000
-384290d83c4c0001
-654ac00039400020
-7d4056ea7c0004ac
-794a060039200008
-7c0004ac6529c000
-712900207d204eea
-3920004041820014
-7c0004ac6529c000
-7929f8047d204eea
-79290fc339002000
-600000006508c000
-3d00001cf9028018
-7d4a439261082000
-6000000041820080
-9922802039200001
-3920ff803900200c
-7c0004ac6508c000
-e92280187d2047aa
-7d404faa7c0004ac
-794ac202e9228018
-7c0004ac39290004
-e92280187d404faa
-3929000c39400003
+3c4c000100000000
+7c0802a63842916c
+fbc1fff0fbe1fff8
+f80100103be3ffff
+8fdf0001f821ffd1
+408200102c1e0000
+3860000038210030
+2c1e000a48000c10
+3860000d4082000c
+7bc300204bffff3d
+4bffffd04bffff35
+0100000000000000
+3c4c000100000280
+394000203842910c
+7c0004ac654ac000
+392000087d4056ea
+6529c000794a0600
+7d204eea7c0004ac
+4182001471290020
+6529c00039200040
+7d204eea7c0004ac
+390020007929f804
+6508c00079290fc3
+f902801060000000
+610820003d00001c
+418200807d4a4392
+3920000160000000
+3900200c99228018
+6508c0003920ff80
+7d2047aa7c0004ac
+7c0004ace9228010
+e92280107d404faa
+39290004794ac202
 7d404faa7c0004ac
-39290010e9228018
+39400003e9228010
+7c0004ac3929000c
+e92280107d404faa
+7c0004ac39290010
+e92280107d404faa
+3929000839400007
 7d404faa7c0004ac
-39400007e9228018
-7c0004ac39290008
-4e8000207d404faa
-394affff60000000
-3920201899228020
-7c0004ac6529c000
-4e8000207d404fea
-0000000000000000
-78a9e8c200000000
-3929000139400000
-420000287d2903a6
-78a5076078a90724
-7d434a1439050001
-7c844a147d0903a6
-4200001839200000
+600000004e800020
+99228018394affff
+6529c00039202018
+7d404fea7c0004ac
+000000004e800020
+0000000000000000
+3940000078a9e8c2
+7d2903a639290001
+78a9e8c24200002c
+1d29fff839400000
+7c8920507ca54a14
+7d29185039050001
+420000187d0903a6
 7d24502a4e800020
 394a00087d23512a
-7d0448ae4bffffcc
-392900017d0a49ae
+7d0450ae4bffffc8
+394a00017d0951ae
 000000004bffffdc
 0000000000000000
 386000007c691b78
@@ -1143,111 +1169,109 @@ e92280187d404faa
 386300014d820020
 000000004bfffff0
 0000000000000000
-408200082c240000
-280500243881fff0
-38600000f8640000
-3d2000014d810020
-612a2600792983e4
-89090000e9240000
-4181004028080020
+7c691b782c240000
+3881fff040820008
+f924000028050024
+4d81002038600000
+794a83e43d400001
+89090000614a2600
+4181003828080020
 70e700017d474436
-2c25000040820028
-2c050010418200e0
-2c08003040820010
-38a0001041820048
-4800008038600000
+2c25000040820020
+2c050010418200d0
+3929ffff41820028
+4800007838600000
 f924000039290001
-2c2500004bffffb8
-2c0800304082ffd4
-4082ffdc38a0000a
-2c0a007889490001
-392900024082ffd0
-4bffffc0f9240000
+2c2500004bffffc4
+38a0000a4082ffdc
+4082ffd82c080030
 2c0a007889490001
-4bffffe84082ffb4
-54e7063e38eaffd0
-4181003c28070009
-7d2a07343929ffd0
-4c8000207c0a2800
-7c6519d239080001
-f90400007d290734
-e90400007c691a14
-714900ff89480000
-4e8000204082ffc0
-54e7063e38eaff9f
+392900024082ffcc
+f924000038a00010
+38e8ffd04bffffbc
+2807000954e7063e
+394affd041810040
+7c0828007d480734
+7c6519d24c800020
+7d4a073439290002
+7cc93378f9240000
+890900017c6a1a14
+710a00ff38c90001
+4e8000204082ffbc
+54e7063e38e8ff9f
 4181000c28070019
-4bffffb83929ffa9
-554a063e394affbf
-4d810020280a0019
-4bffffa03929ffc9
-4bffff3438a0000a
+4bffffb4394affa9
+5508063e3908ffbf
+4d81002028080019
+4bffff9c394affc9
+4bffff3838a0000a
 0000000000000000
 3923ff9f00000000
 4181000828090019
 7c6307b43863ffe0
 000000004e800020
 0000000000000000
-38428dd83c4c0001
-480008557c0802a6
+38428e183c4c0001
+4800086d7c0802a6
 7c7e1b78f821ffa1
 7ca32b787cfd3b78
 38a0000a7c9c2378
 eb3e000038800000
 7d1b43787cdf3378
-4bfffe657d3a4b78
+4bfffe757d3a4b78
 2b9d001060000000
 2c3f000039400000
 2c0a00004082005c
-3940000140820008
+3940000141810008
 7c0350007d4ad214
-7d2350504081003c
-792900207d2948f8
-7d2903a639290001
+7d4a18504081003c
+794a0020394affff
+7d2903a6392a0001
 7d594850e93e0000
 408000187c2ae040
 e93e00009b690000
 f93e000039290001
 382100604200ffe0
-409e001048000808
+409e001048000820
 394a00017bffe102
 7fffeb924bffff94
 000000004bfffff4
 0000078001000000
-38428d083c4c0001
-4800078d7c0802a6
+38428d483c4c0001
+480007a57c0802a6
 eb630000f821ffb1
 7c9c23787c7f1b78
 3bc000007cbd2b78
-4bfffd7d7fa3eb78
+4bfffd8d7fa3eb78
 7c3e184060000000
 e93f000040800014
 7c2ae0407d5b4850
 382100504180000c
-7d5df0ae48000798
+7d5df0ae480007b0
 994900003bde0001
 39290001e93f0000
 4bffffbcf93f0000
 0100000000000000
 3c4c000100000580
-7c0802a638428c8c
-e9297fb03d22ffff
+7c0802a638428ccc
+e9297fa83d22ffff
 7d7080262b860010
-916100087caa2b78
-f821ffa1480006f5
-7cbe2b787c7c1b78
-3be000007cdd3378
-3d22fffff9210020
-f9210028e9297fb8
-408200342c2a0000
-408200082c1f0000
+4800071191610008
+7c7c1b78f821ffa1
+7cdd33787cbe2b78
+f92100203be00000
+e9297fb03d22ffff
+7ca92b78f9210028
+408200342c290000
+418100082c1f0000
 7fff07b43be00001
 7c3f20402e270000
 408100303b7fffff
 8161000838210060
-480006e87d708120
-794ae102409e0010
+480007007d708120
+7929e102409e0010
 4bffffbc3bff0001
-4bfffff47d4aeb92
+4bfffff47d29eb92
 7f5eeb927f5ed378
 7d29f0507d3ae9d2
 886900207d214a14
@@ -1259,195 +1283,198 @@ e93c00004081ffc8
 f93c00007d29fa14
 000000004bffff90
 0000068003000000
-38428b983c4c0001
-480005e97c0802a6
-7c761b79f821fef1
+38428bd83c4c0001
+480006017c0802a6
+7c751b79f821fef1
 38600000f8610060
-2c2400004182003c
-3b04ffff41820034
-3a8000003aa10040
-ebc1006089250000
-7c76f050712a00ff
-7c23c0404182000c
+2c24000041820044
+7cbd2b784182003c
+3a6100403ae4ffff
+3a4000003b210020
+ebc10060895d0000
+7c75f050714900ff
+7c23b8404182000c
 3920000041800018
 38210110993e0000
-480005e07c6307b4
-390500012c0a0025
-3920000040820564
-7cb32b7889450000
-7d49a9ae8ce50001
-280a007854ea063e
-280a006241810024
-2c0a004f41810024
-2c0a0058418200a0
-2c0a002541820098
-3929000141820090
-3907ff9d4bffffc0
-280400155504063e
-3c82ffff4181ffec
-790815a838847550
-7d0822147d0442aa
-4e8004207d0903a6
+480005f07c6307b4
+391d00012c090025
+3920000040820574
+895d00017d4999ae
+5548063e389d0001
+4181002428080078
+4181002828080062
+418200a42c08004f
+4182009c2c080058
+418200942c080025
+7c9d237839290001
+38eaff9d4bffffc0
+2805001554e5063e
+3ca2ffff4181ffe8
+78e715a838a57518
+7ce72a147ce53aaa
+4e8004207ce903a6
 0000005800000058
-ffffffccffffffcc
-ffffffccffffffcc
-ffffffcc00000058
-ffffffccffffffcc
-ffffffccffffffcc
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+ffffffc800000058
+ffffffc8ffffffc8
+ffffffc8ffffffc8
 0000005800000058
-ffffffccffffffcc
-ffffffcc00000058
-ffffffcc00000058
-00000058ffffffcc
-2c0a002539090001
-38a1002039290002
-7d2907b47d0807b4
-7d254a147d054214
-9a89002098e80020
-393e000140820018
-f9210060995e0000
-4bfffebc38b30002
-eb86000089210041
-3a2600087fe3c050
-3b4100423a400030
-712900fd3929ffd2
-5649063e40820428
-3ae000003de2ffff
-f92100683b200004
-3a0000003b600000
-4800017039ef7fd0
-38da00012c07004f
-390affa8418201dc
-280500225505063e
-3ca2ffff418103bc
-790815a838a57668
-7d082a147d0542aa
-4e8004207d0903a6
-0000039c00000158
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-000002680000039c
-0000039c0000008c
-0000039c0000039c
-0000008c00000380
-0000039c0000039c
-0000039c00000368
-000001ac0000039c
-0000039c00000204
-000002ac0000039c
-0000008c0000039c
-0000039c0000039c
-0000039c0000015c
-2c070075000003c0
-7d4152147b6a0020
-7f9de37839000000
-41820044990a0020
-3940000157281838
-7d4a40363908ffff
-4182002c7f8a5039
-392900013940002d
-9949ffff7fbc00d0
-f92100603d42ffff
-394a7fd07b291e68
-7fbd48387d2a482a
-38e0000ae8810060
-38a100207fa6eb78
-5648063e39200000
-7c9e205038610060
-4bfffabd7c84f850
-7ae707e0e8810060
-7fa5eb7838c0000a
+ffffffc8ffffffc8
+ffffffc800000058
+ffffffc800000058
+00000058ffffffc8
+2c08002538e90001
+7ce707b439290002
+7cf93a147d2907b4
+994700207d394a14
+408200189a490020
+f9210060393e0001
+3bbd0002995e0000
+892100414bfffec0
+7fe3b850eb860000
+3a8000303a260008
+3929ffd23b410042
+4082043c712900fd
+3de2ffff5689063e
+3b0000043ac00000
+3b600000f9210068
+39ef7fc83a000000
+2c06004f4800016c
+418201e038ba0001
+54e4063e38e8ffa8
+418103d028040022
+3884762c3c82ffff
+7ce43aaa78e715a8
+7ce903a67ce72214
+000001544e800420
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+0000008c00000270
+000003b0000003b0
+00000394000003b0
+000003b00000008c
+0000037c000003b0
+000003b0000003b0
+0000020c000001b0
+000003b0000003b0
+000003b0000002b4
+000003b00000008c
+00000158000003b0
+000003d4000003b0
+7b6a00202c060075
+390000007d415214
+990a00207f8ee378
+5707183841820044
+38e7ffff39000001
+7f8840397d083836
+3940002d4182002c
+3ce2ffff39290001
+38e77fc87b081e68
+f92100609949ffff
+7d07402a7d5c00d0
+7c9e48507d4e4038
+7dc6737838e0000a
+7c84f8507f25cb78
+5688063e39200000
+4bfffabd38610060
+7ac707e0e8810060
+7dc5737838c0000a
 7c84f8507c9e2050
 4bfffbe938610060
-895a00003b5a0001
-714700ffe9210060
-7fbe485041820010
-4181fe7c7c3fe840
-4bfffe247e268b78
-7b6900203ae00001
+891a00003b5a0001
+710600ffe9210060
+7dde485041820010
+4181fe807c3f7040
+4bfffe287e268b78
+7b6900203ac00001
 38e00010e9010068
-7c9df8507d214a14
-3861006038a10020
-7b291e689a090020
-392000007d4f482a
-7dc673787f8e5038
-e88100604bfffa39
-38c000107ae707e0
-7dc573787c9e2050
-7b6900204bffff7c
-7d214a1439400000
-7c9df85038e00008
-994900205648063e
-7b291e683d42ffff
-38a10020394a7fd0
-7d4a482a38610060
-7f8e503839200000
-4bfff9dd7dc67378
-7ae707e0e8810060
-7c9e205038c00008
-7b6900204bffffa4
-7d214a1439400000
-7f86e37838e00010
-9949002039000020
-3920000238a10020
-386100607c9df850
-e88100604bfff999
-386100603ca2ffff
-7c9e205038a57fc8
-4bfffa4d7c84f850
-7ae707e0e8810060
-7f85e37838c00010
-4bfffec07c9e2050
-394000007b690020
-390000207d214a14
+7c8ef8507d214a14
+386100607f25cb78
+7b091e689a090020
+392000007d6f482a
+7d665b787f8b5838
+4bfffa35f9610070
+7ac707e0e8810060
+7c9e205038c00010
+7d655b78e9610070
+7b6900204bffff74
+7d214a1439000000
+7c8ef85038e00008
+990900207f25cb78
+7b091e683d02ffff
+3861006039087fc8
+392000007d68482a
+7f8b58385688063e
+f96100707d665b78
+e88100604bfff9d1
+38c000087ac707e0
+4bffff9c7c9e2050
+390000007b690020
+38e000107d214a14
+7f25cb787f86e378
+7c8ef85099090020
+3900002039200002
+4bfff98d38610060
+3ca2ffffe8810060
+38a57fc038610060
+7c84f8507c9e2050
+e88100604bfffa41
+38c000107ac707e0
+7c9e20507f85e378
+7b6900204bfffeb4
+7d214a1439000000
 38c0000138e0000a
-38a1002099490020
-7c9df85039200000
-4bfff93538610060
-9b890000e9210060
-f921006039290001
-7b6a00204bfffe88
-f921007039000000
-38a0000a7d415214
-3861002038800000
-4bfff795990a0020
-7c6e1b7860000000
-4bfff75d7f83e378
-7c2e184060000000
-e921007040810048
-7c6370507fbdf850
-38e0002039400000
-7d09f0503bbd0001
-7d08fa147c691a14
-408200082c280000
-2c3d00013ba00001
-408200283bbdffff
-40820034714a0001
-7f85e378e8810060
-7c9e205038610060
-4bfff9557c84f850
-98e900004bfffde8
-3940000139290001
-4082ffc07c291840
-4bffffccf9210060
-3b200008893a0001
-4082fdbc2c09006c
-4bfffdb47cda3378
-3b200002893a0001
-4082fda42c090068
-3b2000017cda3378
-392affd04bfffd98
+990900207f25cb78
+392000007c8ef850
+3861006039000020
+e92100604bfff929
+392900019b890000
+4bfffe7cf9210060
+38e000007b680020
+7d014214f9210078
+3880000038a0000a
+98e800207f23cb78
+600000004bfff799
+7f83e378f8610070
+600000004bfff761
+e9210078e9010070
+418100207c281840
+7c9e20507d244b78
+7c84f8507f85e378
+4bfff98538610060
+7ce9f0504bfffe18
+7ce7fa147c634050
+2c2700007d4ef850
+7d244b787c691a14
+38c0002039000000
+40820008394a0001
+2c2a000139400001
+40820010394affff
+4082001c71080001
+98c400004bffffa0
+3900000138840001
+4082ffd87c241840
+4bffff88f8810060
+3b000008893a0001
+4082fda42c09006c
+4bfffd9c7cba2b78
+3b000002893a0001
+4082fd8c2c090068
+3b0000017cba2b78
+3928ffd04bfffd80
 280900095529063e
-7b6900204181fd88
+7b6900204181fd70
 7d214a143b7b0001
-4bfffd7499490020
-4bfffd6c3b200008
-3b4100413a400020
-993e00004bfffbd4
-7d0543783bde0001
-4bfffa54fbc10060
+4bfffd5c99090020
+4bfffd543b000008
+3b4100413a800020
+995e00004bfffbc0
+7d1d43783bde0001
+4bfffa44fbc10060
 0100000000000000
 f9c1ff7000001280
 fa01ff80f9e1ff78
@@ -1517,14 +1544,18 @@ e8010010ebc1fff0
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1619,7 +1650,7 @@ e8010010ebc1fff0
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
index 4b6cea9..f54a078 100644
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:12
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:53
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -346,6 +346,7 @@ wire   [29:0] interface0_adr;
 wire   [13:0] interface0_bank_bus_adr;
 reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface0_bank_bus_dat_w;
+wire          interface0_bank_bus_re;
 wire          interface0_bank_bus_we;
 wire    [1:0] interface0_bte;
 wire    [2:0] interface0_cti;
@@ -362,14 +363,18 @@ reg           interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] interface1_bank_bus_adr;
 reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] interface1_bank_bus_dat_w;
+wire          interface1_bank_bus_re;
 wire          interface1_bank_bus_we;
 wire   [31:0] interface1_dat_r;
 reg    [31:0] interface1_dat_w = 32'd0;
 reg    [31:0] interface1_dat_w_next_value0 = 32'd0;
 reg           interface1_dat_w_next_value_ce0 = 1'd0;
+reg           interface1_re = 1'd0;
+reg           interface1_re_next_value2 = 1'd0;
+reg           interface1_re_next_value_ce2 = 1'd0;
 reg           interface1_we = 1'd0;
-reg           interface1_we_next_value2 = 1'd0;
-reg           interface1_we_next_value_ce2 = 1'd0;
+reg           interface1_we_next_value3 = 1'd0;
+reg           interface1_we_next_value_ce3 = 1'd0;
 reg           locked0 = 1'd0;
 reg           locked1 = 1'd0;
 reg           locked2 = 1'd0;
@@ -393,6 +398,7 @@ reg           new_master_wdata_ready0 = 1'd0;
 reg           new_master_wdata_ready1 = 1'd0;
 reg     [1:0] next_state = 2'd0;
 wire          por_clk;
+wire          re;
 reg     [1:0] refresher_next_state = 2'd0;
 reg     [1:0] refresher_state = 2'd0;
 reg           rhs_self0 = 1'd0;
@@ -1646,9 +1652,9 @@ reg           soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [13:0] soc_litedramcore_csr_dfi_p0_address;
 wire    [2:0] soc_litedramcore_csr_dfi_p0_bank;
 reg           soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          soc_litedramcore_csr_dfi_p0_cke;
 reg           soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          soc_litedramcore_csr_dfi_p0_odt;
 reg           soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
 wire          soc_litedramcore_csr_dfi_p0_rddata_en;
@@ -1662,9 +1668,9 @@ reg           soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [13:0] soc_litedramcore_csr_dfi_p1_address;
 wire    [2:0] soc_litedramcore_csr_dfi_p1_bank;
 reg           soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          soc_litedramcore_csr_dfi_p1_cke;
 reg           soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          soc_litedramcore_csr_dfi_p1_odt;
 reg           soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
 wire          soc_litedramcore_csr_dfi_p1_rddata_en;
@@ -1678,9 +1684,9 @@ reg           soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
 wire   [13:0] soc_litedramcore_csr_dfi_p2_address;
 wire    [2:0] soc_litedramcore_csr_dfi_p2_bank;
 reg           soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p2_cke = 1'd0;
+wire          soc_litedramcore_csr_dfi_p2_cke;
 reg           soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p2_odt = 1'd0;
+wire          soc_litedramcore_csr_dfi_p2_odt;
 reg           soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
 reg    [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
 wire          soc_litedramcore_csr_dfi_p2_rddata_en;
@@ -1694,9 +1700,9 @@ reg           soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
 wire   [13:0] soc_litedramcore_csr_dfi_p3_address;
 wire    [2:0] soc_litedramcore_csr_dfi_p3_bank;
 reg           soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p3_cke = 1'd0;
+wire          soc_litedramcore_csr_dfi_p3_cke;
 reg           soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           soc_litedramcore_csr_dfi_p3_odt = 1'd0;
+wire          soc_litedramcore_csr_dfi_p3_odt;
 reg           soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
 reg    [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
 wire          soc_litedramcore_csr_dfi_p3_rddata_en;
@@ -2267,36 +2273,36 @@ always @(*) begin
     soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel0_activate_row <= 14'd0;
+    soc_ddrphy_bankmodel0_activate <= 1'd0;
     case (soc_ddrphy_activates0)
         1'd1: begin
-            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0);
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel0_activate <= 1'd0;
+    soc_ddrphy_bankmodel0_activate_row <= 14'd0;
     case (soc_ddrphy_activates0)
         1'd1: begin
-            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0);
+            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0);
+            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0);
+            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0);
+            soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
@@ -2377,36 +2383,36 @@ always @(*) begin
     soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel0_read <= 1'd0;
+    soc_ddrphy_bankmodel0_read_col <= 10'd0;
     case (soc_ddrphy_reads0)
         1'd1: begin
-            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0);
+            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0);
+            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0);
+            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0);
+            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel0_read_col <= 10'd0;
+    soc_ddrphy_bankmodel0_read <= 1'd0;
     case (soc_ddrphy_reads0)
         1'd1: begin
-            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0);
         end
     endcase
 end
@@ -2483,36 +2489,36 @@ always @(*) begin
     soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-    soc_ddrphy_bank_write1 <= 1'd0;
+    soc_ddrphy_bank_write_col1 <= 10'd0;
     case (soc_ddrphy_writes1)
         1'd1: begin
-            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1);
+            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1);
+            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1);
+            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1);
+            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bank_write_col1 <= 10'd0;
+    soc_ddrphy_bank_write1 <= 1'd0;
     case (soc_ddrphy_writes1)
         1'd1: begin
-            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1);
         end
         2'd2: begin
-            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1);
         end
         3'd4: begin
-            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1);
         end
         4'd8: begin
-            soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1);
         end
     endcase
 end
@@ -2528,36 +2534,36 @@ always @(*) begin
     soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel1_read_col <= 10'd0;
+    soc_ddrphy_bankmodel1_read <= 1'd0;
     case (soc_ddrphy_reads1)
         1'd1: begin
-            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1);
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel1_read <= 1'd0;
+    soc_ddrphy_bankmodel1_read_col <= 10'd0;
     case (soc_ddrphy_reads1)
         1'd1: begin
-            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1);
+            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1);
+            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1);
+            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1);
+            soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
@@ -2569,36 +2575,36 @@ always @(*) begin
     soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel2_activate <= 1'd0;
+    soc_ddrphy_bankmodel2_activate_row <= 14'd0;
     case (soc_ddrphy_activates2)
         1'd1: begin
-            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2);
+            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2);
+            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2);
+            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2);
+            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel2_activate_row <= 14'd0;
+    soc_ddrphy_bankmodel2_activate <= 1'd0;
     case (soc_ddrphy_activates2)
         1'd1: begin
-            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2);
         end
     endcase
 end
@@ -2634,36 +2640,36 @@ always @(*) begin
     soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-    soc_ddrphy_bank_write_col2 <= 10'd0;
+    soc_ddrphy_bank_write2 <= 1'd0;
     case (soc_ddrphy_writes2)
         1'd1: begin
-            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2);
         end
         2'd2: begin
-            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2);
         end
         3'd4: begin
-            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2);
         end
         4'd8: begin
-            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2);
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bank_write2 <= 1'd0;
+    soc_ddrphy_bank_write_col2 <= 10'd0;
     case (soc_ddrphy_writes2)
         1'd1: begin
-            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2);
+            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2);
+            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2);
+            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2);
+            soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
@@ -2720,36 +2726,36 @@ always @(*) begin
     soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel3_activate_row <= 14'd0;
+    soc_ddrphy_bankmodel3_activate <= 1'd0;
     case (soc_ddrphy_activates3)
         1'd1: begin
-            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3);
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel3_activate <= 1'd0;
+    soc_ddrphy_bankmodel3_activate_row <= 14'd0;
     case (soc_ddrphy_activates3)
         1'd1: begin
-            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3);
+            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3);
+            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3);
+            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3);
+            soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
@@ -3087,36 +3093,36 @@ always @(*) begin
     soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-    soc_ddrphy_bank_write5 <= 1'd0;
+    soc_ddrphy_bank_write_col5 <= 10'd0;
     case (soc_ddrphy_writes5)
         1'd1: begin
-            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5);
+            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5);
+            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5);
+            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5);
+            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bank_write_col5 <= 10'd0;
+    soc_ddrphy_bank_write5 <= 1'd0;
     case (soc_ddrphy_writes5)
         1'd1: begin
-            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5);
         end
         2'd2: begin
-            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5);
         end
         3'd4: begin
-            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5);
         end
         4'd8: begin
-            soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5);
         end
     endcase
 end
@@ -3132,36 +3138,36 @@ always @(*) begin
     soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel5_read <= 1'd0;
+    soc_ddrphy_bankmodel5_read_col <= 10'd0;
     case (soc_ddrphy_reads5)
         1'd1: begin
-            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5);
+            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5);
+            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5);
+            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5);
+            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel5_read_col <= 10'd0;
+    soc_ddrphy_bankmodel5_read <= 1'd0;
     case (soc_ddrphy_reads5)
         1'd1: begin
-            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5);
         end
     endcase
 end
@@ -3238,36 +3244,36 @@ always @(*) begin
     soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write;
 end
 always @(*) begin
-    soc_ddrphy_bank_write_col6 <= 10'd0;
+    soc_ddrphy_bank_write6 <= 1'd0;
     case (soc_ddrphy_writes6)
         1'd1: begin
-            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6);
         end
         2'd2: begin
-            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6);
         end
         3'd4: begin
-            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6);
         end
         4'd8: begin
-            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6);
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bank_write6 <= 1'd0;
+    soc_ddrphy_bank_write_col6 <= 10'd0;
     case (soc_ddrphy_writes6)
         1'd1: begin
-            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6);
+            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6);
+            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6);
+            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6);
+            soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
@@ -3283,36 +3289,36 @@ always @(*) begin
     soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel6_read_col <= 10'd0;
+    soc_ddrphy_bankmodel6_read <= 1'd0;
     case (soc_ddrphy_reads6)
         1'd1: begin
-            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6);
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel6_read <= 1'd0;
+    soc_ddrphy_bankmodel6_read_col <= 10'd0;
     case (soc_ddrphy_reads6)
         1'd1: begin
-            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6);
+            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6);
+            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6);
+            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6);
+            soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
@@ -3324,36 +3330,36 @@ always @(*) begin
     soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-    soc_ddrphy_bankmodel7_activate <= 1'd0;
+    soc_ddrphy_bankmodel7_activate_row <= 14'd0;
     case (soc_ddrphy_activates7)
         1'd1: begin
-            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7);
+            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address;
         end
         2'd2: begin
-            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7);
+            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address;
         end
         3'd4: begin
-            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7);
+            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address;
         end
         4'd8: begin
-            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7);
+            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address;
         end
     endcase
 end
 always @(*) begin
-    soc_ddrphy_bankmodel7_activate_row <= 14'd0;
+    soc_ddrphy_bankmodel7_activate <= 1'd0;
     case (soc_ddrphy_activates7)
         1'd1: begin
-            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address;
+            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7);
         end
         2'd2: begin
-            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address;
+            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7);
         end
         3'd4: begin
-            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address;
+            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7);
         end
         4'd8: begin
-            soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address;
+            soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7);
         end
     endcase
 end
@@ -3478,15 +3484,15 @@ assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rd
 assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
 assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
 always @(*) begin
-    soc_ddrphy_dfiphasemodel0_precharge <= 1'd0;
+    soc_ddrphy_dfiphasemodel0_activate <= 1'd0;
     if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
-        soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n);
+        soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n;
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel0_activate <= 1'd0;
+    soc_ddrphy_dfiphasemodel0_precharge <= 1'd0;
     if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
-        soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n;
+        soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n);
     end
 end
 always @(*) begin
@@ -3514,15 +3520,15 @@ always @(*) begin
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel1_write <= 1'd0;
+    soc_ddrphy_dfiphasemodel1_read <= 1'd0;
     if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
-        soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n);
+        soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n;
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel1_read <= 1'd0;
+    soc_ddrphy_dfiphasemodel1_write <= 1'd0;
     if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
-        soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n;
+        soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n);
     end
 end
 always @(*) begin
@@ -3538,27 +3544,27 @@ always @(*) begin
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel2_read <= 1'd0;
+    soc_ddrphy_dfiphasemodel2_write <= 1'd0;
     if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
-        soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n;
+        soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n);
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel2_write <= 1'd0;
+    soc_ddrphy_dfiphasemodel2_read <= 1'd0;
     if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
-        soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n);
+        soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n;
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel3_activate <= 1'd0;
+    soc_ddrphy_dfiphasemodel3_precharge <= 1'd0;
     if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
-        soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n;
+        soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n);
     end
 end
 always @(*) begin
-    soc_ddrphy_dfiphasemodel3_precharge <= 1'd0;
+    soc_ddrphy_dfiphasemodel3_activate <= 1'd0;
     if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
-        soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n);
+        soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n;
     end
 end
 always @(*) begin
@@ -3615,14 +3621,6 @@ always @(*) begin
 end
 assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
 assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
-always @(*) begin
-    soc_ddrphy_bankmodel1_read_data <= 128'd0;
-    if (soc_ddrphy_bankmodel1_active) begin
-        if (soc_ddrphy_bankmodel1_read) begin
-            soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r;
-        end
-    end
-end
 always @(*) begin
     soc_ddrphy_bankmodel1_write_port_adr <= 21'd0;
     if (soc_ddrphy_bankmodel1_active) begin
@@ -3653,6 +3651,14 @@ always @(*) begin
         end
     end
 end
+always @(*) begin
+    soc_ddrphy_bankmodel1_read_data <= 128'd0;
+    if (soc_ddrphy_bankmodel1_active) begin
+        if (soc_ddrphy_bankmodel1_read) begin
+            soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r;
+        end
+    end
+end
 assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
 assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
 always @(*) begin
@@ -3695,12 +3701,6 @@ always @(*) begin
 end
 assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
 assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
-always @(*) begin
-    soc_ddrphy_bankmodel3_write_port_adr <= 21'd0;
-    if (soc_ddrphy_bankmodel3_active) begin
-        soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr;
-    end
-end
 always @(*) begin
     soc_ddrphy_bankmodel3_write_port_we <= 16'd0;
     if (soc_ddrphy_bankmodel3_active) begin
@@ -3733,24 +3733,14 @@ always @(*) begin
         end
     end
 end
-assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
-assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
-always @(*) begin
-    soc_ddrphy_bankmodel4_write_port_we <= 16'd0;
-    if (soc_ddrphy_bankmodel4_active) begin
-        if (4'd8) begin
-            soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
-        end else begin
-            soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write;
-        end
-    end
-end
 always @(*) begin
-    soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0;
-    if (soc_ddrphy_bankmodel4_active) begin
-        soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data;
+    soc_ddrphy_bankmodel3_write_port_adr <= 21'd0;
+    if (soc_ddrphy_bankmodel3_active) begin
+        soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr;
     end
 end
+assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
+assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
 always @(*) begin
     soc_ddrphy_bankmodel4_read_port_adr <= 21'd0;
     if (soc_ddrphy_bankmodel4_active) begin
@@ -3773,16 +3763,24 @@ always @(*) begin
         soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr;
     end
 end
-assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
-assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
 always @(*) begin
-    soc_ddrphy_bankmodel5_read_port_adr <= 21'd0;
-    if (soc_ddrphy_bankmodel5_active) begin
-        if (soc_ddrphy_bankmodel5_read) begin
-            soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr;
+    soc_ddrphy_bankmodel4_write_port_we <= 16'd0;
+    if (soc_ddrphy_bankmodel4_active) begin
+        if (4'd8) begin
+            soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
+        end else begin
+            soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write;
         end
     end
 end
+always @(*) begin
+    soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0;
+    if (soc_ddrphy_bankmodel4_active) begin
+        soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data;
+    end
+end
+assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
+assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
 always @(*) begin
     soc_ddrphy_bankmodel5_read_data <= 128'd0;
     if (soc_ddrphy_bankmodel5_active) begin
@@ -3813,6 +3811,14 @@ always @(*) begin
         soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data;
     end
 end
+always @(*) begin
+    soc_ddrphy_bankmodel5_read_port_adr <= 21'd0;
+    if (soc_ddrphy_bankmodel5_active) begin
+        if (soc_ddrphy_bankmodel5_read) begin
+            soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr;
+        end
+    end
+end
 assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
 assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
 always @(*) begin
@@ -4921,42 +4927,26 @@ always @(*) begin
     end else begin
     end
 end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p0_cke <= 1'd0;
-    soc_litedramcore_csr_dfi_p0_cke <= soc_litedramcore_cke;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p1_cke <= 1'd0;
-    soc_litedramcore_csr_dfi_p1_cke <= soc_litedramcore_cke;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p2_cke <= 1'd0;
-    soc_litedramcore_csr_dfi_p2_cke <= soc_litedramcore_cke;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p3_cke <= 1'd0;
-    soc_litedramcore_csr_dfi_p3_cke <= soc_litedramcore_cke;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p0_odt <= 1'd0;
-    soc_litedramcore_csr_dfi_p0_odt <= soc_litedramcore_odt;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p1_odt <= 1'd0;
-    soc_litedramcore_csr_dfi_p1_odt <= soc_litedramcore_odt;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p2_odt <= 1'd0;
-    soc_litedramcore_csr_dfi_p2_odt <= soc_litedramcore_odt;
-end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p3_odt <= 1'd0;
-    soc_litedramcore_csr_dfi_p3_odt <= soc_litedramcore_odt;
-end
+assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke;
+assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt;
+assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt;
 assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n;
 assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n;
+always @(*) begin
+    soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+        soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas);
+    end else begin
+        soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4989,20 +4979,20 @@ always @(*) begin
         soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas);
-    end else begin
-        soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
-    end
-end
 assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage;
 assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
 assign soc_litedramcore_csr_dfi_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_wren);
 assign soc_litedramcore_csr_dfi_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_rden);
 assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
 assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+        soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas);
+    end else begin
+        soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector1_command_issue_re) begin
@@ -5035,20 +5025,20 @@ always @(*) begin
         soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas);
-    end else begin
-        soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
-    end
-end
 assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage;
 assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
 assign soc_litedramcore_csr_dfi_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_wren);
 assign soc_litedramcore_csr_dfi_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_rden);
 assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
 assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
+always @(*) begin
+    soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+        soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas);
+    end else begin
+        soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector2_command_issue_re) begin
@@ -5081,20 +5071,20 @@ always @(*) begin
         soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas);
-    end else begin
-        soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
-    end
-end
 assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage;
 assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
 assign soc_litedramcore_csr_dfi_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_wren);
 assign soc_litedramcore_csr_dfi_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_rden);
 assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
 assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+always @(*) begin
+    soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+        soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas);
+    end else begin
+        soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+    end
+end
 always @(*) begin
     soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
     if (soc_litedramcore_phaseinjector3_command_issue_re) begin
@@ -5127,14 +5117,6 @@ always @(*) begin
         soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     end
 end
-always @(*) begin
-    soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-        soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas);
-    end else begin
-        soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
-    end
-end
 assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage;
 assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
 assign soc_litedramcore_csr_dfi_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_csrfield_wren);
@@ -5463,32 +5445,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine0_row_close <= 1'd0;
-    case (bankmachine0_state)
-        1'd1: begin
-            soc_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        2'd2: begin
-            soc_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            soc_litedramcore_bankmachine0_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
     case (bankmachine0_state)
@@ -5855,21 +5811,59 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    case (bankmachine0_state)
+        1'd1: begin
+            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+                soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (soc_litedramcore_bankmachine0_trccon_ready) begin
+                soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine0_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine0_row_opened) begin
+                        if (soc_litedramcore_bankmachine0_row_hit) begin
+                            soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine0_row_close <= 1'd0;
     case (bankmachine0_state)
         1'd1: begin
-            if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-                soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
+            soc_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd2: begin
+            soc_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         2'd3: begin
-            if (soc_litedramcore_bankmachine0_trccon_ready) begin
-                soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-            end
         end
         3'd4: begin
+            soc_litedramcore_bankmachine0_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -5880,18 +5874,6 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (soc_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine0_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine0_row_opened) begin
-                        if (soc_litedramcore_bankmachine0_row_hit) begin
-                            soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
@@ -6034,41 +6016,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
-    case (bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine1_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine1_row_opened) begin
-                        if (soc_litedramcore_bankmachine1_row_hit) begin
-                            soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
     case (bankmachine1_state)
@@ -6466,6 +6413,41 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+    case (bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine1_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine1_row_opened) begin
+                        if (soc_litedramcore_bankmachine1_row_hit) begin
+                            soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid;
 assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready;
 assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
@@ -6605,74 +6587,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-    case (bankmachine2_state)
-        1'd1: begin
-            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-            end
-        end
-        3'd4: begin
-            soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-    case (bankmachine2_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine2_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine2_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine2_row_opened) begin
-                        if (soc_litedramcore_bankmachine2_row_hit) begin
-                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
-                            end else begin
-                                soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
     case (bankmachine2_state)
@@ -7037,6 +6951,74 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+    case (bankmachine2_state)
+        1'd1: begin
+            if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (soc_litedramcore_bankmachine2_trccon_ready) begin
+                soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+    case (bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine2_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine2_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine2_row_opened) begin
+                        if (soc_litedramcore_bankmachine2_row_hit) begin
+                            if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid;
 assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready;
 assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
@@ -7177,7 +7159,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
     case (bankmachine3_state)
         1'd1: begin
         end
@@ -7186,6 +7168,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
+                soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -7196,37 +7181,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (soc_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine3_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine3_row_opened) begin
-                        if (soc_litedramcore_bankmachine3_row_hit) begin
-                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
-                            end else begin
-                                soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+    soc_litedramcore_bankmachine3_row_open <= 1'd0;
     case (bankmachine3_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (soc_litedramcore_bankmachine3_trccon_ready) begin
+                soc_litedramcore_bankmachine3_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
-                soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -7307,32 +7277,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine3_row_open <= 1'd0;
-    case (bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                soc_litedramcore_bankmachine3_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
     case (bankmachine3_state)
@@ -7608,6 +7552,44 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+    case (bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine3_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine3_row_opened) begin
+                        if (soc_litedramcore_bankmachine3_row_hit) begin
+                            if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign soc_litedramcore_bankmachine4_sink_valid = soc_litedramcore_bankmachine4_req_valid;
 assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_sink_ready;
 assign soc_litedramcore_bankmachine4_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
@@ -7747,32 +7729,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine4_row_close <= 1'd0;
-    case (bankmachine4_state)
-        1'd1: begin
-            soc_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        2'd2: begin
-            soc_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            soc_litedramcore_bankmachine4_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
     case (bankmachine4_state)
@@ -8179,6 +8135,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine4_row_close <= 1'd0;
+    case (bankmachine4_state)
+        1'd1: begin
+            soc_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        2'd2: begin
+            soc_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine4_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid;
 assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready;
 assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
@@ -8318,41 +8300,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
-    case (bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine5_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine5_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine5_row_opened) begin
-                        if (soc_litedramcore_bankmachine5_row_hit) begin
-                            soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
     case (bankmachine5_state)
@@ -8750,6 +8697,41 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+    case (bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine5_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine5_row_opened) begin
+                        if (soc_litedramcore_bankmachine5_row_hit) begin
+                            soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid;
 assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready;
 assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
@@ -8822,135 +8804,67 @@ assign soc_litedramcore_bankmachine6_pipe_valid_sink_first = soc_litedramcore_ba
 assign soc_litedramcore_bankmachine6_pipe_valid_sink_last = soc_litedramcore_bankmachine6_sink_sink_last;
 assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine6_sink_sink_payload_we;
 assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine6_sink_sink_payload_addr;
-assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid;
-assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready;
-assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first;
-assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last;
-assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we;
-assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
-always @(*) begin
-    bankmachine6_next_state <= 4'd0;
-    bankmachine6_next_state <= bankmachine6_state;
-    case (bankmachine6_state)
-        1'd1: begin
-            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                if (soc_litedramcore_bankmachine6_cmd_ready) begin
-                    bankmachine6_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                bankmachine6_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                if (soc_litedramcore_bankmachine6_cmd_ready) begin
-                    bankmachine6_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
-                bankmachine6_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            bankmachine6_next_state <= 3'd6;
-        end
-        3'd6: begin
-            bankmachine6_next_state <= 2'd3;
-        end
-        3'd7: begin
-            bankmachine6_next_state <= 4'd8;
-        end
-        4'd8: begin
-            bankmachine6_next_state <= 1'd0;
-        end
-        default: begin
-            if (soc_litedramcore_bankmachine6_refresh_req) begin
-                bankmachine6_next_state <= 3'd4;
-            end else begin
-                if (soc_litedramcore_bankmachine6_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine6_row_opened) begin
-                        if (soc_litedramcore_bankmachine6_row_hit) begin
-                            if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
-                                bankmachine6_next_state <= 2'd2;
-                            end
-                        end else begin
-                            bankmachine6_next_state <= 1'd1;
-                        end
-                    end else begin
-                        bankmachine6_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
+assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready;
+assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
 always @(*) begin
-    soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    bankmachine6_next_state <= 4'd0;
+    bankmachine6_next_state <= bankmachine6_state;
     case (bankmachine6_state)
         1'd1: begin
             if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                if (soc_litedramcore_bankmachine6_cmd_ready) begin
+                    bankmachine6_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+                bankmachine6_next_state <= 3'd5;
+            end
         end
         2'd3: begin
             if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                if (soc_litedramcore_bankmachine6_cmd_ready) begin
+                    bankmachine6_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
-            soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
-    case (bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
+            if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
+                bankmachine6_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            bankmachine6_next_state <= 3'd6;
         end
         3'd6: begin
+            bankmachine6_next_state <= 2'd3;
         end
         3'd7: begin
+            bankmachine6_next_state <= 4'd8;
         end
         4'd8: begin
+            bankmachine6_next_state <= 1'd0;
         end
         default: begin
             if (soc_litedramcore_bankmachine6_refresh_req) begin
+                bankmachine6_next_state <= 3'd4;
             end else begin
                 if (soc_litedramcore_bankmachine6_source_source_valid) begin
                     if (soc_litedramcore_bankmachine6_row_opened) begin
                         if (soc_litedramcore_bankmachine6_row_hit) begin
-                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
-                            end else begin
-                                soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                            if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
+                                bankmachine6_next_state <= 2'd2;
                             end
                         end else begin
+                            bankmachine6_next_state <= 1'd1;
                         end
                     end else begin
+                        bankmachine6_next_state <= 2'd3;
                     end
                 end
             end
@@ -9321,6 +9235,74 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+    case (bankmachine6_state)
+        1'd1: begin
+            if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (soc_litedramcore_bankmachine6_trccon_ready) begin
+                soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+            end
+        end
+        3'd4: begin
+            soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+    case (bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine6_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine6_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine6_row_opened) begin
+                        if (soc_litedramcore_bankmachine6_row_hit) begin
+                            if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign soc_litedramcore_bankmachine7_sink_valid = soc_litedramcore_bankmachine7_req_valid;
 assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_sink_ready;
 assign soc_litedramcore_bankmachine7_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
@@ -9461,7 +9443,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
     case (bankmachine7_state)
         1'd1: begin
         end
@@ -9470,6 +9452,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
+                soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9480,37 +9465,22 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (soc_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (soc_litedramcore_bankmachine7_source_source_valid) begin
-                    if (soc_litedramcore_bankmachine7_row_opened) begin
-                        if (soc_litedramcore_bankmachine7_row_hit) begin
-                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    soc_litedramcore_bankmachine7_row_open <= 1'd0;
     case (bankmachine7_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (soc_litedramcore_bankmachine7_trccon_ready) begin
+                soc_litedramcore_bankmachine7_row_open <= 1'd1;
+            end
         end
         3'd4: begin
-            if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
-                soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
         end
         3'd5: begin
         end
@@ -9591,32 +9561,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    soc_litedramcore_bankmachine7_row_open <= 1'd0;
-    case (bankmachine7_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                soc_litedramcore_bankmachine7_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
     case (bankmachine7_state)
@@ -9892,6 +9836,44 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    case (bankmachine7_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (soc_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (soc_litedramcore_bankmachine7_source_source_valid) begin
+                    if (soc_litedramcore_bankmachine7_row_opened) begin
+                        if (soc_litedramcore_bankmachine7_row_hit) begin
+                            if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+                            end else begin
+                                soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
 assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
 assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
@@ -10141,43 +10123,10 @@ always @(*) begin
     case (multiplexer_state)
         1'd1: begin
             if (1'd0) begin
-                soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
-            end else begin
-                soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        4'd9: begin
-        end
-        4'd10: begin
-        end
-        default: begin
-            if (1'd0) begin
-                soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
-            end else begin
-                soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
-            end
-        end
-    endcase
-end
-always @(*) begin
-    soc_litedramcore_en1 <= 1'd0;
-    case (multiplexer_state)
-        1'd1: begin
-            soc_litedramcore_en1 <= 1'd1;
+                soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+            end else begin
+                soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -10198,20 +10147,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+                soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+            end else begin
+                soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_steerer3 <= 2'd0;
+    soc_litedramcore_en1 <= 1'd0;
     case (multiplexer_state)
         1'd1: begin
-            soc_litedramcore_steerer3 <= 1'd0;
-            if (1'd1) begin
-                soc_litedramcore_steerer3 <= 2'd2;
-            end
-            if (1'd0) begin
-                soc_litedramcore_steerer3 <= 1'd1;
-            end
+            soc_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -10232,13 +10180,6 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            soc_litedramcore_steerer3 <= 1'd0;
-            if (1'd0) begin
-                soc_litedramcore_steerer3 <= 2'd2;
-            end
-            if (1'd0) begin
-                soc_litedramcore_steerer3 <= 1'd1;
-            end
         end
     endcase
 end
@@ -10402,9 +10343,16 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    soc_litedramcore_en0 <= 1'd0;
+    soc_litedramcore_steerer3 <= 2'd0;
     case (multiplexer_state)
         1'd1: begin
+            soc_litedramcore_steerer3 <= 1'd0;
+            if (1'd1) begin
+                soc_litedramcore_steerer3 <= 2'd2;
+            end
+            if (1'd0) begin
+                soc_litedramcore_steerer3 <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -10425,17 +10373,22 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            soc_litedramcore_en0 <= 1'd1;
+            soc_litedramcore_steerer3 <= 1'd0;
+            if (1'd0) begin
+                soc_litedramcore_steerer3 <= 2'd2;
+            end
+            if (1'd0) begin
+                soc_litedramcore_steerer3 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_cmd_ready <= 1'd0;
+    soc_litedramcore_en0 <= 1'd0;
     case (multiplexer_state)
         1'd1: begin
         end
         2'd2: begin
-            soc_litedramcore_cmd_ready <= 1'd1;
         end
         2'd3: begin
         end
@@ -10454,6 +10407,7 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            soc_litedramcore_en0 <= 1'd1;
         end
     endcase
 end
@@ -10520,6 +10474,34 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    soc_litedramcore_cmd_ready <= 1'd0;
+    case (multiplexer_state)
+        1'd1: begin
+        end
+        2'd2: begin
+            soc_litedramcore_cmd_ready <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        4'd9: begin
+        end
+        4'd10: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     soc_litedramcore_choose_req_want_writes <= 1'd0;
     case (multiplexer_state)
@@ -10592,24 +10574,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) &
 assign soc_user_port_wdata_ready = new_master_wdata_ready1;
 assign soc_user_port_rdata_valid = new_master_rdata_valid8;
 always @(*) begin
-    soc_litedramcore_interface_wdata_we <= 16'd0;
+    soc_litedramcore_interface_wdata <= 128'd0;
     case ({new_master_wdata_ready1})
         1'd1: begin
-            soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
+            soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
         end
         default: begin
-            soc_litedramcore_interface_wdata_we <= 1'd0;
+            soc_litedramcore_interface_wdata <= 1'd0;
         end
     endcase
 end
 always @(*) begin
-    soc_litedramcore_interface_wdata <= 128'd0;
+    soc_litedramcore_interface_wdata_we <= 16'd0;
     case ({new_master_wdata_ready1})
         1'd1: begin
-            soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
+            soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
         end
         default: begin
-            soc_litedramcore_interface_wdata <= 1'd0;
+            soc_litedramcore_interface_wdata_we <= 1'd0;
         end
     endcase
 end
@@ -10639,6 +10621,36 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    interface1_we_next_value3 <= 1'd0;
+    case (state)
+        1'd1: begin
+            interface1_we_next_value3 <= 1'd0;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0));
+            end
+        end
+    endcase
+end
+always @(*) begin
+    interface1_we_next_value_ce3 <= 1'd0;
+    case (state)
+        1'd1: begin
+            interface1_we_next_value_ce3 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_we_next_value_ce3 <= 1'd1;
+            end
+        end
+    endcase
+end
 always @(*) begin
     interface1_dat_w_next_value0 <= 32'd0;
     case (state)
@@ -10652,98 +10664,98 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    interface1_dat_w_next_value_ce0 <= 1'd0;
+    interface0_ack <= 1'd0;
     case (state)
         1'd1: begin
         end
         2'd2: begin
+            interface0_ack <= 1'd1;
         end
         default: begin
-            interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    interface1_adr_next_value1 <= 14'd0;
+    interface1_dat_w_next_value_ce0 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
-            if ((interface0_cyc & interface0_stb)) begin
-                interface1_adr_next_value1 <= interface0_adr[29:0];
-            end
+            interface1_dat_w_next_value_ce0 <= 1'd1;
         end
     endcase
 end
 always @(*) begin
-    interface1_adr_next_value_ce1 <= 1'd0;
+    interface0_dat_r <= 32'd0;
     case (state)
         1'd1: begin
-            interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
+            interface0_dat_r <= interface1_dat_r;
         end
         default: begin
-            if ((interface0_cyc & interface0_stb)) begin
-                interface1_adr_next_value_ce1 <= 1'd1;
-            end
         end
     endcase
 end
 always @(*) begin
-    interface1_we_next_value2 <= 1'd0;
+    interface1_adr_next_value1 <= 14'd0;
     case (state)
         1'd1: begin
-            interface1_we_next_value2 <= 1'd0;
+            interface1_adr_next_value1 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((interface0_cyc & interface0_stb)) begin
-                interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0));
+                interface1_adr_next_value1 <= interface0_adr;
             end
         end
     endcase
 end
 always @(*) begin
-    interface1_we_next_value_ce2 <= 1'd0;
+    interface1_adr_next_value_ce1 <= 1'd0;
     case (state)
         1'd1: begin
-            interface1_we_next_value_ce2 <= 1'd1;
+            interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((interface0_cyc & interface0_stb)) begin
-                interface1_we_next_value_ce2 <= 1'd1;
+                interface1_adr_next_value_ce1 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    interface0_dat_r <= 32'd0;
+    interface1_re_next_value2 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
-            interface0_dat_r <= interface1_dat_r;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0));
+            end
         end
     endcase
 end
 always @(*) begin
-    interface0_ack <= 1'd0;
+    interface1_re_next_value_ce2 <= 1'd0;
     case (state)
         1'd1: begin
+            interface1_re_next_value_ce2 <= 1'd1;
         end
         2'd2: begin
-            interface0_ack <= 1'd1;
         end
         default: begin
+            if ((interface0_cyc & interface0_stb)) begin
+                interface1_re_next_value_ce2 <= 1'd1;
+            end
         end
     endcase
 end
@@ -10758,20 +10770,20 @@ end
 always @(*) begin
     csrbank0_init_done0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_done0_we <= interface0_bank_bus_re;
     end
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-    csrbank0_init_error0_re <= 1'd0;
+    csrbank0_init_error0_we <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_re <= interface0_bank_bus_we;
+        csrbank0_init_error0_we <= interface0_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank0_init_error0_we <= 1'd0;
+    csrbank0_init_error0_re <= 1'd0;
     if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+        csrbank0_init_error0_re <= interface0_bank_bus_we;
     end
 end
 assign csrbank0_init_done0_w = soc_init_done_storage;
@@ -10779,61 +10791,61 @@ assign csrbank0_init_error0_w = soc_init_error_storage;
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
 always @(*) begin
-    csrbank1_dfii_control0_re <= 1'd0;
+    csrbank1_dfii_control0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dfii_control0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_control0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_control0_we <= 1'd0;
+    csrbank1_dfii_control0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        csrbank1_dfii_control0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_control0_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank1_dfii_pi0_command0_we <= 1'd0;
+    csrbank1_dfii_pi0_command0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_command0_re <= 1'd0;
+    csrbank1_dfii_pi0_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_command0_we <= interface1_bank_bus_re;
     end
 end
 assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
+        soc_litedramcore_phaseinjector0_command_issue_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we);
+        soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank1_dfii_pi0_address0_re <= 1'd0;
+    csrbank1_dfii_pi0_address0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_address0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_address0_we <= 1'd0;
+    csrbank1_dfii_pi0_address0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
     csrbank1_dfii_pi0_baddress0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_baddress0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10842,37 +10854,37 @@ always @(*) begin
         csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we;
     end
 end
-assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w;
 always @(*) begin
-    csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
+    csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
+    csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_wrdata0_we <= interface1_bank_bus_re;
     end
 end
-assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w;
 always @(*) begin
-    csrbank1_dfii_pi0_rddata_re <= 1'd0;
+    csrbank1_dfii_pi0_rddata_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi0_rddata_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi0_rddata_we <= 1'd0;
+    csrbank1_dfii_pi0_rddata_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
     csrbank1_dfii_pi1_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_command0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10883,57 +10895,57 @@ always @(*) begin
 end
 assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
+        soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
+        soc_litedramcore_phaseinjector1_command_issue_we <= interface1_bank_bus_re;
     end
 end
 assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank1_dfii_pi1_address0_we <= 1'd0;
+    csrbank1_dfii_pi1_address0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi1_address0_re <= 1'd0;
+    csrbank1_dfii_pi1_address0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi1_address0_we <= interface1_bank_bus_re;
     end
 end
 assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank1_dfii_pi1_baddress0_re <= 1'd0;
+    csrbank1_dfii_pi1_baddress0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi1_baddress0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi1_baddress0_we <= 1'd0;
+    csrbank1_dfii_pi1_baddress0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
     end
 end
-assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w;
 always @(*) begin
-    csrbank1_dfii_pi1_wrdata0_we <= 1'd0;
+    csrbank1_dfii_pi1_wrdata0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi1_wrdata0_re <= 1'd0;
+    csrbank1_dfii_pi1_wrdata0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi1_wrdata0_we <= interface1_bank_bus_re;
     end
 end
-assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w;
 always @(*) begin
     csrbank1_dfii_pi1_rddata_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
@@ -10943,46 +10955,46 @@ end
 always @(*) begin
     csrbank1_dfii_pi1_rddata_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi1_rddata_we <= interface1_bank_bus_re;
     end
 end
 assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-    csrbank1_dfii_pi2_command0_re <= 1'd0;
+    csrbank1_dfii_pi2_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_command0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_command0_we <= 1'd0;
+    csrbank1_dfii_pi2_command0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
-        csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
     end
 end
 assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-    soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-        soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we;
+        soc_litedramcore_phaseinjector2_command_issue_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-        soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we);
+        soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank1_dfii_pi2_address0_we <= 1'd0;
+    csrbank1_dfii_pi2_address0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_address0_re <= 1'd0;
+    csrbank1_dfii_pi2_address0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
-        csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_address0_we <= interface1_bank_bus_re;
     end
 end
 assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
@@ -10995,33 +11007,33 @@ end
 always @(*) begin
     csrbank1_dfii_pi2_baddress0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
-        csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_baddress0_we <= interface1_bank_bus_re;
     end
 end
-assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w;
 always @(*) begin
-    csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
+    csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_wrdata0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
+    csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
-        csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
     end
 end
-assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w;
 always @(*) begin
-    csrbank1_dfii_pi2_rddata_we <= 1'd0;
+    csrbank1_dfii_pi2_rddata_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi2_rddata_re <= 1'd0;
+    csrbank1_dfii_pi2_rddata_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
-        csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi2_rddata_we <= interface1_bank_bus_re;
     end
 end
 assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[7:0];
@@ -11034,14 +11046,14 @@ end
 always @(*) begin
     csrbank1_dfii_pi3_command0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-        csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_command0_we <= interface1_bank_bus_re;
     end
 end
 assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
     soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
-        soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we);
+        soc_litedramcore_phaseinjector3_command_issue_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11052,48 +11064,48 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
 always @(*) begin
-    csrbank1_dfii_pi3_address0_re <= 1'd0;
+    csrbank1_dfii_pi3_address0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi3_address0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi3_address0_we <= 1'd0;
+    csrbank1_dfii_pi3_address0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
-        csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
     end
 end
 assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
 always @(*) begin
-    csrbank1_dfii_pi3_baddress0_we <= 1'd0;
+    csrbank1_dfii_pi3_baddress0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi3_baddress0_re <= 1'd0;
+    csrbank1_dfii_pi3_baddress0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
-        csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi3_baddress0_we <= interface1_bank_bus_re;
     end
 end
-assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w;
 always @(*) begin
-    csrbank1_dfii_pi3_wrdata0_re <= 1'd0;
+    csrbank1_dfii_pi3_wrdata0_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we;
+        csrbank1_dfii_pi3_wrdata0_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    csrbank1_dfii_pi3_wrdata0_we <= 1'd0;
+    csrbank1_dfii_pi3_wrdata0_re <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-        csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we;
     end
 end
-assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w;
 always @(*) begin
     csrbank1_dfii_pi3_rddata_we <= 1'd0;
     if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
-        csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we);
+        csrbank1_dfii_pi3_rddata_we <= interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11106,7 +11118,7 @@ assign soc_litedramcore_sel = soc_litedramcore_storage[0];
 assign soc_litedramcore_cke = soc_litedramcore_storage[1];
 assign soc_litedramcore_odt = soc_litedramcore_storage[2];
 assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
-assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0];
+assign csrbank1_dfii_control0_w = soc_litedramcore_storage;
 assign soc_litedramcore_phaseinjector0_csrfield_cs = soc_litedramcore_phaseinjector0_command_storage[0];
 assign soc_litedramcore_phaseinjector0_csrfield_we = soc_litedramcore_phaseinjector0_command_storage[1];
 assign soc_litedramcore_phaseinjector0_csrfield_cas = soc_litedramcore_phaseinjector0_command_storage[2];
@@ -11115,11 +11127,11 @@ assign soc_litedramcore_phaseinjector0_csrfield_wren = soc_litedramcore_phaseinj
 assign soc_litedramcore_phaseinjector0_csrfield_rden = soc_litedramcore_phaseinjector0_command_storage[5];
 assign soc_litedramcore_phaseinjector0_csrfield_cs_top = soc_litedramcore_phaseinjector0_command_storage[6];
 assign soc_litedramcore_phaseinjector0_csrfield_cs_bottom = soc_litedramcore_phaseinjector0_command_storage[7];
-assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[7:0];
-assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0];
-assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status[31:0];
+assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage;
+assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage;
+assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage;
+assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage;
+assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status;
 assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata_we;
 assign soc_litedramcore_phaseinjector1_csrfield_cs = soc_litedramcore_phaseinjector1_command_storage[0];
 assign soc_litedramcore_phaseinjector1_csrfield_we = soc_litedramcore_phaseinjector1_command_storage[1];
@@ -11129,11 +11141,11 @@ assign soc_litedramcore_phaseinjector1_csrfield_wren = soc_litedramcore_phaseinj
 assign soc_litedramcore_phaseinjector1_csrfield_rden = soc_litedramcore_phaseinjector1_command_storage[5];
 assign soc_litedramcore_phaseinjector1_csrfield_cs_top = soc_litedramcore_phaseinjector1_command_storage[6];
 assign soc_litedramcore_phaseinjector1_csrfield_cs_bottom = soc_litedramcore_phaseinjector1_command_storage[7];
-assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[7:0];
-assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0];
-assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status[31:0];
+assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage;
+assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage;
+assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage;
+assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage;
+assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status;
 assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata_we;
 assign soc_litedramcore_phaseinjector2_csrfield_cs = soc_litedramcore_phaseinjector2_command_storage[0];
 assign soc_litedramcore_phaseinjector2_csrfield_we = soc_litedramcore_phaseinjector2_command_storage[1];
@@ -11143,11 +11155,11 @@ assign soc_litedramcore_phaseinjector2_csrfield_wren = soc_litedramcore_phaseinj
 assign soc_litedramcore_phaseinjector2_csrfield_rden = soc_litedramcore_phaseinjector2_command_storage[5];
 assign soc_litedramcore_phaseinjector2_csrfield_cs_top = soc_litedramcore_phaseinjector2_command_storage[6];
 assign soc_litedramcore_phaseinjector2_csrfield_cs_bottom = soc_litedramcore_phaseinjector2_command_storage[7];
-assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[7:0];
-assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0];
-assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status[31:0];
+assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage;
+assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage;
+assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage;
+assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage;
+assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status;
 assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata_we;
 assign soc_litedramcore_phaseinjector3_csrfield_cs = soc_litedramcore_phaseinjector3_command_storage[0];
 assign soc_litedramcore_phaseinjector3_csrfield_we = soc_litedramcore_phaseinjector3_command_storage[1];
@@ -11157,18 +11169,21 @@ assign soc_litedramcore_phaseinjector3_csrfield_wren = soc_litedramcore_phaseinj
 assign soc_litedramcore_phaseinjector3_csrfield_rden = soc_litedramcore_phaseinjector3_command_storage[5];
 assign soc_litedramcore_phaseinjector3_csrfield_cs_top = soc_litedramcore_phaseinjector3_command_storage[6];
 assign soc_litedramcore_phaseinjector3_csrfield_cs_bottom = soc_litedramcore_phaseinjector3_command_storage[7];
-assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[7:0];
-assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0];
-assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status[31:0];
+assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage;
+assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage;
+assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage;
+assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage;
+assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status;
 assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we;
 assign adr = interface1_adr;
+assign re = interface1_re;
 assign we = interface1_we;
 assign dat_w = interface1_dat_w;
 assign interface1_dat_r = dat_r;
 assign interface0_bank_bus_adr = adr;
 assign interface1_bank_bus_adr = adr;
+assign interface0_bank_bus_re = re;
+assign interface1_bank_bus_re = re;
 assign interface0_bank_bus_we = we;
 assign interface1_bank_bus_we = we;
 assign interface0_bank_bus_dat_w = dat_w;
@@ -11908,16 +11923,16 @@ always @(*) begin
     self0 <= 3'd0;
     case (soc_litedramcore_steerer0)
         1'd0: begin
-            self0 <= soc_litedramcore_nop_ba[2:0];
+            self0 <= soc_litedramcore_nop_ba;
         end
         1'd1: begin
-            self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self0 <= soc_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self0 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self0 <= soc_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12027,16 +12042,16 @@ always @(*) begin
     self7 <= 3'd0;
     case (soc_litedramcore_steerer1)
         1'd0: begin
-            self7 <= soc_litedramcore_nop_ba[2:0];
+            self7 <= soc_litedramcore_nop_ba;
         end
         1'd1: begin
-            self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self7 <= soc_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self7 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self7 <= soc_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12146,16 +12161,16 @@ always @(*) begin
     self14 <= 3'd0;
     case (soc_litedramcore_steerer2)
         1'd0: begin
-            self14 <= soc_litedramcore_nop_ba[2:0];
+            self14 <= soc_litedramcore_nop_ba;
         end
         1'd1: begin
-            self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self14 <= soc_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self14 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self14 <= soc_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12265,16 +12280,16 @@ always @(*) begin
     self21 <= 3'd0;
     case (soc_litedramcore_steerer3)
         1'd0: begin
-            self21 <= soc_litedramcore_nop_ba[2:0];
+            self21 <= soc_litedramcore_nop_ba;
         end
         1'd1: begin
-            self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            self21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+            self21 <= soc_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            self21 <= soc_litedramcore_cmd_payload_ba[2:0];
+            self21 <= soc_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -13798,8 +13813,11 @@ always @(posedge sys_clk) begin
     if (interface1_adr_next_value_ce1) begin
         interface1_adr <= interface1_adr_next_value1;
     end
-    if (interface1_we_next_value_ce2) begin
-        interface1_we <= interface1_we_next_value2;
+    if (interface1_re_next_value_ce2) begin
+        interface1_re <= interface1_re_next_value2;
+    end
+    if (interface1_we_next_value_ce3) begin
+        interface1_we <= interface1_we_next_value3;
     end
     interface0_bank_bus_dat_r <= 1'd0;
     if (csrbank0_sel) begin
@@ -13901,74 +13919,74 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (csrbank1_dfii_control0_re) begin
-        soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r;
+        soc_litedramcore_storage <= csrbank1_dfii_control0_r;
     end
     soc_litedramcore_re <= csrbank1_dfii_control0_re;
     if (csrbank1_dfii_pi0_command0_re) begin
-        soc_litedramcore_phaseinjector0_command_storage[7:0] <= csrbank1_dfii_pi0_command0_r;
+        soc_litedramcore_phaseinjector0_command_storage <= csrbank1_dfii_pi0_command0_r;
     end
     soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
     if (csrbank1_dfii_pi0_address0_re) begin
-        soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
+        soc_litedramcore_phaseinjector0_address_storage <= csrbank1_dfii_pi0_address0_r;
     end
     soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
     if (csrbank1_dfii_pi0_baddress0_re) begin
-        soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
+        soc_litedramcore_phaseinjector0_baddress_storage <= csrbank1_dfii_pi0_baddress0_r;
     end
     soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
     if (csrbank1_dfii_pi0_wrdata0_re) begin
-        soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
+        soc_litedramcore_phaseinjector0_wrdata_storage <= csrbank1_dfii_pi0_wrdata0_r;
     end
     soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
     soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re;
     if (csrbank1_dfii_pi1_command0_re) begin
-        soc_litedramcore_phaseinjector1_command_storage[7:0] <= csrbank1_dfii_pi1_command0_r;
+        soc_litedramcore_phaseinjector1_command_storage <= csrbank1_dfii_pi1_command0_r;
     end
     soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
     if (csrbank1_dfii_pi1_address0_re) begin
-        soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
+        soc_litedramcore_phaseinjector1_address_storage <= csrbank1_dfii_pi1_address0_r;
     end
     soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
     if (csrbank1_dfii_pi1_baddress0_re) begin
-        soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
+        soc_litedramcore_phaseinjector1_baddress_storage <= csrbank1_dfii_pi1_baddress0_r;
     end
     soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
     if (csrbank1_dfii_pi1_wrdata0_re) begin
-        soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
+        soc_litedramcore_phaseinjector1_wrdata_storage <= csrbank1_dfii_pi1_wrdata0_r;
     end
     soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
     soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re;
     if (csrbank1_dfii_pi2_command0_re) begin
-        soc_litedramcore_phaseinjector2_command_storage[7:0] <= csrbank1_dfii_pi2_command0_r;
+        soc_litedramcore_phaseinjector2_command_storage <= csrbank1_dfii_pi2_command0_r;
     end
     soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
     if (csrbank1_dfii_pi2_address0_re) begin
-        soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
+        soc_litedramcore_phaseinjector2_address_storage <= csrbank1_dfii_pi2_address0_r;
     end
     soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
     if (csrbank1_dfii_pi2_baddress0_re) begin
-        soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
+        soc_litedramcore_phaseinjector2_baddress_storage <= csrbank1_dfii_pi2_baddress0_r;
     end
     soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
     if (csrbank1_dfii_pi2_wrdata0_re) begin
-        soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
+        soc_litedramcore_phaseinjector2_wrdata_storage <= csrbank1_dfii_pi2_wrdata0_r;
     end
     soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
     soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re;
     if (csrbank1_dfii_pi3_command0_re) begin
-        soc_litedramcore_phaseinjector3_command_storage[7:0] <= csrbank1_dfii_pi3_command0_r;
+        soc_litedramcore_phaseinjector3_command_storage <= csrbank1_dfii_pi3_command0_r;
     end
     soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
     if (csrbank1_dfii_pi3_address0_re) begin
-        soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
+        soc_litedramcore_phaseinjector3_address_storage <= csrbank1_dfii_pi3_address0_r;
     end
     soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
     if (csrbank1_dfii_pi3_baddress0_re) begin
-        soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
+        soc_litedramcore_phaseinjector3_baddress_storage <= csrbank1_dfii_pi3_baddress0_r;
     end
     soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
     if (csrbank1_dfii_pi3_wrdata0_re) begin
-        soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
+        soc_litedramcore_phaseinjector3_wrdata_storage <= csrbank1_dfii_pi3_wrdata0_r;
     end
     soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
     soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re;
@@ -14225,6 +14243,7 @@ always @(posedge sys_clk) begin
         soc_init_done_re <= 1'd0;
         soc_init_error_storage <= 1'd0;
         soc_init_error_re <= 1'd0;
+        interface1_re <= 1'd0;
         interface1_we <= 1'd0;
         refresher_state <= 2'd0;
         bankmachine0_state <= 4'd0;
@@ -14787,5 +14806,5 @@ assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_b
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:12.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:54.
 //------------------------------------------------------------------------------
diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init
index 0573632..843a495 100644
--- a/litedram/generated/wukong-v2/litedram_core.init
+++ b/litedram/generated/wukong-v2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d4658cff00
+618c114c658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -510,14 +510,29 @@ a64b5a7d14004a39
 0000000000000000
 0000000000000000
 0000000000000000
-3920000039406004
+3920000239406004
 7c0004ac654ac000
-600000007d2057aa
+4e8000207d2057aa
+0000000000000000
+3940600400000000
+654ac00039200000
+7d2057aa7c0004ac
 6000000060000000
 6000000060000000
-000000004e800020
+4e80002060000000
 0000000000000000
-3842adc83c4c0001
+3c4c000100000000
+7c0802a63842aea4
+f821ffc148002885
+3ba000053bc06000
+4bffff8567dec000
+7fa0f7aa7c0004ac
+7fe0f6aa7c0004ac
+73ff00014bffff95
+382100404082ffe4
+000000004800289c
+0000038001000000
+3842ae503c4c0001
 fbe1fff87c0802a6
 f821ff51f8010010
 f8a100e0f88100d8
@@ -525,11 +540,11 @@ f8a100e0f88100d8
 38610020f8c100e8
 f8e100f038c100d8
 f9210100f90100f8
-48002175f9410108
+480021b9f9410108
 7c7f1b7860000000
-48001bc538610020
+48001c1538610020
 382100b060000000
-480027e87fe3fb78
+480028447fe3fb78
 0100000000000000
 4e80002000000180
 0000000000000000
@@ -537,273 +552,284 @@ f9210100f90100f8
 4e8000204c00012c
 0000000000000000
 3c4c000100000000
-7c0802a63842ad2c
-480027217d600026
-f821fed191610008
-6000000048001bc1
-38637a983c62ffff
-3c80c0004bffff41
-7c0004ac78840020
+7c0802a63842adb4
+480027797d600026
+f821fec191610008
+6000000048001c11
+38637a683c62ffff
+388000034bffff41
+7c0004ac7884f000
 3c62ffff7c8026ea
-38637ab83be00008
+38637a883be00008
 4bffff1d67ffc000
-38637ad83c62ffff
+38637aa83c62ffff
 7c0004ac4bffff11
 73e900017fe0feea
 3c62ffff41820010
-4bfffef538637af0
+4bfffef538637ac0
 4e00000073e90002
 3c62ffff41820010
-4bfffedd38637af8
+4bfffedd38637ac8
 4d80000073e90004
 3c62ffff41820010
-4bfffec538637b00
+4bfffec538637ad0
 4d00000073e90008
 3c62ffff41820010
-4bfffead38637b08
+4bfffead38637ad8
 4182001073e90010
-38637b183c62ffff
+38637ae83c62ffff
 73ff01004bfffe99
 3c62ffff41820010
-4bfffe8538637b28
-3b7b7b303f62ffff
-4bfffe757f63db78
+4bfffe8538637af8
+3b397b003f22ffff
+4bfffe757f23cb78
 38800010418e0024
 7c0004ac6484c000
 3c62ffff7c8026ea
-38637b387884b582
+38637b087884b582
 419200444bfffe51
 6484c00038800018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2d38637b50
+4bfffe2d38637b20
 6484c00038800030
 7c8026ea7c0004ac
 7884b2823c62ffff
-4bfffe0d38637b68
+4bfffe0d38637b38
 6529c00039200020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637b807c892392
-3b4000003be00000
-418a02004bfffdd9
-679cc0003b800038
-7f80e6ea7c0004ac
-3920000239406004
-7c0004ac654ac000
-3be060007d2057aa
-67ffc0003920ff9f
-7d20ffaa7c0004ac
-7fc0feaa7c0004ac
-7fa0feaa7c0004ac
-7fe0feaa7c0004ac
-3c62ffff4bfffd41
-57a5063e57e6063e
-38637ba057c4063e
-4bfffd6557f8063e
-57b9063e7fc9eb78
-57da063e7d29fb78
+38637b507c892392
+3b8000003be00000
+418a04204bfffdd9
+675ac0003b400038
+7f40d6ea7c0004ac
+4bfffd053bc06000
+3920ff9f67dec000
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+7f80f6aa7c0004ac
+7fa0f6aa7c0004ac
+3c62ffff4bfffcfd
+5785063e57a6063e
+38637b7057e4063e
+4bfffd75579b063e
+57b7063e7fe9e378
+57f8063e7d29eb78
 2c0900005529063e
-7fdee8384182015c
-57de063e7fdef838
-418201482c1e00ff
-408203742c1a0001
-418200102c190002
-2c1d002073bd00bf
-3bffffe840820124
-281f000157ff063e
-3be0600041810114
-67ffc00039200035
-7d20ffaa7c0004ac
-3b4000023bc06004
-7c0004ac67dec000
-7c0004ac7f40f7aa
-7c0004ac7d20ffaa
-4bfffc8d7fa0feaa
-57a4063e3c62ffff
-4bfffcbd38637bc0
-4082009073a90002
-38637be03c62ffff
-7c0004ac4bfffca9
-392000067f40f7aa
-7d20ffaa7c0004ac
-7c0004ac4bfffc51
-392000017f40f7aa
+7fffe0384182038c
+57ff063e7fffe838
+418203782c1f00ff
+408200d82c180001
+418200102c1b0002
+2c1c0020739c00bf
+3bbdffe840820354
+281d000157bd063e
+3be0600041810344
+67ffc0003bc00035
+7fc0ffaa7c0004ac
+7c0004ac4bfffc49
+7c0004ac7fc0ffaa
+4bfffc597fc0feaa
+57c4063e3c62ffff
+4bfffcdd38637b90
+4082006473c90002
+38637bb03c62ffff
+4bfffc0d4bfffcc9
+7c0004ac39200006
+4bfffc217d20ffaa
+392000014bfffbf9
 7d20ffaa7c0004ac
 7c0004ac39200000
-63bd00027d20ffaa
-7fa0ffaa7c0004ac
-7d20f7aa7c0004ac
-3b0000024bfffc19
-7ff9fb783b400005
-7f00f7aa7c0004ac
-7f40cfaa7c0004ac
-7fa0feaa7c0004ac
-73bd00014bfffbf1
-3c62ffff4082ffe0
-4bfffc1d38637bf8
-654ac00039406008
-7d20562a7c0004ac
-652920005529021e
-7c0004ac61291f6b
-7f63db787d20572a
-3c62ffff4bfffbf1
-38637c087b840020
-4bfffbdd7f9ae378
-7f63db783be00001
-419200384bfffbd1
-792900203d20c800
-7d204e2a7c0004ac
-408200202c090000
-3c62ffff3c82ffff
-38637c3838847c28
-48000bf54bfffba1
-3940002860000000
-7c0004ac654ac000
-7929e0427d2056ea
-7c0004ac79292000
-418e00187d2057ea
-38637c583c62ffff
-386000004bfffb69
-73ff000148000128
+63de00027d20ffaa
+7fc0ffaa7c0004ac
+654ac00039406004
+7d2057aa7c0004ac
+4bfffc214bfffbe5
+63ff1f6b3fe02000
+2c18002048000268
+2c1b00ba408201c8
+2c17001840820284
+3c62ffff4082027c
+4bfffc4538637bc0
+73ff00014bffffd0
 3c62ffff418200a4
-4bfffb4d38637c70
-38a000403c9af000
+4bfffc2d38637c60
+38a000403c9cf000
 3861007078840020
-60000000480018b5
+60000000480019e5
 3d200002e9410070
 6129464c3c62ffff
-792983e438637c88
+792983e438637c78
 6129457f794a0600
 408200247c2a4800
 2c09000189210075
 a121008240820010
 4182007c2c090015
-38637ca83c62ffff
-892100774bfffae9
+38637c983c62ffff
+892100774bfffbc9
 8901007489410076
 3c62ffff88e10073
 88a1007188c10072
-38637d0888810070
+38637cf888810070
 89210075f9210060
-3c62ffff4bfffab9
-4bfffaad38637d38
-3880600038a00000
-6484ff0060a5a000
-480018113c604000
+3c62ffff4bfffb99
+4bfffb8d38637d28
+3880f80338a00000
+7884682860a5a000
+480019413c604000
 3c62ffff60000000
-4bfffa8538637d58
-4bffff184bfffafd
+4bfffb6538637d48
+480002184bfffbdd
 3f22ffffebe10090
-3b397cc03ba00000
-a12100a87ffafa14
+3b397cb03ba00000
+a12100a87ffcfa14
 418000347c1d4840
 3c62ffff80810088
-4bfffa4d38637ce8
-e86100884bfffac5
+4bfffb2d38637cd8
+e86100884bfffba5
 4182ff882c23ffff
-8161000838210130
-480022407d638120
+8161000838210140
+480023787d638120
 38a000383c9ff000
 386100b078840020
-6000000048001795
+60000000480018c5
 2c090001812100b0
-eb6100d040820048
-ebc100b8eb8100c0
+eb4100d040820048
+ebc100b8eb6100c0
 7f23cb787ba40020
-7b6500207f86e378
-4bfff9e53fdef000
-7b6500207c9af214
-7f83e37878840020
-600000004800174d
+7b4500207f66db78
+4bfffac53fdef000
+7b4500207c9cf214
+7f63db7878840020
+600000004800187d
 7fff4a14a12100a6
 4bffff583bbd0001
-4082fdc02c1a0020
-4082fdb82c1900ba
-4082fdb02c180018
-38637bf03c62ffff
-4bfffd704bfff999
-0300000000000000
-7c6903a600000880
-4200fffc60000000
+408200c02c18009d
+2c1b0060577b0734
+2c170019408200b4
+3c62ffff408200ac
+4bfffa7538637bc8
+392000054bfff9b9
+7d20f7aa7c0004ac
+7fe0f6aa7c0004ac
+73e900404bfff9c5
+3c62ffff40820048
+4bfffa4538637bd0
+392000064bfff989
+7d20f7aa7c0004ac
+4bfff9754bfff99d
+7c0004ac39200001
+63ff00407d20f7aa
+7fe0f7aa7c0004ac
+4bfff9b94bfff97d
+63ff3f6c3fe02000
+38637be83c62ffff
+394060084bfff9f9
+7c0004ac654ac000
+5529021e7d20562a
+7c0004ac7d29fb78
+7f23cb787d20572a
+3c62ffff4bfff9d1
+38637bf87b440020
+4bfff9bd7f5cd378
+7f23cb783be00001
+419200384bfff9b1
+7929d80039200019
+7d204e2a7c0004ac
+408200202c090000
+3c62ffff3c82ffff
+38637c2838847c18
+48000a294bfff981
+3940002860000000
+7c0004ac654ac000
+7929e0427d2056ea
+7c0004ac79292000
+418efd187d2057ea
+38637c483c62ffff
+386000004bfff949
+000000004bfffe28
+0000098003000000
+600000007c6903a6
+4e8000204200fffc
+0000000000000000
+3920100400000000
+7c0004ac6529c800
+394010087c604f2a
+654ac80039200001
+7d20572a7c0004ac
 000000004e800020
 0000000000000000
-6529c80039201004
-7c604f2a7c0004ac
-3920000139401008
+3842a7283c4c0001
+4182004428030002
+4182001428030003
+4182005028030001
+4bffffa87c8307b4
+6529c8003920104c
+7c804f2a7c0004ac
+3940105039200001
 7c0004ac654ac800
 4e8000207d20572a
-0000000000000000
-3c4c000100000000
-280300023842a6f4
-2803000341820044
-2803000141820014
-7c8307b441820050
-3920104c4bffffa8
-7c0004ac6529c800
-392000017c804f2a
-654ac80039401050
-7d20572a7c0004ac
-392010344e800020
+6529c80039201034
+7c804f2a7c0004ac
+3940103839200001
+3920101c4bffffd8
 7c0004ac6529c800
 392000017c804f2a
-4bffffd839401038
-6529c8003920101c
-7c804f2a7c0004ac
-3940102039200001
-000000004bffffbc
+4bffffbc39401020
+0000000000000000
+3d40555500000000
+614a55555469f87e
+7c6918507d295038
+612933333d203333
+5463f0be7d2a1838
+7d4a1a147c634838
+7d2952145549e13e
+614a0f0f3d400f0f
+552ac23e7d295038
+5523843e7d2a4a14
+786306a07c634a14
+000000004e800020
 0000000000000000
-5469f87e3d405555
-7d295038614a5555
-3d2033337c691850
-7d2a183861293333
-7c6348385463f0be
-5549e13e7d4a1a14
-3d400f0f7d295214
-7d295038614a0f0f
-7d2a4a14552ac23e
-7c634a145523843e
-4e800020786306a0
+3920000028030002
+4182002c39401040
+3920000028030003
+4182001c39401058
+3920000028030001
+4182000c39401028
+3940101039200000
+7c0004ac654ac800
+4e8000207d20572a
 0000000000000000
 2803000200000000
-3940104039200000
+3940103c39200000
 280300034182002c
-3940105839200000
+3940105439200000
 280300014182001c
-3940102839200000
+3940102439200000
 392000004182000c
-654ac80039401010
+654ac8003940100c
 7d20572a7c0004ac
 000000004e800020
 0000000000000000
-3920000028030002
-4182002c3940103c
-3920000028030003
-4182001c39401054
-3920000028030001
-4182000c39401024
-3940100c39200000
-7c0004ac654ac800
-4e8000207d20572a
-0000000000000000
-3c4c000100000000
-7c0802a63842a554
-f821ff4148001f2d
-3f02ffff23a30001
-3b40100c3ae00003
-3ac010743b201010
-3bc0000020630003
-3b187e503b600000
-675ac80066f78020
-66d6c8006739c800
-7c7f07b47fbd07b4
-3a8100207bc91764
-3aa000047e87a378
-7e9ca3787d58482e
+3842a5883c4c0001
+48001f2d7c0802a6
+3ee2fffff821ff31
+3b20100c3ec0e008
+3aa010743b001010
+236300033b800830
+3ba000003bc00000
+7ad610203af77fac
+6718c8006739c800
+679cc80066b5c800
+687f00017f7b07b4
+3a4100207bc91764
+3a8000047e479378
+7e5a93787d57482e
 4800004439000000
 794a07e07949f862
-7d4ab8387d4a00d0
+7d4ab0387d4a00d0
 7d2a4b787d494a78
 7d293030552907fe
 7d292b7838c60001
@@ -812,253 +838,252 @@ f821ff4148001f2d
 4182001828280004
 38a0000039200008
 38c000007d2903a6
-3ab5ffff4bffffb0
-2c15000038e70004
+3a94ffff4bffffb0
+2c14000038e70004
 7c0004ac4082ff98
-7c0004ac7ea0d72a
-386000097ea0cf2a
-3860000f4bfffd41
-392010144bfffd1d
+7c0004ac7e80cf2a
+386000097e80c72a
+3860000f4bfffd3d
+392010144bfffd19
 38e000046529c800
-7ce903a63914ffff
-8ce8000139400000
+7ce903a63912ffff
+394000003a600004
+3a73ffff8ce80001
 7cea3b787947400c
-7c0004ac4200fff4
+7c0004ac4200fff0
 392900187ce04f2a
-7c29b0003a940004
-3a8008304082ffcc
-7c0004ac6694c800
-5463063e7c60a62a
-7c0004ac4bfffe61
-5463063e7c60a62a
-7c0004ac4bfffdfd
-388000177c60a62a
-4bfffcf95463063e
-3860000f3a80082c
-6694c8004bfffc95
-7c60a62a7c0004ac
-4bfffe1d5463063e
-7c60a62a7c0004ac
-4bfffdb95463063e
-7c60a62a7c0004ac
+7c29a8003a520004
+7c0004ac4082ffc4
+5463063e7c60e62a
+7c0004ac4bfffe5d
+5463063e7c60e62a
+7c0004ac4bfffdf9
+388000177c60e62a
+4bfffcf55463063e
+3860000f3a40082c
+6652c8004bfffc91
+7c60962a7c0004ac
+4bfffe195463063e
+7c60962a7c0004ac
+4bfffdb55463063e
+7c60962a7c0004ac
 5463063e38800025
-3860000f4bfffcb5
-392000004bfffc55
-7d20d72a7c0004ac
+3860000f4bfffcb1
+392000004bfffc51
 7d20cf2a7c0004ac
-7e9cea143860000b
-3860000f4bfffc51
-4bfffc293a601018
-6673c8003a001078
-7e91a3787f9cfa14
-7c0004ac6610c800
-390000047d209e2a
+7d20c72a7c0004ac
+39c010183860000b
+3860000f4bfffc4d
+4bfffc2565cec800
+7e5afa147dfada14
+7e7107b41d330018
+7c0004ac7d297214
+390000047d204e2a
 7d0903a679290020
 9d2affff39410034
 4200fff87929c202
-3a7300187d3da050
-7c69f8ae3a940004
-7c634a78893c0010
-4bfffcb55463063e
-7c721b7889310010
-7c634a788874fffc
-4bfffc9d5463063e
-7c6392147c338000
-4082ff987eb51a14
-7f7baa143bde0001
-4082fddc283e0003
-7f6307b4382100c0
-0000000048001d04
-0000108001000000
-3842a2c03c4c0001
-388000007c0802a6
-f821ff6148001cb5
-3b1864ec3f02ffff
-3bc000007c7d1b78
-7f05c3783b800000
-600000004800084d
-4bfffd397fa3eb78
-7c7f00342c030000
-4082006857ffd97e
-418200602c1c0000
-7ff9fb783bfeffff
-7fdbf3787ffcfb78
-3b5b00017fa3eb78
-2c0300004bfffd05
-7d39d85040820070
-7c0950007d5fe050
-2c1a001f41810068
-3ca2ffff4181006c
-3880000038a564a4
-7f5bd3787fa3eb78
-60000000480007d5
-3bde00014bffffb8
-418200242c1e0020
-38a564a43ca2ffff
+7a3117647a691764
+3a7300017e3a8a14
+892f00107c6f48ae
+5463063e7c634a78
+893200104bfffcad
+7c71f8ae7c701b78
+5463063e7c634a78
+283300044bfffc95
+7e941a147c638214
+3bde00014082ff88
+283e00037fbda214
+382100d04082fdd8
+48001cfc7fa307b4
+0100000000000000
+3c4c000100001280
+7c0802a63842a2ec
+48001cb538800000
+3f02fffff821ff61
+7c7d1b783b1864b4
+3b8000003bc00000
+480008417f05c378
+7fa3eb7860000000
+2c0300004bfffd31
+57ffd97e7c7f0034
+2c1c000040820068
+3bfeffff41820060
+7ffcfb787ff9fb78
+7fa3eb787fdbf378
+4bfffcfd3b5b0001
+408200702c030000
+7d5fe0507d39d850
+418100687c095000
+4181006c2c1a001f
+38a5646c3ca2ffff
 7fa3eb7838800000
-480007a97ffcfb78
-4bffff5c60000000
-4bffff783be0ffff
-4bffffa07f59d378
-7f3fcb787f7cdb78
-2c1c00004bffff94
-7fc907b440800024
-2129001f3b800000
-418000082c290000
-3bde0001239e001f
-2c1f00007f9cf214
-3c62ffff4080001c
-4bfff3cd38637d70
-382100a060000000
-7cbfe05048001bd4
-7ca50e707c9cfa14
-789bfee27ca50194
-7ca507b43c62ffff
-38637d807f64db78
-4bfff3953be00008
-7f05c37860000000
+480007c97f5bd378
+4bffffb860000000
+2c1e00203bde0001
+3ca2ffff41820024
+3880000038a5646c
+7ffcfb787fa3eb78
+600000004800079d
+3be0ffff4bffff5c
+7f59d3784bffff78
+7f7cdb784bffffa0
+4bffff947f3fcb78
+4080001c2c1c0000
+3b8000002c1e0020
+239e001f41820008
+7f9cf2143bde0001
+4080001c2c1f0000
+38637d603c62ffff
+600000004bfff379
+48001bdc382100a0
+7c9fe2147cbfe050
+7ca501947ca50e70
+3c62ffff789bfee2
+7f64db787ca507b4
+3be0000838637d70
+600000004bfff341
+388000007f05c378
+3bc000007fa3eb78
+60000000480006f5
+4bfff9ed38600064
+418100247c1bf000
+4bfffbd57fa3eb78
+4182ff942c030000
+2c1f00003bffffff
+4bffff844082ffc0
+38a5646c3ca2ffff
 7fa3eb7838800000
-480006f93bc00000
+480006a93bde0001
 3860006460000000
-7c1bf0004bfff9ed
-7fa3eb7841810024
-2c0300004bfffbd5
-3bffffff4182ff94
-4082ffc02c1f0000
-3ca2ffff4bffff84
-3880000038a564a4
-3bde00017fa3eb78
-60000000480006ad
-4bfff9a138600064
-000000004bffffb4
-0000088001000000
-3842a0d03c4c0001
-6529c80039201000
-7d404e2a7c0004ac
-4d820020280a000e
-3940000e7c0802a6
-f821ffa1f8010010
-7d404f2a7c0004ac
-38637d983c62ffff
-600000004bfff2d1
-e801001038210060
-4e8000207c0803a6
+4bffffb44bfff9a1
 0100000000000000
-3c4c000100000080
-392010003842a06c
+3c4c000100000880
+392010003842a104
 7c0004ac6529c800
-280a00017d404e2a
+280a000e7d404e2a
 7c0802a64d820020
-f801001039400001
+f80100103940000e
 7c0004acf821ffa1
 3c62ffff7d404f2a
-4bfff26d38637dc0
+4bfff27d38637d88
 3821006060000000
 7c0803a6e8010010
 000000004e800020
 0000008001000000
-3842a0083c4c0001
-480019ed7c0802a6
-3f02fffff821ff31
-3ec2ffff3b186574
-3e82ffff3ea2ffff
-3e62ffff3ee2ffff
-3ad67de83b400000
-3a947e003ab57df8
-3a737e083af77b30
-7f05c3787f5f07b4
+3842a0a03c4c0001
+6529c80039201000
+7d404e2a7c0004ac
+4d820020280a0001
+394000017c0802a6
+f821ffa1f8010010
+7d404f2a7c0004ac
+38637db03c62ffff
+600000004bfff219
+e801001038210060
+4e8000207c0803a6
+0100000000000000
+3c4c000100000080
+7c0802a63842a03c
+f821ff31480019f5
+3b18653c3f02ffff
+3ea2ffff3ec2ffff
+3ee2ffff3e82ffff
+3b4000003e62ffff
+3ab57de83ad67dd8
+3af77b003a947df0
+7f5f07b43a737df8
+388000007f05c378
+480005697fe3fb78
+3b60000060000000
+3bc000003b800000
+7fdbf37848000030
+418200e42c1e0007
+38a564f43ca2ffff
 7fe3fb7838800000
-600000004800056d
-3b8000003b600000
-480000303bc00000
-2c1e00077fdbf378
-3ca2ffff418200e4
-3880000038a5652c
-3bde00017fe3fb78
-480005317fbceb78
-7fc507b460000000
-7ec3b3787fe4fb78
-4bfff19d3b200020
-3ca2ffff60000000
-3880000038a564ec
-3ba000007fe3fb78
-60000000480004fd
-4bfff9e97fe3fb78
-7c64003439400000
-5484d97e212300c0
+7fbceb783bde0001
+600000004800052d
+7fe4fb787fc507b4
+3b2000207ec3b378
+600000004bfff149
+38a564b43ca2ffff
+7fe3fb7838800000
+480004f93ba00000
+7fe3fb7860000000
+392000004bfff9e9
+5484d97e7c640034
 418200082c040000
-7d29521439401800
-7ea3ab78788407e0
-4bfff1457fbd4a14
-3ca2ffff60000000
-3880000038a564a4
-480004a97fe3fb78
-3739ffff60000000
-7e83a3784082ffa8
-600000004bfff119
-4bfffc157fe3fb78
-4bfff1057ee3bb78
-7c1ce84060000000
-7f9de3784180ff20
-7f6507b44bffff1c
-7e639b787fe4fb78
-4bfff0dd3bc00000
-7f05c37860000000
+206300c039201800
+7d291a14788407e0
+7fbd4a147ea3ab78
+600000004bfff0f1
+38a5646c3ca2ffff
+7fe3fb7838800000
+60000000480004a5
+4082ffa83739ffff
+4bfff0c57e83a378
+7fe3fb7860000000
+7ee3bb784bfffc1d
+600000004bfff0b1
+4180ff207c1ce840
+4bffff1c7f9de378
+7fe4fb787f6507b4
+3bc000007e639b78
+600000004bfff089
+388000007f05c378
+480004417fe3fb78
+7c1ed80060000000
+7fe3fb7840820030
+7ee3bb784bfffbc5
+600000004bfff059
+3b400001393a0001
+4082fe982c090002
+48001898382100d0
+38a564f43ca2ffff
 7fe3fb7838800000
-6000000048000445
-418000287c1ed800
-4bfffbbd7fe3fb78
-4bfff0ad7ee3bb78
-2c1a000060000000
-3b4000014082002c
-3ca2ffff4bfffe98
-3880000038a5652c
-3bde00017fe3fb78
-60000000480003fd
-382100d04bffffb8
-0000000048001870
-00000d8001000000
-38429e203c4c0001
-fbc1fff07c0802a6
-f8010010fbe1fff8
-4bfffd3df821ff91
-3bde64ec3fc2ffff
+480003f13bde0001
+4bffffb060000000
+0100000000000000
+3c4c000100000d80
+7c0802a638429e54
+fbe1fff8fbc1fff0
+f821ff91f8010010
+3fc2ffff4bfffd3d
+388000003bde64b4
+7fc5f37838600000
+60000000480003a5
+3bff653c3fe2ffff
 3860000038800000
-480003a97fc5f378
-3fe2ffff60000000
-388000003bff6574
-7fe5fb7838600000
-600000004800038d
-388000007fc5f378
-4800037938600001
-7fe5fb7860000000
+480003897fe5fb78
+7fc5f37860000000
 3860000138800000
-6000000048000365
-38637e203c62ffff
-600000004bffefd9
-4bfffd294bfffd91
-3860000138210070
-0000000048001800
-0000028001000000
-38429d703c4c0001
-3920082c7c0802a6
-4800175d6529c800
+6000000048000375
+388000007fe5fb78
+4800036138600001
+3c62ffff60000000
+4bffef8538637e10
+4bfffd9160000000
+382100704bfffd29
+4800180838600001
+0100000000000000
+3c4c000100000280
+7c0802a638429da4
+3b80082c4800176d
 3b000002f821ff51
-7f004f2a7c0004ac
-3b20000339200830
-7c0004ac6529c800
-3c62ffff7f204f2a
-38637e303c804000
-4bffef653bc00800
-3b80000160000000
-67dec8004bfffc51
-7f80f72a7c0004ac
-3be00000386003e8
-7c0004ac4bfff5bd
-386003e87fe0f72a
-4bfff5a93f60c800
-7c0004ac7b7b0020
-3b4000047fe0df2a
+7c0004ac679cc800
+392008307f00e72a
+6529c8003b200003
+7f204f2a7c0004ac
+3c8040003c62ffff
+3bc0080038637e20
+600000004bffef11
+4bfffc513b600001
+7c0004ac67dec800
+386003e87f60f72a
+4bfff5bd3be00000
+7fe0f72a7c0004ac
+3b9cf7d4386003e8
+7c0004ac4bfff5a9
+3b4000047fe0e72a
 7c0004ac675ac800
 3ba0100c7fe0d72a
 7c0004ac67bdc800
@@ -1068,47 +1093,47 @@ f8010010fbe1fff8
 66f7c8003920000c
 7d20bf2a7c0004ac
 6063c35038600000
-7c0004ac4bfff54d
+7c0004ac4bfff551
 7c0004ac7fe0ef2a
 3920000e7fe0f72a
 7d20bf2a7c0004ac
-4bfff52938602710
+4bfff52d38602710
 7c0004ac39200200
 7c0004ac7d20ef2a
 3860000f7f00f72a
-7c0004ac4bfff529
+7c0004ac4bfff52d
 7c0004ac7fe0ef2a
 3860000f7f20f72a
-392000064bfff511
+392000064bfff515
 7d20ef2a7c0004ac
-7f80f72a7c0004ac
-4bfff4f53860000f
+7f60f72a7c0004ac
+4bfff4f93860000f
 7c0004ac39200930
 7c0004ac7d20ef2a
 3860000f7fe0f72a
-386000c84bfff4d9
-392004004bfff4b5
+386000c84bfff4dd
+392004004bfff4b9
 7d20ef2a7c0004ac
 7fe0f72a7c0004ac
-4bfff4b538600003
-4bfff491386000c8
-4bfffb694bfffdb9
+4bfff4b938600003
+4bfff495386000c8
+4bfffb6d4bfffdbd
 3c6040003c800020
 600000004800085d
 408200242c030000
 7c0004ac7c691b78
-7c0004ac7f80d72a
-382100b07f80df2a
-480015e47d2307b4
+7c0004ac7f60d72a
+382100b07f60e72a
+480015f07d2307b4
 38a0000038c00000
 3c6040003c800020
 60000000480005e5
-7f80df2a7c0004ac
+7f60e72a7c0004ac
 4bffffd039200001
 0100000000000000
 3c4c000100000980
-6000000038429b5c
-3942802078631764
+6000000038429b94
+3942800878631764
 392900017d2a182e
 7d2a192e552906fe
 3920000139400818
@@ -1116,16 +1141,16 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429b14
-3922802078631764
+6000000038429b4c
+3922800878631764
 7d49192e39400000
 3920000139400814
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429ad4
-3942801878631764
+6000000038429b0c
+3942800078631764
 392900017d2a182e
 7d2a192e5529077e
 3920000139400820
@@ -1133,15 +1158,15 @@ f8010010fbe1fff8
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-6000000038429a8c
-3922801878631764
+6000000038429ac4
+3922800078631764
 7d49192e39400000
 392000013940081c
 7c0004ac654ac800
 4e8000207d20572a
 0000000000000000
 3c4c000100000000
-7c0802a638429a4c
+7c0802a638429a84
 39200001fbe1fff8
 7cac2b783be00804
 67ffc8007d291830
@@ -1151,46 +1176,46 @@ f84100187ca903a6
 e84100184e800421
 7c0004ac39200000
 382100307d20ff2a
-000000004800147c
+0000000048001488
 0000018001000000
-384299e83c4c0001
+38429a203c4c0001
 282303ff7c0802a6
 f821ffa1f8010010
 7c641b7841810028
-38637e603c62ffff
-600000004bffec01
+38637e403c62ffff
+600000004bffebb1
 e801001038210060
 4e8000207c0803a6
 7c2348403d200010
 786505a040800028
 7ca54b9239200066
 3c62ffff7864b282
-4bffebc538637e68
+4bffeb7538637e48
 4bffffc460000000
 786465023d204000
 408000247c234840
 788955647863b282
 38a000667d291850
 7ca92b923c62ffff
-4bffffc838637e78
+4bffffc838637e58
 3920006678631782
 7ca5205078655564
 3c62ffff7c641b78
-38637e887ca54b92
+38637e687ca54b92
 000000004bffffa4
 0000008001000000
-384299183c4c0001
+384299503c4c0001
 fbe1fff87c0802a6
 7cbf2b787cc42a14
 7c641b787c852378
 78c600203c62ffff
-f801001038637e98
-4bffeb25f821ff91
+f801001038637e78
+4bffead5f821ff91
 7fe3fb7860000000
 3c62ffff4bfffef9
-4bffeb0d38637ea8
+4bffeabd38637e88
 3821007060000000
-0000000048001344
+0000000048001350
 0000018001000000
 418200242c240000
 786307e07869f842
@@ -1200,14 +1225,14 @@ f801001038637e98
 4bfffff438630001
 0000000000000000
 3c4c000100000000
-7c0802a638429874
+7c0802a6384298ac
 3d40aaaa78840764
 614aaaaa7c691b78
-7f8322144800126d
+7f83221448001279
 f821ffc17884f082
 7c7f1b7839040001
 7c7d1b787d0903a6
-4bffeae142000080
+4bffea9142000080
 7d3fe05060000000
 7929f0823d00aaaa
 392900017feafb78
@@ -1217,12 +1242,12 @@ f821ffc17884f082
 7feafb787929f082
 6108555539290001
 420000587d2903a6
-4bffea917fffe050
+4bffea417fffe050
 7bfff08260000000
 395f00013d205555
 7d4903a661295555
 3821004042000040
-480012207fc307b4
+4800122c7fc307b4
 3929000491490000
 812a00004bffff78
 418200087c094000
@@ -1234,44 +1259,44 @@ f821ffc17884f082
 4bffffac3bbd0004
 0100000000000000
 3c4c000100000480
-7d60002638429764
+7d6000263842979c
 916100087c0802a6
-480011452e260000
+480011512e260000
 7c7f1b78f821ff41
 7cde33787cba2b78
-419200c0789cf082
+419200e4789cf082
 82e6000081260004
-408200442c090000
-3ba000003f02ffff
-7bf900203b600001
-7c3ce8403b187eb0
-3c62ffff4082009c
-38637eb07b851028
-4bfffde57be40020
-38637b303c62ffff
-600000004bffe929
-600000004bffe98d
+418200d82c090000
+600000004bffe97d
 7ffbfb782d970000
 3ac000013ba00000
 7bf500203b200000
-7fb8eb787c3de040
-2c17000040820084
+7fb8eb787c3ce840
+2c170000408200c4
 3c62ffff41820028
-38637ec07b051028
-4bfffd8d7be40020
-38637b303c62ffff
-600000004bffe8d1
+38637ea07b051028
+4bfffdcd7be40020
+38637b003c62ffff
+600000004bffe8c1
 7f2307b4382100c0
 7d61812081610008
-3ae00001480010c0
-7b6300204bffff50
-4bfffdb57f44d378
+7b6300204800110c
+4bfffdfd7f44d378
 7c7f492e7ba91764
 7c7b1b7873a97fff
 7ba5102840820014
 7f03c3787f24cb78
-3bbd00014bfffd31
-7f44d3784bffff2c
+3bbd00014bfffd79
+4082ffc87c3ce840
+7b8510283c62ffff
+7be4002038637e90
+3c62ffff4bfffd59
+4bffe84d38637b00
+4bffff3460000000
+3f02ffff3ae00001
+3b6000013ba00000
+3b187e907bf90020
+7f44d3784bffffb8
 4bfffd7d7ac30020
 7c651b78809b0000
 7c0320407c761b78
@@ -1282,29 +1307,29 @@ e8de00107d8903a6
 f841001878840020
 4e8004217b630020
 2c030000e8410018
-73187fff4082ff58
+73187fff4082ff18
 418e00184082001c
 7ba510283c62ffff
-38637ec07ea4ab78
+38637ea07ea4ab78
 3bbd00014bfffcb1
-4bfffef43b7b0004
+4bfffeb43b7b0004
 0300000000000000
 3c4c000100000b80
-7d708026384295a4
+7d708026384295dc
 916100087c0802a6
-f821ff7148000f9d
+f821ff7148000fa9
 3ba4ffe07cdb3378
 7c7f1b782e3b0000
 7fa3ea147c9e2378
 3c62ffff7c641b78
-7cbc2b7838637ed0
-600000004bffe7a1
-38637ee83c62ffff
+7cbc2b7838637eb0
+600000004bffe751
+38637ec83c62ffff
 3c62ffff4092000c
-4bffe78538637ef8
+4bffe73538637ed8
 7fc3f37860000000
 3c62ffff4bfffb59
-4bffe76d38637f08
+4bffe71d38637ee8
 2c3c000060000000
 7cf602a6408200a8
 38bd002038df0020
@@ -1320,14 +1345,14 @@ f90a0018f90a0010
 639ce10078ea0020
 7f9ee1d279290020
 3c62ffff7d295050
-7f9c4b9238637f10
-600000004bffe6e9
+7f9c4b9238637ef0
+600000004bffe699
 4bfffabd7f83e378
-38637f203c62ffff
-600000004bffe6d1
-38637b303c62ffff
-600000004bffe6c1
-600000004bffe725
+38637f003c62ffff
+600000004bffe681
+38637b003c62ffff
+600000004bffe671
+600000004bffe6d5
 409200487f9602a6
 395f00207d3fe850
 7929d9423bbd0020
@@ -1344,16 +1369,16 @@ e95f0018e95f0010
 7b9c00203d4005f5
 79290020614ae100
 7d29e0507fde51d2
-38637f283c62ffff
-4bffe6257fde4b92
+38637f083c62ffff
+4bffe5d57fde4b92
 7fc3f37860000000
 3c62ffff4bfff9f9
-4bffe60d38637f20
+4bffe5bd38637f00
 3c62ffff60000000
-4bffe5fd38637b30
+4bffe5ad38637b00
 3821009060000000
 7d70812081610008
-7fa407b448000e04
+7fa407b448000e10
 4bfffaed79430020
 7d23db963bbd0001
 7d29d9d67c6a1b78
@@ -1361,16 +1386,16 @@ e95f0018e95f0010
 4bffff687d3f482a
 0300000000000000
 3c4c000100000680
-7c0802a63842936c
-48000d7128240200
+7c0802a6384293a4
+48000d7d28240200
 7c7e1b78f821ff81
 3b8002007c9f2378
 7c9c237841810008
 7fc4f3783c62ffff
-4bffe57538637f38
+4bffe52538637f18
 7fe3fb7860000000
 3c62ffff4bfff949
-4bffe55d38637f08
+4bffe50d38637ee8
 7f84e37860000000
 4bfffaa17fc3f378
 38a0000138c00000
@@ -1379,55 +1404,55 @@ e95f0018e95f0010
 7c7e1b787d23ea14
 418200802c090000
 7b85f8823c62ffff
-38637f487fa4eb78
-600000004bffe511
+38637f287fa4eb78
+600000004bffe4c1
 7fe5fb78283f8000
 38a0ffff4081000c
 3c62ffff54a50420
 3880000078a5f082
-4bffe4e538637f60
+4bffe49538637f40
 3c62ffff60000000
 7fc4f3787be5f082
-4bffe4cd38637f78
+4bffe47d38637f58
 3c62ffff60000000
-4bffe4bd38637f90
+4bffe46d38637f70
 3860000060000000
 786307e038210080
-3c62ffff48000ccc
-4bffe49d38637fa0
+3c62ffff48000cd8
+4bffe44d38637f80
 3860000160000000
 000000004bffffe0
 0000048001000000
-384292403c4c0001
-8922803060000000
-3942802860000000
+384292783c4c0001
+8922801860000000
+3942801060000000
 418200302c090000
 39290014e92a0000
 7d204eaa7c0004ac
 4182ffec71290020
-e922802860000000
+e922801060000000
 7c604faa7c0004ac
 e92a00004e800020
 7c0004ac39290010
 712900087d204eea
 5469063e4082ffec
-e942802860000000
+e942801060000000
 7d2057ea7c0004ac
 000000004e800020
 0000000000000000
-384291b83c4c0001
+384291f03c4c0001
 fbe1fff87c0802a6
 3be3fffffbc1fff0
 f821ffd1f8010010
 2c1e00008fdf0001
 3821003040820010
-48000c0438600000
+48000c1038600000
 4082000c2c1e000a
 4bffff3d3860000d
-4bffff3557c3063e
+4bffff357bc30020
 000000004bffffd0
 0000028001000000
-384291583c4c0001
+384291903c4c0001
 654ac00039400020
 7d4056ea7c0004ac
 794a060039200008
@@ -1438,377 +1463,378 @@ f821ffd1f8010010
 7929f8047d204eea
 79290fc339002000
 600000006508c000
-3d00001cf9028028
+3d00001cf9028010
 7d4a439261082000
 6000000041820080
-9922803039200001
+9922801839200001
 3920ff803900200c
 7c0004ac6508c000
-e92280287d2047aa
+e92280107d2047aa
 7d404faa7c0004ac
-794ac202e9228028
+794ac202e9228010
 7c0004ac39290004
-e92280287d404faa
+e92280107d404faa
 3929000c39400003
 7d404faa7c0004ac
-39290010e9228028
+39290010e9228010
 7d404faa7c0004ac
-39400007e9228028
+39400007e9228010
 7c0004ac39290008
 4e8000207d404faa
 394affff60000000
-3920201899228030
+3920201899228018
 7c0004ac6529c000
 4e8000207d404fea
 0000000000000000
 78a9e8c200000000
 3929000139400000
-420000287d2903a6
-78a5076078a90724
-7d434a1439050001
-7c844a147d0903a6
-4200001839200000
-7d24502a4e800020
-394a00087d23512a
-7d0448ae4bffffcc
-392900017d0a49ae
-000000004bffffdc
-0000000000000000
-386000007c691b78
-2c0a00007d4918ae
-386300014d820020
-000000004bfffff0
-0000000000000000
-408200082c240000
+4200002c7d2903a6
+3940000078a9e8c2
+7ca54a141d29fff8
+390500017c892050
+7d0903a67d291850
+4e80002042000018
+7d23512a7d24502a
+4bffffc8394a0008
+7d0951ae7d0450ae
+4bffffdc394a0001
+0000000000000000
+7c691b7800000000
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
+0000000000000000
+2c24000000000000
+408200087c691b78
 280500243881fff0
-38600000f8640000
-3d2000014d810020
-612a2600792983e4
-89090000e9240000
-4181004028080020
-70e700017d474436
-2c25000040820028
-2c050010418200e0
-2c08003040820010
-38a0001041820048
-4800008038600000
-f924000039290001
-2c2500004bffffb8
-2c0800304082ffd4
-4082ffdc38a0000a
-2c0a007889490001
-392900024082ffd0
-4bffffc0f9240000
-2c0a007889490001
-4bffffe84082ffb4
-54e7063e38eaffd0
-4181003c28070009
-7d2a07343929ffd0
-4c8000207c0a2800
-7c6519d239080001
-f90400007d290734
-e90400007c691a14
-714900ff89480000
-4e8000204082ffc0
-54e7063e38eaff9f
-4181000c28070019
-4bffffb83929ffa9
-554a063e394affbf
-4d810020280a0019
-4bffffa03929ffc9
-4bffff3438a0000a
-0000000000000000
-3923ff9f00000000
-4181000828090019
-7c6307b43863ffe0
-000000004e800020
+38600000f9240000
+3d4000014d810020
+614a2600794a83e4
+2808002089090000
+7d47443641810038
+4082002070e70001
+418200d02c250000
+418200282c050010
+386000003929ffff
+3929000148000078
+4bffffc4f9240000
+4082ffdc2c250000
+2c08003038a0000a
+894900014082ffd8
+4082ffcc2c0a0078
+38a0001039290002
+4bffffbcf9240000
+54e7063e38e8ffd0
+4181004028070009
+7d480734394affd0
+4c8000207c082800
+392900027c6519d2
+f92400007d4a0734
+7c6a1a147cc93378
+38c9000189090001
+4082ffbc710a00ff
+38e8ff9f4e800020
+2807001954e7063e
+394affa94181000c
+3908ffbf4bffffb4
+280800195508063e
+394affc94d810020
+38a0000a4bffff9c
+000000004bffff38
+0000000000000000
+280900193923ff9f
+3863ffe041810008
+4e8000207c6307b4
 0000000000000000
-38428e583c4c0001
-480008557c0802a6
-7c7e1b78f821ffa1
-7ca32b787cfd3b78
-38a0000a7c9c2378
-eb3e000038800000
-7d1b43787cdf3378
-4bfffe657d3a4b78
-2b9d001060000000
-2c3f000039400000
-2c0a00004082005c
-3940000140820008
-7c0350007d4ad214
-7d2350504081003c
-792900207d2948f8
-7d2903a639290001
-7d594850e93e0000
-408000187c2ae040
-e93e00009b690000
-f93e000039290001
-382100604200ffe0
-409e001048000808
-394a00017bffe102
-7fffeb924bffff94
-000000004bfffff4
-0000078001000000
-38428d883c4c0001
-4800078d7c0802a6
-eb630000f821ffb1
-7c9c23787c7f1b78
-3bc000007cbd2b78
-4bfffd7d7fa3eb78
-7c3e184060000000
-e93f000040800014
-7c2ae0407d5b4850
-382100504180000c
-7d5df0ae48000798
-994900003bde0001
-39290001e93f0000
-4bffffbcf93f0000
+3c4c000100000000
+7c0802a638428e9c
+f821ffa14800086d
+7cfd3b787c7e1b78
+7c9c23787ca32b78
+3880000038a0000a
+7cdf3378eb3e0000
+7d3a4b787d1b4378
+600000004bfffe75
+394000002b9d0010
+4082005c2c3f0000
+418100082c0a0000
+7d4ad21439400001
+4081003c7c035000
+394affff7d4a1850
+392a0001794a0020
+e93e00007d2903a6
+7c2ae0407d594850
+9b69000040800018
+39290001e93e0000
+4200ffe0f93e0000
+4800082038210060
+7bffe102409e0010
+4bffff94394a0001
+4bfffff47fffeb92
 0100000000000000
-3c4c000100000580
-7c0802a638428d0c
-e9297fb03d22ffff
-7d7080262b860010
-916100087caa2b78
-f821ffa1480006f5
+3c4c000100000780
+7c0802a638428dcc
+f821ffb1480007a5
+7c7f1b78eb630000
+7cbd2b787c9c2378
+7fa3eb783bc00000
+600000004bfffd8d
+408000147c3e1840
+7d5b4850e93f0000
+4180000c7c2ae040
+480007b038210050
+3bde00017d5df0ae
+e93f000099490000
+f93f000039290001
+000000004bffffbc
+0000058001000000
+38428d503c4c0001
+3d22ffff7c0802a6
+2b860010e9297f90
+916100087d708026
+f821ffa148000711
 7cbe2b787c7c1b78
 3be000007cdd3378
 3d22fffff9210020
-f9210028e9297fb8
-408200342c2a0000
-408200082c1f0000
-7fff07b43be00001
-7c3f20402e270000
-408100303b7fffff
-8161000838210060
-480006e87d708120
-794ae102409e0010
-4bffffbc3bff0001
-4bfffff47d4aeb92
-7f5eeb927f5ed378
-7d29f0507d3ae9d2
-886900207d214a14
-5463063e41920010
-600000004bfffdd5
-e93c00007c3df040
-3b7bffff7c69d9ae
-e93c00004081ffc8
-f93c00007d29fa14
-000000004bffff90
-0000068003000000
-38428c183c4c0001
-480005e97c0802a6
-7c761b79f821fef1
-38600000f8610060
-2c2400004182003c
-3b04ffff41820034
-3a8000003aa10040
-ebc1006089250000
-7c76f050712a00ff
-7c23c0404182000c
-3920000041800018
-38210110993e0000
-480005e07c6307b4
-390500012c0a0025
-3920000040820564
-7cb32b7889450000
-7d49a9ae8ce50001
-280a007854ea063e
-280a006241810024
-2c0a004f41810024
-2c0a0058418200a0
-2c0a002541820098
-3929000141820090
-3907ff9d4bffffc0
-280400155504063e
-3c82ffff4181ffec
-790815a8388474d0
-7d0822147d0442aa
-4e8004207d0903a6
-0000005800000058
-ffffffccffffffcc
-ffffffccffffffcc
-ffffffcc00000058
-ffffffccffffffcc
-ffffffccffffffcc
-0000005800000058
-ffffffccffffffcc
-ffffffcc00000058
-ffffffcc00000058
-00000058ffffffcc
-2c0a002539090001
-38a1002039290002
-7d2907b47d0807b4
-7d254a147d054214
-9a89002098e80020
+f9210028e9297f98
+2c2900007ca92b78
+2c1f000040820034
+3be0000141810008
+2e2700007fff07b4
+3b7fffff7c3f2040
+3821006040810030
+7d70812081610008
+409e001048000700
+3bff00017929e102
+7d29eb924bffffbc
+7f5ed3784bfffff4
+7d3ae9d27f5eeb92
+7d214a147d29f050
+4192001088690020
+4bfffdd55463063e
+7c3df04060000000
+7c69d9aee93c0000
+4081ffc83b7bffff
+7d29fa14e93c0000
+4bffff90f93c0000
+0300000000000000
+3c4c000100000680
+7c0802a638428c5c
+f821fef148000601
+f86100607c751b79
+4182004438600000
+4182003c2c240000
+3ae4ffff7cbd2b78
+3b2100203a610040
+895d00003a400000
+714900ffebc10060
+4182000c7c75f050
+418000187c23b840
+993e000039200000
+7c6307b438210110
+2c090025480005f0
+40820574391d0001
+7d4999ae39200000
+389d0001895d0001
+280800785548063e
+2808006241810024
+2c08004f41810028
+2c080058418200a4
+2c0800254182009c
+3929000141820094
+4bffffc07c9d2378
+54e5063e38eaff9d
+4181ffe828050015
+38a574943ca2ffff
+7ce53aaa78e715a8
+7ce903a67ce72a14
+000000584e800420
+ffffffc800000058
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+ffffffc8ffffffc8
+00000058ffffffc8
+ffffffc800000058
+00000058ffffffc8
+00000058ffffffc8
+ffffffc8ffffffc8
+38e9000100000058
+392900022c080025
+7d2907b47ce707b4
+7d394a147cf93a14
+9a49002099470020
 393e000140820018
-f9210060995e0000
-4bfffebc38b30002
+995e0000f9210060
+4bfffec03bbd0002
 eb86000089210041
-3a2600087fe3c050
-3b4100423a400030
+3a2600087fe3b850
+3b4100423a800030
 712900fd3929ffd2
-5649063e40820428
-3ae000003de2ffff
-f92100683b200004
+5689063e4082043c
+3ac000003de2ffff
+f92100683b000004
 3a0000003b600000
-4800017039ef7fd0
-38da00012c07004f
-390affa8418201dc
-280500225505063e
-3ca2ffff418103bc
-790815a838a575e8
-7d082a147d0542aa
-4e8004207d0903a6
-0000039c00000158
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-0000039c0000039c
-000002680000039c
-0000039c0000008c
-0000039c0000039c
-0000008c00000380
-0000039c0000039c
-0000039c00000368
-000001ac0000039c
-0000039c00000204
-000002ac0000039c
-0000008c0000039c
-0000039c0000039c
-0000039c0000015c
-2c070075000003c0
+4800016c39ef7fb8
+38ba00012c06004f
+38e8ffa8418201e0
+2804002254e4063e
+3c82ffff418103d0
+78e715a8388475a8
+7ce722147ce43aaa
+4e8004207ce903a6
+000003b000000154
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+000003b0000003b0
+00000270000003b0
+000003b00000008c
+000003b0000003b0
+0000008c00000394
+000003b0000003b0
+000003b00000037c
+000001b0000003b0
+000003b00000020c
+000002b4000003b0
+0000008c000003b0
+000003b0000003b0
+000003b000000158
+2c060075000003d4
 7d4152147b6a0020
-7f9de37839000000
+7f8ee37839000000
 41820044990a0020
-3940000157281838
-7d4a40363908ffff
-4182002c7f8a5039
+3900000157071838
+7d08383638e7ffff
+4182002c7f884039
 392900013940002d
-9949ffff7fbc00d0
-f92100603d42ffff
-394a7fd07b291e68
-7fbd48387d2a482a
-38e0000ae8810060
-38a100207fa6eb78
-5648063e39200000
-7c9e205038610060
-4bfffabd7c84f850
-7ae707e0e8810060
-7fa5eb7838c0000a
-7c84f8507c9e2050
-4bfffbe938610060
-895a00003b5a0001
-714700ffe9210060
-7fbe485041820010
-4181fe7c7c3fe840
-4bfffe247e268b78
-7b6900203ae00001
-38e00010e9010068
-7c9df8507d214a14
-3861006038a10020
-7b291e689a090020
-392000007d4f482a
-7dc673787f8e5038
-e88100604bfffa39
-38c000107ae707e0
-7dc573787c9e2050
-7b6900204bffff7c
-7d214a1439400000
-7c9df85038e00008
-994900205648063e
-7b291e683d42ffff
-38a10020394a7fd0
-7d4a482a38610060
-7f8e503839200000
-4bfff9dd7dc67378
-7ae707e0e8810060
+7b081e683ce2ffff
+9949ffff38e77fb8
+7d5c00d0f9210060
+7d4e40387d07402a
+38e0000a7c9e4850
+7f25cb787dc67378
+392000007c84f850
+386100605688063e
+e88100604bfffabd
+38c0000a7ac707e0
+7c9e20507dc57378
+386100607c84f850
+3b5a00014bfffbe9
+e9210060891a0000
+41820010710600ff
+7c3f70407dde4850
+7e268b784181fe80
+3ac000014bfffe28
+e90100687b690020
+7d214a1438e00010
+7f25cb787c8ef850
+9a09002038610060
+7d6f482a7b091e68
+7f8b583839200000
+f96100707d665b78
+e88100604bfffa35
+38c000107ac707e0
+e96100707c9e2050
+4bffff747d655b78
+390000007b690020
+38e000087d214a14
+7f25cb787c8ef850
+3d02ffff99090020
+39087fb87b091e68
+7d68482a38610060
+5688063e39200000
+7d665b787f8b5838
+4bfff9d1f9610070
+7ac707e0e8810060
 7c9e205038c00008
-7b6900204bffffa4
-7d214a1439400000
+7b6900204bffff9c
+7d214a1439000000
 7f86e37838e00010
-9949002039000020
-3920000238a10020
-386100607c9df850
-e88100604bfff999
+990900207f25cb78
+392000027c8ef850
+3861006039000020
+e88100604bfff98d
 386100603ca2ffff
-7c9e205038a57fc8
-4bfffa4d7c84f850
-7ae707e0e8810060
+7c9e205038a57fa8
+4bfffa417c84f850
+7ac707e0e8810060
 7f85e37838c00010
-4bfffec07c9e2050
-394000007b690020
-390000207d214a14
-38c0000138e0000a
-38a1002099490020
-7c9df85039200000
-4bfff93538610060
+4bfffeb47c9e2050
+390000007b690020
+38e0000a7d214a14
+7f25cb7838c00001
+7c8ef85099090020
+3900002039200000
+4bfff92938610060
 9b890000e9210060
 f921006039290001
-7b6a00204bfffe88
-f921007039000000
-38a0000a7d415214
-3861002038800000
-4bfff795990a0020
-7c6e1b7860000000
-4bfff75d7f83e378
-7c2e184060000000
-e921007040810048
-7c6370507fbdf850
-38e0002039400000
-7d09f0503bbd0001
-7d08fa147c691a14
-408200082c280000
-2c3d00013ba00001
-408200283bbdffff
-40820034714a0001
-7f85e378e8810060
-7c9e205038610060
-4bfff9557c84f850
-98e900004bfffde8
-3940000139290001
-4082ffc07c291840
-4bffffccf9210060
-3b200008893a0001
-4082fdbc2c09006c
-4bfffdb47cda3378
-3b200002893a0001
-4082fda42c090068
-3b2000017cda3378
-392affd04bfffd98
-280900095529063e
-7b6900204181fd88
-7d214a143b7b0001
-4bfffd7499490020
-4bfffd6c3b200008
-3b4100413a400020
-993e00004bfffbd4
-7d0543783bde0001
-4bfffa54fbc10060
-0100000000000000
-f9c1ff7000001280
-fa01ff80f9e1ff78
-fa41ff90fa21ff88
-fa81ffa0fa61ff98
-fac1ffb0faa1ffa8
-fb01ffc0fae1ffb8
-fb41ffd0fb21ffc8
-fb81ffe0fb61ffd8
-fbc1fff0fba1ffe8
-f8010010fbe1fff8
-e9c1ff704e800020
-ea01ff80e9e1ff78
-ea41ff90ea21ff88
-ea81ffa0ea61ff98
-eac1ffb0eaa1ffa8
-eb01ffc0eae1ffb8
-eb41ffd0eb21ffc8
-eb81ffe0eb61ffd8
-eba1ffe8e8010010
-ebc1fff07c0803a6
-4e800020ebe1fff8
-e8010010ebc1fff0
-7c0803a6ebe1fff8
-600000004e800020
+7b6800204bfffe7c
+f921007838e00000
+38a0000a7d014214
+7f23cb7838800000
+4bfff79998e80020
+f861007060000000
+4bfff7617f83e378
+e901007060000000
+7c281840e9210078
+7d244b7841810020
+7f85e3787c9e2050
+386100607c84f850
+4bfffe184bfff985
+7c6340507ce9f050
+7d4ef8507ce7fa14
+7c691a142c270000
+390000007d244b78
+394a000138c00020
+3940000140820008
+394affff2c2a0001
+7108000140820010
+4bffffa04082001c
+3884000198c40000
+7c24184039000001
+f88100604082ffd8
+893a00014bffff88
+2c09006c3b000008
+7cba2b784082fda4
+893a00014bfffd9c
+2c0900683b000002
+7cba2b784082fd8c
+4bfffd803b000001
+5529063e3928ffd0
+4181fd7028090009
+3b7b00017b690020
+990900207d214a14
+3b0000084bfffd5c
+3a8000204bfffd54
+4bfffbc03b410041
+3bde0001995e0000
+fbc100607d1d4378
+000000004bfffa44
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
+eb21ffc8eb01ffc0
+eb61ffd8eb41ffd0
+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
 6d6f636c65570a0a
 63694d206f742065
 2120747461776f72
@@ -1853,14 +1879,18 @@ e8010010ebc1fff0
 696c62616e652020
 004441555120676e
 006e6f7263694d20
+0000004953534920
+696c62616e655b20
+5d6461757120676e
+0000000000000000
 4920646175715b20
 005d65646f6d204f
 414c462049505320
 203a46464f204853
 7479622078257830
 00000000000a7365
-3033633733313738
-0000000000000000
+3235663166316362
+0000000000000062
 4d4152446574694c
 6620746c69756220
 6574694c206d6f72
@@ -1921,15 +1951,13 @@ e8010010ebc1fff0
 000000000000207c
 203a747365622020
 302562202c64256d
-6000000000206432
+0000000000206432
 76656c2064616552
 000a3a676e696c65
 696c616974696e49
 52445320676e697a
 3025783040204d41
 000a2e2e2e786c38
-000000540000002a
-6000000000000024
 0000000042756c25
 4b756c252e756c25
 0000000000004269
@@ -1971,11 +1999,12 @@ e8010010ebc1fff0
 20747365746d654d
 00000000000a4f4b
 20747365746d654d
-60000000000a4b4f
+00000000000a4b4f
 3736353433323130
 6665646362613938
 0000000000000000
-0000000000007830
+0000002a00007830
+0000002400000054
 0000000000000000
 00000000000000ff
 000000000000ffff
diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v
index d66961b..25178fe 100644
--- a/litedram/generated/wukong-v2/litedram_core.v
+++ b/litedram/generated/wukong-v2/litedram_core.v
@@ -8,8 +8,8 @@
 //
 // Filename   : litedram_core.v
 // Device     : 
-// LiteX sha1 : 87137c30
-// Date       : 2024-04-01 10:12:10
+// LiteX sha1 : bc1f1f52b
+// Date       : 2025-02-15 19:54:47
 //------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
@@ -80,18 +80,18 @@ LiteDRAMCore
 └─── crg (LiteDRAMS7DDRPHYCRG)
 │    └─── pll (S7PLL)
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
-│    │    └─── [BUFG]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
 │    │    └─── [FDCE]
+│    │    └─── [PLLE2_ADV]
+│    │    └─── [BUFG]
+│    │    └─── [BUFG]
 │    │    └─── [BUFG]
 │    │    └─── [BUFG]
-│    │    └─── [PLLE2_ADV]
 │    └─── idelayctrl (S7IDELAYCTRL)
 │    │    └─── [IDELAYCTRL]
 └─── ddrphy (A7DDRPHY)
@@ -136,102 +136,102 @@ LiteDRAMCore
 │    └─── bitslip_35* (BitSlip)
 │    └─── tappeddelayline_2* (TappedDelayLine)
 │    └─── tappeddelayline_3* (TappedDelayLine)
-│    └─── [IOBUF]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
-│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [OBUFDS]
 │    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
+│    └─── [IOBUFDS]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [ISERDESE2]
-│    └─── [IOBUF]
 │    └─── [IDELAYE2]
-│    └─── [IOBUF]
 │    └─── [IDELAYE2]
+│    └─── [IOBUF]
+│    └─── [OSERDESE2]
 │    └─── [ISERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
 │    └─── [IDELAYE2]
 │    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
+│    └─── [ISERDESE2]
+│    └─── [IDELAYE2]
+│    └─── [IOBUF]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [ISERDESE2]
-│    └─── [IOBUF]
+│    └─── [OBUFDS]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 │    └─── [OSERDESE2]
-│    └─── [IOBUF]
-│    └─── [ISERDESE2]
 │    └─── [OSERDESE2]
-│    └─── [IDELAYE2]
 └─── sdram (LiteDRAMCore)
 │    └─── dfii (DFIInjector)
 │    │    └─── pi0 (PhaseInjector)
@@ -543,6 +543,7 @@ wire   [29:0] builder_interface0_adr;
 wire   [13:0] builder_interface0_bank_bus_adr;
 reg    [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface0_bank_bus_dat_w;
+wire          builder_interface0_bank_bus_re;
 wire          builder_interface0_bank_bus_we;
 wire    [1:0] builder_interface0_bte;
 wire    [2:0] builder_interface0_cti;
@@ -559,17 +560,22 @@ reg           builder_interface1_adr_next_value_ce1 = 1'd0;
 wire   [13:0] builder_interface1_bank_bus_adr;
 reg    [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface1_bank_bus_dat_w;
+wire          builder_interface1_bank_bus_re;
 wire          builder_interface1_bank_bus_we;
 wire   [31:0] builder_interface1_dat_r;
 reg    [31:0] builder_interface1_dat_w = 32'd0;
 reg    [31:0] builder_interface1_dat_w_next_value0 = 32'd0;
 reg           builder_interface1_dat_w_next_value_ce0 = 1'd0;
+reg           builder_interface1_re = 1'd0;
+reg           builder_interface1_re_next_value2 = 1'd0;
+reg           builder_interface1_re_next_value_ce2 = 1'd0;
 reg           builder_interface1_we = 1'd0;
-reg           builder_interface1_we_next_value2 = 1'd0;
-reg           builder_interface1_we_next_value_ce2 = 1'd0;
+reg           builder_interface1_we_next_value3 = 1'd0;
+reg           builder_interface1_we_next_value_ce3 = 1'd0;
 wire   [13:0] builder_interface2_bank_bus_adr;
 reg    [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
 wire   [31:0] builder_interface2_bank_bus_dat_w;
+wire          builder_interface2_bank_bus_re;
 wire          builder_interface2_bank_bus_we;
 reg           builder_locked0 = 1'd0;
 reg           builder_locked1 = 1'd0;
@@ -594,6 +600,7 @@ reg           builder_new_master_wdata_ready0 = 1'd0;
 reg           builder_new_master_wdata_ready1 = 1'd0;
 reg     [1:0] builder_next_state = 2'd0;
 wire          builder_pll_fb;
+wire          builder_re;
 reg     [1:0] builder_refresher_next_state = 2'd0;
 reg     [1:0] builder_refresher_state = 2'd0;
 wire          builder_reset0;
@@ -700,14 +707,14 @@ reg           builder_t_self3 = 1'd0;
 reg           builder_t_self4 = 1'd0;
 reg           builder_t_self5 = 1'd0;
 wire          builder_we;
-wire          builder_xilinxasyncresetsynchronizerimpl0_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl0;
 wire          builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl1_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl1;
 wire          builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl2_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl2;
 wire          builder_xilinxasyncresetsynchronizerimpl2_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire          builder_xilinxasyncresetsynchronizerimpl3_async_reset;
+wire          builder_xilinxasyncresetsynchronizerimpl3;
 wire          builder_xilinxasyncresetsynchronizerimpl3_expr;
 wire          builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
 wire          iodelay_clk;
@@ -1895,9 +1902,9 @@ reg           main_litedramcore_csr_dfi_p0_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p0_address;
 wire    [2:0] main_litedramcore_csr_dfi_p0_bank;
 reg           main_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_cke;
 reg           main_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p0_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p0_odt;
 reg           main_litedramcore_csr_dfi_p0_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p0_rddata_en;
@@ -1911,9 +1918,9 @@ reg           main_litedramcore_csr_dfi_p1_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p1_address;
 wire    [2:0] main_litedramcore_csr_dfi_p1_bank;
 reg           main_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_cke;
 reg           main_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p1_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p1_odt;
 reg           main_litedramcore_csr_dfi_p1_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p1_rddata_en;
@@ -1927,9 +1934,9 @@ reg           main_litedramcore_csr_dfi_p2_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p2_address;
 wire    [2:0] main_litedramcore_csr_dfi_p2_bank;
 reg           main_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_cke;
 reg           main_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p2_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p2_odt;
 reg           main_litedramcore_csr_dfi_p2_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p2_rddata_en;
@@ -1943,9 +1950,9 @@ reg           main_litedramcore_csr_dfi_p3_act_n = 1'd1;
 wire   [13:0] main_litedramcore_csr_dfi_p3_address;
 wire    [2:0] main_litedramcore_csr_dfi_p3_bank;
 reg           main_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_cke = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_cke;
 reg           main_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg           main_litedramcore_csr_dfi_p3_odt = 1'd0;
+wire          main_litedramcore_csr_dfi_p3_odt;
 reg           main_litedramcore_csr_dfi_p3_ras_n = 1'd1;
 reg    [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0;
 wire          main_litedramcore_csr_dfi_p3_rddata_en;
@@ -4763,42 +4770,26 @@ always @(*) begin
         main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en;
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_cke <= 1'd0;
-    main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt;
-end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_odt <= 1'd0;
-    main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt;
-end
+assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke;
+assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt;
+assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt;
 assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n;
 assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n;
+always @(*) begin
+    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector0_command_issue_re) begin
+        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p0_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector0_command_issue_re) begin
@@ -4831,20 +4822,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector0_command_issue_re) begin
-        main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage;
 assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren);
 assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden);
 assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
 assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector1_command_issue_re) begin
+        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p1_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector1_command_issue_re) begin
@@ -4877,20 +4868,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector1_command_issue_re) begin
-        main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage;
 assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren);
 assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden);
 assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
 assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector2_command_issue_re) begin
+        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p2_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector2_command_issue_re) begin
@@ -4923,20 +4914,20 @@ always @(*) begin
         main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector2_command_issue_re) begin
-        main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage;
 assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren);
 assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden);
 assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
 assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
+always @(*) begin
+    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    if (main_litedramcore_phaseinjector3_command_issue_re) begin
+        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
+    end else begin
+        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+    end
+end
 always @(*) begin
     main_litedramcore_csr_dfi_p3_we_n <= 1'd1;
     if (main_litedramcore_phaseinjector3_command_issue_re) begin
@@ -4969,14 +4960,6 @@ always @(*) begin
         main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
     end
 end
-always @(*) begin
-    main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    if (main_litedramcore_phaseinjector3_command_issue_re) begin
-        main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras);
-    end else begin
-        main_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
-    end
-end
 assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage;
 assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
 assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren);
@@ -5085,82 +5068,82 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_cmd_valid <= 1'd0;
+    main_litedramcore_zqcs_executer_start <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
-            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_cmd_valid <= 1'd1;
             if (main_litedramcore_sequencer_done0) begin
                 if (main_litedramcore_wants_zqcs) begin
+                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
-                    main_litedramcore_cmd_valid <= 1'd0;
                 end
             end
         end
         2'd3: begin
-            main_litedramcore_cmd_valid <= 1'd1;
-            if (main_litedramcore_zqcs_executer_done) begin
-                main_litedramcore_cmd_valid <= 1'd0;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_zqcs_executer_start <= 1'd0;
+    main_litedramcore_cmd_last <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
         end
         2'd2: begin
             if (main_litedramcore_sequencer_done0) begin
                 if (main_litedramcore_wants_zqcs) begin
-                    main_litedramcore_zqcs_executer_start <= 1'd1;
                 end else begin
+                    main_litedramcore_cmd_last <= 1'd1;
                 end
             end
         end
         2'd3: begin
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_last <= 1'd1;
+            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_cmd_last <= 1'd0;
+    main_litedramcore_sequencer_start0 <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
+            if (main_litedramcore_cmd_ready) begin
+                main_litedramcore_sequencer_start0 <= 1'd1;
+            end
         end
         2'd2: begin
-            if (main_litedramcore_sequencer_done0) begin
-                if (main_litedramcore_wants_zqcs) begin
-                end else begin
-                    main_litedramcore_cmd_last <= 1'd1;
-                end
-            end
         end
         2'd3: begin
-            if (main_litedramcore_zqcs_executer_done) begin
-                main_litedramcore_cmd_last <= 1'd1;
-            end
         end
         default: begin
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_sequencer_start0 <= 1'd0;
+    main_litedramcore_cmd_valid <= 1'd0;
     case (builder_refresher_state)
         1'd1: begin
-            if (main_litedramcore_cmd_ready) begin
-                main_litedramcore_sequencer_start0 <= 1'd1;
-            end
+            main_litedramcore_cmd_valid <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_sequencer_done0) begin
+                if (main_litedramcore_wants_zqcs) begin
+                end else begin
+                    main_litedramcore_cmd_valid <= 1'd0;
+                end
+            end
         end
         2'd3: begin
+            main_litedramcore_cmd_valid <= 1'd1;
+            if (main_litedramcore_zqcs_executer_done) begin
+                main_litedramcore_cmd_valid <= 1'd0;
+            end
         end
         default: begin
         end
@@ -5306,7 +5289,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
@@ -5331,8 +5314,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine0_row_opened) begin
                         if (main_litedramcore_bankmachine0_row_hit) begin
                             if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
                             end
                         end else begin
                         end
@@ -5344,7 +5327,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
@@ -5353,6 +5336,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -5363,32 +5349,20 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine0_source_source_valid) begin
-                    if (main_litedramcore_bankmachine0_row_opened) begin
-                        if (main_litedramcore_bankmachine0_row_hit) begin
-                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine0_row_open <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine0_trccon_ready) begin
+                main_litedramcore_bankmachine0_row_open <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -5401,78 +5375,11 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine0_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine0_source_source_valid) begin
-                    if (main_litedramcore_bankmachine0_row_opened) begin
-                        if (main_litedramcore_bankmachine0_row_hit) begin
-                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine0_twtpcon_ready) begin
-                main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_row_open <= 1'd0;
-    case (builder_bankmachine0_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine0_trccon_ready) begin
-                main_litedramcore_bankmachine0_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
     case (builder_bankmachine0_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
@@ -5737,6 +5644,82 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine0_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine0_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine0_source_source_valid) begin
+                    if (main_litedramcore_bankmachine0_row_opened) begin
+                        if (main_litedramcore_bankmachine0_row_hit) begin
+                            if (main_litedramcore_bankmachine0_source_source_payload_we) begin
+                                main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid;
 assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready;
 assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we;
@@ -5876,125 +5859,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_row_open <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine1_trccon_ready) begin
-                main_litedramcore_bankmachine1_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine1_trccon_ready) begin
-                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine1_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine1_source_source_valid) begin
-                    if (main_litedramcore_bankmachine1_row_opened) begin
-                        if (main_litedramcore_bankmachine1_row_hit) begin
-                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine1_row_close <= 1'd0;
-    case (builder_bankmachine1_state)
-        1'd1: begin
-            main_litedramcore_bankmachine1_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine1_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine1_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine1_state)
@@ -6308,17 +6172,136 @@ always @(*) begin
         end
     endcase
 end
-assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
-assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
-assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
-assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
-assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
-assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
-assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
-assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
-assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
-assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
-assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+always @(*) begin
+    main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+                main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_row_open <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine1_trccon_ready) begin
+                main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine1_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine1_source_source_valid) begin
+                    if (main_litedramcore_bankmachine1_row_opened) begin
+                        if (main_litedramcore_bankmachine1_row_hit) begin
+                            main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine1_row_close <= 1'd0;
+    case (builder_bankmachine1_state)
+        1'd1: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine1_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready;
+assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid;
+assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready;
+assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first;
+assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last;
+assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we;
+assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr;
+assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
 assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid);
 assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]);
 assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
@@ -6447,32 +6430,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
-    case (builder_bankmachine2_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine2_trccon_ready) begin
-                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine2_state)
@@ -6879,6 +6836,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine2_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine2_trccon_ready) begin
+                main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid;
 assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready;
 assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we;
@@ -7018,76 +7001,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-            end
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine3_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine3_source_source_valid) begin
-                    if (main_litedramcore_bankmachine3_row_opened) begin
-                        if (main_litedramcore_bankmachine3_row_hit) begin
-                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
-                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine3_state)
@@ -7297,33 +7210,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine3_row_open <= 1'd0;
-    case (builder_bankmachine3_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine3_trccon_ready) begin
-                main_litedramcore_bankmachine3_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
     case (builder_bankmachine3_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
@@ -7389,6 +7276,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_row_open <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine3_state)
@@ -7450,6 +7363,76 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine3_trccon_ready) begin
+                main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+    case (builder_bankmachine3_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine3_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine3_source_source_valid) begin
+                    if (main_litedramcore_bankmachine3_row_opened) begin
+                        if (main_litedramcore_bankmachine3_row_hit) begin
+                            if (main_litedramcore_bankmachine3_source_source_payload_we) begin
+                                main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid;
 assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready;
 assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we;
@@ -7589,82 +7572,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine4_source_source_valid) begin
-                    if (main_litedramcore_bankmachine4_row_opened) begin
-                        if (main_litedramcore_bankmachine4_row_hit) begin
-                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
-                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
-    case (builder_bankmachine4_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-            if (main_litedramcore_bankmachine4_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine4_source_source_valid) begin
-                    if (main_litedramcore_bankmachine4_row_opened) begin
-                        if (main_litedramcore_bankmachine4_row_hit) begin
-                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
-                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
     case (builder_bankmachine4_state)
@@ -8021,6 +7928,82 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+    case (builder_bankmachine4_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine4_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine4_source_source_valid) begin
+                    if (main_litedramcore_bankmachine4_row_opened) begin
+                        if (main_litedramcore_bankmachine4_row_hit) begin
+                            if (main_litedramcore_bankmachine4_source_source_payload_we) begin
+                                main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid;
 assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready;
 assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we;
@@ -8105,180 +8088,61 @@ always @(*) begin
     case (builder_bankmachine5_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                if (main_litedramcore_bankmachine5_cmd_ready) begin
-                    builder_bankmachine5_next_state <= 3'd5;
-                end
-            end
-        end
-        2'd2: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                builder_bankmachine5_next_state <= 3'd5;
-            end
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                if (main_litedramcore_bankmachine5_cmd_ready) begin
-                    builder_bankmachine5_next_state <= 3'd7;
-                end
-            end
-        end
-        3'd4: begin
-            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
-                builder_bankmachine5_next_state <= 1'd0;
-            end
-        end
-        3'd5: begin
-            builder_bankmachine5_next_state <= 3'd6;
-        end
-        3'd6: begin
-            builder_bankmachine5_next_state <= 2'd3;
-        end
-        3'd7: begin
-            builder_bankmachine5_next_state <= 4'd8;
-        end
-        4'd8: begin
-            builder_bankmachine5_next_state <= 1'd0;
-        end
-        default: begin
-            if (main_litedramcore_bankmachine5_refresh_req) begin
-                builder_bankmachine5_next_state <= 3'd4;
-            end else begin
-                if (main_litedramcore_bankmachine5_source_source_valid) begin
-                    if (main_litedramcore_bankmachine5_row_opened) begin
-                        if (main_litedramcore_bankmachine5_row_hit) begin
-                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
-                                builder_bankmachine5_next_state <= 2'd2;
-                            end
-                        end else begin
-                            builder_bankmachine5_next_state <= 1'd1;
-                        end
-                    end else begin
-                        builder_bankmachine5_next_state <= 2'd3;
-                    end
-                end
-            end
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-            end
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_row_open <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_row_open <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
-always @(*) begin
-    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd5;
+                end
             end
         end
         2'd2: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                builder_bankmachine5_next_state <= 3'd5;
+            end
         end
         2'd3: begin
             if (main_litedramcore_bankmachine5_trccon_ready) begin
-                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                if (main_litedramcore_bankmachine5_cmd_ready) begin
+                    builder_bankmachine5_next_state <= 3'd7;
+                end
             end
         end
         3'd4: begin
+            if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+                builder_bankmachine5_next_state <= 1'd0;
+            end
         end
         3'd5: begin
+            builder_bankmachine5_next_state <= 3'd6;
         end
         3'd6: begin
+            builder_bankmachine5_next_state <= 2'd3;
         end
         3'd7: begin
+            builder_bankmachine5_next_state <= 4'd8;
         end
         4'd8: begin
+            builder_bankmachine5_next_state <= 1'd0;
         end
         default: begin
             if (main_litedramcore_bankmachine5_refresh_req) begin
+                builder_bankmachine5_next_state <= 3'd4;
             end else begin
                 if (main_litedramcore_bankmachine5_source_source_valid) begin
                     if (main_litedramcore_bankmachine5_row_opened) begin
                         if (main_litedramcore_bankmachine5_row_hit) begin
-                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                            if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+                                builder_bankmachine5_next_state <= 2'd2;
+                            end
                         end else begin
+                            builder_bankmachine5_next_state <= 1'd1;
                         end
                     end else begin
+                        builder_bankmachine5_next_state <= 2'd3;
                     end
                 end
             end
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine5_row_close <= 1'd0;
-    case (builder_bankmachine5_state)
-        1'd1: begin
-            main_litedramcore_bankmachine5_row_close <= 1'd1;
-        end
-        2'd2: begin
-            main_litedramcore_bankmachine5_row_close <= 1'd1;
-        end
-        2'd3: begin
-        end
-        3'd4: begin
-            main_litedramcore_bankmachine5_row_close <= 1'd1;
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine5_state)
@@ -8592,6 +8456,125 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+                main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+            end
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_open <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_row_open <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            end
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine5_trccon_ready) begin
+                main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+            if (main_litedramcore_bankmachine5_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine5_source_source_valid) begin
+                    if (main_litedramcore_bankmachine5_row_opened) begin
+                        if (main_litedramcore_bankmachine5_row_hit) begin
+                            main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
+        end
+    endcase
+end
+always @(*) begin
+    main_litedramcore_bankmachine5_row_close <= 1'd0;
+    case (builder_bankmachine5_state)
+        1'd1: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd2: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        2'd3: begin
+        end
+        3'd4: begin
+            main_litedramcore_bankmachine5_row_close <= 1'd1;
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid;
 assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready;
 assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we;
@@ -8731,32 +8714,6 @@ always @(*) begin
         end
     endcase
 end
-always @(*) begin
-    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
-    case (builder_bankmachine6_state)
-        1'd1: begin
-        end
-        2'd2: begin
-        end
-        2'd3: begin
-            if (main_litedramcore_bankmachine6_trccon_ready) begin
-                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
-            end
-        end
-        3'd4: begin
-        end
-        3'd5: begin
-        end
-        3'd6: begin
-        end
-        3'd7: begin
-        end
-        4'd8: begin
-        end
-        default: begin
-        end
-    endcase
-end
 always @(*) begin
     main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine6_state)
@@ -9163,6 +9120,32 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+    case (builder_bankmachine6_state)
+        1'd1: begin
+        end
+        2'd2: begin
+        end
+        2'd3: begin
+            if (main_litedramcore_bankmachine6_trccon_ready) begin
+                main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+            end
+        end
+        3'd4: begin
+        end
+        3'd5: begin
+        end
+        3'd6: begin
+        end
+        3'd7: begin
+        end
+        4'd8: begin
+        end
+        default: begin
+        end
+    endcase
+end
 assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid;
 assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready;
 assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we;
@@ -9303,21 +9286,22 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
             if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
             end
         end
         3'd4: begin
+            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9332,12 +9316,9 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-            end
         end
         2'd2: begin
         end
@@ -9360,8 +9341,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9373,22 +9354,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
-            if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-            end
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
         end
         3'd5: begin
         end
@@ -9399,11 +9373,26 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                            end else begin
+                            end
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9428,8 +9417,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
                             end else begin
-                                main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                             end
                         end else begin
                         end
@@ -9441,7 +9430,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9466,8 +9455,8 @@ always @(*) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
                             if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                             end else begin
+                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
                             end
                         end else begin
                         end
@@ -9479,7 +9468,7 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
         end
@@ -9488,6 +9477,9 @@ always @(*) begin
         2'd3: begin
         end
         3'd4: begin
+            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+            end
         end
         3'd5: begin
         end
@@ -9498,32 +9490,23 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                                main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
-                            end else begin
-                            end
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
+            if (main_litedramcore_bankmachine7_trccon_ready) begin
+                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+            end
         end
         3'd4: begin
         end
@@ -9541,10 +9524,7 @@ always @(*) begin
                 if (main_litedramcore_bankmachine7_source_source_valid) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
-                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
-                            end else begin
-                                main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
-                            end
+                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                         end else begin
                         end
                     end else begin
@@ -9555,18 +9535,18 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+    main_litedramcore_bankmachine7_row_close <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            if (main_litedramcore_bankmachine7_twtpcon_ready) begin
-                main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-            end
+            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9607,18 +9587,15 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
             end
         end
         3'd4: begin
@@ -9632,34 +9609,19 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
-            if (main_litedramcore_bankmachine7_refresh_req) begin
-            end else begin
-                if (main_litedramcore_bankmachine7_source_source_valid) begin
-                    if (main_litedramcore_bankmachine7_row_opened) begin
-                        if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-                        end else begin
-                        end
-                    end else begin
-                    end
-                end
-            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_close <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd2: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         2'd3: begin
         end
         3'd4: begin
-            main_litedramcore_bankmachine7_row_close <= 1'd1;
         end
         3'd5: begin
         end
@@ -9670,19 +9632,34 @@ always @(*) begin
         4'd8: begin
         end
         default: begin
+            if (main_litedramcore_bankmachine7_refresh_req) begin
+            end else begin
+                if (main_litedramcore_bankmachine7_source_source_valid) begin
+                    if (main_litedramcore_bankmachine7_row_opened) begin
+                        if (main_litedramcore_bankmachine7_row_hit) begin
+                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                        end else begin
+                        end
+                    end else begin
+                    end
+                end
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+            end
         end
         2'd2: begin
         end
         2'd3: begin
             if (main_litedramcore_bankmachine7_trccon_ready) begin
-                main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+                main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
             end
         end
         3'd4: begin
@@ -9700,9 +9677,12 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+    main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
     case (builder_bankmachine7_state)
         1'd1: begin
+            if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+            end
         end
         2'd2: begin
         end
@@ -9724,7 +9704,10 @@ always @(*) begin
                 if (main_litedramcore_bankmachine7_source_source_valid) begin
                     if (main_litedramcore_bankmachine7_row_opened) begin
                         if (main_litedramcore_bankmachine7_row_hit) begin
-                            main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                            if (main_litedramcore_bankmachine7_source_source_payload_we) begin
+                                main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                            end else begin
+                            end
                         end else begin
                         end
                     end else begin
@@ -10328,10 +10311,14 @@ always @(*) begin
     endcase
 end
 always @(*) begin
-    main_litedramcore_en1 <= 1'd0;
+    main_litedramcore_choose_req_cmd_ready <= 1'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            main_litedramcore_en1 <= 1'd1;
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
         2'd2: begin
         end
@@ -10352,18 +10339,19 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
+            if (1'd0) begin
+                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+            end else begin
+                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+            end
         end
     endcase
 end
 always @(*) begin
-    main_litedramcore_choose_req_cmd_ready <= 1'd0;
+    main_litedramcore_en1 <= 1'd0;
     case (builder_multiplexer_state)
         1'd1: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-            end
+            main_litedramcore_en1 <= 1'd1;
         end
         2'd2: begin
         end
@@ -10384,11 +10372,6 @@ always @(*) begin
         4'd10: begin
         end
         default: begin
-            if (1'd0) begin
-                main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-            end else begin
-                main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-            end
         end
     endcase
 end
@@ -10493,64 +10476,82 @@ always @(*) begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0];
+                builder_interface1_adr_next_value1 <= builder_interface0_adr;
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface0_ack <= 1'd0;
+    builder_interface1_adr_next_value_ce1 <= 1'd0;
     case (builder_state)
         1'd1: begin
+            builder_interface1_adr_next_value_ce1 <= 1'd1;
         end
         2'd2: begin
-            builder_interface0_ack <= 1'd1;
         end
         default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_adr_next_value_ce1 <= 1'd1;
+            end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_adr_next_value_ce1 <= 1'd0;
+    builder_interface1_re_next_value2 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_adr_next_value_ce1 <= 1'd1;
+            builder_interface1_re_next_value2 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_adr_next_value_ce1 <= 1'd1;
+                builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0));
+            end
+        end
+    endcase
+end
+always @(*) begin
+    builder_interface1_re_next_value_ce2 <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+            builder_interface1_re_next_value_ce2 <= 1'd1;
+        end
+        2'd2: begin
+        end
+        default: begin
+            if ((builder_interface0_cyc & builder_interface0_stb)) begin
+                builder_interface1_re_next_value_ce2 <= 1'd1;
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value2 <= 1'd0;
+    builder_interface1_we_next_value3 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value2 <= 1'd0;
+            builder_interface1_we_next_value3 <= 1'd0;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
+                builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0));
             end
         end
     endcase
 end
 always @(*) begin
-    builder_interface1_we_next_value_ce2 <= 1'd0;
+    builder_interface1_we_next_value_ce3 <= 1'd0;
     case (builder_state)
         1'd1: begin
-            builder_interface1_we_next_value_ce2 <= 1'd1;
+            builder_interface1_we_next_value_ce3 <= 1'd1;
         end
         2'd2: begin
         end
         default: begin
             if ((builder_interface0_cyc & builder_interface0_stb)) begin
-                builder_interface1_we_next_value_ce2 <= 1'd1;
+                builder_interface1_we_next_value_ce3 <= 1'd1;
             end
         end
     endcase
@@ -10579,6 +10580,18 @@ always @(*) begin
         end
     endcase
 end
+always @(*) begin
+    builder_interface0_ack <= 1'd0;
+    case (builder_state)
+        1'd1: begin
+        end
+        2'd2: begin
+            builder_interface0_ack <= 1'd1;
+        end
+        default: begin
+        end
+    endcase
+end
 always @(*) begin
     builder_interface1_dat_w_next_value_ce0 <= 1'd0;
     case (builder_state)
@@ -10596,7 +10609,7 @@ assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
     builder_csrbank0_init_done0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10607,15 +10620,15 @@ always @(*) begin
 end
 assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank0_init_error0_we <= 1'd0;
+    builder_csrbank0_init_error0_re <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank0_init_error0_re <= 1'd0;
+    builder_csrbank0_init_error0_we <= 1'd0;
     if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+        builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re;
     end
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
@@ -10623,41 +10636,41 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage;
 assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    builder_csrbank1_rst0_we <= 1'd0;
+    builder_csrbank1_rst0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_rst0_re <= 1'd0;
+    builder_csrbank1_rst0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_dly_sel0_re <= 1'd0;
+    builder_csrbank1_dly_sel0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_dly_sel0_we <= 1'd0;
+    builder_csrbank1_dly_sel0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+    builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-        builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
@@ -10670,53 +10683,53 @@ end
 always @(*) begin
     builder_csrbank1_wlevel_en0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+    main_a7ddrphy_wlevel_strobe_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-        main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
-        main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
-        main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
     end
 end
 assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
     main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-        main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10727,75 +10740,75 @@ always @(*) begin
 end
 assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
-        main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
-        main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re;
     end
 end
 assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+    main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
-        main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+        main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_rdphase0_re <= 1'd0;
+    builder_csrbank1_rdphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 always @(*) begin
-    builder_csrbank1_rdphase0_we <= 1'd0;
+    builder_csrbank1_rdphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-    builder_csrbank1_wrphase0_we <= 1'd0;
+    builder_csrbank1_wrphase0_re <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
     end
 end
 always @(*) begin
-    builder_csrbank1_wrphase0_re <= 1'd0;
+    builder_csrbank1_wrphase0_we <= 1'd0;
     if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+        builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re;
     end
 end
 assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
-assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
-assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage;
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage;
 assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
-assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
-assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage;
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage;
 assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 always @(*) begin
@@ -10807,14 +10820,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_control0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
-        builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-        builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10825,15 +10838,15 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-        main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0];
@@ -10846,14 +10859,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-        builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-        builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10862,11 +10875,11 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
-        builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10875,7 +10888,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
@@ -10885,14 +10898,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi0_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-        builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-        builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10903,22 +10916,22 @@ always @(*) begin
 end
 assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-        main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
     builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
-        builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10937,14 +10950,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-        builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-        builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -10953,7 +10966,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
@@ -10963,7 +10976,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi1_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-        builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0];
@@ -10976,27 +10989,27 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-        builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
     end
 end
 always @(*) begin
-    main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+    main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-        main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+        main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0];
 always @(*) begin
     builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-        builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11015,10 +11028,10 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-        builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
@@ -11028,14 +11041,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-        builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi2_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
-        builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11054,7 +11067,7 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-        builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
@@ -11067,7 +11080,7 @@ end
 always @(*) begin
     main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-        main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+        main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0];
@@ -11080,14 +11093,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-        builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re;
     end
 end
 assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
     builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
-        builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11096,7 +11109,7 @@ always @(*) begin
         builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
     end
 end
-assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
@@ -11106,14 +11119,14 @@ end
 always @(*) begin
     builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-        builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re;
     end
 end
-assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0];
+assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w;
 always @(*) begin
     builder_csrbank2_dfii_pi3_rddata_we <= 1'd0;
     if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-        builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we);
+        builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re;
     end
 end
 always @(*) begin
@@ -11126,7 +11139,7 @@ assign main_litedramcore_sel = main_litedramcore_storage[0];
 assign main_litedramcore_cke = main_litedramcore_storage[1];
 assign main_litedramcore_odt = main_litedramcore_storage[2];
 assign main_litedramcore_reset_n = main_litedramcore_storage[3];
-assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage;
 assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0];
 assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1];
 assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2];
@@ -11135,11 +11148,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5];
 assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6];
 assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7];
-assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0];
-assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0];
-assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage;
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage;
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage;
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage;
+assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status;
 assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we;
 assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0];
 assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1];
@@ -11149,11 +11162,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5];
 assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6];
 assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7];
-assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0];
-assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0];
-assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage;
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage;
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage;
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage;
+assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status;
 assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we;
 assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0];
 assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1];
@@ -11163,11 +11176,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5];
 assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6];
 assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7];
-assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0];
-assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0];
-assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage;
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage;
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage;
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage;
+assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status;
 assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we;
 assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0];
 assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1];
@@ -11177,19 +11190,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei
 assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5];
 assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6];
 assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7];
-assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0];
-assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0];
-assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
-assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0];
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage;
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage;
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage;
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage;
+assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status;
 assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we;
 assign builder_adr = builder_interface1_adr;
+assign builder_re = builder_interface1_re;
 assign builder_we = builder_interface1_we;
 assign builder_dat_w = builder_interface1_dat_w;
 assign builder_interface1_dat_r = builder_dat_r;
 assign builder_interface0_bank_bus_adr = builder_adr;
 assign builder_interface1_bank_bus_adr = builder_adr;
 assign builder_interface2_bank_bus_adr = builder_adr;
+assign builder_interface0_bank_bus_re = builder_re;
+assign builder_interface1_bank_bus_re = builder_re;
+assign builder_interface2_bank_bus_re = builder_re;
 assign builder_interface0_bank_bus_we = builder_we;
 assign builder_interface1_bank_bus_we = builder_we;
 assign builder_interface2_bank_bus_we = builder_we;
@@ -11915,16 +11932,16 @@ always @(*) begin
     builder_self0 <= 3'd0;
     case (main_litedramcore_steerer0)
         1'd0: begin
-            builder_self0 <= main_litedramcore_nop_ba[2:0];
+            builder_self0 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self0 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self0 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12034,16 +12051,16 @@ always @(*) begin
     builder_self7 <= 3'd0;
     case (main_litedramcore_steerer1)
         1'd0: begin
-            builder_self7 <= main_litedramcore_nop_ba[2:0];
+            builder_self7 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self7 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self7 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12153,16 +12170,16 @@ always @(*) begin
     builder_self14 <= 3'd0;
     case (main_litedramcore_steerer2)
         1'd0: begin
-            builder_self14 <= main_litedramcore_nop_ba[2:0];
+            builder_self14 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self14 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self14 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12272,16 +12289,16 @@ always @(*) begin
     builder_self21 <= 3'd0;
     case (main_litedramcore_steerer3)
         1'd0: begin
-            builder_self21 <= main_litedramcore_nop_ba[2:0];
+            builder_self21 <= main_litedramcore_nop_ba;
         end
         1'd1: begin
-            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba;
         end
         2'd2: begin
-            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba;
         end
         default: begin
-            builder_self21 <= main_litedramcore_cmd_payload_ba[2:0];
+            builder_self21 <= main_litedramcore_cmd_payload_ba;
         end
     endcase
 end
@@ -12387,10 +12404,10 @@ always @(*) begin
         end
     endcase
 end
-assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked);
-assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
 
 
 //------------------------------------------------------------------------------
@@ -13989,8 +14006,11 @@ always @(posedge sys_clk) begin
     if (builder_interface1_adr_next_value_ce1) begin
         builder_interface1_adr <= builder_interface1_adr_next_value1;
     end
-    if (builder_interface1_we_next_value_ce2) begin
-        builder_interface1_we <= builder_interface1_we_next_value2;
+    if (builder_interface1_re_next_value_ce2) begin
+        builder_interface1_re <= builder_interface1_re_next_value2;
+    end
+    if (builder_interface1_we_next_value_ce3) begin
+        builder_interface1_we <= builder_interface1_we_next_value3;
     end
     builder_interface0_bank_bus_dat_r <= 1'd0;
     if (builder_csrbank0_sel) begin
@@ -14060,11 +14080,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
     if (builder_csrbank1_dly_sel0_re) begin
-        main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+        main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r;
     end
     main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
     if (builder_csrbank1_half_sys8x_taps0_re) begin
-        main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+        main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r;
     end
     main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
     if (builder_csrbank1_wlevel_en0_re) begin
@@ -14072,11 +14092,11 @@ always @(posedge sys_clk) begin
     end
     main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
     if (builder_csrbank1_rdphase0_re) begin
-        main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+        main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r;
     end
     main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
     if (builder_csrbank1_wrphase0_re) begin
-        main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+        main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r;
     end
     main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
     builder_interface2_bank_bus_dat_r <= 1'd0;
@@ -14160,74 +14180,74 @@ always @(posedge sys_clk) begin
         endcase
     end
     if (builder_csrbank2_dfii_control0_re) begin
-        main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+        main_litedramcore_storage <= builder_csrbank2_dfii_control0_r;
     end
     main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
     if (builder_csrbank2_dfii_pi0_command0_re) begin
-        main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r;
+        main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r;
     end
     main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
     if (builder_csrbank2_dfii_pi0_address0_re) begin
-        main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r;
+        main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r;
     end
     main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
     if (builder_csrbank2_dfii_pi0_baddress0_re) begin
-        main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+        main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r;
     end
     main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
     if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
-        main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+        main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r;
     end
     main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
     main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re;
     if (builder_csrbank2_dfii_pi1_command0_re) begin
-        main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r;
+        main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r;
     end
     main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
     if (builder_csrbank2_dfii_pi1_address0_re) begin
-        main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r;
+        main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r;
     end
     main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
     if (builder_csrbank2_dfii_pi1_baddress0_re) begin
-        main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+        main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r;
     end
     main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
     if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
-        main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+        main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r;
     end
     main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
     main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re;
     if (builder_csrbank2_dfii_pi2_command0_re) begin
-        main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r;
+        main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r;
     end
     main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
     if (builder_csrbank2_dfii_pi2_address0_re) begin
-        main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r;
+        main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r;
     end
     main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
     if (builder_csrbank2_dfii_pi2_baddress0_re) begin
-        main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+        main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r;
     end
     main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
     if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
-        main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+        main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r;
     end
     main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
     main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re;
     if (builder_csrbank2_dfii_pi3_command0_re) begin
-        main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r;
+        main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r;
     end
     main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
     if (builder_csrbank2_dfii_pi3_address0_re) begin
-        main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r;
+        main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r;
     end
     main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
     if (builder_csrbank2_dfii_pi3_baddress0_re) begin
-        main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+        main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r;
     end
     main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
     if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
-        main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+        main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r;
     end
     main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
     main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re;
@@ -14500,6 +14520,7 @@ always @(posedge sys_clk) begin
         main_init_done_re <= 1'd0;
         main_init_error_storage <= 1'd0;
         main_init_error_re <= 1'd0;
+        builder_interface1_re <= 1'd0;
         builder_interface1_we <= 1'd0;
         builder_refresher_state <= 2'd0;
         builder_bankmachine0_state <= 4'd0;
@@ -17453,7 +17474,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
@@ -17471,7 +17492,7 @@ FDPE #(
 	.C   (iodelay_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl0),
 
 	// Outputs.
 	.Q   (iodelay_rst)
@@ -17489,7 +17510,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
@@ -17507,7 +17528,7 @@ FDPE #(
 	.C   (sys_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl1),
 
 	// Outputs.
 	.Q   (sys_rst)
@@ -17525,7 +17546,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
@@ -17543,7 +17564,7 @@ FDPE #(
 	.C   (sys4x_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl2),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl2_expr)
@@ -17561,7 +17582,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (1'd0),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
@@ -17579,7 +17600,7 @@ FDPE #(
 	.C   (sys4x_dqs_clk),
 	.CE  (1'd1),
 	.D   (builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
-	.PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset),
+	.PRE (builder_xilinxasyncresetsynchronizerimpl3),
 
 	// Outputs.
 	.Q   (builder_xilinxasyncresetsynchronizerimpl3_expr)
@@ -17588,5 +17609,5 @@ FDPE #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2024-04-01 10:12:10.
+//  Auto-Generated by LiteX on 2025-02-15 19:54:47.
 //------------------------------------------------------------------------------