From 381149b2cc573d667767f383892a7f3598deeadc Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 6 Apr 2020 12:58:42 +1000 Subject: [PATCH] Consolidate trap variants under a single OP_TRAP This replaces OP_TD, OP_TDI, OP_TW and OP_TWI with a single OP_TRAP, distinguishing the cases by the input_reg_b and is_32bit fields of the decode ROM. This adds the twi and td cases to the decode tables. For now we make all of the trap instructions unconditionally generate a trap-type program interrupt if the TO field of the instruction is all ones, and do nothing otherwise. This reduces the number of values in insn_type_t from 65 to 62, meaning that an insn_type_t can now be encoded in 6 bits rather than 7. Signed-off-by: Paul Mackerras --- decode1.vhdl | 8 ++++---- decode_types.vhdl | 4 ++-- execute1.vhdl | 13 ++++++++++--- 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/decode1.vhdl b/decode1.vhdl index 8a62726..c35d916 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -67,8 +67,8 @@ architecture behaviour of decode1 is 36 => (LDST, OP_STORE, RA_OR_ZERO, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- stw 37 => (LDST, OP_STORE, RA_OR_ZERO, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- stwu 8 => (ALU, OP_ADD, RA, CONST_SI, NONE, RT, '0', '0', '1', '0', ONE, '1', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- subfic - 2 => (ALU, OP_TDI, RA, CONST_SI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- tdi - --PPC_TWI 3 + 2 => (ALU, OP_TRAP, RA, CONST_SI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- tdi + 3 => (ALU, OP_TRAP, RA, CONST_SI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '1'), -- twi 26 => (ALU, OP_XOR, NONE, CONST_UI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- xori 27 => (ALU, OP_XOR, NONE, CONST_UI_HI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- xoris others => illegal_inst @@ -317,8 +317,8 @@ architecture behaviour of decode1 is 2#0011001000# => (ALU, OP_ADD, RA, NONE, NONE, RT, '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- subfze 2#1011001000# => (ALU, OP_ADD, RA, NONE, NONE, RT, '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- subfzeo 2#1001010110# => (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- sync - -- 2#0001000100# td - 2#0000000100# => (ALU, OP_TW, RA, RB, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- tw + 2#0001000100# => (ALU, OP_TRAP, RA, RB, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- td + 2#0000000100# => (ALU, OP_TRAP, RA, RB, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '1'), -- tw 2#0100111100# => (ALU, OP_XOR, NONE, RB, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- xor others => illegal_inst ); diff --git a/decode_types.vhdl b/decode_types.vhdl index f22e4b2..fe30005 100644 --- a/decode_types.vhdl +++ b/decode_types.vhdl @@ -16,8 +16,8 @@ package decode_types is OP_POPCNT, OP_PRTY, OP_RFID, OP_RLC, OP_RLCL, OP_RLCR, OP_SC, OP_SETB, OP_SHL, OP_SHR, - OP_SYNC, OP_TD, OP_TDI, OP_TW, - OP_TWI, OP_XOR, OP_SIM_CONFIG + OP_SYNC, OP_TRAP, + OP_XOR, OP_SIM_CONFIG ); type input_reg_a_t is (NONE, RA, RA_OR_ZERO, SPR); type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, CONST_DS, CONST_M1, CONST_SH, CONST_SH32, SPR); diff --git a/execute1.vhdl b/execute1.vhdl index 6c19559..15635ab 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -726,9 +726,16 @@ begin result := x"0000000000000000"; result_en := '1'; - when OP_TDI => - -- Keep our test cases happy for now, ignore trap instructions - report "OP_TDI FIXME"; + when OP_TRAP => + -- For now, generate a program interrupt if the TO field is all 1s + if insn_to(e_in.insn) = "11111" then + exception := '1'; + ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64)); + ctrl_tmp.srr1 <= msr_copy(ctrl.msr); + -- set bit 46 to say a trap occurred + ctrl_tmp.srr1(63 - 46) <= '1'; + report "trap"; + end if; when OP_ISYNC => f_out.redirect <= '1';