From 32b0635d71285b98f0c83b89b856959169b50c12 Mon Sep 17 00:00:00 2001
From: Alaa Salman <38817722+alaasal@users.noreply.github.com>
Date: Mon, 22 Jun 2020 09:09:30 +0200
Subject: [PATCH] removing vhdl 2008 sequentioal conditional assignment syntax

---
 execute1.vhdl | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/execute1.vhdl b/execute1.vhdl
index 8286d30..9956813 100644
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -425,10 +425,31 @@ begin
 	-- Next insn adder used in a couple of places
 	next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 
+	--rotator coontrol signals --Syntax edit to remove vhdl 2009 features
+	if (e_in.insn_type = OP_SHR) then
+		right_shift <= '1';
+	else
+		right_shift <= '0';
+	end if;
+		
+	if ((e_in.insn_type = OP_RLC) or (e_in.insn_type = OP_RLCL)) then
+		rot_clear_left <= '1';
+	else
+		rot_clear_left <= '0';
+	end if;
+		
+	if ((e_in.insn_type = OP_RLC) or (e_in.insn_type = OP_RLCR)) then
+		rot_clear_right <= '1';
+	else
+		rot_clear_right <= '0';
+	end if;
+		
+
+
 	-- rotator control signals
-	right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
-	rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
-	rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
+	--right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
+	--rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
+	--rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 
 	ctrl_tmp.irq_state <= WRITE_SRR0;
 	exception := '0';