From 2b47de30c446ed4914a598d806f737fa67018093 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 17 Dec 2020 15:14:54 +1100 Subject: [PATCH] Add a script to post process the Microwatt verilog for caravel To produce verilog suitable for caravel: make DOCKER=1 FPGA_TARGET=caravel microwatt_asic.v ./caravel/process-microwatt-verilog.sh Signed-off-by: Anton Blanchard --- caravel/insert_power.py | 72 ++++++++++++++++++++++++++++ caravel/process-microwatt-verilog.sh | 37 ++++++++++++++ 2 files changed, 109 insertions(+) create mode 100755 caravel/insert_power.py create mode 100755 caravel/process-microwatt-verilog.sh diff --git a/caravel/insert_power.py b/caravel/insert_power.py new file mode 100755 index 0000000..ba839e4 --- /dev/null +++ b/caravel/insert_power.py @@ -0,0 +1,72 @@ +#!/usr/bin/python + +import argparse +import re + +module_regex = r'[a-zA-Z0-9_:\.\\]+' + +# match: +# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out); +# A bit of a hack - ignore anything contining a '`', and assume that means we've already +# processed this module in a previous run. This helps when having to run this script +# multiple times for different power names. +multiline_module_re = re.compile(r'module\s+(' + module_regex + r')\(([^`]*?)\);', re.DOTALL) +module_re = re.compile(r'module\s+(' + module_regex + r')\((.*?)\);') + +# match: +# dcache_64_2_2_2_2_12_0 dcache_0 ( +hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(') + +header1 = """\ +`ifdef USE_POWER_PINS + {power}, {ground}, +`endif\ +""" + +header2 = """\ +`ifdef USE_POWER_PINS + inout {power}; + inout {ground}; +`endif\ +""" + +header3 = """\ +`ifdef USE_POWER_PINS + .{power}({parent_power}), + .{ground}({parent_ground}), +`endif\ +""" + +parser = argparse.ArgumentParser(description='Insert power and ground into verilog modules') +parser.add_argument('--power', default='VPWR', help='POWER net name (default VPWR)') +parser.add_argument('--ground', default='VGND', help='POWER net name (default VGND)') +parser.add_argument('--parent-power', default='VPWR', help='POWER net name of parent module (default VPWR)') +parser.add_argument('--parent-ground', default='VGND', help='POWER net name of parent module (default VGND)') +parser.add_argument('--verilog', required=True, help='Verilog file to modify') +parser.add_argument('--module', required=True, action='append', help='Module to replace (can be specified multiple times') + +args = parser.parse_args() + +with open(args.verilog, 'r') as f: + d = f.read() + # Remove newlines from module definitions, yosys started doing this as of + # commit ff8e999a7112 ("Split module ports, 20 per line") + fixed = multiline_module_re.sub(lambda m: m.group(0).replace("\n", ""), d) + + for line in fixed.splitlines(): + m = module_re.match(line) + m2 = hookup_re.match(line) + if m and m.group(1) in args.module: + module_name = m.group(1) + module_args = m.group(2) + print('module %s(' % (module_name)) + print("") + print(header1.format(power=args.power, ground=args.ground)) + print(' %s);' % module_args) + print(header2.format(power=args.power, ground=args.ground)) + elif m2 and m2.group(1) in args.module: + print(line) + print(header3.format(parent_power=args.parent_power, parent_ground=args.parent_ground, power=args.power, ground=args.ground)) + else: + print(line) + diff --git a/caravel/process-microwatt-verilog.sh b/caravel/process-microwatt-verilog.sh new file mode 100755 index 0000000..07515d9 --- /dev/null +++ b/caravel/process-microwatt-verilog.sh @@ -0,0 +1,37 @@ +#!/bin/bash -e + +# process microwatt verilog + +FILE_IN=microwatt_asic.v +FILE_OUT=microwatt_asic_processed.v + +# Rename top level +sed 's/toplevel/microwatt/' < $FILE_IN > $FILE_OUT + +# Add power to all macros, and route power in microwatt down to them +caravel/insert_power.py --verilog=$FILE_OUT --parent-power=vccd1 --parent-ground=vssd1 --power=vccd1 --ground=vssd1 --module=microwatt --module=core_0_4_1_4_4_1_2_2_452bf2882a9b5f1c06340d5059c72dbd8af3bf8b --module=execute1_0_47ec8d98366433dc002e7721c9e37d5067547937 --module=multiply_4 --module=soc_4096_100000000_0_0_4_0_4_0_4_1_4_4_1_2_2_32_529beb193518cdd5546a21170d32ebafc9f9cb89 --module=icache_64_8_4_1_4_12_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f --module=dcache_64_4_1_2_2_12_0 --module=cache_ram_5_64_1489f923c4dca729178b3e3233458550d8dddf29 --module=main_bram_64_9_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 --module=register_file_0_3f29546453678b855931c174a97d6c0894b8f546 --module=wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 --module=fpu > ${FILE_OUT}.tmp1 + +# Hard macros use VPWR/VGND +caravel/insert_power.py --verilog=${FILE_OUT}.tmp1 --parent-power=vccd1 --parent-ground=vssd1 --power=VPWR --ground=VGND --module=Microwatt_FP_DFFRFile --module=multiply_add_64x64 --module=RAM32_1RW1R --module=RAM512 > ${FILE_OUT}.tmp2 + +mv ${FILE_OUT}.tmp2 ${FILE_OUT} +rm ${FILE_OUT}.tmp1 + +# Add defines +sed -i '1 a\ +\ +/* JTAG */\ +`include "tap_top.v"\ +\ +/* UART */\ +`include "raminfr.v"\ +`include "uart_receiver.v"\ +`include "uart_rfifo.v"\ +`include "uart_tfifo.v"\ +`include "uart_transmitter.v"\ +`include "uart_defines.v"\ +`include "uart_regs.v"\ +`include "uart_sync_flops.v"\ +`include "uart_wb.v"\ +`include "uart_top.v"\ +`include "simplebus_host.v"' $FILE_OUT