From 265fbf894bcf7e5cb0d140ca840b005b3cf7a1a9 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 15 Oct 2019 16:21:32 +1100 Subject: [PATCH] icache/dcache: Make both caches 32 lines, 2 ways Adding lines seems to add only little extra as the BRAMs aren't full, 2 ways is our current comprimise to limit pressure on small FPGAs. We could go to 64 lines for a little more, but timing is becoming a bit too right to my linking on the tags/LRU path of the icache, so let's leave it at 32 for now. Signed-off-by: Benjamin Herrenschmidt --- core.vhdl | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/core.vhdl b/core.vhdl index e9cd28b..77af882 100644 --- a/core.vhdl +++ b/core.vhdl @@ -115,7 +115,7 @@ begin icache_0: entity work.icache generic map( LINE_SIZE => 64, - NUM_LINES => 16, + NUM_LINES => 32, NUM_WAYS => 2 ) port map( @@ -215,6 +215,11 @@ begin ); dcache_0: entity work.dcache + generic map( + LINE_SIZE => 64, + NUM_LINES => 32, + NUM_WAYS => 2 + ) port map ( clk => clk, rst => core_rst,