diff --git a/core.vhdl b/core.vhdl
index c94db6f..d4efcf3 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -468,6 +468,7 @@ begin
 
     dcache_0: entity work.dcache
         generic map(
+            SIM => SIM,
             LINE_SIZE => 64,
             NUM_LINES => DCACHE_NUM_LINES,
             NUM_WAYS => DCACHE_NUM_WAYS,
diff --git a/dcache.vhdl b/dcache.vhdl
index af9bb0f..a98dde2 100644
--- a/dcache.vhdl
+++ b/dcache.vhdl
@@ -14,6 +14,7 @@ use work.wishbone_types.all;
 
 entity dcache is
     generic (
+        SIM : boolean := false;
         -- Line size in bytes
         LINE_SIZE : positive := 64;
         -- Number of lines in a set
@@ -922,10 +923,10 @@ begin
                 index := get_index(d_in.addr);
                 valid := d_in.valid;
             end if;
-            if valid = '1' then
+            if valid = '1' or not SIM then
                 cache_tag_set <= cache_tags(to_integer(index));
             else
-                cache_tag_set <= (others => '0');
+                cache_tag_set <= (others => 'X');
             end if;
         end if;
     end process;