From 23f5470f0893bf510c02307671e66ebc90e4fad4 Mon Sep 17 00:00:00 2001
From: Antony Vennard <antony@vennard.ch>
Date: Fri, 12 Mar 2021 00:08:38 +0100
Subject: [PATCH] Specify explicitly that files are verilog.

---
 uart16550/uart16550.core | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/uart16550/uart16550.core b/uart16550/uart16550.core
index 962d842..02f9919 100644
--- a/uart16550/uart16550.core
+++ b/uart16550/uart16550.core
@@ -5,13 +5,16 @@ name : ::uart16550
 filesets:
   core:
     files:
-    - raminfr.v
-    - uart_defines.v
-    - uart_receiver.v
-    - uart_regs.v
-    - uart_rfifo.v
-    - uart_sync_flops.v
-    - uart_tfifo.v
-    - uart_top.v
-    - uart_transmitter.v
-    - uart_wb.v
+    - raminfr.v : { filetype = "verilog" }
+    - uart_regs.v : { filetype = "verilog" }
+    - uart_rfifo.v : { filetype = "verilog" }
+    - uart_sync_flops.v : { filetype = "verilog" }
+    - uart_tfifo.v : { filetype = "verilog" }
+    - uart_transmitter.v : { filetype = "verilog" }
+    - uart_wb.v : { filetype = "verilog" }
+  uart_receiver:
+    files:
+    - uart_receiver.v : { filetype = "verilog" }
+  uart_top:
+    files:
+    - uart_wb.v : { filetype = "verilog" }