From 166e3f4ab2b2acc36aff9a500763b4d050e4011f Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 19 Mar 2024 16:21:28 +1100 Subject: [PATCH] ECPIX-5: Add basic support Signed-off-by: Paul Mackerras --- Makefile | 16 +++- constraints/ecpix-5.lpf | 45 ++++++++++++ fpga/top-ecpix5.vhdl | 158 ++++++++++++++++++++++++++++++++++++++++ openocd/ecpix-5.cfg | 6 ++ 4 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 constraints/ecpix-5.lpf create mode 100644 fpga/top-ecpix5.vhdl create mode 100644 openocd/ecpix-5.cfg diff --git a/Makefile b/Makefile index 10c8144..83db713 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex #MEMORY_SIZE=393216 #RAM_INIT_FILE=micropython/firmware.hex -FPGA_TARGET ?= ORANGE-CRAB-0.21 +FPGA_TARGET ?= ECPIX-5 clkgen=fpga/clk_gen_ecp5.vhd toplevel=fpga/top-generic.vhdl @@ -215,6 +215,20 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg endif +# ECPIX-5 +ifeq ($(FPGA_TARGET), ECPIX-5) +RESET_LOW=true +CLK_INPUT=100000000 +CLK_FREQUENCY=50000000 +LPF=constraints/ecpix-5.lpf +PACKAGE=CABGA554 +NEXTPNR_FLAGS=--um5g-85k --speed 8 --freq 50 --timing-allow-fail --ignore-loops +OPENOCD_JTAG_CONFIG=openocd/ecpix-5.cfg +OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg +toplevel=fpga/top-ecpix5.vhdl +dmi_dtm=dmi_dtm_ecp5.vhdl +endif + ifneq ($(litedram_target),) soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \ litedram/generated/$(litedram_target)/litedram-initmem.vhdl diff --git a/constraints/ecpix-5.lpf b/constraints/ecpix-5.lpf new file mode 100644 index 0000000..6517b0f --- /dev/null +++ b/constraints/ecpix-5.lpf @@ -0,0 +1,45 @@ +LOCATE COMP "ext_clk" SITE "K23"; +IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33; + +LOCATE COMP "ext_rst_n" SITE "N5"; +LOCATE COMP "gsrn" SITE "AB1"; +IOBUF PORT "ext_rst_n" IO_TYPE=LVCMOS33; +IOBUF PORT "gsrn" IO_TYPE=LVCMOS33; + +LOCATE COMP "uart0_txd" SITE "R24"; +LOCATE COMP "uart0_rxd" SITE "R26"; + +IOBUF PORT "uart0_txd" IO_TYPE=LVCMOS33; +IOBUF PORT "uart0_rxd" IO_TYPE=LVCMOS33; + +LOCATE COMP "led5_r_n" SITE "T23"; +LOCATE COMP "led5_g_n" SITE "R21"; +LOCATE COMP "led5_b_n" SITE "T22"; + +IOBUF PORT "led5_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led5_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led5_b_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "led6_r_n" SITE "U21"; +LOCATE COMP "led6_g_n" SITE "W21"; +LOCATE COMP "led6_b_n" SITE "T24"; + +IOBUF PORT "led6_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led6_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led6_b_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "led7_r_n" SITE "K21"; +LOCATE COMP "led7_g_n" SITE "K24"; +LOCATE COMP "led7_b_n" SITE "M21"; + +IOBUF PORT "led7_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led7_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led7_b_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "led8_r_n" SITE "P21"; +LOCATE COMP "led8_g_n" SITE "R23"; +LOCATE COMP "led8_b_n" SITE "P22"; + +IOBUF PORT "led8_r_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led8_g_n" IO_TYPE=LVCMOS33; +IOBUF PORT "led8_b_n" IO_TYPE=LVCMOS33; diff --git a/fpga/top-ecpix5.vhdl b/fpga/top-ecpix5.vhdl new file mode 100644 index 0000000..077b801 --- /dev/null +++ b/fpga/top-ecpix5.vhdl @@ -0,0 +1,158 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_INPUT : positive := 100000000; + CLK_FREQUENCY : positive := 50000000; + HAS_FPU : boolean := false; + HAS_BTC : boolean := false; + USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; + SCLK_STARTUPE2 : boolean := false; + LOG_LENGTH : natural := 0; + UART_IS_16550 : boolean := true; + HAS_UART1 : boolean := false; + USE_LITESDCARD : boolean := false; + ICACHE_NUM_LINES : natural := 64; + NGPIO : natural := 0 + ); + port( + ext_clk : in std_ulogic; + ext_rst_n : in std_ulogic; + gsrn : in std_ulogic; + + -- UART0 signals: + uart0_txd : out std_ulogic; + uart0_rxd : in std_ulogic; + + -- LEDs + led5_r_n : out std_ulogic; + led5_g_n : out std_ulogic; + led5_b_n : out std_ulogic; + led6_r_n : out std_ulogic; + led6_g_n : out std_ulogic; + led6_b_n : out std_ulogic; + led7_r_n : out std_ulogic; + led7_g_n : out std_ulogic; + led7_b_n : out std_ulogic; + led8_r_n : out std_ulogic; + led8_g_n : out std_ulogic; + led8_b_n : out std_ulogic + + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; + +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 512 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + HAS_SPI_FLASH => false, + LOG_LENGTH => LOG_LENGTH, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1, + HAS_SD_CARD => USE_LITESDCARD, + ICACHE_NUM_LINES => ICACHE_NUM_LINES, + NGPIO => NGPIO + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => uart0_txd, + uart0_rxd => uart0_rxd + ); + + nodram: if not USE_LITEDRAM generate + signal div2 : std_ulogic := '0'; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n and gsrn, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + process(ext_clk) + begin + if rising_edge(ext_clk) then + div2 <= not div2; + end if; + end process; + + system_clk <= div2; + system_clk_locked <= '1'; + + end generate; + + led5_r_n <= '0'; + led5_g_n <= '1'; + led5_b_n <= '1'; + led6_r_n <= '1'; + led6_g_n <= '0'; + led6_b_n <= '1'; + led7_r_n <= '1'; + led7_g_n <= '1'; + led7_b_n <= '0'; + led8_r_n <= '1'; + led8_g_n <= '1'; + led8_b_n <= '1'; + +end architecture behaviour; diff --git a/openocd/ecpix-5.cfg b/openocd/ecpix-5.cfg new file mode 100644 index 0000000..bab2db8 --- /dev/null +++ b/openocd/ecpix-5.cfg @@ -0,0 +1,6 @@ +adapter driver ftdi +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 +ftdi layout_init 0xfff8 0xfffb +reset_config none +adapter speed 25000