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microwatt
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core: Store hash key SPRs in the SPR RAM

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This moves HASHKEYR and HASHPKEYR to the SPR RAM that also stores
things such as SRR0/1, LR and CTR.  For hashst[p] and hashchk[p]
instructions, execute1 reads the relevant key register from the RAM
and sends it to loadstore1.  This saves several LUTs.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
pull/438/head
Paul Mackerras 2 months ago
parent 2c7d1e5d9c
commit 1395bde3cc
5 changed files with 26 additions and 27 deletions
Show Stats Download Patch File Download Diff File

7
common.vhdl
Unescape Escape View File

@ -141,6 +141,7 @@ package common is
constant RAMSPR_HSPRG0 : ramspr_index := to_unsigned(4,3);
constant RAMSPR_LR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_CTR
constant RAMSPR_TAR : ramspr_index := to_unsigned(6,3);
constant RAMSPR_VRSAVE : ramspr_index := to_unsigned(7,3);
-- Odd half:
constant RAMSPR_SRR1 : ramspr_index := to_unsigned(0,3);
constant RAMSPR_HSRR1 : ramspr_index := to_unsigned(1,3);
@ -148,7 +149,8 @@ package common is
constant RAMSPR_SPRG3 : ramspr_index := to_unsigned(3,3);
constant RAMSPR_HSPRG1 : ramspr_index := to_unsigned(4,3);
constant RAMSPR_CTR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_LR
constant RAMSPR_VRSAVE : ramspr_index := to_unsigned(6,3);
constant RAMSPR_HASHKY : ramspr_index := to_unsigned(6,3);
constant RAMSPR_HASHPK : ramspr_index := to_unsigned(7,3);

type ram_spr_info is record
index : ramspr_index;
@ -601,6 +603,7 @@ package common is
second : std_ulogic;
e2stall : std_ulogic;
msr : std_ulogic_vector(63 downto 0);
hashkey : std_ulogic_vector(63 downto 0);
end record;
constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type :=
(valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
@ -613,7 +616,7 @@ package common is
length => (others => '0'),
mode_32bit => '0', is_32bit => '0', prefixed => '0',
repeat => '0', second => '0', e2stall => '0',
msr => (others => '0'));
msr => (others => '0'), hashkey => (others => '0'));

type Loadstore1ToExecute1Type is record
busy : std_ulogic;

7
decode1.vhdl
Unescape Escape View File

@ -436,8 +436,13 @@ architecture behaviour of decode1 is
ret.isodd := '1';
when SPR_VRSAVE =>
ret.index := RAMSPR_VRSAVE;
ret.isodd := '1';
ret.is32b := '1';
when SPR_HASHKEYR =>
ret.index := RAMSPR_HASHKY;
ret.isodd := '1';
when SPR_HASHPKEYR =>
ret.index := RAMSPR_HASHPK;
ret.isodd := '1';
when others =>
ret.valid := '0';
end case;

17
decode2.vhdl
Unescape Escape View File

@ -518,8 +518,7 @@ begin
when SPR_XER =>
v.input_ov := '1';
when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PTCR |
SPR_DAWR0 | SPR_DAWR1 | SPR_DAWRX0 | SPR_DAWRX1 |
SPR_HASHKEYR | SPR_HASHPKEYR =>
SPR_DAWR0 | SPR_DAWR1 | SPR_DAWRX0 | SPR_DAWRX1 =>
unit := LDST;
when SPR_TAR =>
v.e.uses_tar := '1';
@ -542,8 +541,7 @@ begin
v.e.output_xer := '1';
v.output_ov := '1';
when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PTCR |
SPR_DAWR0 | SPR_DAWR1 | SPR_DAWRX0 | SPR_DAWRX1 |
SPR_HASHKEYR | SPR_HASHPKEYR =>
SPR_DAWR0 | SPR_DAWR1 | SPR_DAWRX0 | SPR_DAWRX1 =>
unit := LDST;
if d_in.valid = '1' then
v.sgl_pipe := '1';
@ -639,6 +637,17 @@ begin
v.e.ramspr_odd_rdaddr := RAMSPR_HSRR1;
end if;
sprs_busy := '1';
when OP_LOAD | OP_STORE =>
if d_in.decode.is_signed = '1' then
-- hash{st,chk}[p]
if d_in.insn(7) = '1' then
v.e.ramspr_odd_rdaddr := RAMSPR_HASHKY;
else
v.e.ramspr_odd_rdaddr := RAMSPR_HASHPK;
end if;
v.e.ramspr_rd_odd := '1';
sprs_busy := '1';
end if;
when others =>
end case;
v.read_rspr := sprs_busy and d_in.valid;

1
execute1.vhdl
Unescape Escape View File

@ -1849,6 +1849,7 @@ begin
lv.repeat := e_in.repeat;
lv.second := e_in.second;
lv.e2stall := fp_in.f2stall;
lv.hashkey := ramspr_odd;

-- Outputs to FPU
fv.op := e_in.insn_type;

21
loadstore1.vhdl
Unescape Escape View File

@ -171,8 +171,6 @@ architecture behave of loadstore1 is
dawrx : dawrx_array_t;
dawr_uplim : dawr_array_t;
dawr_upd : std_ulogic;
hashkeyr : std_ulogic_vector(63 downto 0);
hashpkeyr : std_ulogic_vector(63 downto 0);
end record;

signal req_in : request_t;
@ -388,8 +386,6 @@ begin
r3.dawr_uplim(i) <= (others => '0');
end loop;
r3.dawr_upd <= '0';
r3.hashkeyr <= (others => '0');
r3.hashpkeyr <= (others => '0');
flushing <= '0';
else
r1 <= r1in;
@ -534,11 +530,7 @@ begin
hv.z0 := 31x"7D12B0E6"; -- 0xFA2561CD >> 1
ra := l_in.addr1;
rb := l_in.data;
if l_in.insn(7) = '1' then
key := r3.hashkeyr; -- hashst/hashchk
else
key := r3.hashpkeyr; -- hashstp/hashchkp
end if;
key := l_in.hashkey;
for lane in 0 to 3 loop
j := lane * 16;
k := (3 - lane) * 16;
@ -597,9 +589,6 @@ begin
if sprn(8 downto 7) = "01" then
-- debug registers DAWR[X][01]
v.sprsel := "01" & sprn(3) & sprn(0);
elsif sprn(2) = '1' then
-- HASH[P]KEYR
v.sprsel := "000" & sprn(0);
elsif sprn(1) = '1' then
-- DSISR and DAR
v.sprsel := "001" & sprn(0);
@ -903,10 +892,6 @@ begin
sprval := 48x"0" & r3.dawrx(0);
when "111" =>
sprval := 48x"0" & r3.dawrx(1);
when "000" =>
sprval := r3.hashkeyr;
when "001" =>
sprval := r3.hashpkeyr;
when "010" =>
sprval := x"00000000" & r3.dsisr;
when "011" =>
@ -1149,10 +1134,6 @@ begin
v.dsisr := r2.req.store_data(31 downto 0);
when "0011" =>
v.dar := r2.req.store_data;
when "0000" =>
v.hashkeyr := r2.req.store_data;
when "0001" =>
v.hashpkeyr := r2.req.store_data;
when others =>
end case;
end if;

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