diff --git a/countbits.vhdl b/countbits.vhdl index 87417a9..4f40134 100644 --- a/countbits.vhdl +++ b/countbits.vhdl @@ -50,9 +50,11 @@ architecture behaviour of bit_counter is begin countzero_r: process(clk) begin - if rising_edge(clk) and stall = '0' then - inp_r <= inp; - sum_r <= sum; + if rising_edge(clk) then + if stall = '0' then + inp_r <= inp; + sum_r <= sum; + end if; end if; end process; diff --git a/fetch1.vhdl b/fetch1.vhdl index f0b8360..96c16fb 100644 --- a/fetch1.vhdl +++ b/fetch1.vhdl @@ -152,7 +152,7 @@ begin attribute ram_style of btc_memory : signal is "block"; signal btc_valids : std_ulogic_vector(BTC_SIZE - 1 downto 0); - attribute ram_style of btc_valids : signal is "distributed"; + -- attribute ram_style of btc_valids : signal is "distributed"; signal btc_wr : std_ulogic; signal btc_wr_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0); diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 622b24d..dd35252 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -171,15 +171,15 @@ set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_po set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io33 }]; set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io34 }]; set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io35 }]; -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io36 }]; -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io37 }]; -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io38 }]; -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io39 }]; -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io40 }]; -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io41 }]; -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io42 }]; # A -set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io43 }]; # SCL -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io44 }]; # SDA +#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io36 }]; +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io37 }]; +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io38 }]; +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io39 }]; +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io40 }]; +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io41 }]; +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io42 }]; # A +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io43 }]; # SCL +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io44 }]; # SDA #set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { shield_rst }]; #set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { spi_hdr_ss }]; diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index dc5a0fe..508202c 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -206,6 +206,9 @@ architecture behaviour of toplevel is signal ddram_clk_p_vec : std_logic_vector(0 downto 0); signal ddram_clk_n_vec : std_logic_vector(0 downto 0); + signal uart1_rxd : std_ulogic; + signal uart1_txd : std_ulogic; + -- Fixup various memory sizes based on generics function get_bram_size return natural is begin @@ -266,8 +269,8 @@ begin uart0_rxd => uart_main_rx, -- UART1 signals - --uart1_txd => uart_pmod_tx, - --uart1_rxd => uart_pmod_rx, + uart1_txd => uart1_txd, + uart1_rxd => uart1_rxd, -- SPI signals spi_flash_sck => spi_sck, @@ -302,7 +305,7 @@ begin wishbone_dma_out => wb_sddma_out ); - --uart_pmod_rts_n <= '0'; + uart1_txd <= '1'; -- SPI Flash -- @@ -415,8 +418,9 @@ begin ); -- Generate SoC reset - soc_rst_gen: process(system_clk) + soc_rst_gen: process(system_clk, ext_rst_n) begin + -- XXX why does this need to be an asynchronous reset? if ext_rst_n = '0' then soc_rst <= '1'; elsif rising_edge(system_clk) then diff --git a/icache.vhdl b/icache.vhdl index 8dfbd86..7b0ae59 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -403,12 +403,12 @@ begin variable snoop_addr : real_addr_t; variable next_raddr : real_addr_t; begin - replace_way := to_unsigned(0, WAY_BITS); - if NUM_WAYS > 1 then - -- Get victim way from plru - replace_way := plru_victim; - end if; if rising_edge(clk) then + replace_way := to_unsigned(0, WAY_BITS); + if NUM_WAYS > 1 then + -- Get victim way from plru + replace_way := plru_victim; + end if; -- Read tags using NIA for next cycle if flush_in = '1' or i_in.req = '0' or (stall_in = '0' and stall_out = '0') then next_raddr := i_in.next_rpn & i_in.next_nia(MIN_LG_PGSZ - 1 downto 0); @@ -649,6 +649,7 @@ begin begin if rising_edge(clk) then ev.icache_miss <= '0'; + ev.itlb_miss_resolved <= '0'; r.recv_valid <= '0'; -- On reset, clear all valid bits to force misses if rst = '1' then diff --git a/microwatt.core b/microwatt.core index 3e65325..508b346 100644 --- a/microwatt.core +++ b/microwatt.core @@ -62,14 +62,13 @@ filesets: - fpga/pp_soc_uart.vhd - fpga/pp_utilities.vhd - fpga/firmware.hex : {copyto : firmware.hex, file_type : user} + - nonrandom.vhdl file_type : vhdlSource-2008 xilinx_specific: files: - xilinx-mult.vhdl : {file_type : vhdlSource-2008} - xilinx-mult-32s.vhdl : {file_type : vhdlSource-2008} - - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008} - - fpga/fpga-random.xdc : {file_type : xdc} debug_xilinx: files: diff --git a/xics.vhdl b/xics.vhdl index d4adc1e..62faf77 100644 --- a/xics.vhdl +++ b/xics.vhdl @@ -386,15 +386,14 @@ begin reg_write: process(clk) variable be_in : std_ulogic_vector(31 downto 0); begin - -- Byteswapped input - be_in := bswap(wb_in.dat); - if rising_edge(clk) then if rst = '1' then for i in 0 to SRC_NUM - 1 loop xives(i) <= (pri => pri_masked); end loop; elsif wb_valid = '1' and wb_in.we = '1' then + -- Byteswapped input + be_in := bswap(wb_in.dat); if reg_is_xive then -- TODO: When adding support for other bits, make sure to -- properly implement wb_in.sel to allow partial writes. diff --git a/xilinx-mult-32s.vhdl b/xilinx-mult-32s.vhdl index cacc22d..fc2bf76 100644 --- a/xilinx-mult-32s.vhdl +++ b/xilinx-mult-32s.vhdl @@ -286,9 +286,11 @@ begin process(clk) begin - if rising_edge(clk) and stall = '0' then - m_out.valid <= m_in.valid; - product_lo <= m01_p(5 downto 0) & m00_p(16 downto 0); + if rising_edge(clk) then + if stall = '0' then + m_out.valid <= m_in.valid; + product_lo <= m01_p(5 downto 0) & m00_p(16 downto 0); + end if; end if; end process;