From 04b0c901e0c2db63736a3ae9c0692ab615f54f86 Mon Sep 17 00:00:00 2001
From: Paul Mackerras <paulus@ozlabs.org>
Date: Sat, 19 Apr 2025 18:12:03 +1000
Subject: [PATCH] dcache: Simplify expression for read enable of cache RAM

The path from execute_to_loadstore.valid through to the read enable of
the cache RAM has showed up as a critical path.  In fact we can
simplify this by always asserting read enable when not stalled.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 dcache.vhdl | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/dcache.vhdl b/dcache.vhdl
index 86cbc2c..a0fec63 100644
--- a/dcache.vhdl
+++ b/dcache.vhdl
@@ -1158,12 +1158,11 @@ begin
         -- If we're stalling then we need to keep reading the last
         -- row requested.
         if r0_stall = '0' then
+            early_rd_valid <= '1';
             if m_in.valid = '1' then
                 early_req_row <= get_row(m_in.addr);
-                early_rd_valid <= '1';
             else
                 early_req_row <= get_row(d_in.addr);
-                early_rd_valid <= d_in.valid and d_in.load;
             end if;
         else
             early_req_row <= req_row;