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69 lines
1.4 KiB
INI
69 lines
1.4 KiB
INI
4 years ago
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# This file is the same sa xilinx-xc7.cfg, except we use
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# verify_image instead of verify_bank
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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adapter_khz 25000
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source [find cpld/xilinx-xc7.cfg]
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# From jtagspi.cfg with modification to support
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# specifying file type
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set _USER1 0x02
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if { [info exists JTAGSPI_IR] } {
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set _JTAGSPI_IR $JTAGSPI_IR
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} else {
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set _JTAGSPI_IR $_USER1
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}
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if { [info exists DR_LENGTH] } {
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set _DR_LENGTH $DR_LENGTH
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} else {
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set _DR_LENGTH 1
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}
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if { [info exists TARGETNAME] } {
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set _TARGETNAME $TARGETNAME
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} else {
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set _TARGETNAME $_CHIPNAME.proxy
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}
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if { [info exists FLASHNAME] } {
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set _FLASHNAME $FLASHNAME
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} else {
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set _FLASHNAME $_CHIPNAME.spi
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}
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target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
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flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
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proc jtagspi_init {chain_id proxy_bit} {
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# load proxy bitstream $proxy_bit and probe spi flash
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global _FLASHNAME
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pld load $chain_id $proxy_bit
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reset halt
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flash probe $_FLASHNAME
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}
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proc jtagspi_program {bin addr {type ""} } {
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# write and verify binary file $bin at offset $addr
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global _FLASHNAME
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if { $type eq "" } {
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flash write_image erase $bin $addr
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flash verify_image $bin $addr
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} else {
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flash write_image erase $bin $addr $type
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flash verify_image $bin $addr $type
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}
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}
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# end jtagspi.cfg
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proc fpga_program {} {
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global _CHIPNAME
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xc7_program $_CHIPNAME.tap
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}
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