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microwatt/decode_types.vhdl

441 lines
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VHDL
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Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
library ieee;
use ieee.std_logic_1164.all;
package decode_types is
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
type insn_type_t is (OP_ILLEGAL, OP_NOP, OP_ADD,
core: Do addpcis using the main adder (#189) By adding logic to decode2 to be able to send the instruction address down the A input, and making CONST_DX_HI (renamed to CONST_DXHI4) add 4 to the immediate value (easy since the bottom 16 bits were zero), we can do addpcis using the main adder. This reduces the width of the result mux and frees up one value in insn_type_t, since we can now use OP_ADD for addpcis. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
OP_AND, OP_ATTN, OP_B, OP_BC, OP_BCREG,
FPU: Simplify IDLE state code Do more decoding of the instruction ahead of the IDLE state processing so that the IDLE state code becomes much simpler. To make the decoding easier, we now use four insn_type_t codes for floating-point operations rather than two. This also rearranges the insn_type_t values a little to get the 4 FP opcode values to differ only in the bottom 2 bits, and put OP_DIV, OP_DIVE and OP_MOD next to them. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
OP_BCD, OP_BPERM, OP_CMP, OP_CMPB, OP_CMPEQB, OP_CMPRB,
Rename OP_MCRF to OP_CROP and trim insn_type_t OP_MCRF covers the CR logical ops as well as mcrf since commit c05441bf4793 ("Implement CRNOR and friends"), so this renames OP_MCRF to OP_CROP. The OP_* values for the individual CR logical ops (OP_CRAND, etc.) are not used, so remove them from insn_type_t. No functional change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
OP_CNTZ, OP_CROP,
OP_DARN, OP_DCBF, OP_DCBST, OP_DCBT, OP_DCBTST,
FPU: Simplify IDLE state code Do more decoding of the instruction ahead of the IDLE state processing so that the IDLE state code becomes much simpler. To make the decoding easier, we now use four insn_type_t codes for floating-point operations rather than two. This also rearranges the insn_type_t values a little to get the 4 FP opcode values to differ only in the bottom 2 bits, and put OP_DIV, OP_DIVE and OP_MOD next to them. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
OP_DCBZ, OP_ICBI, OP_ICBT,
OP_FP_CMP, OP_FP_ARITH, OP_FP_MOVE, OP_FP_MISC,
OP_DIV, OP_DIVE, OP_MOD,
OP_EXTS, OP_EXTSWSLI,
OP_ISEL, OP_ISYNC,
core: Implement the maddhd, maddhdu and maddld instructions These instructions use major opcode 4 and have a third GPR input operand, so we need a decode table for major opcode 4 and some plumbing to get the RC register operand read. The multiply-add instructions use the same insn_type_t values as the regular multiply instructions, and we distinguish in execute1 by looking at the major opcode. This turns out to be convenient because we don't have to add any cases in the code that handles the output of the multiplier, and it frees up some insn_type_t values. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
OP_LOAD, OP_STORE,
FPU: Simplify IDLE state code Do more decoding of the instruction ahead of the IDLE state processing so that the IDLE state code becomes much simpler. To make the decoding easier, we now use four insn_type_t codes for floating-point operations rather than two. This also rearranges the insn_type_t values a little to get the 4 FP opcode values to differ only in the bottom 2 bits, and put OP_DIV, OP_DIVE and OP_MOD next to them. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
OP_MCRXRX, OP_MFCR, OP_MFMSR, OP_MFSPR,
Add sc, illegal and decrementer exceptions and some supervisor state This adds the following exceptions: - 0x700 program check (for illegal instructions) - 0x900 decrementer - 0xc00 system call This also adds some supervisor state: - decremeter - msr (SPRG0/1 and SRR0/1 already exist as fast SPRs) It also adds some supporting instructions: - rfid - mtmsrd - mfmsr - sc MSR state is added but only EE is used in this patch set. Other bits are read/written but are not used at all. This adds a 2 stage state machine to execute1.vhdl. This state machine allows fast SPRS SRR0/1 to be written in different cycles. This state machine can be extended later to add DAR and DSISR SPR writing for more complex exceptions like page faults. Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
OP_MTCRF, OP_MTMSRD, OP_MTSPR, OP_MUL_L64,
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
OP_MUL_H64, OP_MUL_H32, OP_OR,
Add sc, illegal and decrementer exceptions and some supervisor state This adds the following exceptions: - 0x700 program check (for illegal instructions) - 0x900 decrementer - 0xc00 system call This also adds some supervisor state: - decremeter - msr (SPRG0/1 and SRR0/1 already exist as fast SPRs) It also adds some supporting instructions: - rfid - mtmsrd - mfmsr - sc MSR state is added but only EE is used in this patch set. Other bits are read/written but are not used at all. This adds a 2 stage state machine to execute1.vhdl. This state machine allows fast SPRS SRR0/1 to be written in different cycles. This state machine can be extended later to add DAR and DSISR SPR writing for more complex exceptions like page faults. Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
OP_POPCNT, OP_PRTY, OP_RFID,
OP_RLC, OP_RLCL, OP_RLCR, OP_SC, OP_SETB,
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
OP_SHL, OP_SHR,
dcache: Implement data TLB This adds a TLB to dcache, providing the ability to translate addresses for loads and stores. No protection mechanism has been implemented yet. The MSR_DR bit controls whether addresses are translated through the TLB. The TLB is a fixed-pagesize, set-associative cache. Currently the page size is 4kB and the TLB is 2-way set associative with 64 entries per set. This implements the tlbie instruction. RB bits 10 and 11 control whether the whole TLB is invalidated (if either bit is 1) or just a single entry corresponding to the effective page number in bits 12-63 of RB. As an extension until we get a hardware page table walk, a tlbie instruction with RB bits 9-11 set to 001 will load an entry into the TLB. The TLB entry value is in RS in the format of a radix PTE. Currently there is no proper handling of TLB misses. The load or store will not be performed but no interrupt is generated. In order to make timing at 100MHz on the Arty A7-100, we compare the real address from each way of the TLB with the tag from each way of the cache in parallel (requiring # TLB ways * # cache ways comparators). Then the result is selected based on which way hit in the TLB. That avoids a timing path going through the TLB EA comparators, the multiplexer that selects the RA, and the cache tag comparators. The hack where addresses of the form 0xc------- are marked as cache-inhibited is kept for now but restricted to real-mode accesses. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
OP_SYNC, OP_TLBIE, OP_TRAP,
Add TLB to icache This adds a direct-mapped TLB to the icache, with 64 entries by default. Execute1 now sends a "virt_mode" signal from MSR[IR] to fetch1 along with redirects to indicate whether instruction addresses should be translated through the TLB, and fetch1 sends that on to icache. Similarly a "priv_mode" signal is sent to indicate the privilege mode for instruction fetches. This means that changes to MSR[IR] or MSR[PR] don't take effect until the next redirect, meaning an isync, rfid, branch, etc. The icache uses a hash of the effective address (i.e. next instruction address) to index the TLB. The hash is an XOR of three fields of the address; with a 64-entry TLB, the fields are bits 12--17, 18--23 and 24--29 of the address. TLB invalidations simply invalidate the indexed TLB entry without checking the contents. If the icache detects a TLB miss with virt_mode=1, it will send a fetch_failed indication through fetch2 to decode1, which will turn it into a special OP_FETCH_FAILED opcode with unit=LDST. That will get sent down to loadstore1 which will currently just raise a Instruction Storage Interrupt (0x400) exception. One bit in the PTE obtained from the TLB is used to check whether an instruction access is allowed -- the privilege bit (bit 3). If bit 3 is 1 and priv_mode=0, then a fetch_failed indication is sent down to fetch2 and to decode1, which generates an OP_FETCH_FAILED. Any PTEs with PTE bit 0 (EAA[3]) clear or bit 8 (R) clear should not be put into the iTLB since such PTEs would not allow execution by any context. Tlbie operations get sent from mmu to icache over a new connection. Unfortunately the privileged instruction tests are broken for now. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
OP_XOR,
FPU: Simplify IDLE state code Do more decoding of the instruction ahead of the IDLE state processing so that the IDLE state code becomes much simpler. To make the decoding easier, we now use four insn_type_t codes for floating-point operations rather than two. This also rearranges the insn_type_t values a little to get the 4 FP opcode values to differ only in the bottom 2 bits, and put OP_DIV, OP_DIVE and OP_MOD next to them. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
OP_ADDG6S,
Add TLB to icache This adds a direct-mapped TLB to the icache, with 64 entries by default. Execute1 now sends a "virt_mode" signal from MSR[IR] to fetch1 along with redirects to indicate whether instruction addresses should be translated through the TLB, and fetch1 sends that on to icache. Similarly a "priv_mode" signal is sent to indicate the privilege mode for instruction fetches. This means that changes to MSR[IR] or MSR[PR] don't take effect until the next redirect, meaning an isync, rfid, branch, etc. The icache uses a hash of the effective address (i.e. next instruction address) to index the TLB. The hash is an XOR of three fields of the address; with a 64-entry TLB, the fields are bits 12--17, 18--23 and 24--29 of the address. TLB invalidations simply invalidate the indexed TLB entry without checking the contents. If the icache detects a TLB miss with virt_mode=1, it will send a fetch_failed indication through fetch2 to decode1, which will turn it into a special OP_FETCH_FAILED opcode with unit=LDST. That will get sent down to loadstore1 which will currently just raise a Instruction Storage Interrupt (0x400) exception. One bit in the PTE obtained from the TLB is used to check whether an instruction access is allowed -- the privilege bit (bit 3). If bit 3 is 1 and priv_mode=0, then a fetch_failed indication is sent down to fetch2 and to decode1, which generates an OP_FETCH_FAILED. Any PTEs with PTE bit 0 (EAA[3]) clear or bit 8 (R) clear should not be put into the iTLB since such PTEs would not allow execution by any context. Tlbie operations get sent from mmu to icache over a new connection. Unfortunately the privileged instruction tests are broken for now. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
OP_FETCH_FAILED
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
);
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
-- The following list is ordered in such a way that we can know some
-- things about which registers are accessed by an instruction by its place
-- in the list. In other words we can decide whether an instruction
-- accesses FPRs and whether it has an RB operand by doing simple
-- comparisons of the insn_code for the instruction with a few constants.
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
type insn_code is (
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
-- The following instructions don't have an RB operand or access FPRs
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_illegal, -- 0
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fetch_fail,
INSN_addi,
INSN_addic,
INSN_addic_dot,
INSN_addis,
INSN_addme,
INSN_addpcis,
INSN_addze,
INSN_andi_dot,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_andis_dot, -- 10
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_attn,
INSN_b,
INSN_bc,
INSN_bcctr,
INSN_bclr,
INSN_bctar,
INSN_cbcdtd,
INSN_cdtbcd,
INSN_cmpi,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cmpli, -- 20
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cntlzw,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cntlzd,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cnttzw,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cnttzd,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_crand,
INSN_crandc,
INSN_creqv,
INSN_crnand,
INSN_crnor,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cror, -- 30
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_crorc,
INSN_crxor,
INSN_darn,
INSN_eieio,
INSN_extsb,
INSN_extsh,
INSN_extsw,
INSN_extswsli,
INSN_isync,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lbz, -- 40
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lbzu,
INSN_ld,
INSN_ldu,
INSN_lha,
INSN_lhau,
INSN_lhz,
INSN_lhzu,
INSN_lwa,
INSN_lwz,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lwzu, -- 50
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_mcrf,
INSN_mcrfs,
INSN_mcrxrx,
INSN_mfcr,
INSN_mfmsr,
INSN_mfspr,
INSN_mtcrf,
INSN_mtfsb,
INSN_mtfsfi,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_mtmsr, -- 60
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_mtmsrd,
INSN_mtspr,
INSN_mulli,
INSN_neg,
INSN_nop,
INSN_ori,
INSN_oris,
INSN_popcntb,
INSN_popcntw,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_popcntd, -- 70
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_prtyw,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_prtyd,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_rfid,
INSN_rldic,
INSN_rldicl,
INSN_rldicr,
INSN_rldimi,
INSN_rlwimi,
INSN_rlwinm,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_sc, -- 80
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_setb,
INSN_slbia,
INSN_sradi,
INSN_srawi,
INSN_stb,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stbu,
INSN_std,
INSN_stdu,
INSN_sth,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_sthu, -- 90
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stw,
INSN_stwu,
INSN_subfic,
INSN_subfme,
INSN_subfze,
INSN_sync,
INSN_tdi,
INSN_tlbsync,
INSN_twi,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_wait, -- 100
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_xori,
INSN_xoris,
-- pad to 112 to simplify comparison logic
INSN_103,
INSN_104, INSN_105, INSN_106, INSN_107,
INSN_108, INSN_109, INSN_110, INSN_111,
-- The following instructions have an RB operand but don't access FPRs
INSN_add,
INSN_addc,
INSN_adde,
INSN_addex,
INSN_addg6s,
INSN_and,
INSN_andc,
INSN_bperm,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cmp, -- 120
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_cmpb,
INSN_cmpeqb,
INSN_cmpl,
INSN_cmprb,
INSN_dcbf,
INSN_dcbst,
INSN_dcbt,
INSN_dcbtst,
INSN_dcbz,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_divd, -- 130
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_divdu,
INSN_divde,
INSN_divdeu,
INSN_divw,
INSN_divwu,
INSN_divwe,
INSN_divweu,
INSN_eqv,
INSN_icbi,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_icbt, -- 140
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_isel,
INSN_lbarx,
INSN_lbzcix,
INSN_lbzux,
INSN_lbzx,
INSN_ldarx,
INSN_ldbrx,
INSN_ldcix,
INSN_ldx,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_ldux, -- 150
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lharx,
INSN_lhax,
INSN_lhaux,
INSN_lhbrx,
INSN_lhzcix,
INSN_lhzx,
INSN_lhzux,
INSN_lwarx,
INSN_lwax,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lwaux, -- 160
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lwbrx,
INSN_lwzcix,
INSN_lwzx,
INSN_lwzux,
INSN_modsd,
INSN_modsw,
INSN_moduw,
INSN_modud,
INSN_mulhw,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_mulhwu, -- 170
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_mulhd,
INSN_mulhdu,
INSN_mullw,
INSN_mulld,
INSN_nand,
INSN_nor,
INSN_or,
INSN_orc,
INSN_rldcl,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_rldcr, -- 180
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_rlwnm,
INSN_slw,
INSN_sld,
INSN_sraw,
INSN_srad,
INSN_srw,
INSN_srd,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stbcix,
INSN_stbcx,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stbx, -- 190
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stbux,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stdbrx,
INSN_stdcix,
INSN_stdcx,
INSN_stdx,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stdux,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_sthbrx,
INSN_sthcix,
INSN_sthcx,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_sthx, -- 200
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_sthux,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stwbrx,
INSN_stwcix,
INSN_stwcx,
INSN_stwx,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stwux,
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_subf,
INSN_subfc,
INSN_subfe,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_td, -- 210
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_tlbie,
INSN_tlbiel,
INSN_tw,
INSN_xor,
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
-- pad to 224 to simplify comparison logic
INSN_215,
INSN_216, INSN_217, INSN_218, INSN_219,
INSN_220, INSN_221, INSN_222, INSN_223,
-- The following instructions have a third input addressed by RC
INSN_maddld,
INSN_maddhd,
INSN_maddhdu,
-- pad to 256 to simplify comparison logic
INSN_227,
INSN_228, INSN_229, INSN_230, INSN_231,
INSN_232, INSN_233, INSN_234, INSN_235,
INSN_236, INSN_237, INSN_238, INSN_239,
INSN_240, INSN_241, INSN_242, INSN_243,
INSN_244, INSN_245, INSN_246, INSN_247,
INSN_248, INSN_249, INSN_250, INSN_251,
INSN_252, INSN_253, INSN_254, INSN_255,
-- The following instructions access floating-point registers
-- These ones have an FRS operand, but RA/RB are GPRs
INSN_stfd,
INSN_stfdu,
INSN_stfs,
INSN_stfsu,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stfdux, -- 260
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_stfdx,
INSN_stfiwx,
INSN_stfsux,
INSN_stfsx,
-- These ones don't actually have an FRS operand (rather an FRT destination)
-- but are here so that all FP instructions are >= INST_first_frs.
INSN_lfd,
INSN_lfdu,
INSN_lfs,
INSN_lfsu,
INSN_lfdx,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lfdux, -- 270
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_lfiwax,
INSN_lfiwzx,
INSN_lfsx,
INSN_lfsux,
INSN_275, -- padding
-- The following instructions access FRA and/or FRB operands
INSN_fabs,
INSN_fadd,
INSN_fadds,
INSN_fcfid,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fcfids, -- 280
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fcfidu,
INSN_fcfidus,
INSN_fcmpo,
INSN_fcmpu,
INSN_fcpsgn,
INSN_fctid,
INSN_fctidz,
INSN_fctidu,
INSN_fctiduz,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fctiw, -- 290
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fctiwz,
INSN_fctiwu,
INSN_fctiwuz,
INSN_fdiv,
INSN_fdivs,
INSN_fmr,
INSN_fmrgew,
INSN_fmrgow,
INSN_fnabs,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fneg, -- 300
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fre,
INSN_fres,
INSN_frim,
INSN_frin,
INSN_frip,
INSN_friz,
INSN_frsp,
INSN_frsqrte,
INSN_frsqrtes,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fsqrt, -- 310
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fsqrts,
INSN_fsub,
INSN_fsubs,
INSN_ftdiv,
INSN_ftsqrt,
INSN_mffs,
INSN_mtfsf,
-- pad to 320
INSN_318, INSN_319,
-- The following instructions access FRA, FRB (possibly) and FRC operands
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fmul, -- 320
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fmuls,
INSN_fmadd,
INSN_fmadds,
INSN_fmsub,
INSN_fmsubs,
INSN_fnmadd,
INSN_fnmadds,
INSN_fnmsub,
INSN_fnmsubs,
predecode: Add more comments to row_predecode_rom and insn_code values This adds comments to row_predecode_rom to aid understanding how the columns in the second half of the table are allocated to different primary opcodes, and to the insn_code values to assist in locating the code with a given numeric value. No code change. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
INSN_fsel -- 330
decode1: Split instruction decoding into two steps This reduces the block RAM requirements for instruction decoding by splitting it into two steps. The first, in a new pipeline stage called decode0 (implemented by code in decode1.vhdl) maps the instruction to a 9-bit instruction code using major and row decode ROMs. The second maps the 9-bit code to the final decode_rom_t (about 44 bits wide). Branch prediction done in decode is now done in decode0 rather than decode1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
);
decode1: Divide insn_code values into ranges to indicate register usage This lets us compute r_out.reg_*_addr and r_out.read_2_enable values without needing access to the primary opcode value. We also have that non-FP instructions are < 256. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
constant INSN_first_rb : insn_code := INSN_add;
constant INSN_first_rc : insn_code := INSN_maddld;
constant INSN_first_frs : insn_code := INSN_stfd;
constant INSN_first_frab : insn_code := INSN_fabs;
constant INSN_first_frabc : insn_code := INSN_fmul;
Finish off taking SPRs out of register file With this, the register file now contains 64 entries, for 32 GPRs and 32 FPRs, rather than the 128 it had previously. Several things get simplified - decode1 no longer has to work out the ispr{1,2,o} values, decode_input_reg_{a,b,c} no longer have the t = SPR case, etc. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
type input_reg_a_t is (NONE, RA, RA_OR_ZERO, CIA, FRA);
core: Do addpcis using the main adder (#189) By adding logic to decode2 to be able to send the instruction address down the A input, and making CONST_DX_HI (renamed to CONST_DXHI4) add 4 to the immediate value (easy since the bottom 16 bits were zero), we can do addpcis using the main adder. This reduces the width of the result mux and frees up one value in insn_type_t, since we can now use OP_ADD for addpcis. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
Finish off taking SPRs out of register file With this, the register file now contains 64 entries, for 32 GPRs and 32 FPRs, rather than the 128 it had previously. Several things get simplified - decode1 no longer has to work out the ispr{1,2,o} values, decode_input_reg_{a,b,c} no longer have the t = SPR case, etc. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, FRB);
FPU: Implement fmul[s] This implements the fmul and fmuls instructions. For fmul[s] with denormalized operands we normalize the inputs before doing the multiplication, to eliminate the need for doing count-leading-zeroes on P. This adds 3 or 5 cycles to the execution time when one or both operands are denormalized. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
type input_reg_c_t is (NONE, RS, RCR, FRC, FRS);
Finish off taking SPRs out of register file With this, the register file now contains 64 entries, for 32 GPRs and 32 FPRs, rather than the 128 it had previously. Several things get simplified - decode1 no longer has to work out the ispr{1,2,o} values, decode_input_reg_{a,b,c} no longer have the t = SPR case, etc. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
type output_reg_a_t is (NONE, RT, RA, FRT);
Eliminate use of primary opcode outside of decode1 This changes code that previously looked at the primary opcode (bits 26 to 31) of the instruction to use other methods, in places other than in stage0 of decode1. * Extend rc_t to have a new value, RCOE, indicating that the instruction has both Rc and OE bits. * Decode2 now tells execute1 whether the instruction has a third operand, used for distinguishing between multiply and multiply-add instructions. * The invert_a field of the decode ROM is overloaded for load/store instructions to indicate cache-inhibited loads and stores. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 years ago
type rc_t is (NONE, ONE, RC, RCOE);
core: Implement the addex instruction The addex instruction is like adde but uses the XER[OV] bit for the carry in and out rather than XER[CA]. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
type carry_in_t is (ZERO, CA, OV, ONE);
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
constant SH_OFFSET : integer := 0;
constant MB_OFFSET : integer := 1;
constant ME_OFFSET : integer := 1;
constant SH32_OFFSET : integer := 0;
constant MB32_OFFSET : integer := 1;
constant ME32_OFFSET : integer := 2;
constant FXM_OFFSET : integer := 0;
constant BO_OFFSET : integer := 0;
constant BI_OFFSET : integer := 1;
constant BH_OFFSET : integer := 2;
constant BF_OFFSET : integer := 0;
constant L_OFFSET : integer := 1;
constant TOO_OFFSET : integer := 0;
core: Add framework for an FPU This adds the skeleton of a floating-point unit and implements the mffs and mtfsf instructions. Execute1 sends FP instructions to the FPU and receives busy, exception, FP interrupt and illegal interrupt signals from it. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
type unit_t is (NONE, ALU, LDST, FPU);
decode: Add a facility field to the instruction decode tables This makes it simpler to work out when to deliver a FPU unavailable interrupt. This also means we can get rid of the OP_FPLOAD and OP_FPSTORE insn_type values. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
type facility_t is (NONE, FPU);
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
type length_t is (NONE, is1B, is2B, is4B, is8B);
core: Implement quadword loads and stores This implements the lq, stq, lqarx and stqcx. instructions. These instructions all access two consecutive GPRs; for example the "lq %r6,0(%r3)" instruction will load the doubleword at the address in R3 into R7 and the doubleword at address R3 + 8 into R6. To cope with having two GPR sources or destinations, the instruction gets repeated at the decode2 stage, that is, for each lq/stq/lqarx/stqcx. coming in from decode1, two instructions get sent out to execute1. For these instructions, the RS or RT register gets modified on one of the iterations by setting the LSB of the register number. In LE mode, the first iteration uses RS|1 or RT|1 and the second iteration uses RS or RT. In BE mode, this is done the other way around. In order for decode2 to know what endianness is currently in use, we pass the big_endian flag down from icache through decode1 to decode2. This is always in sync with what execute1 is using because only rfid or an interrupt can change MSR[LE], and those operations all cause a flush and redirect. There is now an extra column in the decode tables in decode1 to indicate whether the instruction needs to be repeated. Decode1 also enforces the rule that lq with RT = RT and lqarx with RA = RT or RB = RT are illegal. Decode2 now passes a 'repeat' flag and a 'second' flag to execute1, and execute1 passes them on to loadstore1. The 'repeat' flag is set for both iterations of a repeated instruction, and 'second' is set on the second iteration. Execute1 does not take asynchronous or trace interrupts on the second iteration of a repeated instruction. Loadstore1 uses 'next_addr' for the second iteration of a repeated load/store so that we access the second doubleword of the memory operand. Thus loadstore1 accesses the doublewords in increasing memory order. For 16-byte loads this means that the first iteration writes GPR RT|1. It is possible that RA = RT|1 (this is a legal but non-preferred form), meaning that if the memory operand was misaligned, the first iteration would overwrite RA but then the second iteration might take a page fault, leading to corrupted state. To avoid that possibility, 16-byte loads in LE mode take an alignment interrupt if the operand is not 16-byte aligned. (This is the case anyway for lqarx, and we enforce it for lq as well.) Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
type repeat_t is (NONE, -- instruction is not repeated
core: Crack update-form loads into two internal ops This uses the instruction-doubling machinery to send load with update instructions down to loadstore1 as two separate ops, rather than one op with two destinations. This will help to simplify the value tracking mechanisms. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
DUPD); -- update-form load
core: Implement quadword loads and stores This implements the lq, stq, lqarx and stqcx. instructions. These instructions all access two consecutive GPRs; for example the "lq %r6,0(%r3)" instruction will load the doubleword at the address in R3 into R7 and the doubleword at address R3 + 8 into R6. To cope with having two GPR sources or destinations, the instruction gets repeated at the decode2 stage, that is, for each lq/stq/lqarx/stqcx. coming in from decode1, two instructions get sent out to execute1. For these instructions, the RS or RT register gets modified on one of the iterations by setting the LSB of the register number. In LE mode, the first iteration uses RS|1 or RT|1 and the second iteration uses RS or RT. In BE mode, this is done the other way around. In order for decode2 to know what endianness is currently in use, we pass the big_endian flag down from icache through decode1 to decode2. This is always in sync with what execute1 is using because only rfid or an interrupt can change MSR[LE], and those operations all cause a flush and redirect. There is now an extra column in the decode tables in decode1 to indicate whether the instruction needs to be repeated. Decode1 also enforces the rule that lq with RT = RT and lqarx with RA = RT or RB = RT are illegal. Decode2 now passes a 'repeat' flag and a 'second' flag to execute1, and execute1 passes them on to loadstore1. The 'repeat' flag is set for both iterations of a repeated instruction, and 'second' is set on the second iteration. Execute1 does not take asynchronous or trace interrupts on the second iteration of a repeated instruction. Loadstore1 uses 'next_addr' for the second iteration of a repeated load/store so that we access the second doubleword of the memory operand. Thus loadstore1 accesses the doublewords in increasing memory order. For 16-byte loads this means that the first iteration writes GPR RT|1. It is possible that RA = RT|1 (this is a legal but non-preferred form), meaning that if the memory operand was misaligned, the first iteration would overwrite RA but then the second iteration might take a page fault, leading to corrupted state. To avoid that possibility, 16-byte loads in LE mode take an alignment interrupt if the operand is not 16-byte aligned. (This is the case anyway for lqarx, and we enforce it for lq as well.) Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
type decode_rom_t is record
unit : unit_t;
decode: Add a facility field to the instruction decode tables This makes it simpler to work out when to deliver a FPU unavailable interrupt. This also means we can get rid of the OP_FPLOAD and OP_FPSTORE insn_type values. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
facility : facility_t;
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
insn_type : insn_type_t;
input_reg_a : input_reg_a_t;
input_reg_b : input_reg_b_t;
input_reg_c : input_reg_c_t;
output_reg_a : output_reg_a_t;
input_cr : std_ulogic;
output_cr : std_ulogic;
invert_a : std_ulogic;
invert_out : std_ulogic;
input_carry : carry_in_t;
output_carry : std_ulogic;
-- load/store signals
length : length_t;
byte_reverse : std_ulogic;
sign_extend : std_ulogic;
update : std_ulogic;
reserve : std_ulogic;
-- multiplier and ALU signals
is_32bit : std_ulogic;
is_signed : std_ulogic;
rc : rc_t;
lr : std_ulogic;
sgl_pipe : std_ulogic;
core: Implement quadword loads and stores This implements the lq, stq, lqarx and stqcx. instructions. These instructions all access two consecutive GPRs; for example the "lq %r6,0(%r3)" instruction will load the doubleword at the address in R3 into R7 and the doubleword at address R3 + 8 into R6. To cope with having two GPR sources or destinations, the instruction gets repeated at the decode2 stage, that is, for each lq/stq/lqarx/stqcx. coming in from decode1, two instructions get sent out to execute1. For these instructions, the RS or RT register gets modified on one of the iterations by setting the LSB of the register number. In LE mode, the first iteration uses RS|1 or RT|1 and the second iteration uses RS or RT. In BE mode, this is done the other way around. In order for decode2 to know what endianness is currently in use, we pass the big_endian flag down from icache through decode1 to decode2. This is always in sync with what execute1 is using because only rfid or an interrupt can change MSR[LE], and those operations all cause a flush and redirect. There is now an extra column in the decode tables in decode1 to indicate whether the instruction needs to be repeated. Decode1 also enforces the rule that lq with RT = RT and lqarx with RA = RT or RB = RT are illegal. Decode2 now passes a 'repeat' flag and a 'second' flag to execute1, and execute1 passes them on to loadstore1. The 'repeat' flag is set for both iterations of a repeated instruction, and 'second' is set on the second iteration. Execute1 does not take asynchronous or trace interrupts on the second iteration of a repeated instruction. Loadstore1 uses 'next_addr' for the second iteration of a repeated load/store so that we access the second doubleword of the memory operand. Thus loadstore1 accesses the doublewords in increasing memory order. For 16-byte loads this means that the first iteration writes GPR RT|1. It is possible that RA = RT|1 (this is a legal but non-preferred form), meaning that if the memory operand was misaligned, the first iteration would overwrite RA but then the second iteration might take a page fault, leading to corrupted state. To avoid that possibility, 16-byte loads in LE mode take an alignment interrupt if the operand is not 16-byte aligned. (This is the case anyway for lqarx, and we enforce it for lq as well.) Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
repeat : repeat_t;
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
end record;
decode: Add a facility field to the instruction decode tables This makes it simpler to work out when to deliver a FPU unavailable interrupt. This also means we can get rid of the OP_FPLOAD and OP_FPSTORE insn_type values. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
constant decode_rom_init : decode_rom_t := (unit => NONE, facility => NONE,
decode: Reformat decode_types.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
insn_type => OP_ILLEGAL, input_reg_a => NONE,
input_reg_b => NONE, input_reg_c => NONE,
output_reg_a => NONE, input_cr => '0', output_cr => '0',
invert_a => '0', invert_out => '0', input_carry => ZERO, output_carry => '0',
length => NONE, byte_reverse => '0', sign_extend => '0',
update => '0', reserve => '0', is_32bit => '0',
core: Implement quadword loads and stores This implements the lq, stq, lqarx and stqcx. instructions. These instructions all access two consecutive GPRs; for example the "lq %r6,0(%r3)" instruction will load the doubleword at the address in R3 into R7 and the doubleword at address R3 + 8 into R6. To cope with having two GPR sources or destinations, the instruction gets repeated at the decode2 stage, that is, for each lq/stq/lqarx/stqcx. coming in from decode1, two instructions get sent out to execute1. For these instructions, the RS or RT register gets modified on one of the iterations by setting the LSB of the register number. In LE mode, the first iteration uses RS|1 or RT|1 and the second iteration uses RS or RT. In BE mode, this is done the other way around. In order for decode2 to know what endianness is currently in use, we pass the big_endian flag down from icache through decode1 to decode2. This is always in sync with what execute1 is using because only rfid or an interrupt can change MSR[LE], and those operations all cause a flush and redirect. There is now an extra column in the decode tables in decode1 to indicate whether the instruction needs to be repeated. Decode1 also enforces the rule that lq with RT = RT and lqarx with RA = RT or RB = RT are illegal. Decode2 now passes a 'repeat' flag and a 'second' flag to execute1, and execute1 passes them on to loadstore1. The 'repeat' flag is set for both iterations of a repeated instruction, and 'second' is set on the second iteration. Execute1 does not take asynchronous or trace interrupts on the second iteration of a repeated instruction. Loadstore1 uses 'next_addr' for the second iteration of a repeated load/store so that we access the second doubleword of the memory operand. Thus loadstore1 accesses the doublewords in increasing memory order. For 16-byte loads this means that the first iteration writes GPR RT|1. It is possible that RA = RT|1 (this is a legal but non-preferred form), meaning that if the memory operand was misaligned, the first iteration would overwrite RA but then the second iteration might take a page fault, leading to corrupted state. To avoid that possibility, 16-byte loads in LE mode take an alignment interrupt if the operand is not 16-byte aligned. (This is the case anyway for lqarx, and we enforce it for lq as well.) Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
is_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0', repeat => NONE);
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
end decode_types;
package body decode_types is
end decode_types;