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microwatt/litedram/generated/sim/litedram_core.init

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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
618c10a4658cf000
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
384297003c4c0001
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
fbc1fff07c0802a6
f8010010fbe1fff8
3be10020f821fe91
f8a101a0f8810198
f8c101a838800140
38c101987c651b78
7fe3fb78f8e101b0
f92101c0f90101b8
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
48000dc1f94101c8
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c7e1b7860000000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
480008d97fe3fb78
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3821017060000000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
480013807fc3f378
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
0100000000000000
4e80002000000280
0000000000000000
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0007ac00000000
4e8000204c00012c
0000000000000000
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c4c000100000000
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0802a63842965c
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7d800026fbe1fff8
91810008f8010010
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
480007cdf821ff91
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c62ffff60000000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bffff3538637d00
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
548400023880ffff
7c8026ea7c0004ac
3fe0c0003c62ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
63ff000838637d20
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c62ffff4bffff11
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38637d407bff0020
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0004ac4bffff01
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
73e900017fe0feea
3c62ffff41820010
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffee538637d58
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4d80000073e90002
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c62ffff41820010
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffecd38637d60
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4e00000073e90004
3c62ffff41820010
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffeb538637d68
3bff7ff83fe2ffff
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffea57fe3fb78
3c80c00041920028
7884002060840010
7c8026ea7c0004ac
7884b2823c62ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffe7d38637d70
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c80c000418e004c
7884002060840018
7c8026ea7c0004ac
788465023c62ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffe5538637d90
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
608400303c80c000
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0004ac78840020
3c62ffff7c8026ea
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38637db07884b282
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3d20c0004bfffe31
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7929002061290020
7d204eea7c0004ac
3c62ffff3c80000f
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38637dd060844240
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffe057c892392
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c62ffff3c82ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c62ffff41920020
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffdc538637e38
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
8181000838210070
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4800119c7d818120
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c80f0004bfffda9
6084400038a0ffff
7884002054a50422
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
480008713c604000
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3c62ffff60000000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffd7d38637e70
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
e801001038210070
ebe1fff881810008
7d8181207c0803a6
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0802a63842940c
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
614a08003d40c010
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
794a00203920000e
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
f821ffa1f8010010
7d20572a7c0004ac
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3862801860000000
litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
600000004bfffce1
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
e801001038210060
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0100000000000000
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litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0802a6384293b4
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
614a08003d40c010
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f821ffa1f8010010
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litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3d40aaaa39000080
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffc913f60aaaa
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3fa0aaaa60000000
637baaaa3f82ffff
3be000003bc00000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3b9c7e9863bdaaaa
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3d3e10007b7b0020
792917647fc407b4
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffbcd7fff07b4
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3bde000160000000
409effc82bbe0080
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3d2040007d0903a6
91490000614a5555
4200fff839290004
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
600000004bfffc0d
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3f82ffff3fa05555
3bc000003f605555
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3b9c7eb863bd5555
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3d3e1000637b5555
792917647fc407b4
7f85e80080a90000
3bff0001419e001c
7f83e3787f66db78
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffb4d7fff07b4
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3bde000160000000
409effc82bbe0080
419e001c2fbf0000
38a001003c62ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38637ed87fe4fb78
600000004bfffb21
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3fc2ffff3c62ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3bde7f1838637f00
600000004bfffb09
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3d20400039400100
390000017d4903a6
3929000439480001
9149fffc79480020
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffb514200fff0
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3940010060000000
7d4903a639200000
3d09100038c00001
7908176439460001
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7f8a284080a80000
7fc3f378419e0014
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
600000004bfffaa1
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
392900014bffff98
3c62ffff4200ffcc
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffa8538637f38
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3920002060000000
7d2903a639400000
794800203d2a1000
394a000139290002
9109000079291764
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffac94200ffe8
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3f82ffff60000000
3bc000003ba00000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3d3d10003b9c7f50
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
792917647fa607b4
5529043e81290008
7d2507b47f893000
3bde0001419e001c
7f83e3787cc43378
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffa0d7fde07b4
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3bbd000160000000
409effc02bbd0020
419e001c2fbe0000
38a000203c62ffff
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38637f707fc4f378
600000004bfff9e1
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
386000007ffff214
409e00b02f9f0000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38637f983c62ffff
600000004bfff9c1
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
394001007c9602a6
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3d49100039200000
794a176479280020
910a000039290001
7ff602a64200ffec
3fe0000c7c9f2050
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
600000004bfff9ed
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7d3602a67bff0020
7929002039000100
3d4040007d0903a6
394a0004810a0000
7cb602a64200fff8
3ca0000c7d254850
3c62ffff60a58000
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
78a5032038637fa8
600000004bfff929
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3821009038600001
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
0000000048000cdc
litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
0000058001000000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
384290003c4c0001
600000007c0802a6
48000c6538628000
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3f60c010f821ff71
637b10003be00000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfff8dd7b7b0020
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0004ac60000000
3f40c0107fe0df2a
7b5a0020635a1008
7fe0d72a7c0004ac
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4bfffba93fa0c010
7bbd002063bd0818
7fe0ef2a7c0004ac
63de08203fc0c010
7c0004ac7bde0020
3d20c0107fe0f72a
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7c0004ac7fe0ef2a
3940000e7fe0f72a
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7d404f2a7c0004ac
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0004ac39200200
392000027d20ef2a
7d20f72a7c0004ac
4bfffaed3860000f
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7fe0ef2a7c0004ac
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7c0004ac39200003
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3860000f7d20f72a
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
392000064bfffad1
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7d204eea7c0004ac
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
0000000000000000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
419e00102fa90000
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
38e000107d21e214
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
7ea7ab78e8810060
litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
000000204d415242
litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
4152442020202020
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
20747365746d654d
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litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
20747365746d656d
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
20747365746d654d
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litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
6f6e204d41524453
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litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
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