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library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.ppc_fx_insns.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity divider_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end divider_tb;
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architecture behave of divider_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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constant clk_period : time := 10 ns;
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signal d1 : Execute1ToDividerType;
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signal d2 : DividerToExecute1Type;
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begin
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divider_0: entity work.divider
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port map (clk => clk, rst => rst, d_in => d1, d_out => d2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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variable d128: std_ulogic_vector(127 downto 0);
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variable q128: std_ulogic_vector(127 downto 0);
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divider: Return 0 for invalid and overflow cases, like P9 does
This adds logic to detect the cases where the quotient of the
division overflows the range of the output representation, and
return all zeroes in those cases, which is what POWER9 does.
To do this, we extend the dividend register by 1 bit and we do
an extra step in the division process to get a 2^64 bit of the
quotient, which ends up in the 'overflow' signal. This catches all
the cases where dividend >= 2^64 * divisor, including the case
where divisor = 0, and the divde/divdeu cases where |RA| >= |RB|.
Then, in the output stage, we also check that the result fits in
the representable range, which depends on whether the division is
a signed division or not, and whether it is a 32-bit or 64-bit
division. If dividend >= 2^64 or the result doesn't fit in the
representable range, write_data is set to 0 and write_cr_data to
0x20000000 (i.e. cr0.eq = 1).
POWER9 sets the top 32 bits of the result to zero for 32-bit signed
divisions, and sets CR0 when RC=1 according to the 64-bit value
(i.e. CR0.LT is always 0 for 32-bit signed divisions, even if the
32-bit result is negative). However, modsw with a negative result
sets the top 32 bits to all 1s. We follow suit.
This updates divider_tb to check the invalid cases as well as the
valid case.
This also fixes a small bug where the reset signal for the divider
was driven from rst when it should have been driven from core_rst.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
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variable q64: std_ulogic_vector(63 downto 0);
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variable rem32: std_ulogic_vector(31 downto 0);
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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rst <= '1';
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wait for clk_period;
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rst <= '0';
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '0';
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d1.is_modulus <= '0';
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d1.valid <= '0';
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if run("Test interface") then
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d1.valid <= '1';
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d1.dividend <= x"0000000010001000";
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d1.divisor <= x"0000000000001111";
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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check_equal(d2.write_reg_data, 16#f001#);
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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d1.valid <= '1';
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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check_equal(d2.write_reg_data, 16#f001#);
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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elsif run("Test divd") then
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divd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divd(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divd"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divdu") then
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divdu_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divdu(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divdu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divde") then
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divde_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(signed(d128) / signed(rb));
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if q128(127 downto 63) = x"0000000000000000" & '0' or
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q128(127 downto 63) = x"ffffffffffffffff" & '1' then
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behave_rt := q128(63 downto 0);
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end if;
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divde"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divdeu") then
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divdeu_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if unsigned(rb) > unsigned(ra) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
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behave_rt := q128(63 downto 0);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divdeu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divw") then
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divw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divw(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divw"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divwu") then
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divwu_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divwu(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divwu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divwe") then
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divwe_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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q64 := std_ulogic_vector(signed(ra) / signed(rb));
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if q64(63 downto 31) = x"00000000" & '0' or
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q64(63 downto 31) = x"ffffffff" & '1' then
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behave_rt := x"00000000" & q64(31 downto 0);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divwe"));
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end if;
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end loop;
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end loop;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
elsif run("Test divweu") then
|
|
|
|
divweu_loop : for vlength in 1 to 4 loop
|
|
|
|
for dlength in 1 to vlength loop
|
|
|
|
for i in 0 to 100 loop
|
|
|
|
ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 32)) & x"00000000";
|
|
|
|
rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
|
|
|
|
|
|
|
|
d1.dividend <= ra;
|
|
|
|
d1.divisor <= rb;
|
|
|
|
d1.is_32bit <= '1';
|
|
|
|
d1.valid <= '1';
|
|
|
|
|
|
|
|
wait for clk_period;
|
|
|
|
|
|
|
|
d1.valid <= '0';
|
|
|
|
for j in 0 to 66 loop
|
|
|
|
wait for clk_period;
|
|
|
|
if d2.valid = '1' then
|
|
|
|
exit;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
|
|
|
|
behave_rt := (others => '0');
|
|
|
|
if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then
|
|
|
|
behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
|
|
|
|
end if;
|
|
|
|
check_equal(d2.write_reg_data, behave_rt, result("for divweu"));
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
elsif run("Test modsd") then
|
|
|
|
modsd_loop : for dlength in 1 to 8 loop
|
|
|
|
for vlength in 1 to dlength loop
|
|
|
|
for i in 0 to 100 loop
|
|
|
|
ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
|
|
|
|
rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
|
|
|
|
|
|
|
|
d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
|
|
|
|
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
|
|
|
|
d1.is_signed <= '1';
|
|
|
|
d1.neg_result <= ra(63);
|
|
|
|
d1.is_modulus <= '1';
|
|
|
|
d1.valid <= '1';
|
|
|
|
|
|
|
|
wait for clk_period;
|
|
|
|
|
|
|
|
d1.valid <= '0';
|
|
|
|
for j in 0 to 66 loop
|
|
|
|
wait for clk_period;
|
|
|
|
if d2.valid = '1' then
|
|
|
|
exit;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
|
|
|
|
behave_rt := (others => '0');
|
|
|
|
if rb /= x"0000000000000000" then
|
|
|
|
behave_rt := std_ulogic_vector(signed(ra) rem signed(rb));
|
|
|
|
end if;
|
|
|
|
check_equal(d2.write_reg_data, behave_rt, result("for modsd"));
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
elsif run("Test modud") then
|
|
|
|
modud_loop : for dlength in 1 to 8 loop
|
|
|
|
for vlength in 1 to dlength loop
|
|
|
|
for i in 0 to 100 loop
|
|
|
|
ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
|
|
|
|
rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
|
|
|
|
|
|
|
|
d1.dividend <= ra;
|
|
|
|
d1.divisor <= rb;
|
|
|
|
d1.is_modulus <= '1';
|
|
|
|
d1.valid <= '1';
|
|
|
|
|
|
|
|
wait for clk_period;
|
|
|
|
|
|
|
|
d1.valid <= '0';
|
|
|
|
for j in 0 to 66 loop
|
|
|
|
wait for clk_period;
|
|
|
|
if d2.valid = '1' then
|
|
|
|
exit;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
|
|
|
|
behave_rt := (others => '0');
|
|
|
|
if rb /= x"0000000000000000" then
|
|
|
|
behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb));
|
|
|
|
end if;
|
|
|
|
check_equal(d2.write_reg_data, behave_rt, result("for modud"));
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
elsif run("Test modsw") then
|
|
|
|
modsw_loop : for dlength in 1 to 4 loop
|
|
|
|
for vlength in 1 to dlength loop
|
|
|
|
for i in 0 to 100 loop
|
|
|
|
ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
|
|
|
|
rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
|
|
|
|
|
|
|
|
d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
|
|
|
|
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
|
|
|
|
d1.is_signed <= '1';
|
|
|
|
d1.neg_result <= ra(63);
|
|
|
|
d1.is_32bit <= '1';
|
|
|
|
d1.is_modulus <= '1';
|
|
|
|
d1.valid <= '1';
|
|
|
|
|
|
|
|
wait for clk_period;
|
|
|
|
|
|
|
|
d1.valid <= '0';
|
|
|
|
for j in 0 to 66 loop
|
|
|
|
wait for clk_period;
|
|
|
|
if d2.valid = '1' then
|
|
|
|
exit;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
|
|
|
|
behave_rt := (others => '0');
|
|
|
|
if rb /= x"0000000000000000" then
|
|
|
|
rem32 := std_ulogic_vector(signed(ra(31 downto 0)) rem signed(rb(31 downto 0)));
|
|
|
|
if rem32(31) = '0' then
|
|
|
|
behave_rt := x"00000000" & rem32;
|
|
|
|
else
|
|
|
|
behave_rt := x"ffffffff" & rem32;
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
check_equal(d2.write_reg_data, behave_rt, result("for modsw"));
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
elsif run("Test moduw") then
|
|
|
|
moduw_loop : for dlength in 1 to 4 loop
|
|
|
|
for vlength in 1 to dlength loop
|
|
|
|
for i in 0 to 100 loop
|
|
|
|
ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
|
|
|
|
rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
|
|
|
|
|
|
|
|
d1.dividend <= ra;
|
|
|
|
d1.divisor <= rb;
|
|
|
|
d1.is_32bit <= '1';
|
|
|
|
d1.is_modulus <= '1';
|
|
|
|
d1.valid <= '1';
|
|
|
|
|
|
|
|
wait for clk_period;
|
|
|
|
|
|
|
|
d1.valid <= '0';
|
|
|
|
for j in 0 to 66 loop
|
|
|
|
wait for clk_period;
|
|
|
|
if d2.valid = '1' then
|
|
|
|
exit;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
|
|
|
|
behave_rt := (others => '0');
|
|
|
|
if rb /= x"0000000000000000" then
|
|
|
|
behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0)));
|
|
|
|
end if;
|
|
|
|
check_equal(d2.write_reg_data(31 downto 0), behave_rt(31 downto 0), result("for moduw"));
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end loop;
|
|
|
|
end if;
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
test_runner_cleanup(runner);
|
|
|
|
end process;
|
|
|
|
end behave;
|