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13 lines
201 B
VHDL
13 lines
201 B
VHDL
5 years ago
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity BUFG is
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port(I : in std_logic;
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O : out std_logic
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);
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end BUFG;
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architecture behaviour of BUFG is
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begin
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O <= I;
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end architecture behaviour;
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