//--------------------------------------------------------------------------------
// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:26
//--------------------------------------------------------------------------------
module litedram_core(
	input wire clk,
	output wire init_done,
	output wire init_error,
	input wire [29:0] wb_ctrl_adr,
	input wire [31:0] wb_ctrl_dat_w,
	output wire [31:0] wb_ctrl_dat_r,
	input wire [3:0] wb_ctrl_sel,
	input wire wb_ctrl_cyc,
	input wire wb_ctrl_stb,
	output wire wb_ctrl_ack,
	input wire wb_ctrl_we,
	input wire [2:0] wb_ctrl_cti,
	input wire [1:0] wb_ctrl_bte,
	output wire wb_ctrl_err,
	output wire user_clk,
	output wire user_rst,
	input wire user_port_native_0_cmd_valid,
	output wire user_port_native_0_cmd_ready,
	input wire user_port_native_0_cmd_we,
	input wire [23:0] user_port_native_0_cmd_addr,
	input wire user_port_native_0_wdata_valid,
	output wire user_port_native_0_wdata_ready,
	input wire [15:0] user_port_native_0_wdata_we,
	input wire [127:0] user_port_native_0_wdata_data,
	output wire user_port_native_0_rdata_valid,
	input wire user_port_native_0_rdata_ready,
	output wire [127:0] user_port_native_0_rdata_data
);

reg [13:0] litedramcore_adr = 14'd0;
reg litedramcore_we = 1'd0;
wire [31:0] litedramcore_dat_w;
wire [31:0] litedramcore_dat_r;
wire [29:0] litedramcore_wishbone_adr;
wire [31:0] litedramcore_wishbone_dat_w;
wire [31:0] litedramcore_wishbone_dat_r;
wire [3:0] litedramcore_wishbone_sel;
wire litedramcore_wishbone_cyc;
wire litedramcore_wishbone_stb;
reg litedramcore_wishbone_ack = 1'd0;
wire litedramcore_wishbone_we;
wire [2:0] litedramcore_wishbone_cti;
wire [1:0] litedramcore_wishbone_bte;
reg litedramcore_wishbone_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire por_clk;
reg int_rst = 1'd1;
wire [13:0] ddrphy_dfi_p0_address;
wire [2:0] ddrphy_dfi_p0_bank;
wire ddrphy_dfi_p0_cas_n;
wire ddrphy_dfi_p0_cs_n;
wire ddrphy_dfi_p0_ras_n;
wire ddrphy_dfi_p0_we_n;
wire ddrphy_dfi_p0_cke;
wire ddrphy_dfi_p0_odt;
wire ddrphy_dfi_p0_reset_n;
wire ddrphy_dfi_p0_act_n;
wire [31:0] ddrphy_dfi_p0_wrdata;
wire ddrphy_dfi_p0_wrdata_en;
wire [3:0] ddrphy_dfi_p0_wrdata_mask;
wire ddrphy_dfi_p0_rddata_en;
wire [31:0] ddrphy_dfi_p0_rddata;
wire ddrphy_dfi_p0_rddata_valid;
wire [13:0] ddrphy_dfi_p1_address;
wire [2:0] ddrphy_dfi_p1_bank;
wire ddrphy_dfi_p1_cas_n;
wire ddrphy_dfi_p1_cs_n;
wire ddrphy_dfi_p1_ras_n;
wire ddrphy_dfi_p1_we_n;
wire ddrphy_dfi_p1_cke;
wire ddrphy_dfi_p1_odt;
wire ddrphy_dfi_p1_reset_n;
wire ddrphy_dfi_p1_act_n;
wire [31:0] ddrphy_dfi_p1_wrdata;
wire ddrphy_dfi_p1_wrdata_en;
wire [3:0] ddrphy_dfi_p1_wrdata_mask;
wire ddrphy_dfi_p1_rddata_en;
wire [31:0] ddrphy_dfi_p1_rddata;
wire ddrphy_dfi_p1_rddata_valid;
wire [13:0] ddrphy_dfi_p2_address;
wire [2:0] ddrphy_dfi_p2_bank;
wire ddrphy_dfi_p2_cas_n;
wire ddrphy_dfi_p2_cs_n;
wire ddrphy_dfi_p2_ras_n;
wire ddrphy_dfi_p2_we_n;
wire ddrphy_dfi_p2_cke;
wire ddrphy_dfi_p2_odt;
wire ddrphy_dfi_p2_reset_n;
wire ddrphy_dfi_p2_act_n;
wire [31:0] ddrphy_dfi_p2_wrdata;
wire ddrphy_dfi_p2_wrdata_en;
wire [3:0] ddrphy_dfi_p2_wrdata_mask;
wire ddrphy_dfi_p2_rddata_en;
wire [31:0] ddrphy_dfi_p2_rddata;
wire ddrphy_dfi_p2_rddata_valid;
wire [13:0] ddrphy_dfi_p3_address;
wire [2:0] ddrphy_dfi_p3_bank;
wire ddrphy_dfi_p3_cas_n;
wire ddrphy_dfi_p3_cs_n;
wire ddrphy_dfi_p3_ras_n;
wire ddrphy_dfi_p3_we_n;
wire ddrphy_dfi_p3_cke;
wire ddrphy_dfi_p3_odt;
wire ddrphy_dfi_p3_reset_n;
wire ddrphy_dfi_p3_act_n;
wire [31:0] ddrphy_dfi_p3_wrdata;
wire ddrphy_dfi_p3_wrdata_en;
wire [3:0] ddrphy_dfi_p3_wrdata_mask;
wire ddrphy_dfi_p3_rddata_en;
wire [31:0] ddrphy_dfi_p3_rddata;
wire ddrphy_dfi_p3_rddata_valid;
reg ddrphy_dfiphasemodel0_activate = 1'd0;
reg ddrphy_dfiphasemodel0_precharge = 1'd0;
reg ddrphy_dfiphasemodel0_write = 1'd0;
reg ddrphy_dfiphasemodel0_read = 1'd0;
reg ddrphy_dfiphasemodel1_activate = 1'd0;
reg ddrphy_dfiphasemodel1_precharge = 1'd0;
reg ddrphy_dfiphasemodel1_write = 1'd0;
reg ddrphy_dfiphasemodel1_read = 1'd0;
reg ddrphy_dfiphasemodel2_activate = 1'd0;
reg ddrphy_dfiphasemodel2_precharge = 1'd0;
reg ddrphy_dfiphasemodel2_write = 1'd0;
reg ddrphy_dfiphasemodel2_read = 1'd0;
reg ddrphy_dfiphasemodel3_activate = 1'd0;
reg ddrphy_dfiphasemodel3_precharge = 1'd0;
reg ddrphy_dfiphasemodel3_write = 1'd0;
reg ddrphy_dfiphasemodel3_read = 1'd0;
reg ddrphy_bankmodel0_activate = 1'd0;
reg [13:0] ddrphy_bankmodel0_activate_row = 14'd0;
reg ddrphy_bankmodel0_precharge = 1'd0;
wire ddrphy_bankmodel0_write;
wire [9:0] ddrphy_bankmodel0_write_col;
wire [127:0] ddrphy_bankmodel0_write_data;
wire [15:0] ddrphy_bankmodel0_write_mask;
reg ddrphy_bankmodel0_read = 1'd0;
reg [9:0] ddrphy_bankmodel0_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel0_read_data = 128'd0;
reg ddrphy_bankmodel0_active = 1'd0;
reg [13:0] ddrphy_bankmodel0_row = 14'd0;
reg [20:0] ddrphy_bankmodel0_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel0_write_port_dat_r;
reg [15:0] ddrphy_bankmodel0_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel0_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel0_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel0_read_port_dat_r;
wire [20:0] ddrphy_bankmodel0_wraddr;
wire [20:0] ddrphy_bankmodel0_rdaddr;
reg ddrphy_bankmodel1_activate = 1'd0;
reg [13:0] ddrphy_bankmodel1_activate_row = 14'd0;
reg ddrphy_bankmodel1_precharge = 1'd0;
wire ddrphy_bankmodel1_write;
wire [9:0] ddrphy_bankmodel1_write_col;
wire [127:0] ddrphy_bankmodel1_write_data;
wire [15:0] ddrphy_bankmodel1_write_mask;
reg ddrphy_bankmodel1_read = 1'd0;
reg [9:0] ddrphy_bankmodel1_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel1_read_data = 128'd0;
reg ddrphy_bankmodel1_active = 1'd0;
reg [13:0] ddrphy_bankmodel1_row = 14'd0;
reg [20:0] ddrphy_bankmodel1_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel1_write_port_dat_r;
reg [15:0] ddrphy_bankmodel1_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel1_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel1_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel1_read_port_dat_r;
wire [20:0] ddrphy_bankmodel1_wraddr;
wire [20:0] ddrphy_bankmodel1_rdaddr;
reg ddrphy_bankmodel2_activate = 1'd0;
reg [13:0] ddrphy_bankmodel2_activate_row = 14'd0;
reg ddrphy_bankmodel2_precharge = 1'd0;
wire ddrphy_bankmodel2_write;
wire [9:0] ddrphy_bankmodel2_write_col;
wire [127:0] ddrphy_bankmodel2_write_data;
wire [15:0] ddrphy_bankmodel2_write_mask;
reg ddrphy_bankmodel2_read = 1'd0;
reg [9:0] ddrphy_bankmodel2_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel2_read_data = 128'd0;
reg ddrphy_bankmodel2_active = 1'd0;
reg [13:0] ddrphy_bankmodel2_row = 14'd0;
reg [20:0] ddrphy_bankmodel2_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel2_write_port_dat_r;
reg [15:0] ddrphy_bankmodel2_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel2_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel2_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel2_read_port_dat_r;
wire [20:0] ddrphy_bankmodel2_wraddr;
wire [20:0] ddrphy_bankmodel2_rdaddr;
reg ddrphy_bankmodel3_activate = 1'd0;
reg [13:0] ddrphy_bankmodel3_activate_row = 14'd0;
reg ddrphy_bankmodel3_precharge = 1'd0;
wire ddrphy_bankmodel3_write;
wire [9:0] ddrphy_bankmodel3_write_col;
wire [127:0] ddrphy_bankmodel3_write_data;
wire [15:0] ddrphy_bankmodel3_write_mask;
reg ddrphy_bankmodel3_read = 1'd0;
reg [9:0] ddrphy_bankmodel3_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel3_read_data = 128'd0;
reg ddrphy_bankmodel3_active = 1'd0;
reg [13:0] ddrphy_bankmodel3_row = 14'd0;
reg [20:0] ddrphy_bankmodel3_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel3_write_port_dat_r;
reg [15:0] ddrphy_bankmodel3_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel3_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel3_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel3_read_port_dat_r;
wire [20:0] ddrphy_bankmodel3_wraddr;
wire [20:0] ddrphy_bankmodel3_rdaddr;
reg ddrphy_bankmodel4_activate = 1'd0;
reg [13:0] ddrphy_bankmodel4_activate_row = 14'd0;
reg ddrphy_bankmodel4_precharge = 1'd0;
wire ddrphy_bankmodel4_write;
wire [9:0] ddrphy_bankmodel4_write_col;
wire [127:0] ddrphy_bankmodel4_write_data;
wire [15:0] ddrphy_bankmodel4_write_mask;
reg ddrphy_bankmodel4_read = 1'd0;
reg [9:0] ddrphy_bankmodel4_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel4_read_data = 128'd0;
reg ddrphy_bankmodel4_active = 1'd0;
reg [13:0] ddrphy_bankmodel4_row = 14'd0;
reg [20:0] ddrphy_bankmodel4_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel4_write_port_dat_r;
reg [15:0] ddrphy_bankmodel4_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel4_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel4_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel4_read_port_dat_r;
wire [20:0] ddrphy_bankmodel4_wraddr;
wire [20:0] ddrphy_bankmodel4_rdaddr;
reg ddrphy_bankmodel5_activate = 1'd0;
reg [13:0] ddrphy_bankmodel5_activate_row = 14'd0;
reg ddrphy_bankmodel5_precharge = 1'd0;
wire ddrphy_bankmodel5_write;
wire [9:0] ddrphy_bankmodel5_write_col;
wire [127:0] ddrphy_bankmodel5_write_data;
wire [15:0] ddrphy_bankmodel5_write_mask;
reg ddrphy_bankmodel5_read = 1'd0;
reg [9:0] ddrphy_bankmodel5_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel5_read_data = 128'd0;
reg ddrphy_bankmodel5_active = 1'd0;
reg [13:0] ddrphy_bankmodel5_row = 14'd0;
reg [20:0] ddrphy_bankmodel5_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel5_write_port_dat_r;
reg [15:0] ddrphy_bankmodel5_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel5_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel5_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel5_read_port_dat_r;
wire [20:0] ddrphy_bankmodel5_wraddr;
wire [20:0] ddrphy_bankmodel5_rdaddr;
reg ddrphy_bankmodel6_activate = 1'd0;
reg [13:0] ddrphy_bankmodel6_activate_row = 14'd0;
reg ddrphy_bankmodel6_precharge = 1'd0;
wire ddrphy_bankmodel6_write;
wire [9:0] ddrphy_bankmodel6_write_col;
wire [127:0] ddrphy_bankmodel6_write_data;
wire [15:0] ddrphy_bankmodel6_write_mask;
reg ddrphy_bankmodel6_read = 1'd0;
reg [9:0] ddrphy_bankmodel6_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel6_read_data = 128'd0;
reg ddrphy_bankmodel6_active = 1'd0;
reg [13:0] ddrphy_bankmodel6_row = 14'd0;
reg [20:0] ddrphy_bankmodel6_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel6_write_port_dat_r;
reg [15:0] ddrphy_bankmodel6_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel6_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel6_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel6_read_port_dat_r;
wire [20:0] ddrphy_bankmodel6_wraddr;
wire [20:0] ddrphy_bankmodel6_rdaddr;
reg ddrphy_bankmodel7_activate = 1'd0;
reg [13:0] ddrphy_bankmodel7_activate_row = 14'd0;
reg ddrphy_bankmodel7_precharge = 1'd0;
wire ddrphy_bankmodel7_write;
wire [9:0] ddrphy_bankmodel7_write_col;
wire [127:0] ddrphy_bankmodel7_write_data;
wire [15:0] ddrphy_bankmodel7_write_mask;
reg ddrphy_bankmodel7_read = 1'd0;
reg [9:0] ddrphy_bankmodel7_read_col = 10'd0;
reg [127:0] ddrphy_bankmodel7_read_data = 128'd0;
reg ddrphy_bankmodel7_active = 1'd0;
reg [13:0] ddrphy_bankmodel7_row = 14'd0;
reg [20:0] ddrphy_bankmodel7_write_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel7_write_port_dat_r;
reg [15:0] ddrphy_bankmodel7_write_port_we = 16'd0;
reg [127:0] ddrphy_bankmodel7_write_port_dat_w = 128'd0;
reg [20:0] ddrphy_bankmodel7_read_port_adr = 21'd0;
wire [127:0] ddrphy_bankmodel7_read_port_dat_r;
wire [20:0] ddrphy_bankmodel7_wraddr;
wire [20:0] ddrphy_bankmodel7_rdaddr;
reg [3:0] ddrphy_activates0 = 4'd0;
reg [3:0] ddrphy_precharges0 = 4'd0;
reg ddrphy_bank_write0 = 1'd0;
reg [9:0] ddrphy_bank_write_col0 = 10'd0;
reg [3:0] ddrphy_writes0 = 4'd0;
reg ddrphy_new_bank_write0 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col0 = 10'd0;
reg ddrphy_new_bank_write1 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col1 = 10'd0;
reg [3:0] ddrphy_reads0 = 4'd0;
reg [3:0] ddrphy_activates1 = 4'd0;
reg [3:0] ddrphy_precharges1 = 4'd0;
reg ddrphy_bank_write1 = 1'd0;
reg [9:0] ddrphy_bank_write_col1 = 10'd0;
reg [3:0] ddrphy_writes1 = 4'd0;
reg ddrphy_new_bank_write2 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col2 = 10'd0;
reg ddrphy_new_bank_write3 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col3 = 10'd0;
reg [3:0] ddrphy_reads1 = 4'd0;
reg [3:0] ddrphy_activates2 = 4'd0;
reg [3:0] ddrphy_precharges2 = 4'd0;
reg ddrphy_bank_write2 = 1'd0;
reg [9:0] ddrphy_bank_write_col2 = 10'd0;
reg [3:0] ddrphy_writes2 = 4'd0;
reg ddrphy_new_bank_write4 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col4 = 10'd0;
reg ddrphy_new_bank_write5 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col5 = 10'd0;
reg [3:0] ddrphy_reads2 = 4'd0;
reg [3:0] ddrphy_activates3 = 4'd0;
reg [3:0] ddrphy_precharges3 = 4'd0;
reg ddrphy_bank_write3 = 1'd0;
reg [9:0] ddrphy_bank_write_col3 = 10'd0;
reg [3:0] ddrphy_writes3 = 4'd0;
reg ddrphy_new_bank_write6 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col6 = 10'd0;
reg ddrphy_new_bank_write7 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col7 = 10'd0;
reg [3:0] ddrphy_reads3 = 4'd0;
reg [3:0] ddrphy_activates4 = 4'd0;
reg [3:0] ddrphy_precharges4 = 4'd0;
reg ddrphy_bank_write4 = 1'd0;
reg [9:0] ddrphy_bank_write_col4 = 10'd0;
reg [3:0] ddrphy_writes4 = 4'd0;
reg ddrphy_new_bank_write8 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col8 = 10'd0;
reg ddrphy_new_bank_write9 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col9 = 10'd0;
reg [3:0] ddrphy_reads4 = 4'd0;
reg [3:0] ddrphy_activates5 = 4'd0;
reg [3:0] ddrphy_precharges5 = 4'd0;
reg ddrphy_bank_write5 = 1'd0;
reg [9:0] ddrphy_bank_write_col5 = 10'd0;
reg [3:0] ddrphy_writes5 = 4'd0;
reg ddrphy_new_bank_write10 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col10 = 10'd0;
reg ddrphy_new_bank_write11 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col11 = 10'd0;
reg [3:0] ddrphy_reads5 = 4'd0;
reg [3:0] ddrphy_activates6 = 4'd0;
reg [3:0] ddrphy_precharges6 = 4'd0;
reg ddrphy_bank_write6 = 1'd0;
reg [9:0] ddrphy_bank_write_col6 = 10'd0;
reg [3:0] ddrphy_writes6 = 4'd0;
reg ddrphy_new_bank_write12 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col12 = 10'd0;
reg ddrphy_new_bank_write13 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col13 = 10'd0;
reg [3:0] ddrphy_reads6 = 4'd0;
reg [3:0] ddrphy_activates7 = 4'd0;
reg [3:0] ddrphy_precharges7 = 4'd0;
reg ddrphy_bank_write7 = 1'd0;
reg [9:0] ddrphy_bank_write_col7 = 10'd0;
reg [3:0] ddrphy_writes7 = 4'd0;
reg ddrphy_new_bank_write14 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col14 = 10'd0;
reg ddrphy_new_bank_write15 = 1'd0;
reg [9:0] ddrphy_new_bank_write_col15 = 10'd0;
reg [3:0] ddrphy_reads7 = 4'd0;
wire ddrphy_banks_read;
wire [127:0] ddrphy_banks_read_data;
reg ddrphy_new_banks_read0 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data0 = 128'd0;
reg ddrphy_new_banks_read1 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data1 = 128'd0;
reg ddrphy_new_banks_read2 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data2 = 128'd0;
reg ddrphy_new_banks_read3 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data3 = 128'd0;
reg ddrphy_new_banks_read4 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data4 = 128'd0;
reg ddrphy_new_banks_read5 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data5 = 128'd0;
reg ddrphy_new_banks_read6 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data6 = 128'd0;
reg ddrphy_new_banks_read7 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data7 = 128'd0;
reg ddrphy_new_banks_read8 = 1'd0;
reg [127:0] ddrphy_new_banks_read_data8 = 128'd0;
wire [13:0] litedramcore_inti_p0_address;
wire [2:0] litedramcore_inti_p0_bank;
reg litedramcore_inti_p0_cas_n = 1'd1;
reg litedramcore_inti_p0_cs_n = 1'd1;
reg litedramcore_inti_p0_ras_n = 1'd1;
reg litedramcore_inti_p0_we_n = 1'd1;
wire litedramcore_inti_p0_cke;
wire litedramcore_inti_p0_odt;
wire litedramcore_inti_p0_reset_n;
reg litedramcore_inti_p0_act_n = 1'd1;
wire [31:0] litedramcore_inti_p0_wrdata;
wire litedramcore_inti_p0_wrdata_en;
wire [3:0] litedramcore_inti_p0_wrdata_mask;
wire litedramcore_inti_p0_rddata_en;
reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
reg litedramcore_inti_p0_rddata_valid = 1'd0;
wire [13:0] litedramcore_inti_p1_address;
wire [2:0] litedramcore_inti_p1_bank;
reg litedramcore_inti_p1_cas_n = 1'd1;
reg litedramcore_inti_p1_cs_n = 1'd1;
reg litedramcore_inti_p1_ras_n = 1'd1;
reg litedramcore_inti_p1_we_n = 1'd1;
wire litedramcore_inti_p1_cke;
wire litedramcore_inti_p1_odt;
wire litedramcore_inti_p1_reset_n;
reg litedramcore_inti_p1_act_n = 1'd1;
wire [31:0] litedramcore_inti_p1_wrdata;
wire litedramcore_inti_p1_wrdata_en;
wire [3:0] litedramcore_inti_p1_wrdata_mask;
wire litedramcore_inti_p1_rddata_en;
reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
reg litedramcore_inti_p1_rddata_valid = 1'd0;
wire [13:0] litedramcore_inti_p2_address;
wire [2:0] litedramcore_inti_p2_bank;
reg litedramcore_inti_p2_cas_n = 1'd1;
reg litedramcore_inti_p2_cs_n = 1'd1;
reg litedramcore_inti_p2_ras_n = 1'd1;
reg litedramcore_inti_p2_we_n = 1'd1;
wire litedramcore_inti_p2_cke;
wire litedramcore_inti_p2_odt;
wire litedramcore_inti_p2_reset_n;
reg litedramcore_inti_p2_act_n = 1'd1;
wire [31:0] litedramcore_inti_p2_wrdata;
wire litedramcore_inti_p2_wrdata_en;
wire [3:0] litedramcore_inti_p2_wrdata_mask;
wire litedramcore_inti_p2_rddata_en;
reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
reg litedramcore_inti_p2_rddata_valid = 1'd0;
wire [13:0] litedramcore_inti_p3_address;
wire [2:0] litedramcore_inti_p3_bank;
reg litedramcore_inti_p3_cas_n = 1'd1;
reg litedramcore_inti_p3_cs_n = 1'd1;
reg litedramcore_inti_p3_ras_n = 1'd1;
reg litedramcore_inti_p3_we_n = 1'd1;
wire litedramcore_inti_p3_cke;
wire litedramcore_inti_p3_odt;
wire litedramcore_inti_p3_reset_n;
reg litedramcore_inti_p3_act_n = 1'd1;
wire [31:0] litedramcore_inti_p3_wrdata;
wire litedramcore_inti_p3_wrdata_en;
wire [3:0] litedramcore_inti_p3_wrdata_mask;
wire litedramcore_inti_p3_rddata_en;
reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
reg litedramcore_inti_p3_rddata_valid = 1'd0;
wire [13:0] litedramcore_slave_p0_address;
wire [2:0] litedramcore_slave_p0_bank;
wire litedramcore_slave_p0_cas_n;
wire litedramcore_slave_p0_cs_n;
wire litedramcore_slave_p0_ras_n;
wire litedramcore_slave_p0_we_n;
wire litedramcore_slave_p0_cke;
wire litedramcore_slave_p0_odt;
wire litedramcore_slave_p0_reset_n;
wire litedramcore_slave_p0_act_n;
wire [31:0] litedramcore_slave_p0_wrdata;
wire litedramcore_slave_p0_wrdata_en;
wire [3:0] litedramcore_slave_p0_wrdata_mask;
wire litedramcore_slave_p0_rddata_en;
reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
reg litedramcore_slave_p0_rddata_valid = 1'd0;
wire [13:0] litedramcore_slave_p1_address;
wire [2:0] litedramcore_slave_p1_bank;
wire litedramcore_slave_p1_cas_n;
wire litedramcore_slave_p1_cs_n;
wire litedramcore_slave_p1_ras_n;
wire litedramcore_slave_p1_we_n;
wire litedramcore_slave_p1_cke;
wire litedramcore_slave_p1_odt;
wire litedramcore_slave_p1_reset_n;
wire litedramcore_slave_p1_act_n;
wire [31:0] litedramcore_slave_p1_wrdata;
wire litedramcore_slave_p1_wrdata_en;
wire [3:0] litedramcore_slave_p1_wrdata_mask;
wire litedramcore_slave_p1_rddata_en;
reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
reg litedramcore_slave_p1_rddata_valid = 1'd0;
wire [13:0] litedramcore_slave_p2_address;
wire [2:0] litedramcore_slave_p2_bank;
wire litedramcore_slave_p2_cas_n;
wire litedramcore_slave_p2_cs_n;
wire litedramcore_slave_p2_ras_n;
wire litedramcore_slave_p2_we_n;
wire litedramcore_slave_p2_cke;
wire litedramcore_slave_p2_odt;
wire litedramcore_slave_p2_reset_n;
wire litedramcore_slave_p2_act_n;
wire [31:0] litedramcore_slave_p2_wrdata;
wire litedramcore_slave_p2_wrdata_en;
wire [3:0] litedramcore_slave_p2_wrdata_mask;
wire litedramcore_slave_p2_rddata_en;
reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
reg litedramcore_slave_p2_rddata_valid = 1'd0;
wire [13:0] litedramcore_slave_p3_address;
wire [2:0] litedramcore_slave_p3_bank;
wire litedramcore_slave_p3_cas_n;
wire litedramcore_slave_p3_cs_n;
wire litedramcore_slave_p3_ras_n;
wire litedramcore_slave_p3_we_n;
wire litedramcore_slave_p3_cke;
wire litedramcore_slave_p3_odt;
wire litedramcore_slave_p3_reset_n;
wire litedramcore_slave_p3_act_n;
wire [31:0] litedramcore_slave_p3_wrdata;
wire litedramcore_slave_p3_wrdata_en;
wire [3:0] litedramcore_slave_p3_wrdata_mask;
wire litedramcore_slave_p3_rddata_en;
reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
reg litedramcore_slave_p3_rddata_valid = 1'd0;
reg [13:0] litedramcore_master_p0_address = 14'd0;
reg [2:0] litedramcore_master_p0_bank = 3'd0;
reg litedramcore_master_p0_cas_n = 1'd1;
reg litedramcore_master_p0_cs_n = 1'd1;
reg litedramcore_master_p0_ras_n = 1'd1;
reg litedramcore_master_p0_we_n = 1'd1;
reg litedramcore_master_p0_cke = 1'd0;
reg litedramcore_master_p0_odt = 1'd0;
reg litedramcore_master_p0_reset_n = 1'd0;
reg litedramcore_master_p0_act_n = 1'd1;
reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
reg litedramcore_master_p0_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
reg litedramcore_master_p0_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p0_rddata;
wire litedramcore_master_p0_rddata_valid;
reg [13:0] litedramcore_master_p1_address = 14'd0;
reg [2:0] litedramcore_master_p1_bank = 3'd0;
reg litedramcore_master_p1_cas_n = 1'd1;
reg litedramcore_master_p1_cs_n = 1'd1;
reg litedramcore_master_p1_ras_n = 1'd1;
reg litedramcore_master_p1_we_n = 1'd1;
reg litedramcore_master_p1_cke = 1'd0;
reg litedramcore_master_p1_odt = 1'd0;
reg litedramcore_master_p1_reset_n = 1'd0;
reg litedramcore_master_p1_act_n = 1'd1;
reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
reg litedramcore_master_p1_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
reg litedramcore_master_p1_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p1_rddata;
wire litedramcore_master_p1_rddata_valid;
reg [13:0] litedramcore_master_p2_address = 14'd0;
reg [2:0] litedramcore_master_p2_bank = 3'd0;
reg litedramcore_master_p2_cas_n = 1'd1;
reg litedramcore_master_p2_cs_n = 1'd1;
reg litedramcore_master_p2_ras_n = 1'd1;
reg litedramcore_master_p2_we_n = 1'd1;
reg litedramcore_master_p2_cke = 1'd0;
reg litedramcore_master_p2_odt = 1'd0;
reg litedramcore_master_p2_reset_n = 1'd0;
reg litedramcore_master_p2_act_n = 1'd1;
reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
reg litedramcore_master_p2_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
reg litedramcore_master_p2_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p2_rddata;
wire litedramcore_master_p2_rddata_valid;
reg [13:0] litedramcore_master_p3_address = 14'd0;
reg [2:0] litedramcore_master_p3_bank = 3'd0;
reg litedramcore_master_p3_cas_n = 1'd1;
reg litedramcore_master_p3_cs_n = 1'd1;
reg litedramcore_master_p3_ras_n = 1'd1;
reg litedramcore_master_p3_we_n = 1'd1;
reg litedramcore_master_p3_cke = 1'd0;
reg litedramcore_master_p3_odt = 1'd0;
reg litedramcore_master_p3_reset_n = 1'd0;
reg litedramcore_master_p3_act_n = 1'd1;
reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
reg litedramcore_master_p3_wrdata_en = 1'd0;
reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
reg litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p3_rddata;
wire litedramcore_master_p3_rddata_valid;
wire litedramcore_sel;
wire litedramcore_cke;
wire litedramcore_odt;
wire litedramcore_reset_n;
reg [3:0] litedramcore_storage = 4'd1;
reg litedramcore_re = 1'd0;
reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
reg litedramcore_phaseinjector0_command_re = 1'd0;
wire litedramcore_phaseinjector0_command_issue_re;
wire litedramcore_phaseinjector0_command_issue_r;
wire litedramcore_phaseinjector0_command_issue_we;
reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
reg litedramcore_phaseinjector0_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
reg litedramcore_phaseinjector0_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
wire litedramcore_phaseinjector0_we;
reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
reg litedramcore_phaseinjector1_command_re = 1'd0;
wire litedramcore_phaseinjector1_command_issue_re;
wire litedramcore_phaseinjector1_command_issue_r;
wire litedramcore_phaseinjector1_command_issue_we;
reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
reg litedramcore_phaseinjector1_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
reg litedramcore_phaseinjector1_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
wire litedramcore_phaseinjector1_we;
reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
reg litedramcore_phaseinjector2_command_re = 1'd0;
wire litedramcore_phaseinjector2_command_issue_re;
wire litedramcore_phaseinjector2_command_issue_r;
wire litedramcore_phaseinjector2_command_issue_we;
reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
reg litedramcore_phaseinjector2_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
reg litedramcore_phaseinjector2_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
wire litedramcore_phaseinjector2_we;
reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
reg litedramcore_phaseinjector3_command_re = 1'd0;
wire litedramcore_phaseinjector3_command_issue_re;
wire litedramcore_phaseinjector3_command_issue_r;
wire litedramcore_phaseinjector3_command_issue_we;
reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
reg litedramcore_phaseinjector3_address_re = 1'd0;
reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
reg litedramcore_phaseinjector3_baddress_re = 1'd0;
reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
wire litedramcore_phaseinjector3_we;
wire litedramcore_interface_bank0_valid;
wire litedramcore_interface_bank0_ready;
wire litedramcore_interface_bank0_we;
wire [20:0] litedramcore_interface_bank0_addr;
wire litedramcore_interface_bank0_lock;
wire litedramcore_interface_bank0_wdata_ready;
wire litedramcore_interface_bank0_rdata_valid;
wire litedramcore_interface_bank1_valid;
wire litedramcore_interface_bank1_ready;
wire litedramcore_interface_bank1_we;
wire [20:0] litedramcore_interface_bank1_addr;
wire litedramcore_interface_bank1_lock;
wire litedramcore_interface_bank1_wdata_ready;
wire litedramcore_interface_bank1_rdata_valid;
wire litedramcore_interface_bank2_valid;
wire litedramcore_interface_bank2_ready;
wire litedramcore_interface_bank2_we;
wire [20:0] litedramcore_interface_bank2_addr;
wire litedramcore_interface_bank2_lock;
wire litedramcore_interface_bank2_wdata_ready;
wire litedramcore_interface_bank2_rdata_valid;
wire litedramcore_interface_bank3_valid;
wire litedramcore_interface_bank3_ready;
wire litedramcore_interface_bank3_we;
wire [20:0] litedramcore_interface_bank3_addr;
wire litedramcore_interface_bank3_lock;
wire litedramcore_interface_bank3_wdata_ready;
wire litedramcore_interface_bank3_rdata_valid;
wire litedramcore_interface_bank4_valid;
wire litedramcore_interface_bank4_ready;
wire litedramcore_interface_bank4_we;
wire [20:0] litedramcore_interface_bank4_addr;
wire litedramcore_interface_bank4_lock;
wire litedramcore_interface_bank4_wdata_ready;
wire litedramcore_interface_bank4_rdata_valid;
wire litedramcore_interface_bank5_valid;
wire litedramcore_interface_bank5_ready;
wire litedramcore_interface_bank5_we;
wire [20:0] litedramcore_interface_bank5_addr;
wire litedramcore_interface_bank5_lock;
wire litedramcore_interface_bank5_wdata_ready;
wire litedramcore_interface_bank5_rdata_valid;
wire litedramcore_interface_bank6_valid;
wire litedramcore_interface_bank6_ready;
wire litedramcore_interface_bank6_we;
wire [20:0] litedramcore_interface_bank6_addr;
wire litedramcore_interface_bank6_lock;
wire litedramcore_interface_bank6_wdata_ready;
wire litedramcore_interface_bank6_rdata_valid;
wire litedramcore_interface_bank7_valid;
wire litedramcore_interface_bank7_ready;
wire litedramcore_interface_bank7_we;
wire [20:0] litedramcore_interface_bank7_addr;
wire litedramcore_interface_bank7_lock;
wire litedramcore_interface_bank7_wdata_ready;
wire litedramcore_interface_bank7_rdata_valid;
reg [127:0] litedramcore_interface_wdata = 128'd0;
reg [15:0] litedramcore_interface_wdata_we = 16'd0;
wire [127:0] litedramcore_interface_rdata;
reg [13:0] litedramcore_dfi_p0_address = 14'd0;
reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
reg litedramcore_dfi_p0_cas_n = 1'd1;
reg litedramcore_dfi_p0_cs_n = 1'd1;
reg litedramcore_dfi_p0_ras_n = 1'd1;
reg litedramcore_dfi_p0_we_n = 1'd1;
wire litedramcore_dfi_p0_cke;
wire litedramcore_dfi_p0_odt;
wire litedramcore_dfi_p0_reset_n;
reg litedramcore_dfi_p0_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p0_wrdata;
reg litedramcore_dfi_p0_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p0_wrdata_mask;
reg litedramcore_dfi_p0_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p0_rddata;
wire litedramcore_dfi_p0_rddata_valid;
reg [13:0] litedramcore_dfi_p1_address = 14'd0;
reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
reg litedramcore_dfi_p1_cas_n = 1'd1;
reg litedramcore_dfi_p1_cs_n = 1'd1;
reg litedramcore_dfi_p1_ras_n = 1'd1;
reg litedramcore_dfi_p1_we_n = 1'd1;
wire litedramcore_dfi_p1_cke;
wire litedramcore_dfi_p1_odt;
wire litedramcore_dfi_p1_reset_n;
reg litedramcore_dfi_p1_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p1_wrdata;
reg litedramcore_dfi_p1_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p1_wrdata_mask;
reg litedramcore_dfi_p1_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p1_rddata;
wire litedramcore_dfi_p1_rddata_valid;
reg [13:0] litedramcore_dfi_p2_address = 14'd0;
reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
reg litedramcore_dfi_p2_cas_n = 1'd1;
reg litedramcore_dfi_p2_cs_n = 1'd1;
reg litedramcore_dfi_p2_ras_n = 1'd1;
reg litedramcore_dfi_p2_we_n = 1'd1;
wire litedramcore_dfi_p2_cke;
wire litedramcore_dfi_p2_odt;
wire litedramcore_dfi_p2_reset_n;
reg litedramcore_dfi_p2_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p2_wrdata;
reg litedramcore_dfi_p2_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p2_wrdata_mask;
reg litedramcore_dfi_p2_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p2_rddata;
wire litedramcore_dfi_p2_rddata_valid;
reg [13:0] litedramcore_dfi_p3_address = 14'd0;
reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
reg litedramcore_dfi_p3_cas_n = 1'd1;
reg litedramcore_dfi_p3_cs_n = 1'd1;
reg litedramcore_dfi_p3_ras_n = 1'd1;
reg litedramcore_dfi_p3_we_n = 1'd1;
wire litedramcore_dfi_p3_cke;
wire litedramcore_dfi_p3_odt;
wire litedramcore_dfi_p3_reset_n;
reg litedramcore_dfi_p3_act_n = 1'd1;
wire [31:0] litedramcore_dfi_p3_wrdata;
reg litedramcore_dfi_p3_wrdata_en = 1'd0;
wire [3:0] litedramcore_dfi_p3_wrdata_mask;
reg litedramcore_dfi_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_dfi_p3_rddata;
wire litedramcore_dfi_p3_rddata_valid;
reg litedramcore_cmd_valid = 1'd0;
reg litedramcore_cmd_ready = 1'd0;
reg litedramcore_cmd_last = 1'd0;
reg [13:0] litedramcore_cmd_payload_a = 14'd0;
reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
reg litedramcore_cmd_payload_cas = 1'd0;
reg litedramcore_cmd_payload_ras = 1'd0;
reg litedramcore_cmd_payload_we = 1'd0;
reg litedramcore_cmd_payload_is_read = 1'd0;
reg litedramcore_cmd_payload_is_write = 1'd0;
wire litedramcore_wants_refresh;
wire litedramcore_wants_zqcs;
wire litedramcore_timer_wait;
wire litedramcore_timer_done0;
wire [9:0] litedramcore_timer_count0;
wire litedramcore_timer_done1;
reg [9:0] litedramcore_timer_count1 = 10'd781;
wire litedramcore_postponer_req_i;
reg litedramcore_postponer_req_o = 1'd0;
reg litedramcore_postponer_count = 1'd0;
reg litedramcore_sequencer_start0 = 1'd0;
wire litedramcore_sequencer_done0;
wire litedramcore_sequencer_start1;
reg litedramcore_sequencer_done1 = 1'd0;
reg [5:0] litedramcore_sequencer_counter = 6'd0;
reg litedramcore_sequencer_count = 1'd0;
wire litedramcore_zqcs_timer_wait;
wire litedramcore_zqcs_timer_done0;
wire [26:0] litedramcore_zqcs_timer_count0;
wire litedramcore_zqcs_timer_done1;
reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
reg litedramcore_zqcs_executer_start = 1'd0;
reg litedramcore_zqcs_executer_done = 1'd0;
reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
wire litedramcore_bankmachine0_req_valid;
wire litedramcore_bankmachine0_req_ready;
wire litedramcore_bankmachine0_req_we;
wire [20:0] litedramcore_bankmachine0_req_addr;
wire litedramcore_bankmachine0_req_lock;
reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine0_refresh_req;
reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
reg litedramcore_bankmachine0_cmd_valid = 1'd0;
reg litedramcore_bankmachine0_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine0_auto_precharge = 1'd0;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
wire litedramcore_bankmachine0_cmd_buffer_sink_first;
wire litedramcore_bankmachine0_cmd_buffer_sink_last;
wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine0_cmd_buffer_source_ready;
reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine0_row = 14'd0;
reg litedramcore_bankmachine0_row_opened = 1'd0;
wire litedramcore_bankmachine0_row_hit;
reg litedramcore_bankmachine0_row_open = 1'd0;
reg litedramcore_bankmachine0_row_close = 1'd0;
reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine0_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
wire litedramcore_bankmachine0_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
wire litedramcore_bankmachine0_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
wire litedramcore_bankmachine1_req_valid;
wire litedramcore_bankmachine1_req_ready;
wire litedramcore_bankmachine1_req_we;
wire [20:0] litedramcore_bankmachine1_req_addr;
wire litedramcore_bankmachine1_req_lock;
reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine1_refresh_req;
reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
reg litedramcore_bankmachine1_cmd_valid = 1'd0;
reg litedramcore_bankmachine1_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine1_auto_precharge = 1'd0;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
wire litedramcore_bankmachine1_cmd_buffer_sink_first;
wire litedramcore_bankmachine1_cmd_buffer_sink_last;
wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine1_cmd_buffer_source_ready;
reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine1_row = 14'd0;
reg litedramcore_bankmachine1_row_opened = 1'd0;
wire litedramcore_bankmachine1_row_hit;
reg litedramcore_bankmachine1_row_open = 1'd0;
reg litedramcore_bankmachine1_row_close = 1'd0;
reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine1_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
wire litedramcore_bankmachine1_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
wire litedramcore_bankmachine1_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
wire litedramcore_bankmachine2_req_valid;
wire litedramcore_bankmachine2_req_ready;
wire litedramcore_bankmachine2_req_we;
wire [20:0] litedramcore_bankmachine2_req_addr;
wire litedramcore_bankmachine2_req_lock;
reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine2_refresh_req;
reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
reg litedramcore_bankmachine2_cmd_valid = 1'd0;
reg litedramcore_bankmachine2_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine2_auto_precharge = 1'd0;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
wire litedramcore_bankmachine2_cmd_buffer_sink_first;
wire litedramcore_bankmachine2_cmd_buffer_sink_last;
wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine2_cmd_buffer_source_ready;
reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine2_row = 14'd0;
reg litedramcore_bankmachine2_row_opened = 1'd0;
wire litedramcore_bankmachine2_row_hit;
reg litedramcore_bankmachine2_row_open = 1'd0;
reg litedramcore_bankmachine2_row_close = 1'd0;
reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine2_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
wire litedramcore_bankmachine2_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
wire litedramcore_bankmachine2_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
wire litedramcore_bankmachine3_req_valid;
wire litedramcore_bankmachine3_req_ready;
wire litedramcore_bankmachine3_req_we;
wire [20:0] litedramcore_bankmachine3_req_addr;
wire litedramcore_bankmachine3_req_lock;
reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine3_refresh_req;
reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
reg litedramcore_bankmachine3_cmd_valid = 1'd0;
reg litedramcore_bankmachine3_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine3_auto_precharge = 1'd0;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
wire litedramcore_bankmachine3_cmd_buffer_sink_first;
wire litedramcore_bankmachine3_cmd_buffer_sink_last;
wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine3_cmd_buffer_source_ready;
reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine3_row = 14'd0;
reg litedramcore_bankmachine3_row_opened = 1'd0;
wire litedramcore_bankmachine3_row_hit;
reg litedramcore_bankmachine3_row_open = 1'd0;
reg litedramcore_bankmachine3_row_close = 1'd0;
reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine3_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
wire litedramcore_bankmachine3_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
wire litedramcore_bankmachine3_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
wire litedramcore_bankmachine4_req_valid;
wire litedramcore_bankmachine4_req_ready;
wire litedramcore_bankmachine4_req_we;
wire [20:0] litedramcore_bankmachine4_req_addr;
wire litedramcore_bankmachine4_req_lock;
reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine4_refresh_req;
reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
reg litedramcore_bankmachine4_cmd_valid = 1'd0;
reg litedramcore_bankmachine4_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine4_auto_precharge = 1'd0;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
wire litedramcore_bankmachine4_cmd_buffer_sink_first;
wire litedramcore_bankmachine4_cmd_buffer_sink_last;
wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine4_cmd_buffer_source_ready;
reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine4_row = 14'd0;
reg litedramcore_bankmachine4_row_opened = 1'd0;
wire litedramcore_bankmachine4_row_hit;
reg litedramcore_bankmachine4_row_open = 1'd0;
reg litedramcore_bankmachine4_row_close = 1'd0;
reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine4_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
wire litedramcore_bankmachine4_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
wire litedramcore_bankmachine4_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
wire litedramcore_bankmachine5_req_valid;
wire litedramcore_bankmachine5_req_ready;
wire litedramcore_bankmachine5_req_we;
wire [20:0] litedramcore_bankmachine5_req_addr;
wire litedramcore_bankmachine5_req_lock;
reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine5_refresh_req;
reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
reg litedramcore_bankmachine5_cmd_valid = 1'd0;
reg litedramcore_bankmachine5_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine5_auto_precharge = 1'd0;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
wire litedramcore_bankmachine5_cmd_buffer_sink_first;
wire litedramcore_bankmachine5_cmd_buffer_sink_last;
wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine5_cmd_buffer_source_ready;
reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine5_row = 14'd0;
reg litedramcore_bankmachine5_row_opened = 1'd0;
wire litedramcore_bankmachine5_row_hit;
reg litedramcore_bankmachine5_row_open = 1'd0;
reg litedramcore_bankmachine5_row_close = 1'd0;
reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine5_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
wire litedramcore_bankmachine5_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
wire litedramcore_bankmachine5_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
wire litedramcore_bankmachine6_req_valid;
wire litedramcore_bankmachine6_req_ready;
wire litedramcore_bankmachine6_req_we;
wire [20:0] litedramcore_bankmachine6_req_addr;
wire litedramcore_bankmachine6_req_lock;
reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine6_refresh_req;
reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
reg litedramcore_bankmachine6_cmd_valid = 1'd0;
reg litedramcore_bankmachine6_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine6_auto_precharge = 1'd0;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
wire litedramcore_bankmachine6_cmd_buffer_sink_first;
wire litedramcore_bankmachine6_cmd_buffer_sink_last;
wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine6_cmd_buffer_source_ready;
reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine6_row = 14'd0;
reg litedramcore_bankmachine6_row_opened = 1'd0;
wire litedramcore_bankmachine6_row_hit;
reg litedramcore_bankmachine6_row_open = 1'd0;
reg litedramcore_bankmachine6_row_close = 1'd0;
reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine6_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
wire litedramcore_bankmachine6_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
wire litedramcore_bankmachine6_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
wire litedramcore_bankmachine7_req_valid;
wire litedramcore_bankmachine7_req_ready;
wire litedramcore_bankmachine7_req_we;
wire [20:0] litedramcore_bankmachine7_req_addr;
wire litedramcore_bankmachine7_req_lock;
reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
wire litedramcore_bankmachine7_refresh_req;
reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
reg litedramcore_bankmachine7_cmd_valid = 1'd0;
reg litedramcore_bankmachine7_cmd_ready = 1'd0;
reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
reg litedramcore_bankmachine7_auto_precharge = 1'd0;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
wire litedramcore_bankmachine7_cmd_buffer_sink_first;
wire litedramcore_bankmachine7_cmd_buffer_sink_last;
wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
wire litedramcore_bankmachine7_cmd_buffer_source_ready;
reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] litedramcore_bankmachine7_row = 14'd0;
reg litedramcore_bankmachine7_row_opened = 1'd0;
wire litedramcore_bankmachine7_row_hit;
reg litedramcore_bankmachine7_row_open = 1'd0;
reg litedramcore_bankmachine7_row_close = 1'd0;
reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
wire litedramcore_bankmachine7_twtpcon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
wire litedramcore_bankmachine7_trccon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
wire litedramcore_bankmachine7_trascon_valid;
(* no_retiming = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
wire litedramcore_ras_allowed;
wire litedramcore_cas_allowed;
reg litedramcore_choose_cmd_want_reads = 1'd0;
reg litedramcore_choose_cmd_want_writes = 1'd0;
reg litedramcore_choose_cmd_want_cmds = 1'd0;
reg litedramcore_choose_cmd_want_activates = 1'd0;
wire litedramcore_choose_cmd_cmd_valid;
reg litedramcore_choose_cmd_cmd_ready = 1'd0;
wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
wire litedramcore_choose_cmd_cmd_payload_is_cmd;
wire litedramcore_choose_cmd_cmd_payload_is_read;
wire litedramcore_choose_cmd_cmd_payload_is_write;
reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
wire [7:0] litedramcore_choose_cmd_request;
reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
wire litedramcore_choose_cmd_ce;
reg litedramcore_choose_req_want_reads = 1'd0;
reg litedramcore_choose_req_want_writes = 1'd0;
reg litedramcore_choose_req_want_cmds = 1'd0;
reg litedramcore_choose_req_want_activates = 1'd0;
wire litedramcore_choose_req_cmd_valid;
reg litedramcore_choose_req_cmd_ready = 1'd0;
wire [13:0] litedramcore_choose_req_cmd_payload_a;
wire [2:0] litedramcore_choose_req_cmd_payload_ba;
reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
reg litedramcore_choose_req_cmd_payload_we = 1'd0;
wire litedramcore_choose_req_cmd_payload_is_cmd;
wire litedramcore_choose_req_cmd_payload_is_read;
wire litedramcore_choose_req_cmd_payload_is_write;
reg [7:0] litedramcore_choose_req_valids = 8'd0;
wire [7:0] litedramcore_choose_req_request;
reg [2:0] litedramcore_choose_req_grant = 3'd0;
wire litedramcore_choose_req_ce;
reg [13:0] litedramcore_nop_a = 14'd0;
reg [2:0] litedramcore_nop_ba = 3'd0;
reg [1:0] litedramcore_steerer_sel0 = 2'd0;
reg [1:0] litedramcore_steerer_sel1 = 2'd0;
reg [1:0] litedramcore_steerer_sel2 = 2'd0;
reg [1:0] litedramcore_steerer_sel3 = 2'd0;
reg litedramcore_steerer0 = 1'd1;
reg litedramcore_steerer1 = 1'd1;
reg litedramcore_steerer2 = 1'd1;
reg litedramcore_steerer3 = 1'd1;
reg litedramcore_steerer4 = 1'd1;
reg litedramcore_steerer5 = 1'd1;
reg litedramcore_steerer6 = 1'd1;
reg litedramcore_steerer7 = 1'd1;
wire litedramcore_trrdcon_valid;
(* no_retiming = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
reg litedramcore_trrdcon_count = 1'd0;
wire litedramcore_tfawcon_valid;
(* no_retiming = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
wire [2:0] litedramcore_tfawcon_count;
reg [4:0] litedramcore_tfawcon_window = 5'd0;
wire litedramcore_tccdcon_valid;
(* no_retiming = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
reg litedramcore_tccdcon_count = 1'd0;
wire litedramcore_twtrcon_valid;
(* no_retiming = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
reg [2:0] litedramcore_twtrcon_count = 3'd0;
wire litedramcore_read_available;
wire litedramcore_write_available;
reg litedramcore_en0 = 1'd0;
wire litedramcore_max_time0;
reg [4:0] litedramcore_time0 = 5'd0;
reg litedramcore_en1 = 1'd0;
wire litedramcore_max_time1;
reg [3:0] litedramcore_time1 = 4'd0;
wire litedramcore_go_to_refresh;
reg init_done_storage = 1'd0;
reg init_done_re = 1'd0;
reg init_error_storage = 1'd0;
reg init_error_re = 1'd0;
wire [29:0] wb_bus_adr;
wire [31:0] wb_bus_dat_w;
wire [31:0] wb_bus_dat_r;
wire [3:0] wb_bus_sel;
wire wb_bus_cyc;
wire wb_bus_stb;
wire wb_bus_ack;
wire wb_bus_we;
wire [2:0] wb_bus_cti;
wire [1:0] wb_bus_bte;
wire wb_bus_err;
wire user_port_cmd_valid;
wire user_port_cmd_ready;
wire user_port_cmd_payload_we;
wire [23:0] user_port_cmd_payload_addr;
wire user_port_wdata_valid;
wire user_port_wdata_ready;
wire [127:0] user_port_wdata_payload_data;
wire [15:0] user_port_wdata_payload_we;
wire user_port_rdata_valid;
wire user_port_rdata_ready;
wire [127:0] user_port_rdata_payload_data;
reg state = 1'd0;
reg next_state = 1'd0;
reg [1:0] refresher_state = 2'd0;
reg [1:0] refresher_next_state = 2'd0;
reg [3:0] bankmachine0_state = 4'd0;
reg [3:0] bankmachine0_next_state = 4'd0;
reg [3:0] bankmachine1_state = 4'd0;
reg [3:0] bankmachine1_next_state = 4'd0;
reg [3:0] bankmachine2_state = 4'd0;
reg [3:0] bankmachine2_next_state = 4'd0;
reg [3:0] bankmachine3_state = 4'd0;
reg [3:0] bankmachine3_next_state = 4'd0;
reg [3:0] bankmachine4_state = 4'd0;
reg [3:0] bankmachine4_next_state = 4'd0;
reg [3:0] bankmachine5_state = 4'd0;
reg [3:0] bankmachine5_next_state = 4'd0;
reg [3:0] bankmachine6_state = 4'd0;
reg [3:0] bankmachine6_next_state = 4'd0;
reg [3:0] bankmachine7_state = 4'd0;
reg [3:0] bankmachine7_next_state = 4'd0;
reg [3:0] multiplexer_state = 4'd0;
reg [3:0] multiplexer_next_state = 4'd0;
wire roundrobin0_request;
wire roundrobin0_grant;
wire roundrobin0_ce;
wire roundrobin1_request;
wire roundrobin1_grant;
wire roundrobin1_ce;
wire roundrobin2_request;
wire roundrobin2_grant;
wire roundrobin2_ce;
wire roundrobin3_request;
wire roundrobin3_grant;
wire roundrobin3_ce;
wire roundrobin4_request;
wire roundrobin4_grant;
wire roundrobin4_ce;
wire roundrobin5_request;
wire roundrobin5_grant;
wire roundrobin5_ce;
wire roundrobin6_request;
wire roundrobin6_grant;
wire roundrobin6_ce;
wire roundrobin7_request;
wire roundrobin7_grant;
wire roundrobin7_ce;
reg locked0 = 1'd0;
reg locked1 = 1'd0;
reg locked2 = 1'd0;
reg locked3 = 1'd0;
reg locked4 = 1'd0;
reg locked5 = 1'd0;
reg locked6 = 1'd0;
reg locked7 = 1'd0;
reg new_master_wdata_ready0 = 1'd0;
reg new_master_wdata_ready1 = 1'd0;
reg new_master_wdata_ready2 = 1'd0;
reg new_master_rdata_valid0 = 1'd0;
reg new_master_rdata_valid1 = 1'd0;
reg new_master_rdata_valid2 = 1'd0;
reg new_master_rdata_valid3 = 1'd0;
reg new_master_rdata_valid4 = 1'd0;
reg new_master_rdata_valid5 = 1'd0;
reg new_master_rdata_valid6 = 1'd0;
reg new_master_rdata_valid7 = 1'd0;
reg new_master_rdata_valid8 = 1'd0;
reg new_master_rdata_valid9 = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
wire [31:0] interface0_bank_bus_dat_w;
reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we;
wire csrbank0_init_done0_w;
wire csrbank0_init_error0_re;
wire csrbank0_init_error0_r;
wire csrbank0_init_error0_we;
wire csrbank0_init_error0_w;
wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire [31:0] interface1_bank_bus_dat_w;
reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_dfii_control0_re;
wire [3:0] csrbank1_dfii_control0_r;
wire csrbank1_dfii_control0_we;
wire [3:0] csrbank1_dfii_control0_w;
wire csrbank1_dfii_pi0_command0_re;
wire [5:0] csrbank1_dfii_pi0_command0_r;
wire csrbank1_dfii_pi0_command0_we;
wire [5:0] csrbank1_dfii_pi0_command0_w;
wire csrbank1_dfii_pi0_address0_re;
wire [13:0] csrbank1_dfii_pi0_address0_r;
wire csrbank1_dfii_pi0_address0_we;
wire [13:0] csrbank1_dfii_pi0_address0_w;
wire csrbank1_dfii_pi0_baddress0_re;
wire [2:0] csrbank1_dfii_pi0_baddress0_r;
wire csrbank1_dfii_pi0_baddress0_we;
wire [2:0] csrbank1_dfii_pi0_baddress0_w;
wire csrbank1_dfii_pi0_wrdata0_re;
wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
wire csrbank1_dfii_pi0_wrdata0_we;
wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
wire csrbank1_dfii_pi0_rddata_re;
wire [31:0] csrbank1_dfii_pi0_rddata_r;
wire csrbank1_dfii_pi0_rddata_we;
wire [31:0] csrbank1_dfii_pi0_rddata_w;
wire csrbank1_dfii_pi1_command0_re;
wire [5:0] csrbank1_dfii_pi1_command0_r;
wire csrbank1_dfii_pi1_command0_we;
wire [5:0] csrbank1_dfii_pi1_command0_w;
wire csrbank1_dfii_pi1_address0_re;
wire [13:0] csrbank1_dfii_pi1_address0_r;
wire csrbank1_dfii_pi1_address0_we;
wire [13:0] csrbank1_dfii_pi1_address0_w;
wire csrbank1_dfii_pi1_baddress0_re;
wire [2:0] csrbank1_dfii_pi1_baddress0_r;
wire csrbank1_dfii_pi1_baddress0_we;
wire [2:0] csrbank1_dfii_pi1_baddress0_w;
wire csrbank1_dfii_pi1_wrdata0_re;
wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
wire csrbank1_dfii_pi1_wrdata0_we;
wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
wire csrbank1_dfii_pi1_rddata_re;
wire [31:0] csrbank1_dfii_pi1_rddata_r;
wire csrbank1_dfii_pi1_rddata_we;
wire [31:0] csrbank1_dfii_pi1_rddata_w;
wire csrbank1_dfii_pi2_command0_re;
wire [5:0] csrbank1_dfii_pi2_command0_r;
wire csrbank1_dfii_pi2_command0_we;
wire [5:0] csrbank1_dfii_pi2_command0_w;
wire csrbank1_dfii_pi2_address0_re;
wire [13:0] csrbank1_dfii_pi2_address0_r;
wire csrbank1_dfii_pi2_address0_we;
wire [13:0] csrbank1_dfii_pi2_address0_w;
wire csrbank1_dfii_pi2_baddress0_re;
wire [2:0] csrbank1_dfii_pi2_baddress0_r;
wire csrbank1_dfii_pi2_baddress0_we;
wire [2:0] csrbank1_dfii_pi2_baddress0_w;
wire csrbank1_dfii_pi2_wrdata0_re;
wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
wire csrbank1_dfii_pi2_wrdata0_we;
wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
wire csrbank1_dfii_pi2_rddata_re;
wire [31:0] csrbank1_dfii_pi2_rddata_r;
wire csrbank1_dfii_pi2_rddata_we;
wire [31:0] csrbank1_dfii_pi2_rddata_w;
wire csrbank1_dfii_pi3_command0_re;
wire [5:0] csrbank1_dfii_pi3_command0_r;
wire csrbank1_dfii_pi3_command0_we;
wire [5:0] csrbank1_dfii_pi3_command0_w;
wire csrbank1_dfii_pi3_address0_re;
wire [13:0] csrbank1_dfii_pi3_address0_r;
wire csrbank1_dfii_pi3_address0_we;
wire [13:0] csrbank1_dfii_pi3_address0_w;
wire csrbank1_dfii_pi3_baddress0_re;
wire [2:0] csrbank1_dfii_pi3_baddress0_r;
wire csrbank1_dfii_pi3_baddress0_we;
wire [2:0] csrbank1_dfii_pi3_baddress0_w;
wire csrbank1_dfii_pi3_wrdata0_re;
wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
wire csrbank1_dfii_pi3_wrdata0_we;
wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
wire csrbank1_dfii_pi3_rddata_re;
wire [31:0] csrbank1_dfii_pi3_rddata_r;
wire csrbank1_dfii_pi3_rddata_we;
wire [31:0] csrbank1_dfii_pi3_rddata_w;
wire csrbank1_sel;
wire [13:0] adr;
wire we;
wire [31:0] dat_w;
wire [31:0] dat_r;
wire [24:0] slice_proxy0;
wire [24:0] slice_proxy1;
wire [24:0] slice_proxy2;
wire [24:0] slice_proxy3;
wire [24:0] slice_proxy4;
wire [24:0] slice_proxy5;
wire [24:0] slice_proxy6;
wire [24:0] slice_proxy7;
wire [24:0] slice_proxy8;
wire [24:0] slice_proxy9;
wire [24:0] slice_proxy10;
wire [24:0] slice_proxy11;
wire [24:0] slice_proxy12;
wire [24:0] slice_proxy13;
wire [24:0] slice_proxy14;
wire [24:0] slice_proxy15;
reg rhs_array_muxed0 = 1'd0;
reg [13:0] rhs_array_muxed1 = 14'd0;
reg [2:0] rhs_array_muxed2 = 3'd0;
reg rhs_array_muxed3 = 1'd0;
reg rhs_array_muxed4 = 1'd0;
reg rhs_array_muxed5 = 1'd0;
reg t_array_muxed0 = 1'd0;
reg t_array_muxed1 = 1'd0;
reg t_array_muxed2 = 1'd0;
reg rhs_array_muxed6 = 1'd0;
reg [13:0] rhs_array_muxed7 = 14'd0;
reg [2:0] rhs_array_muxed8 = 3'd0;
reg rhs_array_muxed9 = 1'd0;
reg rhs_array_muxed10 = 1'd0;
reg rhs_array_muxed11 = 1'd0;
reg t_array_muxed3 = 1'd0;
reg t_array_muxed4 = 1'd0;
reg t_array_muxed5 = 1'd0;
reg [20:0] rhs_array_muxed12 = 21'd0;
reg rhs_array_muxed13 = 1'd0;
reg rhs_array_muxed14 = 1'd0;
reg [20:0] rhs_array_muxed15 = 21'd0;
reg rhs_array_muxed16 = 1'd0;
reg rhs_array_muxed17 = 1'd0;
reg [20:0] rhs_array_muxed18 = 21'd0;
reg rhs_array_muxed19 = 1'd0;
reg rhs_array_muxed20 = 1'd0;
reg [20:0] rhs_array_muxed21 = 21'd0;
reg rhs_array_muxed22 = 1'd0;
reg rhs_array_muxed23 = 1'd0;
reg [20:0] rhs_array_muxed24 = 21'd0;
reg rhs_array_muxed25 = 1'd0;
reg rhs_array_muxed26 = 1'd0;
reg [20:0] rhs_array_muxed27 = 21'd0;
reg rhs_array_muxed28 = 1'd0;
reg rhs_array_muxed29 = 1'd0;
reg [20:0] rhs_array_muxed30 = 21'd0;
reg rhs_array_muxed31 = 1'd0;
reg rhs_array_muxed32 = 1'd0;
reg [20:0] rhs_array_muxed33 = 21'd0;
reg rhs_array_muxed34 = 1'd0;
reg rhs_array_muxed35 = 1'd0;
reg [2:0] array_muxed0 = 3'd0;
reg [13:0] array_muxed1 = 14'd0;
reg array_muxed2 = 1'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg array_muxed6 = 1'd0;
reg [2:0] array_muxed7 = 3'd0;
reg [13:0] array_muxed8 = 14'd0;
reg array_muxed9 = 1'd0;
reg array_muxed10 = 1'd0;
reg array_muxed11 = 1'd0;
reg array_muxed12 = 1'd0;
reg array_muxed13 = 1'd0;
reg [2:0] array_muxed14 = 3'd0;
reg [13:0] array_muxed15 = 14'd0;
reg array_muxed16 = 1'd0;
reg array_muxed17 = 1'd0;
reg array_muxed18 = 1'd0;
reg array_muxed19 = 1'd0;
reg array_muxed20 = 1'd0;
reg [2:0] array_muxed21 = 3'd0;
reg [13:0] array_muxed22 = 14'd0;
reg array_muxed23 = 1'd0;
reg array_muxed24 = 1'd0;
reg array_muxed25 = 1'd0;
reg array_muxed26 = 1'd0;
reg array_muxed27 = 1'd0;

assign init_done = init_done_storage;
assign init_error = init_error_storage;
assign wb_bus_adr = wb_ctrl_adr;
assign wb_bus_dat_w = wb_ctrl_dat_w;
assign wb_ctrl_dat_r = wb_bus_dat_r;
assign wb_bus_sel = wb_ctrl_sel;
assign wb_bus_cyc = wb_ctrl_cyc;
assign wb_bus_stb = wb_ctrl_stb;
assign wb_ctrl_ack = wb_bus_ack;
assign wb_bus_we = wb_ctrl_we;
assign wb_bus_cti = wb_ctrl_cti;
assign wb_bus_bte = wb_ctrl_bte;
assign wb_ctrl_err = wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign user_port_cmd_valid = user_port_native_0_cmd_valid;
assign user_port_native_0_cmd_ready = user_port_cmd_ready;
assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
assign user_port_wdata_valid = user_port_native_0_wdata_valid;
assign user_port_native_0_wdata_ready = user_port_wdata_ready;
assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
assign user_port_native_0_rdata_valid = user_port_rdata_valid;
assign user_port_rdata_ready = user_port_native_0_rdata_ready;
assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
assign litedramcore_wishbone_dat_r = litedramcore_dat_r;
always @(*) begin
	next_state = 1'd0;
	next_state = state;
	case (state)
		1'd1: begin
			next_state = 1'd0;
		end
		default: begin
			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
				next_state = 1'd1;
			end
		end
	endcase
end
always @(*) begin
	litedramcore_wishbone_ack = 1'd0;
	case (state)
		1'd1: begin
			litedramcore_wishbone_ack = 1'd1;
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_adr = 14'd0;
	case (state)
		1'd1: begin
		end
		default: begin
			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
				litedramcore_adr = litedramcore_wishbone_adr;
			end
		end
	endcase
end
always @(*) begin
	litedramcore_we = 1'd0;
	case (state)
		1'd1: begin
		end
		default: begin
			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
				litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
			end
		end
	endcase
end
assign sys_clk = clk;
assign por_clk = clk;
assign sys_rst = int_rst;
always @(*) begin
	ddrphy_activates0 = 4'd0;
	ddrphy_activates0[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates0[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates0[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates0[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel0_activate_row = 14'd0;
	case (ddrphy_activates0)
		1'd1: begin
			ddrphy_bankmodel0_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel0_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel0_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel0_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel0_activate = 1'd0;
	case (ddrphy_activates0)
		1'd1: begin
			ddrphy_bankmodel0_activate = (ddrphy_dfi_p0_bank == 1'd0);
		end
		2'd2: begin
			ddrphy_bankmodel0_activate = (ddrphy_dfi_p1_bank == 1'd0);
		end
		3'd4: begin
			ddrphy_bankmodel0_activate = (ddrphy_dfi_p2_bank == 1'd0);
		end
		4'd8: begin
			ddrphy_bankmodel0_activate = (ddrphy_dfi_p3_bank == 1'd0);
		end
	endcase
end
always @(*) begin
	ddrphy_precharges0 = 4'd0;
	ddrphy_precharges0[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges0[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges0[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges0[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel0_precharge = 1'd0;
	case (ddrphy_precharges0)
		1'd1: begin
			ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes0 = 4'd0;
	ddrphy_writes0[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes0[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes0[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write0 = 1'd0;
	case (ddrphy_writes0)
		1'd1: begin
			ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0);
		end
		2'd2: begin
			ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0);
		end
		3'd4: begin
			ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0);
		end
		4'd8: begin
			ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0);
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write_col0 = 10'd0;
	case (ddrphy_writes0)
		1'd1: begin
			ddrphy_bank_write_col0 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col0 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col0 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col0 = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_bankmodel0_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel0_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel0_write = ddrphy_new_bank_write1;
assign ddrphy_bankmodel0_write_col = ddrphy_new_bank_write_col1;
always @(*) begin
	ddrphy_reads0 = 4'd0;
	ddrphy_reads0[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads0[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads0[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads0[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel0_read = 1'd0;
	case (ddrphy_reads0)
		1'd1: begin
			ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0);
		end
		2'd2: begin
			ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0);
		end
		3'd4: begin
			ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0);
		end
		4'd8: begin
			ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel0_read_col = 10'd0;
	case (ddrphy_reads0)
		1'd1: begin
			ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_activates1 = 4'd0;
	ddrphy_activates1[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates1[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates1[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates1[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel1_activate = 1'd0;
	case (ddrphy_activates1)
		1'd1: begin
			ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1);
		end
		2'd2: begin
			ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1);
		end
		3'd4: begin
			ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1);
		end
		4'd8: begin
			ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel1_activate_row = 14'd0;
	case (ddrphy_activates1)
		1'd1: begin
			ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_precharges1 = 4'd0;
	ddrphy_precharges1[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges1[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges1[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges1[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel1_precharge = 1'd0;
	case (ddrphy_precharges1)
		1'd1: begin
			ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes1 = 4'd0;
	ddrphy_writes1[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes1[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes1[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes1[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write1 = 1'd0;
	case (ddrphy_writes1)
		1'd1: begin
			ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1);
		end
		2'd2: begin
			ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1);
		end
		3'd4: begin
			ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1);
		end
		4'd8: begin
			ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1);
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write_col1 = 10'd0;
	case (ddrphy_writes1)
		1'd1: begin
			ddrphy_bank_write_col1 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col1 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col1 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col1 = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_bankmodel1_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel1_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel1_write = ddrphy_new_bank_write3;
assign ddrphy_bankmodel1_write_col = ddrphy_new_bank_write_col3;
always @(*) begin
	ddrphy_reads1 = 4'd0;
	ddrphy_reads1[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads1[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads1[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads1[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel1_read = 1'd0;
	case (ddrphy_reads1)
		1'd1: begin
			ddrphy_bankmodel1_read = (ddrphy_dfi_p0_bank == 1'd1);
		end
		2'd2: begin
			ddrphy_bankmodel1_read = (ddrphy_dfi_p1_bank == 1'd1);
		end
		3'd4: begin
			ddrphy_bankmodel1_read = (ddrphy_dfi_p2_bank == 1'd1);
		end
		4'd8: begin
			ddrphy_bankmodel1_read = (ddrphy_dfi_p3_bank == 1'd1);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel1_read_col = 10'd0;
	case (ddrphy_reads1)
		1'd1: begin
			ddrphy_bankmodel1_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel1_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel1_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel1_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_activates2 = 4'd0;
	ddrphy_activates2[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates2[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates2[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates2[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel2_activate = 1'd0;
	case (ddrphy_activates2)
		1'd1: begin
			ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2);
		end
		2'd2: begin
			ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2);
		end
		3'd4: begin
			ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2);
		end
		4'd8: begin
			ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel2_activate_row = 14'd0;
	case (ddrphy_activates2)
		1'd1: begin
			ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_precharges2 = 4'd0;
	ddrphy_precharges2[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges2[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges2[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges2[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel2_precharge = 1'd0;
	case (ddrphy_precharges2)
		1'd1: begin
			ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes2 = 4'd0;
	ddrphy_writes2[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes2[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes2[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes2[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write_col2 = 10'd0;
	case (ddrphy_writes2)
		1'd1: begin
			ddrphy_bank_write_col2 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col2 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col2 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col2 = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write2 = 1'd0;
	case (ddrphy_writes2)
		1'd1: begin
			ddrphy_bank_write2 = (ddrphy_dfi_p0_bank == 2'd2);
		end
		2'd2: begin
			ddrphy_bank_write2 = (ddrphy_dfi_p1_bank == 2'd2);
		end
		3'd4: begin
			ddrphy_bank_write2 = (ddrphy_dfi_p2_bank == 2'd2);
		end
		4'd8: begin
			ddrphy_bank_write2 = (ddrphy_dfi_p3_bank == 2'd2);
		end
	endcase
end
assign ddrphy_bankmodel2_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel2_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel2_write = ddrphy_new_bank_write5;
assign ddrphy_bankmodel2_write_col = ddrphy_new_bank_write_col5;
always @(*) begin
	ddrphy_reads2 = 4'd0;
	ddrphy_reads2[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads2[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads2[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel2_read = 1'd0;
	case (ddrphy_reads2)
		1'd1: begin
			ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2);
		end
		2'd2: begin
			ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2);
		end
		3'd4: begin
			ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2);
		end
		4'd8: begin
			ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel2_read_col = 10'd0;
	case (ddrphy_reads2)
		1'd1: begin
			ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_activates3 = 4'd0;
	ddrphy_activates3[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates3[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates3[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates3[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel3_activate = 1'd0;
	case (ddrphy_activates3)
		1'd1: begin
			ddrphy_bankmodel3_activate = (ddrphy_dfi_p0_bank == 2'd3);
		end
		2'd2: begin
			ddrphy_bankmodel3_activate = (ddrphy_dfi_p1_bank == 2'd3);
		end
		3'd4: begin
			ddrphy_bankmodel3_activate = (ddrphy_dfi_p2_bank == 2'd3);
		end
		4'd8: begin
			ddrphy_bankmodel3_activate = (ddrphy_dfi_p3_bank == 2'd3);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel3_activate_row = 14'd0;
	case (ddrphy_activates3)
		1'd1: begin
			ddrphy_bankmodel3_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel3_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel3_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel3_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_precharges3 = 4'd0;
	ddrphy_precharges3[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges3[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges3[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges3[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel3_precharge = 1'd0;
	case (ddrphy_precharges3)
		1'd1: begin
			ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes3 = 4'd0;
	ddrphy_writes3[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes3[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes3[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes3[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write3 = 1'd0;
	case (ddrphy_writes3)
		1'd1: begin
			ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3);
		end
		2'd2: begin
			ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3);
		end
		3'd4: begin
			ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3);
		end
		4'd8: begin
			ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3);
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write_col3 = 10'd0;
	case (ddrphy_writes3)
		1'd1: begin
			ddrphy_bank_write_col3 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col3 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col3 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col3 = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_bankmodel3_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel3_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel3_write = ddrphy_new_bank_write7;
assign ddrphy_bankmodel3_write_col = ddrphy_new_bank_write_col7;
always @(*) begin
	ddrphy_reads3 = 4'd0;
	ddrphy_reads3[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads3[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads3[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads3[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel3_read_col = 10'd0;
	case (ddrphy_reads3)
		1'd1: begin
			ddrphy_bankmodel3_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel3_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel3_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel3_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel3_read = 1'd0;
	case (ddrphy_reads3)
		1'd1: begin
			ddrphy_bankmodel3_read = (ddrphy_dfi_p0_bank == 2'd3);
		end
		2'd2: begin
			ddrphy_bankmodel3_read = (ddrphy_dfi_p1_bank == 2'd3);
		end
		3'd4: begin
			ddrphy_bankmodel3_read = (ddrphy_dfi_p2_bank == 2'd3);
		end
		4'd8: begin
			ddrphy_bankmodel3_read = (ddrphy_dfi_p3_bank == 2'd3);
		end
	endcase
end
always @(*) begin
	ddrphy_activates4 = 4'd0;
	ddrphy_activates4[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates4[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates4[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel4_activate = 1'd0;
	case (ddrphy_activates4)
		1'd1: begin
			ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4);
		end
		2'd2: begin
			ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4);
		end
		3'd4: begin
			ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4);
		end
		4'd8: begin
			ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel4_activate_row = 14'd0;
	case (ddrphy_activates4)
		1'd1: begin
			ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_precharges4 = 4'd0;
	ddrphy_precharges4[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges4[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges4[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges4[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel4_precharge = 1'd0;
	case (ddrphy_precharges4)
		1'd1: begin
			ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes4 = 4'd0;
	ddrphy_writes4[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes4[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes4[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write4 = 1'd0;
	case (ddrphy_writes4)
		1'd1: begin
			ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4);
		end
		2'd2: begin
			ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4);
		end
		3'd4: begin
			ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4);
		end
		4'd8: begin
			ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4);
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write_col4 = 10'd0;
	case (ddrphy_writes4)
		1'd1: begin
			ddrphy_bank_write_col4 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col4 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col4 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col4 = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_bankmodel4_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel4_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel4_write = ddrphy_new_bank_write9;
assign ddrphy_bankmodel4_write_col = ddrphy_new_bank_write_col9;
always @(*) begin
	ddrphy_reads4 = 4'd0;
	ddrphy_reads4[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads4[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads4[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads4[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel4_read = 1'd0;
	case (ddrphy_reads4)
		1'd1: begin
			ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4);
		end
		2'd2: begin
			ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4);
		end
		3'd4: begin
			ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4);
		end
		4'd8: begin
			ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel4_read_col = 10'd0;
	case (ddrphy_reads4)
		1'd1: begin
			ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_activates5 = 4'd0;
	ddrphy_activates5[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates5[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates5[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates5[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel5_activate_row = 14'd0;
	case (ddrphy_activates5)
		1'd1: begin
			ddrphy_bankmodel5_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel5_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel5_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel5_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel5_activate = 1'd0;
	case (ddrphy_activates5)
		1'd1: begin
			ddrphy_bankmodel5_activate = (ddrphy_dfi_p0_bank == 3'd5);
		end
		2'd2: begin
			ddrphy_bankmodel5_activate = (ddrphy_dfi_p1_bank == 3'd5);
		end
		3'd4: begin
			ddrphy_bankmodel5_activate = (ddrphy_dfi_p2_bank == 3'd5);
		end
		4'd8: begin
			ddrphy_bankmodel5_activate = (ddrphy_dfi_p3_bank == 3'd5);
		end
	endcase
end
always @(*) begin
	ddrphy_precharges5 = 4'd0;
	ddrphy_precharges5[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges5[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges5[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges5[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel5_precharge = 1'd0;
	case (ddrphy_precharges5)
		1'd1: begin
			ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes5 = 4'd0;
	ddrphy_writes5[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes5[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes5[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes5[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write5 = 1'd0;
	case (ddrphy_writes5)
		1'd1: begin
			ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5);
		end
		2'd2: begin
			ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5);
		end
		3'd4: begin
			ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5);
		end
		4'd8: begin
			ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5);
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write_col5 = 10'd0;
	case (ddrphy_writes5)
		1'd1: begin
			ddrphy_bank_write_col5 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col5 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col5 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col5 = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_bankmodel5_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel5_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel5_write = ddrphy_new_bank_write11;
assign ddrphy_bankmodel5_write_col = ddrphy_new_bank_write_col11;
always @(*) begin
	ddrphy_reads5 = 4'd0;
	ddrphy_reads5[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads5[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads5[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads5[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel5_read = 1'd0;
	case (ddrphy_reads5)
		1'd1: begin
			ddrphy_bankmodel5_read = (ddrphy_dfi_p0_bank == 3'd5);
		end
		2'd2: begin
			ddrphy_bankmodel5_read = (ddrphy_dfi_p1_bank == 3'd5);
		end
		3'd4: begin
			ddrphy_bankmodel5_read = (ddrphy_dfi_p2_bank == 3'd5);
		end
		4'd8: begin
			ddrphy_bankmodel5_read = (ddrphy_dfi_p3_bank == 3'd5);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel5_read_col = 10'd0;
	case (ddrphy_reads5)
		1'd1: begin
			ddrphy_bankmodel5_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel5_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel5_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel5_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_activates6 = 4'd0;
	ddrphy_activates6[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates6[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates6[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates6[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel6_activate = 1'd0;
	case (ddrphy_activates6)
		1'd1: begin
			ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6);
		end
		2'd2: begin
			ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6);
		end
		3'd4: begin
			ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6);
		end
		4'd8: begin
			ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel6_activate_row = 14'd0;
	case (ddrphy_activates6)
		1'd1: begin
			ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_precharges6 = 4'd0;
	ddrphy_precharges6[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges6[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges6[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges6[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel6_precharge = 1'd0;
	case (ddrphy_precharges6)
		1'd1: begin
			ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes6 = 4'd0;
	ddrphy_writes6[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes6[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes6[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes6[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write_col6 = 10'd0;
	case (ddrphy_writes6)
		1'd1: begin
			ddrphy_bank_write_col6 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col6 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col6 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col6 = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write6 = 1'd0;
	case (ddrphy_writes6)
		1'd1: begin
			ddrphy_bank_write6 = (ddrphy_dfi_p0_bank == 3'd6);
		end
		2'd2: begin
			ddrphy_bank_write6 = (ddrphy_dfi_p1_bank == 3'd6);
		end
		3'd4: begin
			ddrphy_bank_write6 = (ddrphy_dfi_p2_bank == 3'd6);
		end
		4'd8: begin
			ddrphy_bank_write6 = (ddrphy_dfi_p3_bank == 3'd6);
		end
	endcase
end
assign ddrphy_bankmodel6_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel6_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel6_write = ddrphy_new_bank_write13;
assign ddrphy_bankmodel6_write_col = ddrphy_new_bank_write_col13;
always @(*) begin
	ddrphy_reads6 = 4'd0;
	ddrphy_reads6[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads6[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads6[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads6[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel6_read_col = 10'd0;
	case (ddrphy_reads6)
		1'd1: begin
			ddrphy_bankmodel6_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel6_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel6_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel6_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel6_read = 1'd0;
	case (ddrphy_reads6)
		1'd1: begin
			ddrphy_bankmodel6_read = (ddrphy_dfi_p0_bank == 3'd6);
		end
		2'd2: begin
			ddrphy_bankmodel6_read = (ddrphy_dfi_p1_bank == 3'd6);
		end
		3'd4: begin
			ddrphy_bankmodel6_read = (ddrphy_dfi_p2_bank == 3'd6);
		end
		4'd8: begin
			ddrphy_bankmodel6_read = (ddrphy_dfi_p3_bank == 3'd6);
		end
	endcase
end
always @(*) begin
	ddrphy_activates7 = 4'd0;
	ddrphy_activates7[0] = ddrphy_dfiphasemodel0_activate;
	ddrphy_activates7[1] = ddrphy_dfiphasemodel1_activate;
	ddrphy_activates7[2] = ddrphy_dfiphasemodel2_activate;
	ddrphy_activates7[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
	ddrphy_bankmodel7_activate = 1'd0;
	case (ddrphy_activates7)
		1'd1: begin
			ddrphy_bankmodel7_activate = (ddrphy_dfi_p0_bank == 3'd7);
		end
		2'd2: begin
			ddrphy_bankmodel7_activate = (ddrphy_dfi_p1_bank == 3'd7);
		end
		3'd4: begin
			ddrphy_bankmodel7_activate = (ddrphy_dfi_p2_bank == 3'd7);
		end
		4'd8: begin
			ddrphy_bankmodel7_activate = (ddrphy_dfi_p3_bank == 3'd7);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel7_activate_row = 14'd0;
	case (ddrphy_activates7)
		1'd1: begin
			ddrphy_bankmodel7_activate_row = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel7_activate_row = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel7_activate_row = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel7_activate_row = ddrphy_dfi_p3_address;
		end
	endcase
end
always @(*) begin
	ddrphy_precharges7 = 4'd0;
	ddrphy_precharges7[0] = ddrphy_dfiphasemodel0_precharge;
	ddrphy_precharges7[1] = ddrphy_dfiphasemodel1_precharge;
	ddrphy_precharges7[2] = ddrphy_dfiphasemodel2_precharge;
	ddrphy_precharges7[3] = ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
	ddrphy_bankmodel7_precharge = 1'd0;
	case (ddrphy_precharges7)
		1'd1: begin
			ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfi_p0_address[10]);
		end
		2'd2: begin
			ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfi_p1_address[10]);
		end
		3'd4: begin
			ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfi_p2_address[10]);
		end
		4'd8: begin
			ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfi_p3_address[10]);
		end
	endcase
end
always @(*) begin
	ddrphy_writes7 = 4'd0;
	ddrphy_writes7[0] = ddrphy_dfiphasemodel0_write;
	ddrphy_writes7[1] = ddrphy_dfiphasemodel1_write;
	ddrphy_writes7[2] = ddrphy_dfiphasemodel2_write;
	ddrphy_writes7[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
	ddrphy_bank_write7 = 1'd0;
	case (ddrphy_writes7)
		1'd1: begin
			ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7);
		end
		2'd2: begin
			ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7);
		end
		3'd4: begin
			ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7);
		end
		4'd8: begin
			ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7);
		end
	endcase
end
always @(*) begin
	ddrphy_bank_write_col7 = 10'd0;
	case (ddrphy_writes7)
		1'd1: begin
			ddrphy_bank_write_col7 = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bank_write_col7 = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bank_write_col7 = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bank_write_col7 = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_bankmodel7_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
assign ddrphy_bankmodel7_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
assign ddrphy_bankmodel7_write = ddrphy_new_bank_write15;
assign ddrphy_bankmodel7_write_col = ddrphy_new_bank_write_col15;
always @(*) begin
	ddrphy_reads7 = 4'd0;
	ddrphy_reads7[0] = ddrphy_dfiphasemodel0_read;
	ddrphy_reads7[1] = ddrphy_dfiphasemodel1_read;
	ddrphy_reads7[2] = ddrphy_dfiphasemodel2_read;
	ddrphy_reads7[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
	ddrphy_bankmodel7_read = 1'd0;
	case (ddrphy_reads7)
		1'd1: begin
			ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7);
		end
		2'd2: begin
			ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7);
		end
		3'd4: begin
			ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7);
		end
		4'd8: begin
			ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7);
		end
	endcase
end
always @(*) begin
	ddrphy_bankmodel7_read_col = 10'd0;
	case (ddrphy_reads7)
		1'd1: begin
			ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address;
		end
		2'd2: begin
			ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address;
		end
		3'd4: begin
			ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address;
		end
		4'd8: begin
			ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address;
		end
	endcase
end
assign ddrphy_banks_read = (((((((ddrphy_bankmodel0_read | ddrphy_bankmodel1_read) | ddrphy_bankmodel2_read) | ddrphy_bankmodel3_read) | ddrphy_bankmodel4_read) | ddrphy_bankmodel5_read) | ddrphy_bankmodel6_read) | ddrphy_bankmodel7_read);
assign ddrphy_banks_read_data = (((((((ddrphy_bankmodel0_read_data | ddrphy_bankmodel1_read_data) | ddrphy_bankmodel2_read_data) | ddrphy_bankmodel3_read_data) | ddrphy_bankmodel4_read_data) | ddrphy_bankmodel5_read_data) | ddrphy_bankmodel6_read_data) | ddrphy_bankmodel7_read_data);
assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
always @(*) begin
	ddrphy_dfiphasemodel0_precharge = 1'd0;
	if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin
		ddrphy_dfiphasemodel0_precharge = (~ddrphy_dfi_p0_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel0_activate = 1'd0;
	if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin
		ddrphy_dfiphasemodel0_activate = ddrphy_dfi_p0_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel0_write = 1'd0;
	if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin
		ddrphy_dfiphasemodel0_write = (~ddrphy_dfi_p0_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel0_read = 1'd0;
	if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin
		ddrphy_dfiphasemodel0_read = ddrphy_dfi_p0_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel1_activate = 1'd0;
	if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin
		ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel1_precharge = 1'd0;
	if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin
		ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel1_write = 1'd0;
	if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin
		ddrphy_dfiphasemodel1_write = (~ddrphy_dfi_p1_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel1_read = 1'd0;
	if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin
		ddrphy_dfiphasemodel1_read = ddrphy_dfi_p1_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel2_activate = 1'd0;
	if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin
		ddrphy_dfiphasemodel2_activate = ddrphy_dfi_p2_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel2_precharge = 1'd0;
	if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin
		ddrphy_dfiphasemodel2_precharge = (~ddrphy_dfi_p2_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel2_read = 1'd0;
	if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin
		ddrphy_dfiphasemodel2_read = ddrphy_dfi_p2_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel2_write = 1'd0;
	if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin
		ddrphy_dfiphasemodel2_write = (~ddrphy_dfi_p2_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel3_activate = 1'd0;
	if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin
		ddrphy_dfiphasemodel3_activate = ddrphy_dfi_p3_we_n;
	end
end
always @(*) begin
	ddrphy_dfiphasemodel3_precharge = 1'd0;
	if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin
		ddrphy_dfiphasemodel3_precharge = (~ddrphy_dfi_p3_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel3_write = 1'd0;
	if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin
		ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n);
	end
end
always @(*) begin
	ddrphy_dfiphasemodel3_read = 1'd0;
	if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin
		ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n;
	end
end
assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
always @(*) begin
	ddrphy_bankmodel0_read_data = 128'd0;
	if (ddrphy_bankmodel0_active) begin
		if (ddrphy_bankmodel0_read) begin
			ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel0_write_port_adr = 21'd0;
	if (ddrphy_bankmodel0_active) begin
		ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel0_write_port_we = 16'd0;
	if (ddrphy_bankmodel0_active) begin
		if (4'd8) begin
			ddrphy_bankmodel0_write_port_we = ({16{ddrphy_bankmodel0_write}} & (~ddrphy_bankmodel0_write_mask));
		end else begin
			ddrphy_bankmodel0_write_port_we = ddrphy_bankmodel0_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel0_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel0_active) begin
		ddrphy_bankmodel0_write_port_dat_w = ddrphy_bankmodel0_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel0_read_port_adr = 21'd0;
	if (ddrphy_bankmodel0_active) begin
		if (ddrphy_bankmodel0_read) begin
			ddrphy_bankmodel0_read_port_adr = ddrphy_bankmodel0_rdaddr;
		end
	end
end
assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
	ddrphy_bankmodel1_write_port_adr = 21'd0;
	if (ddrphy_bankmodel1_active) begin
		ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel1_write_port_we = 16'd0;
	if (ddrphy_bankmodel1_active) begin
		if (4'd8) begin
			ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask));
		end else begin
			ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel1_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel1_active) begin
		ddrphy_bankmodel1_write_port_dat_w = ddrphy_bankmodel1_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel1_read_port_adr = 21'd0;
	if (ddrphy_bankmodel1_active) begin
		if (ddrphy_bankmodel1_read) begin
			ddrphy_bankmodel1_read_port_adr = ddrphy_bankmodel1_rdaddr;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel1_read_data = 128'd0;
	if (ddrphy_bankmodel1_active) begin
		if (ddrphy_bankmodel1_read) begin
			ddrphy_bankmodel1_read_data = ddrphy_bankmodel1_read_port_dat_r;
		end
	end
end
assign ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
assign ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
always @(*) begin
	ddrphy_bankmodel2_write_port_adr = 21'd0;
	if (ddrphy_bankmodel2_active) begin
		ddrphy_bankmodel2_write_port_adr = ddrphy_bankmodel2_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel2_write_port_we = 16'd0;
	if (ddrphy_bankmodel2_active) begin
		if (4'd8) begin
			ddrphy_bankmodel2_write_port_we = ({16{ddrphy_bankmodel2_write}} & (~ddrphy_bankmodel2_write_mask));
		end else begin
			ddrphy_bankmodel2_write_port_we = ddrphy_bankmodel2_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel2_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel2_active) begin
		ddrphy_bankmodel2_write_port_dat_w = ddrphy_bankmodel2_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel2_read_port_adr = 21'd0;
	if (ddrphy_bankmodel2_active) begin
		if (ddrphy_bankmodel2_read) begin
			ddrphy_bankmodel2_read_port_adr = ddrphy_bankmodel2_rdaddr;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel2_read_data = 128'd0;
	if (ddrphy_bankmodel2_active) begin
		if (ddrphy_bankmodel2_read) begin
			ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r;
		end
	end
end
assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
always @(*) begin
	ddrphy_bankmodel3_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel3_active) begin
		ddrphy_bankmodel3_write_port_dat_w = ddrphy_bankmodel3_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel3_read_port_adr = 21'd0;
	if (ddrphy_bankmodel3_active) begin
		if (ddrphy_bankmodel3_read) begin
			ddrphy_bankmodel3_read_port_adr = ddrphy_bankmodel3_rdaddr;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel3_read_data = 128'd0;
	if (ddrphy_bankmodel3_active) begin
		if (ddrphy_bankmodel3_read) begin
			ddrphy_bankmodel3_read_data = ddrphy_bankmodel3_read_port_dat_r;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel3_write_port_adr = 21'd0;
	if (ddrphy_bankmodel3_active) begin
		ddrphy_bankmodel3_write_port_adr = ddrphy_bankmodel3_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel3_write_port_we = 16'd0;
	if (ddrphy_bankmodel3_active) begin
		if (4'd8) begin
			ddrphy_bankmodel3_write_port_we = ({16{ddrphy_bankmodel3_write}} & (~ddrphy_bankmodel3_write_mask));
		end else begin
			ddrphy_bankmodel3_write_port_we = ddrphy_bankmodel3_write;
		end
	end
end
assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
always @(*) begin
	ddrphy_bankmodel4_read_port_adr = 21'd0;
	if (ddrphy_bankmodel4_active) begin
		if (ddrphy_bankmodel4_read) begin
			ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel4_read_data = 128'd0;
	if (ddrphy_bankmodel4_active) begin
		if (ddrphy_bankmodel4_read) begin
			ddrphy_bankmodel4_read_data = ddrphy_bankmodel4_read_port_dat_r;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel4_write_port_adr = 21'd0;
	if (ddrphy_bankmodel4_active) begin
		ddrphy_bankmodel4_write_port_adr = ddrphy_bankmodel4_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel4_write_port_we = 16'd0;
	if (ddrphy_bankmodel4_active) begin
		if (4'd8) begin
			ddrphy_bankmodel4_write_port_we = ({16{ddrphy_bankmodel4_write}} & (~ddrphy_bankmodel4_write_mask));
		end else begin
			ddrphy_bankmodel4_write_port_we = ddrphy_bankmodel4_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel4_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel4_active) begin
		ddrphy_bankmodel4_write_port_dat_w = ddrphy_bankmodel4_write_data;
	end
end
assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
	ddrphy_bankmodel5_read_data = 128'd0;
	if (ddrphy_bankmodel5_active) begin
		if (ddrphy_bankmodel5_read) begin
			ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel5_write_port_adr = 21'd0;
	if (ddrphy_bankmodel5_active) begin
		ddrphy_bankmodel5_write_port_adr = ddrphy_bankmodel5_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel5_write_port_we = 16'd0;
	if (ddrphy_bankmodel5_active) begin
		if (4'd8) begin
			ddrphy_bankmodel5_write_port_we = ({16{ddrphy_bankmodel5_write}} & (~ddrphy_bankmodel5_write_mask));
		end else begin
			ddrphy_bankmodel5_write_port_we = ddrphy_bankmodel5_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel5_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel5_active) begin
		ddrphy_bankmodel5_write_port_dat_w = ddrphy_bankmodel5_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel5_read_port_adr = 21'd0;
	if (ddrphy_bankmodel5_active) begin
		if (ddrphy_bankmodel5_read) begin
			ddrphy_bankmodel5_read_port_adr = ddrphy_bankmodel5_rdaddr;
		end
	end
end
assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
always @(*) begin
	ddrphy_bankmodel6_read_data = 128'd0;
	if (ddrphy_bankmodel6_active) begin
		if (ddrphy_bankmodel6_read) begin
			ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel6_write_port_adr = 21'd0;
	if (ddrphy_bankmodel6_active) begin
		ddrphy_bankmodel6_write_port_adr = ddrphy_bankmodel6_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel6_write_port_we = 16'd0;
	if (ddrphy_bankmodel6_active) begin
		if (4'd8) begin
			ddrphy_bankmodel6_write_port_we = ({16{ddrphy_bankmodel6_write}} & (~ddrphy_bankmodel6_write_mask));
		end else begin
			ddrphy_bankmodel6_write_port_we = ddrphy_bankmodel6_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel6_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel6_active) begin
		ddrphy_bankmodel6_write_port_dat_w = ddrphy_bankmodel6_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel6_read_port_adr = 21'd0;
	if (ddrphy_bankmodel6_active) begin
		if (ddrphy_bankmodel6_read) begin
			ddrphy_bankmodel6_read_port_adr = ddrphy_bankmodel6_rdaddr;
		end
	end
end
assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
always @(*) begin
	ddrphy_bankmodel7_write_port_adr = 21'd0;
	if (ddrphy_bankmodel7_active) begin
		ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr;
	end
end
always @(*) begin
	ddrphy_bankmodel7_write_port_we = 16'd0;
	if (ddrphy_bankmodel7_active) begin
		if (4'd8) begin
			ddrphy_bankmodel7_write_port_we = ({16{ddrphy_bankmodel7_write}} & (~ddrphy_bankmodel7_write_mask));
		end else begin
			ddrphy_bankmodel7_write_port_we = ddrphy_bankmodel7_write;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel7_write_port_dat_w = 128'd0;
	if (ddrphy_bankmodel7_active) begin
		ddrphy_bankmodel7_write_port_dat_w = ddrphy_bankmodel7_write_data;
	end
end
always @(*) begin
	ddrphy_bankmodel7_read_port_adr = 21'd0;
	if (ddrphy_bankmodel7_active) begin
		if (ddrphy_bankmodel7_read) begin
			ddrphy_bankmodel7_read_port_adr = ddrphy_bankmodel7_rdaddr;
		end
	end
end
always @(*) begin
	ddrphy_bankmodel7_read_data = 128'd0;
	if (ddrphy_bankmodel7_active) begin
		if (ddrphy_bankmodel7_read) begin
			ddrphy_bankmodel7_read_data = ddrphy_bankmodel7_read_port_dat_r;
		end
	end
end
assign ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata;
assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid;
assign ddrphy_dfi_p1_address = litedramcore_master_p1_address;
assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata;
assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid;
assign ddrphy_dfi_p2_address = litedramcore_master_p2_address;
assign ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
assign ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
assign ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
assign ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
assign ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
assign ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
assign ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
assign ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
assign ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
assign ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
assign ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
assign ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
assign ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
assign litedramcore_master_p2_rddata = ddrphy_dfi_p2_rddata;
assign litedramcore_master_p2_rddata_valid = ddrphy_dfi_p2_rddata_valid;
assign ddrphy_dfi_p3_address = litedramcore_master_p3_address;
assign ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
assign ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
assign ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
assign ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
assign ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
assign ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
assign ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
assign ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
assign ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
assign ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
assign ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
assign ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
assign ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
assign litedramcore_master_p3_rddata = ddrphy_dfi_p3_rddata;
assign litedramcore_master_p3_rddata_valid = ddrphy_dfi_p3_rddata_valid;
assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
	litedramcore_master_p2_we_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n;
	end else begin
		litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n;
	end
end
always @(*) begin
	litedramcore_slave_p2_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p2_cke = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_cke = litedramcore_slave_p2_cke;
	end else begin
		litedramcore_master_p2_cke = litedramcore_inti_p2_cke;
	end
end
always @(*) begin
	litedramcore_master_p2_odt = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_odt = litedramcore_slave_p2_odt;
	end else begin
		litedramcore_master_p2_odt = litedramcore_inti_p2_odt;
	end
end
always @(*) begin
	litedramcore_master_p2_reset_n = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n;
	end else begin
		litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n;
	end
end
always @(*) begin
	litedramcore_master_p2_act_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n;
	end else begin
		litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n;
	end
end
always @(*) begin
	litedramcore_master_p2_wrdata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata;
	end else begin
		litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata;
	end
end
always @(*) begin
	litedramcore_inti_p3_rddata = 32'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata;
	end
end
always @(*) begin
	litedramcore_master_p2_wrdata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en;
	end else begin
		litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en;
	end
end
always @(*) begin
	litedramcore_inti_p3_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
	end
end
always @(*) begin
	litedramcore_master_p2_wrdata_mask = 4'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask;
	end else begin
		litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask;
	end
end
always @(*) begin
	litedramcore_master_p2_rddata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en;
	end else begin
		litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en;
	end
end
always @(*) begin
	litedramcore_master_p3_address = 14'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_address = litedramcore_slave_p3_address;
	end else begin
		litedramcore_master_p3_address = litedramcore_inti_p3_address;
	end
end
always @(*) begin
	litedramcore_master_p3_bank = 3'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_bank = litedramcore_slave_p3_bank;
	end else begin
		litedramcore_master_p3_bank = litedramcore_inti_p3_bank;
	end
end
always @(*) begin
	litedramcore_master_p3_cas_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n;
	end else begin
		litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n;
	end
end
always @(*) begin
	litedramcore_master_p3_cs_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n;
	end else begin
		litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n;
	end
end
always @(*) begin
	litedramcore_master_p3_ras_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n;
	end else begin
		litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n;
	end
end
always @(*) begin
	litedramcore_slave_p3_rddata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p3_we_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n;
	end else begin
		litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n;
	end
end
always @(*) begin
	litedramcore_slave_p3_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p3_cke = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_cke = litedramcore_slave_p3_cke;
	end else begin
		litedramcore_master_p3_cke = litedramcore_inti_p3_cke;
	end
end
always @(*) begin
	litedramcore_master_p3_odt = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_odt = litedramcore_slave_p3_odt;
	end else begin
		litedramcore_master_p3_odt = litedramcore_inti_p3_odt;
	end
end
always @(*) begin
	litedramcore_master_p3_reset_n = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n;
	end else begin
		litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n;
	end
end
always @(*) begin
	litedramcore_master_p3_act_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n;
	end else begin
		litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n;
	end
end
always @(*) begin
	litedramcore_master_p3_wrdata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata;
	end else begin
		litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata;
	end
end
always @(*) begin
	litedramcore_inti_p0_rddata = 32'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata;
	end
end
always @(*) begin
	litedramcore_master_p3_wrdata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en;
	end else begin
		litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en;
	end
end
always @(*) begin
	litedramcore_inti_p0_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
	end
end
always @(*) begin
	litedramcore_slave_p2_rddata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p3_wrdata_mask = 4'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask;
	end else begin
		litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask;
	end
end
always @(*) begin
	litedramcore_master_p3_rddata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en;
	end else begin
		litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en;
	end
end
always @(*) begin
	litedramcore_master_p0_address = 14'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_address = litedramcore_slave_p0_address;
	end else begin
		litedramcore_master_p0_address = litedramcore_inti_p0_address;
	end
end
always @(*) begin
	litedramcore_master_p0_bank = 3'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_bank = litedramcore_slave_p0_bank;
	end else begin
		litedramcore_master_p0_bank = litedramcore_inti_p0_bank;
	end
end
always @(*) begin
	litedramcore_master_p0_cas_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n;
	end else begin
		litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n;
	end
end
always @(*) begin
	litedramcore_master_p0_cs_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n;
	end else begin
		litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n;
	end
end
always @(*) begin
	litedramcore_slave_p0_rddata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p0_ras_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n;
	end else begin
		litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n;
	end
end
always @(*) begin
	litedramcore_master_p0_we_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n;
	end else begin
		litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n;
	end
end
always @(*) begin
	litedramcore_slave_p0_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p0_cke = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_cke = litedramcore_slave_p0_cke;
	end else begin
		litedramcore_master_p0_cke = litedramcore_inti_p0_cke;
	end
end
always @(*) begin
	litedramcore_master_p0_odt = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_odt = litedramcore_slave_p0_odt;
	end else begin
		litedramcore_master_p0_odt = litedramcore_inti_p0_odt;
	end
end
always @(*) begin
	litedramcore_master_p0_reset_n = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n;
	end else begin
		litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n;
	end
end
always @(*) begin
	litedramcore_master_p0_act_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n;
	end else begin
		litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n;
	end
end
always @(*) begin
	litedramcore_master_p0_wrdata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata;
	end else begin
		litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata;
	end
end
always @(*) begin
	litedramcore_inti_p1_rddata = 32'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata;
	end
end
always @(*) begin
	litedramcore_master_p0_wrdata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en;
	end else begin
		litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en;
	end
end
always @(*) begin
	litedramcore_inti_p1_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
	end
end
always @(*) begin
	litedramcore_master_p0_wrdata_mask = 4'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask;
	end else begin
		litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask;
	end
end
always @(*) begin
	litedramcore_master_p0_rddata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en;
	end else begin
		litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en;
	end
end
always @(*) begin
	litedramcore_master_p1_address = 14'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_address = litedramcore_slave_p1_address;
	end else begin
		litedramcore_master_p1_address = litedramcore_inti_p1_address;
	end
end
always @(*) begin
	litedramcore_master_p1_bank = 3'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_bank = litedramcore_slave_p1_bank;
	end else begin
		litedramcore_master_p1_bank = litedramcore_inti_p1_bank;
	end
end
always @(*) begin
	litedramcore_master_p1_cas_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n;
	end else begin
		litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n;
	end
end
always @(*) begin
	litedramcore_master_p1_cs_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n;
	end else begin
		litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n;
	end
end
always @(*) begin
	litedramcore_master_p1_ras_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n;
	end else begin
		litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n;
	end
end
always @(*) begin
	litedramcore_slave_p1_rddata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p1_we_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n;
	end else begin
		litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n;
	end
end
always @(*) begin
	litedramcore_slave_p1_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
	end else begin
	end
end
always @(*) begin
	litedramcore_master_p1_cke = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_cke = litedramcore_slave_p1_cke;
	end else begin
		litedramcore_master_p1_cke = litedramcore_inti_p1_cke;
	end
end
always @(*) begin
	litedramcore_master_p1_odt = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_odt = litedramcore_slave_p1_odt;
	end else begin
		litedramcore_master_p1_odt = litedramcore_inti_p1_odt;
	end
end
always @(*) begin
	litedramcore_master_p1_reset_n = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n;
	end else begin
		litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n;
	end
end
always @(*) begin
	litedramcore_master_p1_act_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n;
	end else begin
		litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n;
	end
end
always @(*) begin
	litedramcore_master_p1_wrdata = 32'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata;
	end else begin
		litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata;
	end
end
always @(*) begin
	litedramcore_inti_p2_rddata = 32'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata;
	end
end
always @(*) begin
	litedramcore_master_p1_wrdata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en;
	end else begin
		litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en;
	end
end
always @(*) begin
	litedramcore_inti_p2_rddata_valid = 1'd0;
	if (litedramcore_sel) begin
	end else begin
		litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
	end
end
always @(*) begin
	litedramcore_master_p1_wrdata_mask = 4'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask;
	end else begin
		litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask;
	end
end
always @(*) begin
	litedramcore_master_p1_rddata_en = 1'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en;
	end else begin
		litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en;
	end
end
always @(*) begin
	litedramcore_master_p2_address = 14'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_address = litedramcore_slave_p2_address;
	end else begin
		litedramcore_master_p2_address = litedramcore_inti_p2_address;
	end
end
always @(*) begin
	litedramcore_master_p2_bank = 3'd0;
	if (litedramcore_sel) begin
		litedramcore_master_p2_bank = litedramcore_slave_p2_bank;
	end else begin
		litedramcore_master_p2_bank = litedramcore_inti_p2_bank;
	end
end
always @(*) begin
	litedramcore_master_p2_cas_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n;
	end else begin
		litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n;
	end
end
always @(*) begin
	litedramcore_master_p2_cs_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n;
	end else begin
		litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n;
	end
end
always @(*) begin
	litedramcore_master_p2_ras_n = 1'd1;
	if (litedramcore_sel) begin
		litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n;
	end else begin
		litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n;
	end
end
assign litedramcore_inti_p0_cke = litedramcore_cke;
assign litedramcore_inti_p1_cke = litedramcore_cke;
assign litedramcore_inti_p2_cke = litedramcore_cke;
assign litedramcore_inti_p3_cke = litedramcore_cke;
assign litedramcore_inti_p0_odt = litedramcore_odt;
assign litedramcore_inti_p1_odt = litedramcore_odt;
assign litedramcore_inti_p2_odt = litedramcore_odt;
assign litedramcore_inti_p3_odt = litedramcore_odt;
assign litedramcore_inti_p0_reset_n = litedramcore_reset_n;
assign litedramcore_inti_p1_reset_n = litedramcore_reset_n;
assign litedramcore_inti_p2_reset_n = litedramcore_reset_n;
assign litedramcore_inti_p3_reset_n = litedramcore_reset_n;
always @(*) begin
	litedramcore_inti_p0_we_n = 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]);
	end else begin
		litedramcore_inti_p0_we_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p0_cas_n = 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]);
	end else begin
		litedramcore_inti_p0_cas_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p0_cs_n = 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}};
	end else begin
		litedramcore_inti_p0_cs_n = {1{1'd1}};
	end
end
always @(*) begin
	litedramcore_inti_p0_ras_n = 1'd1;
	if (litedramcore_phaseinjector0_command_issue_re) begin
		litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]);
	end else begin
		litedramcore_inti_p0_ras_n = 1'd1;
	end
end
assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_inti_p0_wrdata_mask = 1'd0;
always @(*) begin
	litedramcore_inti_p1_we_n = 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]);
	end else begin
		litedramcore_inti_p1_we_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p1_cas_n = 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]);
	end else begin
		litedramcore_inti_p1_cas_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p1_cs_n = 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}};
	end else begin
		litedramcore_inti_p1_cs_n = {1{1'd1}};
	end
end
always @(*) begin
	litedramcore_inti_p1_ras_n = 1'd1;
	if (litedramcore_phaseinjector1_command_issue_re) begin
		litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]);
	end else begin
		litedramcore_inti_p1_ras_n = 1'd1;
	end
end
assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_inti_p1_wrdata_mask = 1'd0;
always @(*) begin
	litedramcore_inti_p2_we_n = 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]);
	end else begin
		litedramcore_inti_p2_we_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p2_cas_n = 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_cas_n = (~litedramcore_phaseinjector2_command_storage[2]);
	end else begin
		litedramcore_inti_p2_cas_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p2_cs_n = 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}};
	end else begin
		litedramcore_inti_p2_cs_n = {1{1'd1}};
	end
end
always @(*) begin
	litedramcore_inti_p2_ras_n = 1'd1;
	if (litedramcore_phaseinjector2_command_issue_re) begin
		litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]);
	end else begin
		litedramcore_inti_p2_ras_n = 1'd1;
	end
end
assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_inti_p2_wrdata_mask = 1'd0;
always @(*) begin
	litedramcore_inti_p3_we_n = 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_we_n = (~litedramcore_phaseinjector3_command_storage[1]);
	end else begin
		litedramcore_inti_p3_we_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p3_cas_n = 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_cas_n = (~litedramcore_phaseinjector3_command_storage[2]);
	end else begin
		litedramcore_inti_p3_cas_n = 1'd1;
	end
end
always @(*) begin
	litedramcore_inti_p3_cs_n = 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}};
	end else begin
		litedramcore_inti_p3_cs_n = {1{1'd1}};
	end
end
always @(*) begin
	litedramcore_inti_p3_ras_n = 1'd1;
	if (litedramcore_phaseinjector3_command_issue_re) begin
		litedramcore_inti_p3_ras_n = (~litedramcore_phaseinjector3_command_storage[3]);
	end else begin
		litedramcore_inti_p3_ras_n = 1'd1;
	end
end
assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
assign litedramcore_inti_p3_wrdata_mask = 1'd0;
assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
assign litedramcore_timer_wait = (~litedramcore_timer_done0);
assign litedramcore_postponer_req_i = litedramcore_timer_done0;
assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
assign litedramcore_timer_done0 = litedramcore_timer_done1;
assign litedramcore_timer_count0 = litedramcore_timer_count1;
assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
	refresher_next_state = 2'd0;
	refresher_next_state = refresher_state;
	case (refresher_state)
		1'd1: begin
			if (litedramcore_cmd_ready) begin
				refresher_next_state = 2'd2;
			end
		end
		2'd2: begin
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
					refresher_next_state = 2'd3;
				end else begin
					refresher_next_state = 1'd0;
				end
			end
		end
		2'd3: begin
			if (litedramcore_zqcs_executer_done) begin
				refresher_next_state = 1'd0;
			end
		end
		default: begin
			if (1'd1) begin
				if (litedramcore_wants_refresh) begin
					refresher_next_state = 1'd1;
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_cmd_valid = 1'd0;
	case (refresher_state)
		1'd1: begin
			litedramcore_cmd_valid = 1'd1;
		end
		2'd2: begin
			litedramcore_cmd_valid = 1'd1;
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
				end else begin
					litedramcore_cmd_valid = 1'd0;
				end
			end
		end
		2'd3: begin
			litedramcore_cmd_valid = 1'd1;
			if (litedramcore_zqcs_executer_done) begin
				litedramcore_cmd_valid = 1'd0;
			end
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_zqcs_executer_start = 1'd0;
	case (refresher_state)
		1'd1: begin
		end
		2'd2: begin
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
					litedramcore_zqcs_executer_start = 1'd1;
				end else begin
				end
			end
		end
		2'd3: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_cmd_last = 1'd0;
	case (refresher_state)
		1'd1: begin
		end
		2'd2: begin
			if (litedramcore_sequencer_done0) begin
				if (litedramcore_wants_zqcs) begin
				end else begin
					litedramcore_cmd_last = 1'd1;
				end
			end
		end
		2'd3: begin
			if (litedramcore_zqcs_executer_done) begin
				litedramcore_cmd_last = 1'd1;
			end
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_sequencer_start0 = 1'd0;
	case (refresher_state)
		1'd1: begin
			if (litedramcore_cmd_ready) begin
				litedramcore_sequencer_start0 = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		default: begin
		end
	endcase
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
		litedramcore_bankmachine0_cmd_payload_a = litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine0_cmd_payload_a = ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
	litedramcore_bankmachine0_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine0_auto_precharge = (litedramcore_bankmachine0_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
always @(*) begin
	bankmachine0_next_state = 4'd0;
	bankmachine0_next_state = bankmachine0_state;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				if (litedramcore_bankmachine0_cmd_ready) begin
					bankmachine0_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				bankmachine0_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				if (litedramcore_bankmachine0_cmd_ready) begin
					bankmachine0_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine0_refresh_req)) begin
				bankmachine0_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine0_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine0_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine0_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine0_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
				bankmachine0_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
								bankmachine0_next_state = 2'd2;
							end
						end else begin
							bankmachine0_next_state = 1'd1;
						end
					end else begin
						bankmachine0_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_req_wdata_ready = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_req_rdata_valid = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_refresh_gnt = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine0_twtpcon_ready) begin
				litedramcore_bankmachine0_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_valid = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							litedramcore_bankmachine0_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_row_open = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_row_close = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			litedramcore_bankmachine0_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine0_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine0_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							litedramcore_bankmachine0_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_we = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine0_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
			if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
				litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine0_trccon_ready) begin
				litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine0_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
	case (bankmachine0_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine0_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine0_row_opened) begin
						if (litedramcore_bankmachine0_row_hit) begin
							if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine0_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
		litedramcore_bankmachine1_cmd_payload_a = litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine1_cmd_payload_a = ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
	litedramcore_bankmachine1_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine1_auto_precharge = (litedramcore_bankmachine1_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
always @(*) begin
	bankmachine1_next_state = 4'd0;
	bankmachine1_next_state = bankmachine1_state;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				if (litedramcore_bankmachine1_cmd_ready) begin
					bankmachine1_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				bankmachine1_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				if (litedramcore_bankmachine1_cmd_ready) begin
					bankmachine1_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine1_refresh_req)) begin
				bankmachine1_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine1_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine1_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine1_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine1_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
				bankmachine1_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
								bankmachine1_next_state = 2'd2;
							end
						end else begin
							bankmachine1_next_state = 1'd1;
						end
					end else begin
						bankmachine1_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_req_wdata_ready = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_req_rdata_valid = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_refresh_gnt = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine1_twtpcon_ready) begin
				litedramcore_bankmachine1_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_valid = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							litedramcore_bankmachine1_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_row_open = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_row_close = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			litedramcore_bankmachine1_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine1_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine1_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							litedramcore_bankmachine1_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_we = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine1_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
			if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
				litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine1_trccon_ready) begin
				litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine1_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
	case (bankmachine1_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine1_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine1_row_opened) begin
						if (litedramcore_bankmachine1_row_hit) begin
							if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine1_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
		litedramcore_bankmachine2_cmd_payload_a = litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine2_cmd_payload_a = ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
	litedramcore_bankmachine2_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine2_auto_precharge = (litedramcore_bankmachine2_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
always @(*) begin
	bankmachine2_next_state = 4'd0;
	bankmachine2_next_state = bankmachine2_state;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				if (litedramcore_bankmachine2_cmd_ready) begin
					bankmachine2_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				bankmachine2_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				if (litedramcore_bankmachine2_cmd_ready) begin
					bankmachine2_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine2_refresh_req)) begin
				bankmachine2_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine2_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine2_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine2_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine2_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
				bankmachine2_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
								bankmachine2_next_state = 2'd2;
							end
						end else begin
							bankmachine2_next_state = 1'd1;
						end
					end else begin
						bankmachine2_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_req_wdata_ready = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_req_rdata_valid = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_refresh_gnt = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine2_twtpcon_ready) begin
				litedramcore_bankmachine2_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_valid = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							litedramcore_bankmachine2_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_row_open = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_row_close = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			litedramcore_bankmachine2_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine2_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine2_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							litedramcore_bankmachine2_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_we = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine2_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
			if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
				litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine2_trccon_ready) begin
				litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine2_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
	case (bankmachine2_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine2_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine2_row_opened) begin
						if (litedramcore_bankmachine2_row_hit) begin
							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine2_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
		litedramcore_bankmachine3_cmd_payload_a = litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine3_cmd_payload_a = ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
	litedramcore_bankmachine3_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine3_auto_precharge = (litedramcore_bankmachine3_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
always @(*) begin
	bankmachine3_next_state = 4'd0;
	bankmachine3_next_state = bankmachine3_state;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				if (litedramcore_bankmachine3_cmd_ready) begin
					bankmachine3_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				bankmachine3_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				if (litedramcore_bankmachine3_cmd_ready) begin
					bankmachine3_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine3_refresh_req)) begin
				bankmachine3_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine3_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine3_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine3_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine3_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
				bankmachine3_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
								bankmachine3_next_state = 2'd2;
							end
						end else begin
							bankmachine3_next_state = 1'd1;
						end
					end else begin
						bankmachine3_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_req_wdata_ready = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_req_rdata_valid = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_refresh_gnt = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine3_twtpcon_ready) begin
				litedramcore_bankmachine3_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_valid = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							litedramcore_bankmachine3_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_row_open = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_row_close = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			litedramcore_bankmachine3_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine3_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine3_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							litedramcore_bankmachine3_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_we = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine3_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
			if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
				litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine3_trccon_ready) begin
				litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine3_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
	case (bankmachine3_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine3_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine3_row_opened) begin
						if (litedramcore_bankmachine3_row_hit) begin
							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine3_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
		litedramcore_bankmachine4_cmd_payload_a = litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine4_cmd_payload_a = ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
	litedramcore_bankmachine4_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine4_auto_precharge = (litedramcore_bankmachine4_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
always @(*) begin
	bankmachine4_next_state = 4'd0;
	bankmachine4_next_state = bankmachine4_state;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				if (litedramcore_bankmachine4_cmd_ready) begin
					bankmachine4_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				bankmachine4_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				if (litedramcore_bankmachine4_cmd_ready) begin
					bankmachine4_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine4_refresh_req)) begin
				bankmachine4_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine4_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine4_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine4_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine4_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
				bankmachine4_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
								bankmachine4_next_state = 2'd2;
							end
						end else begin
							bankmachine4_next_state = 1'd1;
						end
					end else begin
						bankmachine4_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_req_wdata_ready = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_req_rdata_valid = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_refresh_gnt = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine4_twtpcon_ready) begin
				litedramcore_bankmachine4_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_valid = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							litedramcore_bankmachine4_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_row_open = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_row_close = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			litedramcore_bankmachine4_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine4_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine4_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							litedramcore_bankmachine4_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_we = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine4_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
			if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
				litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine4_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine4_trccon_ready) begin
				litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
	case (bankmachine4_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine4_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine4_row_opened) begin
						if (litedramcore_bankmachine4_row_hit) begin
							if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine4_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
		litedramcore_bankmachine5_cmd_payload_a = litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine5_cmd_payload_a = ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
	litedramcore_bankmachine5_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine5_auto_precharge = (litedramcore_bankmachine5_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
always @(*) begin
	bankmachine5_next_state = 4'd0;
	bankmachine5_next_state = bankmachine5_state;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				if (litedramcore_bankmachine5_cmd_ready) begin
					bankmachine5_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				bankmachine5_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				if (litedramcore_bankmachine5_cmd_ready) begin
					bankmachine5_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine5_refresh_req)) begin
				bankmachine5_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine5_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine5_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine5_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine5_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
				bankmachine5_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
								bankmachine5_next_state = 2'd2;
							end
						end else begin
							bankmachine5_next_state = 1'd1;
						end
					end else begin
						bankmachine5_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_req_wdata_ready = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_req_rdata_valid = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_refresh_gnt = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine5_twtpcon_ready) begin
				litedramcore_bankmachine5_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_valid = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							litedramcore_bankmachine5_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_row_open = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_row_close = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			litedramcore_bankmachine5_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine5_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine5_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							litedramcore_bankmachine5_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_we = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine5_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
			if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
				litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine5_trccon_ready) begin
				litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine5_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
	case (bankmachine5_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine5_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine5_row_opened) begin
						if (litedramcore_bankmachine5_row_hit) begin
							if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine5_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
		litedramcore_bankmachine6_cmd_payload_a = litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine6_cmd_payload_a = ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
	litedramcore_bankmachine6_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine6_auto_precharge = (litedramcore_bankmachine6_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
always @(*) begin
	bankmachine6_next_state = 4'd0;
	bankmachine6_next_state = bankmachine6_state;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				if (litedramcore_bankmachine6_cmd_ready) begin
					bankmachine6_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				bankmachine6_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				if (litedramcore_bankmachine6_cmd_ready) begin
					bankmachine6_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine6_refresh_req)) begin
				bankmachine6_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine6_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine6_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine6_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine6_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
				bankmachine6_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
								bankmachine6_next_state = 2'd2;
							end
						end else begin
							bankmachine6_next_state = 1'd1;
						end
					end else begin
						bankmachine6_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_req_wdata_ready = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_req_rdata_valid = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_refresh_gnt = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine6_twtpcon_ready) begin
				litedramcore_bankmachine6_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_valid = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							litedramcore_bankmachine6_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_row_open = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_row_close = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			litedramcore_bankmachine6_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine6_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine6_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							litedramcore_bankmachine6_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_we = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine6_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
			if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
				litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine6_trccon_ready) begin
				litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine6_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
	case (bankmachine6_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine6_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine6_row_opened) begin
						if (litedramcore_bankmachine6_row_hit) begin
							if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_a = 14'd0;
	if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
		litedramcore_bankmachine7_cmd_payload_a = litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
	end else begin
		litedramcore_bankmachine7_cmd_payload_a = ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
	end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
	litedramcore_bankmachine7_auto_precharge = 1'd0;
	if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
		if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
			litedramcore_bankmachine7_auto_precharge = (litedramcore_bankmachine7_row_close == 1'd0);
		end
	end
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
always @(*) begin
	litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
	if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
	end else begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
	end
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
always @(*) begin
	bankmachine7_next_state = 4'd0;
	bankmachine7_next_state = bankmachine7_state;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				if (litedramcore_bankmachine7_cmd_ready) begin
					bankmachine7_next_state = 3'd5;
				end
			end
		end
		2'd2: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				bankmachine7_next_state = 3'd5;
			end
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				if (litedramcore_bankmachine7_cmd_ready) begin
					bankmachine7_next_state = 3'd7;
				end
			end
		end
		3'd4: begin
			if ((~litedramcore_bankmachine7_refresh_req)) begin
				bankmachine7_next_state = 1'd0;
			end
		end
		3'd5: begin
			bankmachine7_next_state = 3'd6;
		end
		3'd6: begin
			bankmachine7_next_state = 2'd3;
		end
		3'd7: begin
			bankmachine7_next_state = 4'd8;
		end
		4'd8: begin
			bankmachine7_next_state = 1'd0;
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
				bankmachine7_next_state = 3'd4;
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
								bankmachine7_next_state = 2'd2;
							end
						end else begin
							bankmachine7_next_state = 1'd1;
						end
					end else begin
						bankmachine7_next_state = 2'd3;
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_req_wdata_ready = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_req_rdata_valid = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_refresh_gnt = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
			if (litedramcore_bankmachine7_twtpcon_ready) begin
				litedramcore_bankmachine7_refresh_gnt = 1'd1;
			end
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_valid = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_valid = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_cmd_valid = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							litedramcore_bankmachine7_cmd_valid = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_row_open = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_row_open = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_row_close = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			litedramcore_bankmachine7_row_close = 1'd1;
		end
		2'd2: begin
			litedramcore_bankmachine7_row_close = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
			litedramcore_bankmachine7_row_close = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							litedramcore_bankmachine7_cmd_payload_cas = 1'd1;
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
			end
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_we = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_payload_we = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine7_cmd_payload_we = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
			if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
				litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
			end
		end
		2'd2: begin
		end
		2'd3: begin
			if (litedramcore_bankmachine7_trccon_ready) begin
				litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
			end
		end
		3'd4: begin
			litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
							end else begin
								litedramcore_bankmachine7_cmd_payload_is_read = 1'd1;
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
always @(*) begin
	litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
	case (bankmachine7_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		default: begin
			if (litedramcore_bankmachine7_refresh_req) begin
			end else begin
				if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
					if (litedramcore_bankmachine7_row_opened) begin
						if (litedramcore_bankmachine7_row_hit) begin
							if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
								litedramcore_bankmachine7_cmd_payload_is_write = 1'd1;
							end else begin
							end
						end else begin
						end
					end else begin
					end
				end
			end
		end
	endcase
end
assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
	litedramcore_choose_cmd_valids = 8'd0;
	litedramcore_choose_cmd_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
	litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
	litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
	if (litedramcore_choose_cmd_cmd_valid) begin
		litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0;
	end
end
always @(*) begin
	litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
	if (litedramcore_choose_cmd_cmd_valid) begin
		litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1;
	end
end
always @(*) begin
	litedramcore_choose_cmd_cmd_payload_we = 1'd0;
	if (litedramcore_choose_cmd_cmd_valid) begin
		litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2;
	end
end
always @(*) begin
	litedramcore_bankmachine0_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
		litedramcore_bankmachine0_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
		litedramcore_bankmachine0_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine1_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
		litedramcore_bankmachine1_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
		litedramcore_bankmachine1_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine2_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
		litedramcore_bankmachine2_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
		litedramcore_bankmachine2_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine3_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
		litedramcore_bankmachine3_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
		litedramcore_bankmachine3_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine4_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
		litedramcore_bankmachine4_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
		litedramcore_bankmachine4_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine5_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
		litedramcore_bankmachine5_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
		litedramcore_bankmachine5_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine6_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
		litedramcore_bankmachine6_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
		litedramcore_bankmachine6_cmd_ready = 1'd1;
	end
end
always @(*) begin
	litedramcore_bankmachine7_cmd_ready = 1'd0;
	if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
		litedramcore_bankmachine7_cmd_ready = 1'd1;
	end
	if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
		litedramcore_bankmachine7_cmd_ready = 1'd1;
	end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
	litedramcore_choose_req_valids = 8'd0;
	litedramcore_choose_req_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
	litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
	litedramcore_choose_req_cmd_payload_cas = 1'd0;
	if (litedramcore_choose_req_cmd_valid) begin
		litedramcore_choose_req_cmd_payload_cas = t_array_muxed3;
	end
end
always @(*) begin
	litedramcore_choose_req_cmd_payload_ras = 1'd0;
	if (litedramcore_choose_req_cmd_valid) begin
		litedramcore_choose_req_cmd_payload_ras = t_array_muxed4;
	end
end
always @(*) begin
	litedramcore_choose_req_cmd_payload_we = 1'd0;
	if (litedramcore_choose_req_cmd_valid) begin
		litedramcore_choose_req_cmd_payload_we = t_array_muxed5;
	end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
assign litedramcore_dfi_p1_reset_n = 1'd1;
assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
assign litedramcore_dfi_p2_reset_n = 1'd1;
assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
assign litedramcore_dfi_p3_reset_n = 1'd1;
assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
always @(*) begin
	multiplexer_next_state = 4'd0;
	multiplexer_next_state = multiplexer_state;
	case (multiplexer_state)
		1'd1: begin
			if (litedramcore_read_available) begin
				if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
					multiplexer_next_state = 2'd3;
				end
			end
			if (litedramcore_go_to_refresh) begin
				multiplexer_next_state = 2'd2;
			end
		end
		2'd2: begin
			if (litedramcore_cmd_last) begin
				multiplexer_next_state = 1'd0;
			end
		end
		2'd3: begin
			if (litedramcore_twtrcon_ready) begin
				multiplexer_next_state = 1'd0;
			end
		end
		3'd4: begin
			multiplexer_next_state = 3'd5;
		end
		3'd5: begin
			multiplexer_next_state = 3'd6;
		end
		3'd6: begin
			multiplexer_next_state = 3'd7;
		end
		3'd7: begin
			multiplexer_next_state = 4'd8;
		end
		4'd8: begin
			multiplexer_next_state = 4'd9;
		end
		4'd9: begin
			multiplexer_next_state = 4'd10;
		end
		4'd10: begin
			multiplexer_next_state = 4'd11;
		end
		4'd11: begin
			multiplexer_next_state = 1'd1;
		end
		default: begin
			if (litedramcore_write_available) begin
				if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
					multiplexer_next_state = 3'd4;
				end
			end
			if (litedramcore_go_to_refresh) begin
				multiplexer_next_state = 2'd2;
			end
		end
	endcase
end
always @(*) begin
	litedramcore_choose_cmd_want_activates = 1'd0;
	case (multiplexer_state)
		1'd1: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
			end
		end
	endcase
end
always @(*) begin
	litedramcore_steerer_sel3 = 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel3 = 2'd2;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			litedramcore_steerer_sel3 = 1'd0;
		end
	endcase
end
always @(*) begin
	litedramcore_en0 = 1'd0;
	case (multiplexer_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			litedramcore_en0 = 1'd1;
		end
	endcase
end
always @(*) begin
	litedramcore_cmd_ready = 1'd0;
	case (multiplexer_state)
		1'd1: begin
		end
		2'd2: begin
			litedramcore_cmd_ready = 1'd1;
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_choose_cmd_cmd_ready = 1'd0;
	case (multiplexer_state)
		1'd1: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			if (1'd0) begin
			end else begin
				litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
			end
		end
	endcase
end
always @(*) begin
	litedramcore_choose_req_want_reads = 1'd0;
	case (multiplexer_state)
		1'd1: begin
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			litedramcore_choose_req_want_reads = 1'd1;
		end
	endcase
end
always @(*) begin
	litedramcore_choose_req_want_writes = 1'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_choose_req_want_writes = 1'd1;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_choose_req_cmd_ready = 1'd0;
	case (multiplexer_state)
		1'd1: begin
			if (1'd0) begin
				litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
			end else begin
				litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
			end
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			if (1'd0) begin
				litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
			end else begin
				litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
			end
		end
	endcase
end
always @(*) begin
	litedramcore_en1 = 1'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_en1 = 1'd1;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
		end
	endcase
end
always @(*) begin
	litedramcore_steerer_sel0 = 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel0 = 1'd0;
		end
		2'd2: begin
			litedramcore_steerer_sel0 = 2'd3;
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			litedramcore_steerer_sel0 = 1'd0;
		end
	endcase
end
always @(*) begin
	litedramcore_steerer_sel1 = 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel1 = 1'd0;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			litedramcore_steerer_sel1 = 1'd1;
		end
	endcase
end
always @(*) begin
	litedramcore_steerer_sel2 = 2'd0;
	case (multiplexer_state)
		1'd1: begin
			litedramcore_steerer_sel2 = 1'd1;
		end
		2'd2: begin
		end
		2'd3: begin
		end
		3'd4: begin
		end
		3'd5: begin
		end
		3'd6: begin
		end
		3'd7: begin
		end
		4'd8: begin
		end
		4'd9: begin
		end
		4'd10: begin
		end
		4'd11: begin
		end
		default: begin
			litedramcore_steerer_sel2 = 2'd2;
		end
	endcase
end
assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
assign litedramcore_interface_bank0_we = rhs_array_muxed13;
assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
assign litedramcore_interface_bank1_we = rhs_array_muxed16;
assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
assign litedramcore_interface_bank2_we = rhs_array_muxed19;
assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
assign litedramcore_interface_bank3_we = rhs_array_muxed22;
assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
assign litedramcore_interface_bank4_we = rhs_array_muxed25;
assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
assign litedramcore_interface_bank5_we = rhs_array_muxed28;
assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
assign litedramcore_interface_bank6_we = rhs_array_muxed31;
assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
assign litedramcore_interface_bank7_we = rhs_array_muxed34;
assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
assign user_port_wdata_ready = new_master_wdata_ready2;
assign user_port_rdata_valid = new_master_rdata_valid9;
always @(*) begin
	litedramcore_interface_wdata = 128'd0;
	case ({new_master_wdata_ready2})
		1'd1: begin
			litedramcore_interface_wdata = user_port_wdata_payload_data;
		end
		default: begin
			litedramcore_interface_wdata = 1'd0;
		end
	endcase
end
always @(*) begin
	litedramcore_interface_wdata_we = 16'd0;
	case ({new_master_wdata_ready2})
		1'd1: begin
			litedramcore_interface_wdata_we = user_port_wdata_payload_we;
		end
		default: begin
			litedramcore_interface_wdata_we = 1'd0;
		end
	endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign roundrobin0_grant = 1'd0;
assign roundrobin1_grant = 1'd0;
assign roundrobin2_grant = 1'd0;
assign roundrobin3_grant = 1'd0;
assign roundrobin4_grant = 1'd0;
assign roundrobin5_grant = 1'd0;
assign roundrobin6_grant = 1'd0;
assign roundrobin7_grant = 1'd0;
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
assign litedramcore_wishbone_sel = wb_bus_sel;
assign litedramcore_wishbone_cyc = wb_bus_cyc;
assign litedramcore_wishbone_stb = wb_bus_stb;
assign wb_bus_ack = litedramcore_wishbone_ack;
assign litedramcore_wishbone_we = wb_bus_we;
assign litedramcore_wishbone_cti = wb_bus_cti;
assign litedramcore_wishbone_bte = wb_bus_bte;
assign wb_bus_err = litedramcore_wishbone_err;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0));
assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1));
assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17));
assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17));
assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18));
assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18));
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19));
assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20));
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20));
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21));
assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21));
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22));
assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22));
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23));
assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23));
assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign litedramcore_odt = litedramcore_storage[2];
assign litedramcore_reset_n = litedramcore_storage[3];
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
assign adr = litedramcore_adr;
assign we = litedramcore_we;
assign dat_w = litedramcore_dat_w;
assign litedramcore_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface0_bank_bus_we = we;
assign interface1_bank_bus_we = we;
assign interface0_bank_bus_dat_w = dat_w;
assign interface1_bank_bus_dat_w = dat_w;
assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r);
assign slice_proxy0 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_write_col);
assign slice_proxy1 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_read_col);
assign slice_proxy2 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_write_col);
assign slice_proxy3 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_read_col);
assign slice_proxy4 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_write_col);
assign slice_proxy5 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_read_col);
assign slice_proxy6 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_write_col);
assign slice_proxy7 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_read_col);
assign slice_proxy8 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_write_col);
assign slice_proxy9 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_read_col);
assign slice_proxy10 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_write_col);
assign slice_proxy11 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_read_col);
assign slice_proxy12 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_write_col);
assign slice_proxy13 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_read_col);
assign slice_proxy14 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_write_col);
assign slice_proxy15 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_read_col);
always @(*) begin
	rhs_array_muxed0 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[0];
		end
		1'd1: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[1];
		end
		2'd2: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[2];
		end
		2'd3: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[3];
		end
		3'd4: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[4];
		end
		3'd5: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[5];
		end
		3'd6: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[6];
		end
		default: begin
			rhs_array_muxed0 = litedramcore_choose_cmd_valids[7];
		end
	endcase
end
always @(*) begin
	rhs_array_muxed1 = 14'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a;
		end
		1'd1: begin
			rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a;
		end
		2'd2: begin
			rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a;
		end
		2'd3: begin
			rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a;
		end
		3'd4: begin
			rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a;
		end
		3'd5: begin
			rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a;
		end
		3'd6: begin
			rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a;
		end
		default: begin
			rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed2 = 3'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba;
		end
		1'd1: begin
			rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba;
		end
		2'd2: begin
			rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba;
		end
		2'd3: begin
			rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba;
		end
		3'd4: begin
			rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba;
		end
		3'd5: begin
			rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba;
		end
		3'd6: begin
			rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba;
		end
		default: begin
			rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed3 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read;
		end
		1'd1: begin
			rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read;
		end
		2'd2: begin
			rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read;
		end
		2'd3: begin
			rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read;
		end
		3'd4: begin
			rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read;
		end
		3'd5: begin
			rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read;
		end
		3'd6: begin
			rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read;
		end
		default: begin
			rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed4 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write;
		end
		1'd1: begin
			rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write;
		end
		2'd2: begin
			rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write;
		end
		2'd3: begin
			rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write;
		end
		3'd4: begin
			rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write;
		end
		3'd5: begin
			rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write;
		end
		3'd6: begin
			rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write;
		end
		default: begin
			rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed5 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd;
		end
		1'd1: begin
			rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd;
		end
		2'd2: begin
			rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd;
		end
		2'd3: begin
			rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd;
		end
		3'd4: begin
			rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd;
		end
		3'd5: begin
			rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd;
		end
		3'd6: begin
			rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd;
		end
		default: begin
			rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd;
		end
	endcase
end
always @(*) begin
	t_array_muxed0 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas;
		end
		1'd1: begin
			t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas;
		end
		2'd2: begin
			t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas;
		end
		2'd3: begin
			t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas;
		end
		3'd4: begin
			t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas;
		end
		3'd5: begin
			t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas;
		end
		3'd6: begin
			t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas;
		end
		default: begin
			t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas;
		end
	endcase
end
always @(*) begin
	t_array_muxed1 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras;
		end
		1'd1: begin
			t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras;
		end
		2'd2: begin
			t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras;
		end
		2'd3: begin
			t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras;
		end
		3'd4: begin
			t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras;
		end
		3'd5: begin
			t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras;
		end
		3'd6: begin
			t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras;
		end
		default: begin
			t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras;
		end
	endcase
end
always @(*) begin
	t_array_muxed2 = 1'd0;
	case (litedramcore_choose_cmd_grant)
		1'd0: begin
			t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we;
		end
		1'd1: begin
			t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we;
		end
		2'd2: begin
			t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we;
		end
		2'd3: begin
			t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we;
		end
		3'd4: begin
			t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we;
		end
		3'd5: begin
			t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we;
		end
		3'd6: begin
			t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we;
		end
		default: begin
			t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed6 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[0];
		end
		1'd1: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[1];
		end
		2'd2: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[2];
		end
		2'd3: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[3];
		end
		3'd4: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[4];
		end
		3'd5: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[5];
		end
		3'd6: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[6];
		end
		default: begin
			rhs_array_muxed6 = litedramcore_choose_req_valids[7];
		end
	endcase
end
always @(*) begin
	rhs_array_muxed7 = 14'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a;
		end
		1'd1: begin
			rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a;
		end
		2'd2: begin
			rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a;
		end
		2'd3: begin
			rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a;
		end
		3'd4: begin
			rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a;
		end
		3'd5: begin
			rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a;
		end
		3'd6: begin
			rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a;
		end
		default: begin
			rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed8 = 3'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba;
		end
		1'd1: begin
			rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba;
		end
		2'd2: begin
			rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba;
		end
		2'd3: begin
			rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba;
		end
		3'd4: begin
			rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba;
		end
		3'd5: begin
			rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba;
		end
		3'd6: begin
			rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba;
		end
		default: begin
			rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed9 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read;
		end
		1'd1: begin
			rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read;
		end
		2'd2: begin
			rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read;
		end
		2'd3: begin
			rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read;
		end
		3'd4: begin
			rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read;
		end
		3'd5: begin
			rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read;
		end
		3'd6: begin
			rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read;
		end
		default: begin
			rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed10 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write;
		end
		1'd1: begin
			rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write;
		end
		2'd2: begin
			rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write;
		end
		2'd3: begin
			rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write;
		end
		3'd4: begin
			rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write;
		end
		3'd5: begin
			rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write;
		end
		3'd6: begin
			rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write;
		end
		default: begin
			rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed11 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd;
		end
		1'd1: begin
			rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd;
		end
		2'd2: begin
			rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd;
		end
		2'd3: begin
			rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd;
		end
		3'd4: begin
			rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd;
		end
		3'd5: begin
			rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd;
		end
		3'd6: begin
			rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd;
		end
		default: begin
			rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd;
		end
	endcase
end
always @(*) begin
	t_array_muxed3 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas;
		end
		1'd1: begin
			t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas;
		end
		2'd2: begin
			t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas;
		end
		2'd3: begin
			t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas;
		end
		3'd4: begin
			t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas;
		end
		3'd5: begin
			t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas;
		end
		3'd6: begin
			t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas;
		end
		default: begin
			t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas;
		end
	endcase
end
always @(*) begin
	t_array_muxed4 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras;
		end
		1'd1: begin
			t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras;
		end
		2'd2: begin
			t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras;
		end
		2'd3: begin
			t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras;
		end
		3'd4: begin
			t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras;
		end
		3'd5: begin
			t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras;
		end
		3'd6: begin
			t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras;
		end
		default: begin
			t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras;
		end
	endcase
end
always @(*) begin
	t_array_muxed5 = 1'd0;
	case (litedramcore_choose_req_grant)
		1'd0: begin
			t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we;
		end
		1'd1: begin
			t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we;
		end
		2'd2: begin
			t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we;
		end
		2'd3: begin
			t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we;
		end
		3'd4: begin
			t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we;
		end
		3'd5: begin
			t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we;
		end
		3'd6: begin
			t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we;
		end
		default: begin
			t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed12 = 21'd0;
	case (roundrobin0_grant)
		default: begin
			rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed13 = 1'd0;
	case (roundrobin0_grant)
		default: begin
			rhs_array_muxed13 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed14 = 1'd0;
	case (roundrobin0_grant)
		default: begin
			rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed15 = 21'd0;
	case (roundrobin1_grant)
		default: begin
			rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed16 = 1'd0;
	case (roundrobin1_grant)
		default: begin
			rhs_array_muxed16 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed17 = 1'd0;
	case (roundrobin1_grant)
		default: begin
			rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed18 = 21'd0;
	case (roundrobin2_grant)
		default: begin
			rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed19 = 1'd0;
	case (roundrobin2_grant)
		default: begin
			rhs_array_muxed19 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed20 = 1'd0;
	case (roundrobin2_grant)
		default: begin
			rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed21 = 21'd0;
	case (roundrobin3_grant)
		default: begin
			rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed22 = 1'd0;
	case (roundrobin3_grant)
		default: begin
			rhs_array_muxed22 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed23 = 1'd0;
	case (roundrobin3_grant)
		default: begin
			rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed24 = 21'd0;
	case (roundrobin4_grant)
		default: begin
			rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed25 = 1'd0;
	case (roundrobin4_grant)
		default: begin
			rhs_array_muxed25 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed26 = 1'd0;
	case (roundrobin4_grant)
		default: begin
			rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed27 = 21'd0;
	case (roundrobin5_grant)
		default: begin
			rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed28 = 1'd0;
	case (roundrobin5_grant)
		default: begin
			rhs_array_muxed28 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed29 = 1'd0;
	case (roundrobin5_grant)
		default: begin
			rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed30 = 21'd0;
	case (roundrobin6_grant)
		default: begin
			rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed31 = 1'd0;
	case (roundrobin6_grant)
		default: begin
			rhs_array_muxed31 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed32 = 1'd0;
	case (roundrobin6_grant)
		default: begin
			rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	rhs_array_muxed33 = 21'd0;
	case (roundrobin7_grant)
		default: begin
			rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
		end
	endcase
end
always @(*) begin
	rhs_array_muxed34 = 1'd0;
	case (roundrobin7_grant)
		default: begin
			rhs_array_muxed34 = user_port_cmd_payload_we;
		end
	endcase
end
always @(*) begin
	rhs_array_muxed35 = 1'd0;
	case (roundrobin7_grant)
		default: begin
			rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
		end
	endcase
end
always @(*) begin
	array_muxed0 = 3'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed0 = litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed0 = litedramcore_cmd_payload_ba[2:0];
		end
	endcase
end
always @(*) begin
	array_muxed1 = 14'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed1 = litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed1 = litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed1 = litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed1 = litedramcore_cmd_payload_a;
		end
	endcase
end
always @(*) begin
	array_muxed2 = 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed2 = 1'd0;
		end
		1'd1: begin
			array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
end
always @(*) begin
	array_muxed3 = 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed3 = 1'd0;
		end
		1'd1: begin
			array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
end
always @(*) begin
	array_muxed4 = 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed4 = 1'd0;
		end
		1'd1: begin
			array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
end
always @(*) begin
	array_muxed5 = 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed5 = 1'd0;
		end
		1'd1: begin
			array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
end
always @(*) begin
	array_muxed6 = 1'd0;
	case (litedramcore_steerer_sel0)
		1'd0: begin
			array_muxed6 = 1'd0;
		end
		1'd1: begin
			array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
end
always @(*) begin
	array_muxed7 = 3'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed7 = litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed7 = litedramcore_cmd_payload_ba[2:0];
		end
	endcase
end
always @(*) begin
	array_muxed8 = 14'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed8 = litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed8 = litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed8 = litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed8 = litedramcore_cmd_payload_a;
		end
	endcase
end
always @(*) begin
	array_muxed9 = 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed9 = 1'd0;
		end
		1'd1: begin
			array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
end
always @(*) begin
	array_muxed10 = 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed10 = 1'd0;
		end
		1'd1: begin
			array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
end
always @(*) begin
	array_muxed11 = 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed11 = 1'd0;
		end
		1'd1: begin
			array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
end
always @(*) begin
	array_muxed12 = 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed12 = 1'd0;
		end
		1'd1: begin
			array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
end
always @(*) begin
	array_muxed13 = 1'd0;
	case (litedramcore_steerer_sel1)
		1'd0: begin
			array_muxed13 = 1'd0;
		end
		1'd1: begin
			array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
end
always @(*) begin
	array_muxed14 = 3'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed14 = litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed14 = litedramcore_cmd_payload_ba[2:0];
		end
	endcase
end
always @(*) begin
	array_muxed15 = 14'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed15 = litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed15 = litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed15 = litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed15 = litedramcore_cmd_payload_a;
		end
	endcase
end
always @(*) begin
	array_muxed16 = 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed16 = 1'd0;
		end
		1'd1: begin
			array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
end
always @(*) begin
	array_muxed17 = 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed17 = 1'd0;
		end
		1'd1: begin
			array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
end
always @(*) begin
	array_muxed18 = 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed18 = 1'd0;
		end
		1'd1: begin
			array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
end
always @(*) begin
	array_muxed19 = 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed19 = 1'd0;
		end
		1'd1: begin
			array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
end
always @(*) begin
	array_muxed20 = 1'd0;
	case (litedramcore_steerer_sel2)
		1'd0: begin
			array_muxed20 = 1'd0;
		end
		1'd1: begin
			array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
end
always @(*) begin
	array_muxed21 = 3'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed21 = litedramcore_nop_ba[2:0];
		end
		1'd1: begin
			array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
		end
		2'd2: begin
			array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0];
		end
		default: begin
			array_muxed21 = litedramcore_cmd_payload_ba[2:0];
		end
	endcase
end
always @(*) begin
	array_muxed22 = 14'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed22 = litedramcore_nop_a;
		end
		1'd1: begin
			array_muxed22 = litedramcore_choose_cmd_cmd_payload_a;
		end
		2'd2: begin
			array_muxed22 = litedramcore_choose_req_cmd_payload_a;
		end
		default: begin
			array_muxed22 = litedramcore_cmd_payload_a;
		end
	endcase
end
always @(*) begin
	array_muxed23 = 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed23 = 1'd0;
		end
		1'd1: begin
			array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
		end
		2'd2: begin
			array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
		end
		default: begin
			array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
		end
	endcase
end
always @(*) begin
	array_muxed24 = 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed24 = 1'd0;
		end
		1'd1: begin
			array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
		end
		2'd2: begin
			array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
		end
		default: begin
			array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
		end
	endcase
end
always @(*) begin
	array_muxed25 = 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed25 = 1'd0;
		end
		1'd1: begin
			array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
		end
		2'd2: begin
			array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
		end
		default: begin
			array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
		end
	endcase
end
always @(*) begin
	array_muxed26 = 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed26 = 1'd0;
		end
		1'd1: begin
			array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
		end
		2'd2: begin
			array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
		end
		default: begin
			array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
		end
	endcase
end
always @(*) begin
	array_muxed27 = 1'd0;
	case (litedramcore_steerer_sel3)
		1'd0: begin
			array_muxed27 = 1'd0;
		end
		1'd1: begin
			array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
		end
		2'd2: begin
			array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
		end
		default: begin
			array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
		end
	endcase
end

always @(posedge por_clk) begin
	int_rst <= 1'd0;
end

always @(posedge sys_clk) begin
	state <= next_state;
	ddrphy_new_bank_write0 <= ddrphy_bank_write0;
	ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0;
	ddrphy_new_bank_write1 <= ddrphy_new_bank_write0;
	ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0;
	ddrphy_new_bank_write2 <= ddrphy_bank_write1;
	ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1;
	ddrphy_new_bank_write3 <= ddrphy_new_bank_write2;
	ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2;
	ddrphy_new_bank_write4 <= ddrphy_bank_write2;
	ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2;
	ddrphy_new_bank_write5 <= ddrphy_new_bank_write4;
	ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4;
	ddrphy_new_bank_write6 <= ddrphy_bank_write3;
	ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3;
	ddrphy_new_bank_write7 <= ddrphy_new_bank_write6;
	ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6;
	ddrphy_new_bank_write8 <= ddrphy_bank_write4;
	ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4;
	ddrphy_new_bank_write9 <= ddrphy_new_bank_write8;
	ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8;
	ddrphy_new_bank_write10 <= ddrphy_bank_write5;
	ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5;
	ddrphy_new_bank_write11 <= ddrphy_new_bank_write10;
	ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10;
	ddrphy_new_bank_write12 <= ddrphy_bank_write6;
	ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6;
	ddrphy_new_bank_write13 <= ddrphy_new_bank_write12;
	ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12;
	ddrphy_new_bank_write14 <= ddrphy_bank_write7;
	ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7;
	ddrphy_new_bank_write15 <= ddrphy_new_bank_write14;
	ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14;
	ddrphy_new_banks_read0 <= ddrphy_banks_read;
	ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data;
	ddrphy_new_banks_read1 <= ddrphy_new_banks_read0;
	ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0;
	ddrphy_new_banks_read2 <= ddrphy_new_banks_read1;
	ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1;
	ddrphy_new_banks_read3 <= ddrphy_new_banks_read2;
	ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2;
	ddrphy_new_banks_read4 <= ddrphy_new_banks_read3;
	ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3;
	ddrphy_new_banks_read5 <= ddrphy_new_banks_read4;
	ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4;
	ddrphy_new_banks_read6 <= ddrphy_new_banks_read5;
	ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5;
	ddrphy_new_banks_read7 <= ddrphy_new_banks_read6;
	ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6;
	ddrphy_new_banks_read8 <= ddrphy_new_banks_read7;
	ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7;
	if (ddrphy_bankmodel0_precharge) begin
		ddrphy_bankmodel0_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel0_activate) begin
			ddrphy_bankmodel0_active <= 1'd1;
			ddrphy_bankmodel0_row <= ddrphy_bankmodel0_activate_row;
		end
	end
	if (ddrphy_bankmodel1_precharge) begin
		ddrphy_bankmodel1_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel1_activate) begin
			ddrphy_bankmodel1_active <= 1'd1;
			ddrphy_bankmodel1_row <= ddrphy_bankmodel1_activate_row;
		end
	end
	if (ddrphy_bankmodel2_precharge) begin
		ddrphy_bankmodel2_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel2_activate) begin
			ddrphy_bankmodel2_active <= 1'd1;
			ddrphy_bankmodel2_row <= ddrphy_bankmodel2_activate_row;
		end
	end
	if (ddrphy_bankmodel3_precharge) begin
		ddrphy_bankmodel3_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel3_activate) begin
			ddrphy_bankmodel3_active <= 1'd1;
			ddrphy_bankmodel3_row <= ddrphy_bankmodel3_activate_row;
		end
	end
	if (ddrphy_bankmodel4_precharge) begin
		ddrphy_bankmodel4_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel4_activate) begin
			ddrphy_bankmodel4_active <= 1'd1;
			ddrphy_bankmodel4_row <= ddrphy_bankmodel4_activate_row;
		end
	end
	if (ddrphy_bankmodel5_precharge) begin
		ddrphy_bankmodel5_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel5_activate) begin
			ddrphy_bankmodel5_active <= 1'd1;
			ddrphy_bankmodel5_row <= ddrphy_bankmodel5_activate_row;
		end
	end
	if (ddrphy_bankmodel6_precharge) begin
		ddrphy_bankmodel6_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel6_activate) begin
			ddrphy_bankmodel6_active <= 1'd1;
			ddrphy_bankmodel6_row <= ddrphy_bankmodel6_activate_row;
		end
	end
	if (ddrphy_bankmodel7_precharge) begin
		ddrphy_bankmodel7_active <= 1'd0;
	end else begin
		if (ddrphy_bankmodel7_activate) begin
			ddrphy_bankmodel7_active <= 1'd1;
			ddrphy_bankmodel7_row <= ddrphy_bankmodel7_activate_row;
		end
	end
	if (litedramcore_inti_p0_rddata_valid) begin
		litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
	end
	if (litedramcore_inti_p1_rddata_valid) begin
		litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
	end
	if (litedramcore_inti_p2_rddata_valid) begin
		litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
	end
	if (litedramcore_inti_p3_rddata_valid) begin
		litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
	end
	if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
		litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
	end else begin
		litedramcore_timer_count1 <= 10'd781;
	end
	litedramcore_postponer_req_o <= 1'd0;
	if (litedramcore_postponer_req_i) begin
		litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
		if ((litedramcore_postponer_count == 1'd0)) begin
			litedramcore_postponer_count <= 1'd0;
			litedramcore_postponer_req_o <= 1'd1;
		end
	end
	if (litedramcore_sequencer_start0) begin
		litedramcore_sequencer_count <= 1'd0;
	end else begin
		if (litedramcore_sequencer_done1) begin
			if ((litedramcore_sequencer_count != 1'd0)) begin
				litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
			end
		end
	end
	litedramcore_cmd_payload_a <= 1'd0;
	litedramcore_cmd_payload_ba <= 1'd0;
	litedramcore_cmd_payload_cas <= 1'd0;
	litedramcore_cmd_payload_ras <= 1'd0;
	litedramcore_cmd_payload_we <= 1'd0;
	litedramcore_sequencer_done1 <= 1'd0;
	if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
		litedramcore_cmd_payload_a <= 11'd1024;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd1;
		litedramcore_cmd_payload_we <= 1'd1;
	end
	if ((litedramcore_sequencer_counter == 2'd3)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd1;
		litedramcore_cmd_payload_ras <= 1'd1;
		litedramcore_cmd_payload_we <= 1'd0;
	end
	if ((litedramcore_sequencer_counter == 6'd35)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd0;
		litedramcore_cmd_payload_we <= 1'd0;
		litedramcore_sequencer_done1 <= 1'd1;
	end
	if ((litedramcore_sequencer_counter == 6'd35)) begin
		litedramcore_sequencer_counter <= 1'd0;
	end else begin
		if ((litedramcore_sequencer_counter != 1'd0)) begin
			litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
		end else begin
			if (litedramcore_sequencer_start1) begin
				litedramcore_sequencer_counter <= 1'd1;
			end
		end
	end
	if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
		litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
	end else begin
		litedramcore_zqcs_timer_count1 <= 27'd99999999;
	end
	litedramcore_zqcs_executer_done <= 1'd0;
	if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
		litedramcore_cmd_payload_a <= 11'd1024;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd1;
		litedramcore_cmd_payload_we <= 1'd1;
	end
	if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd0;
		litedramcore_cmd_payload_we <= 1'd1;
	end
	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
		litedramcore_cmd_payload_a <= 1'd0;
		litedramcore_cmd_payload_ba <= 1'd0;
		litedramcore_cmd_payload_cas <= 1'd0;
		litedramcore_cmd_payload_ras <= 1'd0;
		litedramcore_cmd_payload_we <= 1'd0;
		litedramcore_zqcs_executer_done <= 1'd1;
	end
	if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
		litedramcore_zqcs_executer_counter <= 1'd0;
	end else begin
		if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
			litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
		end else begin
			if (litedramcore_zqcs_executer_start) begin
				litedramcore_zqcs_executer_counter <= 1'd1;
			end
		end
	end
	refresher_state <= refresher_next_state;
	if (litedramcore_bankmachine0_row_close) begin
		litedramcore_bankmachine0_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine0_row_open) begin
			litedramcore_bankmachine0_row_opened <= 1'd1;
			litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
		litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
		litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
		litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine0_twtpcon_valid) begin
		litedramcore_bankmachine0_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
			litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine0_trccon_valid) begin
		litedramcore_bankmachine0_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine0_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine0_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine0_trccon_ready)) begin
			litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
			if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
				litedramcore_bankmachine0_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine0_trascon_valid) begin
		litedramcore_bankmachine0_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine0_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine0_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine0_trascon_ready)) begin
			litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
			if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
				litedramcore_bankmachine0_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine0_state <= bankmachine0_next_state;
	if (litedramcore_bankmachine1_row_close) begin
		litedramcore_bankmachine1_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine1_row_open) begin
			litedramcore_bankmachine1_row_opened <= 1'd1;
			litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
		litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
		litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
		litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine1_twtpcon_valid) begin
		litedramcore_bankmachine1_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
			litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine1_trccon_valid) begin
		litedramcore_bankmachine1_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine1_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine1_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine1_trccon_ready)) begin
			litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
			if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
				litedramcore_bankmachine1_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine1_trascon_valid) begin
		litedramcore_bankmachine1_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine1_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine1_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine1_trascon_ready)) begin
			litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
			if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
				litedramcore_bankmachine1_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine1_state <= bankmachine1_next_state;
	if (litedramcore_bankmachine2_row_close) begin
		litedramcore_bankmachine2_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine2_row_open) begin
			litedramcore_bankmachine2_row_opened <= 1'd1;
			litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
		litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
		litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
		litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine2_twtpcon_valid) begin
		litedramcore_bankmachine2_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
			litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine2_trccon_valid) begin
		litedramcore_bankmachine2_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine2_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine2_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine2_trccon_ready)) begin
			litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
			if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
				litedramcore_bankmachine2_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine2_trascon_valid) begin
		litedramcore_bankmachine2_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine2_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine2_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine2_trascon_ready)) begin
			litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
			if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
				litedramcore_bankmachine2_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine2_state <= bankmachine2_next_state;
	if (litedramcore_bankmachine3_row_close) begin
		litedramcore_bankmachine3_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine3_row_open) begin
			litedramcore_bankmachine3_row_opened <= 1'd1;
			litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
		litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
		litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
		litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine3_twtpcon_valid) begin
		litedramcore_bankmachine3_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
			litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine3_trccon_valid) begin
		litedramcore_bankmachine3_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine3_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine3_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine3_trccon_ready)) begin
			litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
			if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
				litedramcore_bankmachine3_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine3_trascon_valid) begin
		litedramcore_bankmachine3_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine3_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine3_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine3_trascon_ready)) begin
			litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
			if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
				litedramcore_bankmachine3_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine3_state <= bankmachine3_next_state;
	if (litedramcore_bankmachine4_row_close) begin
		litedramcore_bankmachine4_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine4_row_open) begin
			litedramcore_bankmachine4_row_opened <= 1'd1;
			litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
		litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
		litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
		litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine4_twtpcon_valid) begin
		litedramcore_bankmachine4_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
			litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine4_trccon_valid) begin
		litedramcore_bankmachine4_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine4_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine4_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine4_trccon_ready)) begin
			litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
			if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
				litedramcore_bankmachine4_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine4_trascon_valid) begin
		litedramcore_bankmachine4_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine4_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine4_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine4_trascon_ready)) begin
			litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
			if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
				litedramcore_bankmachine4_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine4_state <= bankmachine4_next_state;
	if (litedramcore_bankmachine5_row_close) begin
		litedramcore_bankmachine5_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine5_row_open) begin
			litedramcore_bankmachine5_row_opened <= 1'd1;
			litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
		litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
		litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
		litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine5_twtpcon_valid) begin
		litedramcore_bankmachine5_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
			litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine5_trccon_valid) begin
		litedramcore_bankmachine5_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine5_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine5_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine5_trccon_ready)) begin
			litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
			if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
				litedramcore_bankmachine5_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine5_trascon_valid) begin
		litedramcore_bankmachine5_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine5_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine5_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine5_trascon_ready)) begin
			litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
			if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
				litedramcore_bankmachine5_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine5_state <= bankmachine5_next_state;
	if (litedramcore_bankmachine6_row_close) begin
		litedramcore_bankmachine6_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine6_row_open) begin
			litedramcore_bankmachine6_row_opened <= 1'd1;
			litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
		litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
		litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
		litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine6_twtpcon_valid) begin
		litedramcore_bankmachine6_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
			litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine6_trccon_valid) begin
		litedramcore_bankmachine6_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine6_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine6_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine6_trccon_ready)) begin
			litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
			if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
				litedramcore_bankmachine6_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine6_trascon_valid) begin
		litedramcore_bankmachine6_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine6_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine6_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine6_trascon_ready)) begin
			litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
			if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
				litedramcore_bankmachine6_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine6_state <= bankmachine6_next_state;
	if (litedramcore_bankmachine7_row_close) begin
		litedramcore_bankmachine7_row_opened <= 1'd0;
	end else begin
		if (litedramcore_bankmachine7_row_open) begin
			litedramcore_bankmachine7_row_opened <= 1'd1;
			litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
		end
	end
	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
	end
	if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
	end
	if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
		if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
		end
	end else begin
		if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
			litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
		end
	end
	if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
		litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
		litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
		litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
		litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
		litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
	end
	if (litedramcore_bankmachine7_twtpcon_valid) begin
		litedramcore_bankmachine7_twtpcon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
			litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
			if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
				litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine7_trccon_valid) begin
		litedramcore_bankmachine7_trccon_count <= 3'd5;
		if (1'd0) begin
			litedramcore_bankmachine7_trccon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine7_trccon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine7_trccon_ready)) begin
			litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
			if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
				litedramcore_bankmachine7_trccon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_bankmachine7_trascon_valid) begin
		litedramcore_bankmachine7_trascon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_bankmachine7_trascon_ready <= 1'd1;
		end else begin
			litedramcore_bankmachine7_trascon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_bankmachine7_trascon_ready)) begin
			litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
			if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
				litedramcore_bankmachine7_trascon_ready <= 1'd1;
			end
		end
	end
	bankmachine7_state <= bankmachine7_next_state;
	if ((~litedramcore_en0)) begin
		litedramcore_time0 <= 5'd31;
	end else begin
		if ((~litedramcore_max_time0)) begin
			litedramcore_time0 <= (litedramcore_time0 - 1'd1);
		end
	end
	if ((~litedramcore_en1)) begin
		litedramcore_time1 <= 4'd15;
	end else begin
		if ((~litedramcore_max_time1)) begin
			litedramcore_time1 <= (litedramcore_time1 - 1'd1);
		end
	end
	if (litedramcore_choose_cmd_ce) begin
		case (litedramcore_choose_cmd_grant)
			1'd0: begin
				if (litedramcore_choose_cmd_request[1]) begin
					litedramcore_choose_cmd_grant <= 1'd1;
				end else begin
					if (litedramcore_choose_cmd_request[2]) begin
						litedramcore_choose_cmd_grant <= 2'd2;
					end else begin
						if (litedramcore_choose_cmd_request[3]) begin
							litedramcore_choose_cmd_grant <= 2'd3;
						end else begin
							if (litedramcore_choose_cmd_request[4]) begin
								litedramcore_choose_cmd_grant <= 3'd4;
							end else begin
								if (litedramcore_choose_cmd_request[5]) begin
									litedramcore_choose_cmd_grant <= 3'd5;
								end else begin
									if (litedramcore_choose_cmd_request[6]) begin
										litedramcore_choose_cmd_grant <= 3'd6;
									end else begin
										if (litedramcore_choose_cmd_request[7]) begin
											litedramcore_choose_cmd_grant <= 3'd7;
										end
									end
								end
							end
						end
					end
				end
			end
			1'd1: begin
				if (litedramcore_choose_cmd_request[2]) begin
					litedramcore_choose_cmd_grant <= 2'd2;
				end else begin
					if (litedramcore_choose_cmd_request[3]) begin
						litedramcore_choose_cmd_grant <= 2'd3;
					end else begin
						if (litedramcore_choose_cmd_request[4]) begin
							litedramcore_choose_cmd_grant <= 3'd4;
						end else begin
							if (litedramcore_choose_cmd_request[5]) begin
								litedramcore_choose_cmd_grant <= 3'd5;
							end else begin
								if (litedramcore_choose_cmd_request[6]) begin
									litedramcore_choose_cmd_grant <= 3'd6;
								end else begin
									if (litedramcore_choose_cmd_request[7]) begin
										litedramcore_choose_cmd_grant <= 3'd7;
									end else begin
										if (litedramcore_choose_cmd_request[0]) begin
											litedramcore_choose_cmd_grant <= 1'd0;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd2: begin
				if (litedramcore_choose_cmd_request[3]) begin
					litedramcore_choose_cmd_grant <= 2'd3;
				end else begin
					if (litedramcore_choose_cmd_request[4]) begin
						litedramcore_choose_cmd_grant <= 3'd4;
					end else begin
						if (litedramcore_choose_cmd_request[5]) begin
							litedramcore_choose_cmd_grant <= 3'd5;
						end else begin
							if (litedramcore_choose_cmd_request[6]) begin
								litedramcore_choose_cmd_grant <= 3'd6;
							end else begin
								if (litedramcore_choose_cmd_request[7]) begin
									litedramcore_choose_cmd_grant <= 3'd7;
								end else begin
									if (litedramcore_choose_cmd_request[0]) begin
										litedramcore_choose_cmd_grant <= 1'd0;
									end else begin
										if (litedramcore_choose_cmd_request[1]) begin
											litedramcore_choose_cmd_grant <= 1'd1;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd3: begin
				if (litedramcore_choose_cmd_request[4]) begin
					litedramcore_choose_cmd_grant <= 3'd4;
				end else begin
					if (litedramcore_choose_cmd_request[5]) begin
						litedramcore_choose_cmd_grant <= 3'd5;
					end else begin
						if (litedramcore_choose_cmd_request[6]) begin
							litedramcore_choose_cmd_grant <= 3'd6;
						end else begin
							if (litedramcore_choose_cmd_request[7]) begin
								litedramcore_choose_cmd_grant <= 3'd7;
							end else begin
								if (litedramcore_choose_cmd_request[0]) begin
									litedramcore_choose_cmd_grant <= 1'd0;
								end else begin
									if (litedramcore_choose_cmd_request[1]) begin
										litedramcore_choose_cmd_grant <= 1'd1;
									end else begin
										if (litedramcore_choose_cmd_request[2]) begin
											litedramcore_choose_cmd_grant <= 2'd2;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd4: begin
				if (litedramcore_choose_cmd_request[5]) begin
					litedramcore_choose_cmd_grant <= 3'd5;
				end else begin
					if (litedramcore_choose_cmd_request[6]) begin
						litedramcore_choose_cmd_grant <= 3'd6;
					end else begin
						if (litedramcore_choose_cmd_request[7]) begin
							litedramcore_choose_cmd_grant <= 3'd7;
						end else begin
							if (litedramcore_choose_cmd_request[0]) begin
								litedramcore_choose_cmd_grant <= 1'd0;
							end else begin
								if (litedramcore_choose_cmd_request[1]) begin
									litedramcore_choose_cmd_grant <= 1'd1;
								end else begin
									if (litedramcore_choose_cmd_request[2]) begin
										litedramcore_choose_cmd_grant <= 2'd2;
									end else begin
										if (litedramcore_choose_cmd_request[3]) begin
											litedramcore_choose_cmd_grant <= 2'd3;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd5: begin
				if (litedramcore_choose_cmd_request[6]) begin
					litedramcore_choose_cmd_grant <= 3'd6;
				end else begin
					if (litedramcore_choose_cmd_request[7]) begin
						litedramcore_choose_cmd_grant <= 3'd7;
					end else begin
						if (litedramcore_choose_cmd_request[0]) begin
							litedramcore_choose_cmd_grant <= 1'd0;
						end else begin
							if (litedramcore_choose_cmd_request[1]) begin
								litedramcore_choose_cmd_grant <= 1'd1;
							end else begin
								if (litedramcore_choose_cmd_request[2]) begin
									litedramcore_choose_cmd_grant <= 2'd2;
								end else begin
									if (litedramcore_choose_cmd_request[3]) begin
										litedramcore_choose_cmd_grant <= 2'd3;
									end else begin
										if (litedramcore_choose_cmd_request[4]) begin
											litedramcore_choose_cmd_grant <= 3'd4;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd6: begin
				if (litedramcore_choose_cmd_request[7]) begin
					litedramcore_choose_cmd_grant <= 3'd7;
				end else begin
					if (litedramcore_choose_cmd_request[0]) begin
						litedramcore_choose_cmd_grant <= 1'd0;
					end else begin
						if (litedramcore_choose_cmd_request[1]) begin
							litedramcore_choose_cmd_grant <= 1'd1;
						end else begin
							if (litedramcore_choose_cmd_request[2]) begin
								litedramcore_choose_cmd_grant <= 2'd2;
							end else begin
								if (litedramcore_choose_cmd_request[3]) begin
									litedramcore_choose_cmd_grant <= 2'd3;
								end else begin
									if (litedramcore_choose_cmd_request[4]) begin
										litedramcore_choose_cmd_grant <= 3'd4;
									end else begin
										if (litedramcore_choose_cmd_request[5]) begin
											litedramcore_choose_cmd_grant <= 3'd5;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd7: begin
				if (litedramcore_choose_cmd_request[0]) begin
					litedramcore_choose_cmd_grant <= 1'd0;
				end else begin
					if (litedramcore_choose_cmd_request[1]) begin
						litedramcore_choose_cmd_grant <= 1'd1;
					end else begin
						if (litedramcore_choose_cmd_request[2]) begin
							litedramcore_choose_cmd_grant <= 2'd2;
						end else begin
							if (litedramcore_choose_cmd_request[3]) begin
								litedramcore_choose_cmd_grant <= 2'd3;
							end else begin
								if (litedramcore_choose_cmd_request[4]) begin
									litedramcore_choose_cmd_grant <= 3'd4;
								end else begin
									if (litedramcore_choose_cmd_request[5]) begin
										litedramcore_choose_cmd_grant <= 3'd5;
									end else begin
										if (litedramcore_choose_cmd_request[6]) begin
											litedramcore_choose_cmd_grant <= 3'd6;
										end
									end
								end
							end
						end
					end
				end
			end
		endcase
	end
	if (litedramcore_choose_req_ce) begin
		case (litedramcore_choose_req_grant)
			1'd0: begin
				if (litedramcore_choose_req_request[1]) begin
					litedramcore_choose_req_grant <= 1'd1;
				end else begin
					if (litedramcore_choose_req_request[2]) begin
						litedramcore_choose_req_grant <= 2'd2;
					end else begin
						if (litedramcore_choose_req_request[3]) begin
							litedramcore_choose_req_grant <= 2'd3;
						end else begin
							if (litedramcore_choose_req_request[4]) begin
								litedramcore_choose_req_grant <= 3'd4;
							end else begin
								if (litedramcore_choose_req_request[5]) begin
									litedramcore_choose_req_grant <= 3'd5;
								end else begin
									if (litedramcore_choose_req_request[6]) begin
										litedramcore_choose_req_grant <= 3'd6;
									end else begin
										if (litedramcore_choose_req_request[7]) begin
											litedramcore_choose_req_grant <= 3'd7;
										end
									end
								end
							end
						end
					end
				end
			end
			1'd1: begin
				if (litedramcore_choose_req_request[2]) begin
					litedramcore_choose_req_grant <= 2'd2;
				end else begin
					if (litedramcore_choose_req_request[3]) begin
						litedramcore_choose_req_grant <= 2'd3;
					end else begin
						if (litedramcore_choose_req_request[4]) begin
							litedramcore_choose_req_grant <= 3'd4;
						end else begin
							if (litedramcore_choose_req_request[5]) begin
								litedramcore_choose_req_grant <= 3'd5;
							end else begin
								if (litedramcore_choose_req_request[6]) begin
									litedramcore_choose_req_grant <= 3'd6;
								end else begin
									if (litedramcore_choose_req_request[7]) begin
										litedramcore_choose_req_grant <= 3'd7;
									end else begin
										if (litedramcore_choose_req_request[0]) begin
											litedramcore_choose_req_grant <= 1'd0;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd2: begin
				if (litedramcore_choose_req_request[3]) begin
					litedramcore_choose_req_grant <= 2'd3;
				end else begin
					if (litedramcore_choose_req_request[4]) begin
						litedramcore_choose_req_grant <= 3'd4;
					end else begin
						if (litedramcore_choose_req_request[5]) begin
							litedramcore_choose_req_grant <= 3'd5;
						end else begin
							if (litedramcore_choose_req_request[6]) begin
								litedramcore_choose_req_grant <= 3'd6;
							end else begin
								if (litedramcore_choose_req_request[7]) begin
									litedramcore_choose_req_grant <= 3'd7;
								end else begin
									if (litedramcore_choose_req_request[0]) begin
										litedramcore_choose_req_grant <= 1'd0;
									end else begin
										if (litedramcore_choose_req_request[1]) begin
											litedramcore_choose_req_grant <= 1'd1;
										end
									end
								end
							end
						end
					end
				end
			end
			2'd3: begin
				if (litedramcore_choose_req_request[4]) begin
					litedramcore_choose_req_grant <= 3'd4;
				end else begin
					if (litedramcore_choose_req_request[5]) begin
						litedramcore_choose_req_grant <= 3'd5;
					end else begin
						if (litedramcore_choose_req_request[6]) begin
							litedramcore_choose_req_grant <= 3'd6;
						end else begin
							if (litedramcore_choose_req_request[7]) begin
								litedramcore_choose_req_grant <= 3'd7;
							end else begin
								if (litedramcore_choose_req_request[0]) begin
									litedramcore_choose_req_grant <= 1'd0;
								end else begin
									if (litedramcore_choose_req_request[1]) begin
										litedramcore_choose_req_grant <= 1'd1;
									end else begin
										if (litedramcore_choose_req_request[2]) begin
											litedramcore_choose_req_grant <= 2'd2;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd4: begin
				if (litedramcore_choose_req_request[5]) begin
					litedramcore_choose_req_grant <= 3'd5;
				end else begin
					if (litedramcore_choose_req_request[6]) begin
						litedramcore_choose_req_grant <= 3'd6;
					end else begin
						if (litedramcore_choose_req_request[7]) begin
							litedramcore_choose_req_grant <= 3'd7;
						end else begin
							if (litedramcore_choose_req_request[0]) begin
								litedramcore_choose_req_grant <= 1'd0;
							end else begin
								if (litedramcore_choose_req_request[1]) begin
									litedramcore_choose_req_grant <= 1'd1;
								end else begin
									if (litedramcore_choose_req_request[2]) begin
										litedramcore_choose_req_grant <= 2'd2;
									end else begin
										if (litedramcore_choose_req_request[3]) begin
											litedramcore_choose_req_grant <= 2'd3;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd5: begin
				if (litedramcore_choose_req_request[6]) begin
					litedramcore_choose_req_grant <= 3'd6;
				end else begin
					if (litedramcore_choose_req_request[7]) begin
						litedramcore_choose_req_grant <= 3'd7;
					end else begin
						if (litedramcore_choose_req_request[0]) begin
							litedramcore_choose_req_grant <= 1'd0;
						end else begin
							if (litedramcore_choose_req_request[1]) begin
								litedramcore_choose_req_grant <= 1'd1;
							end else begin
								if (litedramcore_choose_req_request[2]) begin
									litedramcore_choose_req_grant <= 2'd2;
								end else begin
									if (litedramcore_choose_req_request[3]) begin
										litedramcore_choose_req_grant <= 2'd3;
									end else begin
										if (litedramcore_choose_req_request[4]) begin
											litedramcore_choose_req_grant <= 3'd4;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd6: begin
				if (litedramcore_choose_req_request[7]) begin
					litedramcore_choose_req_grant <= 3'd7;
				end else begin
					if (litedramcore_choose_req_request[0]) begin
						litedramcore_choose_req_grant <= 1'd0;
					end else begin
						if (litedramcore_choose_req_request[1]) begin
							litedramcore_choose_req_grant <= 1'd1;
						end else begin
							if (litedramcore_choose_req_request[2]) begin
								litedramcore_choose_req_grant <= 2'd2;
							end else begin
								if (litedramcore_choose_req_request[3]) begin
									litedramcore_choose_req_grant <= 2'd3;
								end else begin
									if (litedramcore_choose_req_request[4]) begin
										litedramcore_choose_req_grant <= 3'd4;
									end else begin
										if (litedramcore_choose_req_request[5]) begin
											litedramcore_choose_req_grant <= 3'd5;
										end
									end
								end
							end
						end
					end
				end
			end
			3'd7: begin
				if (litedramcore_choose_req_request[0]) begin
					litedramcore_choose_req_grant <= 1'd0;
				end else begin
					if (litedramcore_choose_req_request[1]) begin
						litedramcore_choose_req_grant <= 1'd1;
					end else begin
						if (litedramcore_choose_req_request[2]) begin
							litedramcore_choose_req_grant <= 2'd2;
						end else begin
							if (litedramcore_choose_req_request[3]) begin
								litedramcore_choose_req_grant <= 2'd3;
							end else begin
								if (litedramcore_choose_req_request[4]) begin
									litedramcore_choose_req_grant <= 3'd4;
								end else begin
									if (litedramcore_choose_req_request[5]) begin
										litedramcore_choose_req_grant <= 3'd5;
									end else begin
										if (litedramcore_choose_req_request[6]) begin
											litedramcore_choose_req_grant <= 3'd6;
										end
									end
								end
							end
						end
					end
				end
			end
		endcase
	end
	litedramcore_dfi_p0_cs_n <= 1'd0;
	litedramcore_dfi_p0_bank <= array_muxed0;
	litedramcore_dfi_p0_address <= array_muxed1;
	litedramcore_dfi_p0_cas_n <= (~array_muxed2);
	litedramcore_dfi_p0_ras_n <= (~array_muxed3);
	litedramcore_dfi_p0_we_n <= (~array_muxed4);
	litedramcore_dfi_p0_rddata_en <= array_muxed5;
	litedramcore_dfi_p0_wrdata_en <= array_muxed6;
	litedramcore_dfi_p1_cs_n <= 1'd0;
	litedramcore_dfi_p1_bank <= array_muxed7;
	litedramcore_dfi_p1_address <= array_muxed8;
	litedramcore_dfi_p1_cas_n <= (~array_muxed9);
	litedramcore_dfi_p1_ras_n <= (~array_muxed10);
	litedramcore_dfi_p1_we_n <= (~array_muxed11);
	litedramcore_dfi_p1_rddata_en <= array_muxed12;
	litedramcore_dfi_p1_wrdata_en <= array_muxed13;
	litedramcore_dfi_p2_cs_n <= 1'd0;
	litedramcore_dfi_p2_bank <= array_muxed14;
	litedramcore_dfi_p2_address <= array_muxed15;
	litedramcore_dfi_p2_cas_n <= (~array_muxed16);
	litedramcore_dfi_p2_ras_n <= (~array_muxed17);
	litedramcore_dfi_p2_we_n <= (~array_muxed18);
	litedramcore_dfi_p2_rddata_en <= array_muxed19;
	litedramcore_dfi_p2_wrdata_en <= array_muxed20;
	litedramcore_dfi_p3_cs_n <= 1'd0;
	litedramcore_dfi_p3_bank <= array_muxed21;
	litedramcore_dfi_p3_address <= array_muxed22;
	litedramcore_dfi_p3_cas_n <= (~array_muxed23);
	litedramcore_dfi_p3_ras_n <= (~array_muxed24);
	litedramcore_dfi_p3_we_n <= (~array_muxed25);
	litedramcore_dfi_p3_rddata_en <= array_muxed26;
	litedramcore_dfi_p3_wrdata_en <= array_muxed27;
	if (litedramcore_trrdcon_valid) begin
		litedramcore_trrdcon_count <= 1'd1;
		if (1'd0) begin
			litedramcore_trrdcon_ready <= 1'd1;
		end else begin
			litedramcore_trrdcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_trrdcon_ready)) begin
			litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
			if ((litedramcore_trrdcon_count == 1'd1)) begin
				litedramcore_trrdcon_ready <= 1'd1;
			end
		end
	end
	litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
	if ((litedramcore_tfawcon_count < 3'd4)) begin
		if ((litedramcore_tfawcon_count == 2'd3)) begin
			litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
		end else begin
			litedramcore_tfawcon_ready <= 1'd1;
		end
	end
	if (litedramcore_tccdcon_valid) begin
		litedramcore_tccdcon_count <= 1'd0;
		if (1'd1) begin
			litedramcore_tccdcon_ready <= 1'd1;
		end else begin
			litedramcore_tccdcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_tccdcon_ready)) begin
			litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
			if ((litedramcore_tccdcon_count == 1'd1)) begin
				litedramcore_tccdcon_ready <= 1'd1;
			end
		end
	end
	if (litedramcore_twtrcon_valid) begin
		litedramcore_twtrcon_count <= 3'd4;
		if (1'd0) begin
			litedramcore_twtrcon_ready <= 1'd1;
		end else begin
			litedramcore_twtrcon_ready <= 1'd0;
		end
	end else begin
		if ((~litedramcore_twtrcon_ready)) begin
			litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
			if ((litedramcore_twtrcon_count == 1'd1)) begin
				litedramcore_twtrcon_ready <= 1'd1;
			end
		end
	end
	multiplexer_state <= multiplexer_next_state;
	new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
	new_master_wdata_ready1 <= new_master_wdata_ready0;
	new_master_wdata_ready2 <= new_master_wdata_ready1;
	new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
	new_master_rdata_valid1 <= new_master_rdata_valid0;
	new_master_rdata_valid2 <= new_master_rdata_valid1;
	new_master_rdata_valid3 <= new_master_rdata_valid2;
	new_master_rdata_valid4 <= new_master_rdata_valid3;
	new_master_rdata_valid5 <= new_master_rdata_valid4;
	new_master_rdata_valid6 <= new_master_rdata_valid5;
	new_master_rdata_valid7 <= new_master_rdata_valid6;
	new_master_rdata_valid8 <= new_master_rdata_valid7;
	new_master_rdata_valid9 <= new_master_rdata_valid8;
	interface0_bank_bus_dat_r <= 1'd0;
	if (csrbank0_sel) begin
		case (interface0_bank_bus_adr[0])
			1'd0: begin
				interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
			end
			1'd1: begin
				interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
			end
		endcase
	end
	if (csrbank0_init_done0_re) begin
		init_done_storage <= csrbank0_init_done0_r;
	end
	init_done_re <= csrbank0_init_done0_re;
	if (csrbank0_init_error0_re) begin
		init_error_storage <= csrbank0_init_error0_r;
	end
	init_error_re <= csrbank0_init_error0_re;
	interface1_bank_bus_dat_r <= 1'd0;
	if (csrbank1_sel) begin
		case (interface1_bank_bus_adr[4:0])
			1'd0: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
			end
			1'd1: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w;
			end
			2'd2: begin
				interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
			end
			2'd3: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
			end
			3'd4: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
			end
			3'd5: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
			end
			3'd6: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
			end
			3'd7: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
			end
			4'd8: begin
				interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
			end
			4'd9: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
			end
			4'd10: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
			end
			4'd11: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
			end
			4'd12: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
			end
			4'd13: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
			end
			4'd14: begin
				interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
			end
			4'd15: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
			end
			5'd16: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
			end
			5'd17: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
			end
			5'd18: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
			end
			5'd19: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
			end
			5'd20: begin
				interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
			end
			5'd21: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
			end
			5'd22: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
			end
			5'd23: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
			end
			5'd24: begin
				interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
			end
		endcase
	end
	if (csrbank1_dfii_control0_re) begin
		litedramcore_storage[3:0] <= csrbank1_dfii_control0_r;
	end
	litedramcore_re <= csrbank1_dfii_control0_re;
	if (csrbank1_dfii_pi0_command0_re) begin
		litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
	end
	litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
	if (csrbank1_dfii_pi0_address0_re) begin
		litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
	end
	litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
	if (csrbank1_dfii_pi0_baddress0_re) begin
		litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
	end
	litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
	if (csrbank1_dfii_pi0_wrdata0_re) begin
		litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
	end
	litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
	if (csrbank1_dfii_pi1_command0_re) begin
		litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
	end
	litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
	if (csrbank1_dfii_pi1_address0_re) begin
		litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
	end
	litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
	if (csrbank1_dfii_pi1_baddress0_re) begin
		litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
	end
	litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
	if (csrbank1_dfii_pi1_wrdata0_re) begin
		litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
	end
	litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
	if (csrbank1_dfii_pi2_command0_re) begin
		litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
	end
	litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
	if (csrbank1_dfii_pi2_address0_re) begin
		litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
	end
	litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
	if (csrbank1_dfii_pi2_baddress0_re) begin
		litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
	end
	litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
	if (csrbank1_dfii_pi2_wrdata0_re) begin
		litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
	end
	litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
	if (csrbank1_dfii_pi3_command0_re) begin
		litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
	end
	litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
	if (csrbank1_dfii_pi3_address0_re) begin
		litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
	end
	litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
	if (csrbank1_dfii_pi3_baddress0_re) begin
		litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
	end
	litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
	if (csrbank1_dfii_pi3_wrdata0_re) begin
		litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
	end
	litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
	if (sys_rst) begin
		ddrphy_bankmodel0_active <= 1'd0;
		ddrphy_bankmodel0_row <= 14'd0;
		ddrphy_bankmodel1_active <= 1'd0;
		ddrphy_bankmodel1_row <= 14'd0;
		ddrphy_bankmodel2_active <= 1'd0;
		ddrphy_bankmodel2_row <= 14'd0;
		ddrphy_bankmodel3_active <= 1'd0;
		ddrphy_bankmodel3_row <= 14'd0;
		ddrphy_bankmodel4_active <= 1'd0;
		ddrphy_bankmodel4_row <= 14'd0;
		ddrphy_bankmodel5_active <= 1'd0;
		ddrphy_bankmodel5_row <= 14'd0;
		ddrphy_bankmodel6_active <= 1'd0;
		ddrphy_bankmodel6_row <= 14'd0;
		ddrphy_bankmodel7_active <= 1'd0;
		ddrphy_bankmodel7_row <= 14'd0;
		ddrphy_new_bank_write0 <= 1'd0;
		ddrphy_new_bank_write_col0 <= 10'd0;
		ddrphy_new_bank_write1 <= 1'd0;
		ddrphy_new_bank_write_col1 <= 10'd0;
		ddrphy_new_bank_write2 <= 1'd0;
		ddrphy_new_bank_write_col2 <= 10'd0;
		ddrphy_new_bank_write3 <= 1'd0;
		ddrphy_new_bank_write_col3 <= 10'd0;
		ddrphy_new_bank_write4 <= 1'd0;
		ddrphy_new_bank_write_col4 <= 10'd0;
		ddrphy_new_bank_write5 <= 1'd0;
		ddrphy_new_bank_write_col5 <= 10'd0;
		ddrphy_new_bank_write6 <= 1'd0;
		ddrphy_new_bank_write_col6 <= 10'd0;
		ddrphy_new_bank_write7 <= 1'd0;
		ddrphy_new_bank_write_col7 <= 10'd0;
		ddrphy_new_bank_write8 <= 1'd0;
		ddrphy_new_bank_write_col8 <= 10'd0;
		ddrphy_new_bank_write9 <= 1'd0;
		ddrphy_new_bank_write_col9 <= 10'd0;
		ddrphy_new_bank_write10 <= 1'd0;
		ddrphy_new_bank_write_col10 <= 10'd0;
		ddrphy_new_bank_write11 <= 1'd0;
		ddrphy_new_bank_write_col11 <= 10'd0;
		ddrphy_new_bank_write12 <= 1'd0;
		ddrphy_new_bank_write_col12 <= 10'd0;
		ddrphy_new_bank_write13 <= 1'd0;
		ddrphy_new_bank_write_col13 <= 10'd0;
		ddrphy_new_bank_write14 <= 1'd0;
		ddrphy_new_bank_write_col14 <= 10'd0;
		ddrphy_new_bank_write15 <= 1'd0;
		ddrphy_new_bank_write_col15 <= 10'd0;
		ddrphy_new_banks_read0 <= 1'd0;
		ddrphy_new_banks_read_data0 <= 128'd0;
		ddrphy_new_banks_read1 <= 1'd0;
		ddrphy_new_banks_read_data1 <= 128'd0;
		ddrphy_new_banks_read2 <= 1'd0;
		ddrphy_new_banks_read_data2 <= 128'd0;
		ddrphy_new_banks_read3 <= 1'd0;
		ddrphy_new_banks_read_data3 <= 128'd0;
		ddrphy_new_banks_read4 <= 1'd0;
		ddrphy_new_banks_read_data4 <= 128'd0;
		ddrphy_new_banks_read5 <= 1'd0;
		ddrphy_new_banks_read_data5 <= 128'd0;
		ddrphy_new_banks_read6 <= 1'd0;
		ddrphy_new_banks_read_data6 <= 128'd0;
		ddrphy_new_banks_read7 <= 1'd0;
		ddrphy_new_banks_read_data7 <= 128'd0;
		ddrphy_new_banks_read8 <= 1'd0;
		ddrphy_new_banks_read_data8 <= 128'd0;
		litedramcore_storage <= 4'd1;
		litedramcore_re <= 1'd0;
		litedramcore_phaseinjector0_command_storage <= 6'd0;
		litedramcore_phaseinjector0_command_re <= 1'd0;
		litedramcore_phaseinjector0_address_re <= 1'd0;
		litedramcore_phaseinjector0_baddress_re <= 1'd0;
		litedramcore_phaseinjector0_wrdata_re <= 1'd0;
		litedramcore_phaseinjector0_status <= 32'd0;
		litedramcore_phaseinjector1_command_storage <= 6'd0;
		litedramcore_phaseinjector1_command_re <= 1'd0;
		litedramcore_phaseinjector1_address_re <= 1'd0;
		litedramcore_phaseinjector1_baddress_re <= 1'd0;
		litedramcore_phaseinjector1_wrdata_re <= 1'd0;
		litedramcore_phaseinjector1_status <= 32'd0;
		litedramcore_phaseinjector2_command_storage <= 6'd0;
		litedramcore_phaseinjector2_command_re <= 1'd0;
		litedramcore_phaseinjector2_address_re <= 1'd0;
		litedramcore_phaseinjector2_baddress_re <= 1'd0;
		litedramcore_phaseinjector2_wrdata_re <= 1'd0;
		litedramcore_phaseinjector2_status <= 32'd0;
		litedramcore_phaseinjector3_command_storage <= 6'd0;
		litedramcore_phaseinjector3_command_re <= 1'd0;
		litedramcore_phaseinjector3_address_re <= 1'd0;
		litedramcore_phaseinjector3_baddress_re <= 1'd0;
		litedramcore_phaseinjector3_wrdata_re <= 1'd0;
		litedramcore_phaseinjector3_status <= 32'd0;
		litedramcore_dfi_p0_address <= 14'd0;
		litedramcore_dfi_p0_bank <= 3'd0;
		litedramcore_dfi_p0_cas_n <= 1'd1;
		litedramcore_dfi_p0_cs_n <= 1'd1;
		litedramcore_dfi_p0_ras_n <= 1'd1;
		litedramcore_dfi_p0_we_n <= 1'd1;
		litedramcore_dfi_p0_wrdata_en <= 1'd0;
		litedramcore_dfi_p0_rddata_en <= 1'd0;
		litedramcore_dfi_p1_address <= 14'd0;
		litedramcore_dfi_p1_bank <= 3'd0;
		litedramcore_dfi_p1_cas_n <= 1'd1;
		litedramcore_dfi_p1_cs_n <= 1'd1;
		litedramcore_dfi_p1_ras_n <= 1'd1;
		litedramcore_dfi_p1_we_n <= 1'd1;
		litedramcore_dfi_p1_wrdata_en <= 1'd0;
		litedramcore_dfi_p1_rddata_en <= 1'd0;
		litedramcore_dfi_p2_address <= 14'd0;
		litedramcore_dfi_p2_bank <= 3'd0;
		litedramcore_dfi_p2_cas_n <= 1'd1;
		litedramcore_dfi_p2_cs_n <= 1'd1;
		litedramcore_dfi_p2_ras_n <= 1'd1;
		litedramcore_dfi_p2_we_n <= 1'd1;
		litedramcore_dfi_p2_wrdata_en <= 1'd0;
		litedramcore_dfi_p2_rddata_en <= 1'd0;
		litedramcore_dfi_p3_address <= 14'd0;
		litedramcore_dfi_p3_bank <= 3'd0;
		litedramcore_dfi_p3_cas_n <= 1'd1;
		litedramcore_dfi_p3_cs_n <= 1'd1;
		litedramcore_dfi_p3_ras_n <= 1'd1;
		litedramcore_dfi_p3_we_n <= 1'd1;
		litedramcore_dfi_p3_wrdata_en <= 1'd0;
		litedramcore_dfi_p3_rddata_en <= 1'd0;
		litedramcore_timer_count1 <= 10'd781;
		litedramcore_postponer_req_o <= 1'd0;
		litedramcore_postponer_count <= 1'd0;
		litedramcore_sequencer_done1 <= 1'd0;
		litedramcore_sequencer_counter <= 6'd0;
		litedramcore_sequencer_count <= 1'd0;
		litedramcore_zqcs_timer_count1 <= 27'd99999999;
		litedramcore_zqcs_executer_done <= 1'd0;
		litedramcore_zqcs_executer_counter <= 5'd0;
		litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine0_row <= 14'd0;
		litedramcore_bankmachine0_row_opened <= 1'd0;
		litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine0_twtpcon_count <= 3'd0;
		litedramcore_bankmachine0_trccon_ready <= 1'd0;
		litedramcore_bankmachine0_trccon_count <= 3'd0;
		litedramcore_bankmachine0_trascon_ready <= 1'd0;
		litedramcore_bankmachine0_trascon_count <= 3'd0;
		litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine1_row <= 14'd0;
		litedramcore_bankmachine1_row_opened <= 1'd0;
		litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine1_twtpcon_count <= 3'd0;
		litedramcore_bankmachine1_trccon_ready <= 1'd0;
		litedramcore_bankmachine1_trccon_count <= 3'd0;
		litedramcore_bankmachine1_trascon_ready <= 1'd0;
		litedramcore_bankmachine1_trascon_count <= 3'd0;
		litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine2_row <= 14'd0;
		litedramcore_bankmachine2_row_opened <= 1'd0;
		litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine2_twtpcon_count <= 3'd0;
		litedramcore_bankmachine2_trccon_ready <= 1'd0;
		litedramcore_bankmachine2_trccon_count <= 3'd0;
		litedramcore_bankmachine2_trascon_ready <= 1'd0;
		litedramcore_bankmachine2_trascon_count <= 3'd0;
		litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine3_row <= 14'd0;
		litedramcore_bankmachine3_row_opened <= 1'd0;
		litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine3_twtpcon_count <= 3'd0;
		litedramcore_bankmachine3_trccon_ready <= 1'd0;
		litedramcore_bankmachine3_trccon_count <= 3'd0;
		litedramcore_bankmachine3_trascon_ready <= 1'd0;
		litedramcore_bankmachine3_trascon_count <= 3'd0;
		litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine4_row <= 14'd0;
		litedramcore_bankmachine4_row_opened <= 1'd0;
		litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine4_twtpcon_count <= 3'd0;
		litedramcore_bankmachine4_trccon_ready <= 1'd0;
		litedramcore_bankmachine4_trccon_count <= 3'd0;
		litedramcore_bankmachine4_trascon_ready <= 1'd0;
		litedramcore_bankmachine4_trascon_count <= 3'd0;
		litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine5_row <= 14'd0;
		litedramcore_bankmachine5_row_opened <= 1'd0;
		litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine5_twtpcon_count <= 3'd0;
		litedramcore_bankmachine5_trccon_ready <= 1'd0;
		litedramcore_bankmachine5_trccon_count <= 3'd0;
		litedramcore_bankmachine5_trascon_ready <= 1'd0;
		litedramcore_bankmachine5_trascon_count <= 3'd0;
		litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine6_row <= 14'd0;
		litedramcore_bankmachine6_row_opened <= 1'd0;
		litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine6_twtpcon_count <= 3'd0;
		litedramcore_bankmachine6_trccon_ready <= 1'd0;
		litedramcore_bankmachine6_trccon_count <= 3'd0;
		litedramcore_bankmachine6_trascon_ready <= 1'd0;
		litedramcore_bankmachine6_trascon_count <= 3'd0;
		litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
		litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
		litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
		litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
		litedramcore_bankmachine7_row <= 14'd0;
		litedramcore_bankmachine7_row_opened <= 1'd0;
		litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
		litedramcore_bankmachine7_twtpcon_count <= 3'd0;
		litedramcore_bankmachine7_trccon_ready <= 1'd0;
		litedramcore_bankmachine7_trccon_count <= 3'd0;
		litedramcore_bankmachine7_trascon_ready <= 1'd0;
		litedramcore_bankmachine7_trascon_count <= 3'd0;
		litedramcore_choose_cmd_grant <= 3'd0;
		litedramcore_choose_req_grant <= 3'd0;
		litedramcore_trrdcon_ready <= 1'd0;
		litedramcore_trrdcon_count <= 1'd0;
		litedramcore_tfawcon_ready <= 1'd1;
		litedramcore_tfawcon_window <= 5'd0;
		litedramcore_tccdcon_ready <= 1'd0;
		litedramcore_tccdcon_count <= 1'd0;
		litedramcore_twtrcon_ready <= 1'd0;
		litedramcore_twtrcon_count <= 3'd0;
		litedramcore_time0 <= 5'd0;
		litedramcore_time1 <= 4'd0;
		init_done_storage <= 1'd0;
		init_done_re <= 1'd0;
		init_error_storage <= 1'd0;
		init_error_re <= 1'd0;
		state <= 1'd0;
		refresher_state <= 2'd0;
		bankmachine0_state <= 4'd0;
		bankmachine1_state <= 4'd0;
		bankmachine2_state <= 4'd0;
		bankmachine3_state <= 4'd0;
		bankmachine4_state <= 4'd0;
		bankmachine5_state <= 4'd0;
		bankmachine6_state <= 4'd0;
		bankmachine7_state <= 4'd0;
		multiplexer_state <= 4'd0;
		new_master_wdata_ready0 <= 1'd0;
		new_master_wdata_ready1 <= 1'd0;
		new_master_wdata_ready2 <= 1'd0;
		new_master_rdata_valid0 <= 1'd0;
		new_master_rdata_valid1 <= 1'd0;
		new_master_rdata_valid2 <= 1'd0;
		new_master_rdata_valid3 <= 1'd0;
		new_master_rdata_valid4 <= 1'd0;
		new_master_rdata_valid5 <= 1'd0;
		new_master_rdata_valid6 <= 1'd0;
		new_master_rdata_valid7 <= 1'd0;
		new_master_rdata_valid8 <= 1'd0;
		new_master_rdata_valid9 <= 1'd0;
	end
end

reg [127:0] mem[0:2097151];
reg [20:0] memadr;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel0_write_port_we[0])
		mem[ddrphy_bankmodel0_write_port_adr][7:0] <= ddrphy_bankmodel0_write_port_dat_w[7:0];
	if (ddrphy_bankmodel0_write_port_we[1])
		mem[ddrphy_bankmodel0_write_port_adr][15:8] <= ddrphy_bankmodel0_write_port_dat_w[15:8];
	if (ddrphy_bankmodel0_write_port_we[2])
		mem[ddrphy_bankmodel0_write_port_adr][23:16] <= ddrphy_bankmodel0_write_port_dat_w[23:16];
	if (ddrphy_bankmodel0_write_port_we[3])
		mem[ddrphy_bankmodel0_write_port_adr][31:24] <= ddrphy_bankmodel0_write_port_dat_w[31:24];
	if (ddrphy_bankmodel0_write_port_we[4])
		mem[ddrphy_bankmodel0_write_port_adr][39:32] <= ddrphy_bankmodel0_write_port_dat_w[39:32];
	if (ddrphy_bankmodel0_write_port_we[5])
		mem[ddrphy_bankmodel0_write_port_adr][47:40] <= ddrphy_bankmodel0_write_port_dat_w[47:40];
	if (ddrphy_bankmodel0_write_port_we[6])
		mem[ddrphy_bankmodel0_write_port_adr][55:48] <= ddrphy_bankmodel0_write_port_dat_w[55:48];
	if (ddrphy_bankmodel0_write_port_we[7])
		mem[ddrphy_bankmodel0_write_port_adr][63:56] <= ddrphy_bankmodel0_write_port_dat_w[63:56];
	if (ddrphy_bankmodel0_write_port_we[8])
		mem[ddrphy_bankmodel0_write_port_adr][71:64] <= ddrphy_bankmodel0_write_port_dat_w[71:64];
	if (ddrphy_bankmodel0_write_port_we[9])
		mem[ddrphy_bankmodel0_write_port_adr][79:72] <= ddrphy_bankmodel0_write_port_dat_w[79:72];
	if (ddrphy_bankmodel0_write_port_we[10])
		mem[ddrphy_bankmodel0_write_port_adr][87:80] <= ddrphy_bankmodel0_write_port_dat_w[87:80];
	if (ddrphy_bankmodel0_write_port_we[11])
		mem[ddrphy_bankmodel0_write_port_adr][95:88] <= ddrphy_bankmodel0_write_port_dat_w[95:88];
	if (ddrphy_bankmodel0_write_port_we[12])
		mem[ddrphy_bankmodel0_write_port_adr][103:96] <= ddrphy_bankmodel0_write_port_dat_w[103:96];
	if (ddrphy_bankmodel0_write_port_we[13])
		mem[ddrphy_bankmodel0_write_port_adr][111:104] <= ddrphy_bankmodel0_write_port_dat_w[111:104];
	if (ddrphy_bankmodel0_write_port_we[14])
		mem[ddrphy_bankmodel0_write_port_adr][119:112] <= ddrphy_bankmodel0_write_port_dat_w[119:112];
	if (ddrphy_bankmodel0_write_port_we[15])
		mem[ddrphy_bankmodel0_write_port_adr][127:120] <= ddrphy_bankmodel0_write_port_dat_w[127:120];
	memadr <= ddrphy_bankmodel0_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel0_write_port_dat_r = mem[memadr];
assign ddrphy_bankmodel0_read_port_dat_r = mem[ddrphy_bankmodel0_read_port_adr];

reg [127:0] mem_1[0:2097151];
reg [20:0] memadr_1;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel1_write_port_we[0])
		mem_1[ddrphy_bankmodel1_write_port_adr][7:0] <= ddrphy_bankmodel1_write_port_dat_w[7:0];
	if (ddrphy_bankmodel1_write_port_we[1])
		mem_1[ddrphy_bankmodel1_write_port_adr][15:8] <= ddrphy_bankmodel1_write_port_dat_w[15:8];
	if (ddrphy_bankmodel1_write_port_we[2])
		mem_1[ddrphy_bankmodel1_write_port_adr][23:16] <= ddrphy_bankmodel1_write_port_dat_w[23:16];
	if (ddrphy_bankmodel1_write_port_we[3])
		mem_1[ddrphy_bankmodel1_write_port_adr][31:24] <= ddrphy_bankmodel1_write_port_dat_w[31:24];
	if (ddrphy_bankmodel1_write_port_we[4])
		mem_1[ddrphy_bankmodel1_write_port_adr][39:32] <= ddrphy_bankmodel1_write_port_dat_w[39:32];
	if (ddrphy_bankmodel1_write_port_we[5])
		mem_1[ddrphy_bankmodel1_write_port_adr][47:40] <= ddrphy_bankmodel1_write_port_dat_w[47:40];
	if (ddrphy_bankmodel1_write_port_we[6])
		mem_1[ddrphy_bankmodel1_write_port_adr][55:48] <= ddrphy_bankmodel1_write_port_dat_w[55:48];
	if (ddrphy_bankmodel1_write_port_we[7])
		mem_1[ddrphy_bankmodel1_write_port_adr][63:56] <= ddrphy_bankmodel1_write_port_dat_w[63:56];
	if (ddrphy_bankmodel1_write_port_we[8])
		mem_1[ddrphy_bankmodel1_write_port_adr][71:64] <= ddrphy_bankmodel1_write_port_dat_w[71:64];
	if (ddrphy_bankmodel1_write_port_we[9])
		mem_1[ddrphy_bankmodel1_write_port_adr][79:72] <= ddrphy_bankmodel1_write_port_dat_w[79:72];
	if (ddrphy_bankmodel1_write_port_we[10])
		mem_1[ddrphy_bankmodel1_write_port_adr][87:80] <= ddrphy_bankmodel1_write_port_dat_w[87:80];
	if (ddrphy_bankmodel1_write_port_we[11])
		mem_1[ddrphy_bankmodel1_write_port_adr][95:88] <= ddrphy_bankmodel1_write_port_dat_w[95:88];
	if (ddrphy_bankmodel1_write_port_we[12])
		mem_1[ddrphy_bankmodel1_write_port_adr][103:96] <= ddrphy_bankmodel1_write_port_dat_w[103:96];
	if (ddrphy_bankmodel1_write_port_we[13])
		mem_1[ddrphy_bankmodel1_write_port_adr][111:104] <= ddrphy_bankmodel1_write_port_dat_w[111:104];
	if (ddrphy_bankmodel1_write_port_we[14])
		mem_1[ddrphy_bankmodel1_write_port_adr][119:112] <= ddrphy_bankmodel1_write_port_dat_w[119:112];
	if (ddrphy_bankmodel1_write_port_we[15])
		mem_1[ddrphy_bankmodel1_write_port_adr][127:120] <= ddrphy_bankmodel1_write_port_dat_w[127:120];
	memadr_1 <= ddrphy_bankmodel1_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1];
assign ddrphy_bankmodel1_read_port_dat_r = mem_1[ddrphy_bankmodel1_read_port_adr];

reg [127:0] mem_2[0:2097151];
reg [20:0] memadr_2;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel2_write_port_we[0])
		mem_2[ddrphy_bankmodel2_write_port_adr][7:0] <= ddrphy_bankmodel2_write_port_dat_w[7:0];
	if (ddrphy_bankmodel2_write_port_we[1])
		mem_2[ddrphy_bankmodel2_write_port_adr][15:8] <= ddrphy_bankmodel2_write_port_dat_w[15:8];
	if (ddrphy_bankmodel2_write_port_we[2])
		mem_2[ddrphy_bankmodel2_write_port_adr][23:16] <= ddrphy_bankmodel2_write_port_dat_w[23:16];
	if (ddrphy_bankmodel2_write_port_we[3])
		mem_2[ddrphy_bankmodel2_write_port_adr][31:24] <= ddrphy_bankmodel2_write_port_dat_w[31:24];
	if (ddrphy_bankmodel2_write_port_we[4])
		mem_2[ddrphy_bankmodel2_write_port_adr][39:32] <= ddrphy_bankmodel2_write_port_dat_w[39:32];
	if (ddrphy_bankmodel2_write_port_we[5])
		mem_2[ddrphy_bankmodel2_write_port_adr][47:40] <= ddrphy_bankmodel2_write_port_dat_w[47:40];
	if (ddrphy_bankmodel2_write_port_we[6])
		mem_2[ddrphy_bankmodel2_write_port_adr][55:48] <= ddrphy_bankmodel2_write_port_dat_w[55:48];
	if (ddrphy_bankmodel2_write_port_we[7])
		mem_2[ddrphy_bankmodel2_write_port_adr][63:56] <= ddrphy_bankmodel2_write_port_dat_w[63:56];
	if (ddrphy_bankmodel2_write_port_we[8])
		mem_2[ddrphy_bankmodel2_write_port_adr][71:64] <= ddrphy_bankmodel2_write_port_dat_w[71:64];
	if (ddrphy_bankmodel2_write_port_we[9])
		mem_2[ddrphy_bankmodel2_write_port_adr][79:72] <= ddrphy_bankmodel2_write_port_dat_w[79:72];
	if (ddrphy_bankmodel2_write_port_we[10])
		mem_2[ddrphy_bankmodel2_write_port_adr][87:80] <= ddrphy_bankmodel2_write_port_dat_w[87:80];
	if (ddrphy_bankmodel2_write_port_we[11])
		mem_2[ddrphy_bankmodel2_write_port_adr][95:88] <= ddrphy_bankmodel2_write_port_dat_w[95:88];
	if (ddrphy_bankmodel2_write_port_we[12])
		mem_2[ddrphy_bankmodel2_write_port_adr][103:96] <= ddrphy_bankmodel2_write_port_dat_w[103:96];
	if (ddrphy_bankmodel2_write_port_we[13])
		mem_2[ddrphy_bankmodel2_write_port_adr][111:104] <= ddrphy_bankmodel2_write_port_dat_w[111:104];
	if (ddrphy_bankmodel2_write_port_we[14])
		mem_2[ddrphy_bankmodel2_write_port_adr][119:112] <= ddrphy_bankmodel2_write_port_dat_w[119:112];
	if (ddrphy_bankmodel2_write_port_we[15])
		mem_2[ddrphy_bankmodel2_write_port_adr][127:120] <= ddrphy_bankmodel2_write_port_dat_w[127:120];
	memadr_2 <= ddrphy_bankmodel2_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2];
assign ddrphy_bankmodel2_read_port_dat_r = mem_2[ddrphy_bankmodel2_read_port_adr];

reg [127:0] mem_3[0:2097151];
reg [20:0] memadr_3;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel3_write_port_we[0])
		mem_3[ddrphy_bankmodel3_write_port_adr][7:0] <= ddrphy_bankmodel3_write_port_dat_w[7:0];
	if (ddrphy_bankmodel3_write_port_we[1])
		mem_3[ddrphy_bankmodel3_write_port_adr][15:8] <= ddrphy_bankmodel3_write_port_dat_w[15:8];
	if (ddrphy_bankmodel3_write_port_we[2])
		mem_3[ddrphy_bankmodel3_write_port_adr][23:16] <= ddrphy_bankmodel3_write_port_dat_w[23:16];
	if (ddrphy_bankmodel3_write_port_we[3])
		mem_3[ddrphy_bankmodel3_write_port_adr][31:24] <= ddrphy_bankmodel3_write_port_dat_w[31:24];
	if (ddrphy_bankmodel3_write_port_we[4])
		mem_3[ddrphy_bankmodel3_write_port_adr][39:32] <= ddrphy_bankmodel3_write_port_dat_w[39:32];
	if (ddrphy_bankmodel3_write_port_we[5])
		mem_3[ddrphy_bankmodel3_write_port_adr][47:40] <= ddrphy_bankmodel3_write_port_dat_w[47:40];
	if (ddrphy_bankmodel3_write_port_we[6])
		mem_3[ddrphy_bankmodel3_write_port_adr][55:48] <= ddrphy_bankmodel3_write_port_dat_w[55:48];
	if (ddrphy_bankmodel3_write_port_we[7])
		mem_3[ddrphy_bankmodel3_write_port_adr][63:56] <= ddrphy_bankmodel3_write_port_dat_w[63:56];
	if (ddrphy_bankmodel3_write_port_we[8])
		mem_3[ddrphy_bankmodel3_write_port_adr][71:64] <= ddrphy_bankmodel3_write_port_dat_w[71:64];
	if (ddrphy_bankmodel3_write_port_we[9])
		mem_3[ddrphy_bankmodel3_write_port_adr][79:72] <= ddrphy_bankmodel3_write_port_dat_w[79:72];
	if (ddrphy_bankmodel3_write_port_we[10])
		mem_3[ddrphy_bankmodel3_write_port_adr][87:80] <= ddrphy_bankmodel3_write_port_dat_w[87:80];
	if (ddrphy_bankmodel3_write_port_we[11])
		mem_3[ddrphy_bankmodel3_write_port_adr][95:88] <= ddrphy_bankmodel3_write_port_dat_w[95:88];
	if (ddrphy_bankmodel3_write_port_we[12])
		mem_3[ddrphy_bankmodel3_write_port_adr][103:96] <= ddrphy_bankmodel3_write_port_dat_w[103:96];
	if (ddrphy_bankmodel3_write_port_we[13])
		mem_3[ddrphy_bankmodel3_write_port_adr][111:104] <= ddrphy_bankmodel3_write_port_dat_w[111:104];
	if (ddrphy_bankmodel3_write_port_we[14])
		mem_3[ddrphy_bankmodel3_write_port_adr][119:112] <= ddrphy_bankmodel3_write_port_dat_w[119:112];
	if (ddrphy_bankmodel3_write_port_we[15])
		mem_3[ddrphy_bankmodel3_write_port_adr][127:120] <= ddrphy_bankmodel3_write_port_dat_w[127:120];
	memadr_3 <= ddrphy_bankmodel3_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3];
assign ddrphy_bankmodel3_read_port_dat_r = mem_3[ddrphy_bankmodel3_read_port_adr];

reg [127:0] mem_4[0:2097151];
reg [20:0] memadr_4;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel4_write_port_we[0])
		mem_4[ddrphy_bankmodel4_write_port_adr][7:0] <= ddrphy_bankmodel4_write_port_dat_w[7:0];
	if (ddrphy_bankmodel4_write_port_we[1])
		mem_4[ddrphy_bankmodel4_write_port_adr][15:8] <= ddrphy_bankmodel4_write_port_dat_w[15:8];
	if (ddrphy_bankmodel4_write_port_we[2])
		mem_4[ddrphy_bankmodel4_write_port_adr][23:16] <= ddrphy_bankmodel4_write_port_dat_w[23:16];
	if (ddrphy_bankmodel4_write_port_we[3])
		mem_4[ddrphy_bankmodel4_write_port_adr][31:24] <= ddrphy_bankmodel4_write_port_dat_w[31:24];
	if (ddrphy_bankmodel4_write_port_we[4])
		mem_4[ddrphy_bankmodel4_write_port_adr][39:32] <= ddrphy_bankmodel4_write_port_dat_w[39:32];
	if (ddrphy_bankmodel4_write_port_we[5])
		mem_4[ddrphy_bankmodel4_write_port_adr][47:40] <= ddrphy_bankmodel4_write_port_dat_w[47:40];
	if (ddrphy_bankmodel4_write_port_we[6])
		mem_4[ddrphy_bankmodel4_write_port_adr][55:48] <= ddrphy_bankmodel4_write_port_dat_w[55:48];
	if (ddrphy_bankmodel4_write_port_we[7])
		mem_4[ddrphy_bankmodel4_write_port_adr][63:56] <= ddrphy_bankmodel4_write_port_dat_w[63:56];
	if (ddrphy_bankmodel4_write_port_we[8])
		mem_4[ddrphy_bankmodel4_write_port_adr][71:64] <= ddrphy_bankmodel4_write_port_dat_w[71:64];
	if (ddrphy_bankmodel4_write_port_we[9])
		mem_4[ddrphy_bankmodel4_write_port_adr][79:72] <= ddrphy_bankmodel4_write_port_dat_w[79:72];
	if (ddrphy_bankmodel4_write_port_we[10])
		mem_4[ddrphy_bankmodel4_write_port_adr][87:80] <= ddrphy_bankmodel4_write_port_dat_w[87:80];
	if (ddrphy_bankmodel4_write_port_we[11])
		mem_4[ddrphy_bankmodel4_write_port_adr][95:88] <= ddrphy_bankmodel4_write_port_dat_w[95:88];
	if (ddrphy_bankmodel4_write_port_we[12])
		mem_4[ddrphy_bankmodel4_write_port_adr][103:96] <= ddrphy_bankmodel4_write_port_dat_w[103:96];
	if (ddrphy_bankmodel4_write_port_we[13])
		mem_4[ddrphy_bankmodel4_write_port_adr][111:104] <= ddrphy_bankmodel4_write_port_dat_w[111:104];
	if (ddrphy_bankmodel4_write_port_we[14])
		mem_4[ddrphy_bankmodel4_write_port_adr][119:112] <= ddrphy_bankmodel4_write_port_dat_w[119:112];
	if (ddrphy_bankmodel4_write_port_we[15])
		mem_4[ddrphy_bankmodel4_write_port_adr][127:120] <= ddrphy_bankmodel4_write_port_dat_w[127:120];
	memadr_4 <= ddrphy_bankmodel4_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4];
assign ddrphy_bankmodel4_read_port_dat_r = mem_4[ddrphy_bankmodel4_read_port_adr];

reg [127:0] mem_5[0:2097151];
reg [20:0] memadr_5;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel5_write_port_we[0])
		mem_5[ddrphy_bankmodel5_write_port_adr][7:0] <= ddrphy_bankmodel5_write_port_dat_w[7:0];
	if (ddrphy_bankmodel5_write_port_we[1])
		mem_5[ddrphy_bankmodel5_write_port_adr][15:8] <= ddrphy_bankmodel5_write_port_dat_w[15:8];
	if (ddrphy_bankmodel5_write_port_we[2])
		mem_5[ddrphy_bankmodel5_write_port_adr][23:16] <= ddrphy_bankmodel5_write_port_dat_w[23:16];
	if (ddrphy_bankmodel5_write_port_we[3])
		mem_5[ddrphy_bankmodel5_write_port_adr][31:24] <= ddrphy_bankmodel5_write_port_dat_w[31:24];
	if (ddrphy_bankmodel5_write_port_we[4])
		mem_5[ddrphy_bankmodel5_write_port_adr][39:32] <= ddrphy_bankmodel5_write_port_dat_w[39:32];
	if (ddrphy_bankmodel5_write_port_we[5])
		mem_5[ddrphy_bankmodel5_write_port_adr][47:40] <= ddrphy_bankmodel5_write_port_dat_w[47:40];
	if (ddrphy_bankmodel5_write_port_we[6])
		mem_5[ddrphy_bankmodel5_write_port_adr][55:48] <= ddrphy_bankmodel5_write_port_dat_w[55:48];
	if (ddrphy_bankmodel5_write_port_we[7])
		mem_5[ddrphy_bankmodel5_write_port_adr][63:56] <= ddrphy_bankmodel5_write_port_dat_w[63:56];
	if (ddrphy_bankmodel5_write_port_we[8])
		mem_5[ddrphy_bankmodel5_write_port_adr][71:64] <= ddrphy_bankmodel5_write_port_dat_w[71:64];
	if (ddrphy_bankmodel5_write_port_we[9])
		mem_5[ddrphy_bankmodel5_write_port_adr][79:72] <= ddrphy_bankmodel5_write_port_dat_w[79:72];
	if (ddrphy_bankmodel5_write_port_we[10])
		mem_5[ddrphy_bankmodel5_write_port_adr][87:80] <= ddrphy_bankmodel5_write_port_dat_w[87:80];
	if (ddrphy_bankmodel5_write_port_we[11])
		mem_5[ddrphy_bankmodel5_write_port_adr][95:88] <= ddrphy_bankmodel5_write_port_dat_w[95:88];
	if (ddrphy_bankmodel5_write_port_we[12])
		mem_5[ddrphy_bankmodel5_write_port_adr][103:96] <= ddrphy_bankmodel5_write_port_dat_w[103:96];
	if (ddrphy_bankmodel5_write_port_we[13])
		mem_5[ddrphy_bankmodel5_write_port_adr][111:104] <= ddrphy_bankmodel5_write_port_dat_w[111:104];
	if (ddrphy_bankmodel5_write_port_we[14])
		mem_5[ddrphy_bankmodel5_write_port_adr][119:112] <= ddrphy_bankmodel5_write_port_dat_w[119:112];
	if (ddrphy_bankmodel5_write_port_we[15])
		mem_5[ddrphy_bankmodel5_write_port_adr][127:120] <= ddrphy_bankmodel5_write_port_dat_w[127:120];
	memadr_5 <= ddrphy_bankmodel5_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5];
assign ddrphy_bankmodel5_read_port_dat_r = mem_5[ddrphy_bankmodel5_read_port_adr];

reg [127:0] mem_6[0:2097151];
reg [20:0] memadr_6;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel6_write_port_we[0])
		mem_6[ddrphy_bankmodel6_write_port_adr][7:0] <= ddrphy_bankmodel6_write_port_dat_w[7:0];
	if (ddrphy_bankmodel6_write_port_we[1])
		mem_6[ddrphy_bankmodel6_write_port_adr][15:8] <= ddrphy_bankmodel6_write_port_dat_w[15:8];
	if (ddrphy_bankmodel6_write_port_we[2])
		mem_6[ddrphy_bankmodel6_write_port_adr][23:16] <= ddrphy_bankmodel6_write_port_dat_w[23:16];
	if (ddrphy_bankmodel6_write_port_we[3])
		mem_6[ddrphy_bankmodel6_write_port_adr][31:24] <= ddrphy_bankmodel6_write_port_dat_w[31:24];
	if (ddrphy_bankmodel6_write_port_we[4])
		mem_6[ddrphy_bankmodel6_write_port_adr][39:32] <= ddrphy_bankmodel6_write_port_dat_w[39:32];
	if (ddrphy_bankmodel6_write_port_we[5])
		mem_6[ddrphy_bankmodel6_write_port_adr][47:40] <= ddrphy_bankmodel6_write_port_dat_w[47:40];
	if (ddrphy_bankmodel6_write_port_we[6])
		mem_6[ddrphy_bankmodel6_write_port_adr][55:48] <= ddrphy_bankmodel6_write_port_dat_w[55:48];
	if (ddrphy_bankmodel6_write_port_we[7])
		mem_6[ddrphy_bankmodel6_write_port_adr][63:56] <= ddrphy_bankmodel6_write_port_dat_w[63:56];
	if (ddrphy_bankmodel6_write_port_we[8])
		mem_6[ddrphy_bankmodel6_write_port_adr][71:64] <= ddrphy_bankmodel6_write_port_dat_w[71:64];
	if (ddrphy_bankmodel6_write_port_we[9])
		mem_6[ddrphy_bankmodel6_write_port_adr][79:72] <= ddrphy_bankmodel6_write_port_dat_w[79:72];
	if (ddrphy_bankmodel6_write_port_we[10])
		mem_6[ddrphy_bankmodel6_write_port_adr][87:80] <= ddrphy_bankmodel6_write_port_dat_w[87:80];
	if (ddrphy_bankmodel6_write_port_we[11])
		mem_6[ddrphy_bankmodel6_write_port_adr][95:88] <= ddrphy_bankmodel6_write_port_dat_w[95:88];
	if (ddrphy_bankmodel6_write_port_we[12])
		mem_6[ddrphy_bankmodel6_write_port_adr][103:96] <= ddrphy_bankmodel6_write_port_dat_w[103:96];
	if (ddrphy_bankmodel6_write_port_we[13])
		mem_6[ddrphy_bankmodel6_write_port_adr][111:104] <= ddrphy_bankmodel6_write_port_dat_w[111:104];
	if (ddrphy_bankmodel6_write_port_we[14])
		mem_6[ddrphy_bankmodel6_write_port_adr][119:112] <= ddrphy_bankmodel6_write_port_dat_w[119:112];
	if (ddrphy_bankmodel6_write_port_we[15])
		mem_6[ddrphy_bankmodel6_write_port_adr][127:120] <= ddrphy_bankmodel6_write_port_dat_w[127:120];
	memadr_6 <= ddrphy_bankmodel6_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6];
assign ddrphy_bankmodel6_read_port_dat_r = mem_6[ddrphy_bankmodel6_read_port_adr];

reg [127:0] mem_7[0:2097151];
reg [20:0] memadr_7;
always @(posedge sys_clk) begin
	if (ddrphy_bankmodel7_write_port_we[0])
		mem_7[ddrphy_bankmodel7_write_port_adr][7:0] <= ddrphy_bankmodel7_write_port_dat_w[7:0];
	if (ddrphy_bankmodel7_write_port_we[1])
		mem_7[ddrphy_bankmodel7_write_port_adr][15:8] <= ddrphy_bankmodel7_write_port_dat_w[15:8];
	if (ddrphy_bankmodel7_write_port_we[2])
		mem_7[ddrphy_bankmodel7_write_port_adr][23:16] <= ddrphy_bankmodel7_write_port_dat_w[23:16];
	if (ddrphy_bankmodel7_write_port_we[3])
		mem_7[ddrphy_bankmodel7_write_port_adr][31:24] <= ddrphy_bankmodel7_write_port_dat_w[31:24];
	if (ddrphy_bankmodel7_write_port_we[4])
		mem_7[ddrphy_bankmodel7_write_port_adr][39:32] <= ddrphy_bankmodel7_write_port_dat_w[39:32];
	if (ddrphy_bankmodel7_write_port_we[5])
		mem_7[ddrphy_bankmodel7_write_port_adr][47:40] <= ddrphy_bankmodel7_write_port_dat_w[47:40];
	if (ddrphy_bankmodel7_write_port_we[6])
		mem_7[ddrphy_bankmodel7_write_port_adr][55:48] <= ddrphy_bankmodel7_write_port_dat_w[55:48];
	if (ddrphy_bankmodel7_write_port_we[7])
		mem_7[ddrphy_bankmodel7_write_port_adr][63:56] <= ddrphy_bankmodel7_write_port_dat_w[63:56];
	if (ddrphy_bankmodel7_write_port_we[8])
		mem_7[ddrphy_bankmodel7_write_port_adr][71:64] <= ddrphy_bankmodel7_write_port_dat_w[71:64];
	if (ddrphy_bankmodel7_write_port_we[9])
		mem_7[ddrphy_bankmodel7_write_port_adr][79:72] <= ddrphy_bankmodel7_write_port_dat_w[79:72];
	if (ddrphy_bankmodel7_write_port_we[10])
		mem_7[ddrphy_bankmodel7_write_port_adr][87:80] <= ddrphy_bankmodel7_write_port_dat_w[87:80];
	if (ddrphy_bankmodel7_write_port_we[11])
		mem_7[ddrphy_bankmodel7_write_port_adr][95:88] <= ddrphy_bankmodel7_write_port_dat_w[95:88];
	if (ddrphy_bankmodel7_write_port_we[12])
		mem_7[ddrphy_bankmodel7_write_port_adr][103:96] <= ddrphy_bankmodel7_write_port_dat_w[103:96];
	if (ddrphy_bankmodel7_write_port_we[13])
		mem_7[ddrphy_bankmodel7_write_port_adr][111:104] <= ddrphy_bankmodel7_write_port_dat_w[111:104];
	if (ddrphy_bankmodel7_write_port_we[14])
		mem_7[ddrphy_bankmodel7_write_port_adr][119:112] <= ddrphy_bankmodel7_write_port_dat_w[119:112];
	if (ddrphy_bankmodel7_write_port_we[15])
		mem_7[ddrphy_bankmodel7_write_port_adr][127:120] <= ddrphy_bankmodel7_write_port_dat_w[127:120];
	memadr_7 <= ddrphy_bankmodel7_write_port_adr;
end

always @(posedge sys_clk) begin
end

assign ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7];
assign ddrphy_bankmodel7_read_port_dat_r = mem_7[ddrphy_bankmodel7_read_port_adr];

reg [23:0] storage[0:15];
reg [23:0] memdat;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
		storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
	memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_1[0:15];
reg [23:0] memdat_1;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
		storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
	memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_2[0:15];
reg [23:0] memdat_2;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
		storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
	memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_3[0:15];
reg [23:0] memdat_3;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
		storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
	memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_4[0:15];
reg [23:0] memdat_4;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
		storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
	memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_5[0:15];
reg [23:0] memdat_5;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
		storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
	memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_6[0:15];
reg [23:0] memdat_6;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
		storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
	memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];

reg [23:0] storage_7[0:15];
reg [23:0] memdat_7;
always @(posedge sys_clk) begin
	if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
		storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
	memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];

endmodule
