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#!/usr/bin/python3
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"""© IBM Corp. 2020
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Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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repository except in compliance with the License as modified.
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You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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Modified Terms:
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1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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the work of authorship in physical form.
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2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
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from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
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under the terms and conditions of the EULA.
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Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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governing permissions and limitations under the License.
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Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
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ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
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ISA) here: https://openpowerfoundation.org.
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Brief explanation of modifications:
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Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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it unambiguously permits a user to make and use the physical chip.
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Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
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and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
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licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received
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under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
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licenses for the specific Power ISA Core are granted under this modified Apache license.
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"""
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from migen import *
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# if want AutoCSR
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#from litex.soc.interconnect.csr import *
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#class WB_ExtMem(Module, AutoCSR):
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class ISSIRam(Module):
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def __init__(self, module, clk, rst, wishbone, pins):
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self.bus = wishbone
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self.data_width = 32
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self.size = 524288
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module.specials += Instance("issiram",
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i_clk = clk,
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i_rst = rst,
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i_wbs_stb_i = wishbone.stb,
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i_wbs_cyc_i = wishbone.cyc,
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i_wbs_adr_i = wishbone.adr,
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i_wbs_we_i = wishbone.we,
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i_wbs_sel_i = wishbone.sel,
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i_wbs_dat_i = wishbone.dat_w,
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o_wbs_ack_o = wishbone.ack,
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o_wbs_dat_o = wishbone.dat_r,
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o_mem_ce_n = pins['ce'],
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o_mem_oe_n = pins['oe'],
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o_mem_we_n = pins['we'],
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o_mem_adr = pins['adr'],
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io_mem_dat = pins['dat']
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)
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#def _to_signal(self, obj):
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# return obj.raw_bits() if isinstance(obj, Record) else obj
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if __name__ == '__main__':
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from litex.build.generic_platform import *
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from litex.soc.interconnect import wishbone
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# need to use local; no oen here
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# from litex_boards.platforms import cmod_a7
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import sys
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binPath = os.path.dirname(os.path.realpath(__file__))
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sys.path.append(os.path.join(binPath, '../../build/litex'))
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from platforms import cmod7
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platform = cmod7.Platform()
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platform.add_source("issiram.v")
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clk = ClockSignal()
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rst = ResetSignal()
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bus = wishbone.Interface()
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issiram = platform.request('issiram')
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pins = {
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'ce': issiram.cen,
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'oe': issiram.oen,
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'we': issiram.wen,
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'adr': issiram.addr,
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'dat': issiram.data
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}
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module = Module()
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extmem = ISSIRam(module, clk, rst, bus, pins)
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platform.build(module)
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