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26 lines
513 B
Verilog
26 lines
513 B
Verilog
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module smp # (
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) (
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);
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// larx/stcx
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// assume: if larx hits L1, core invalidates line automatically -> do not need to send back-invalidate
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// reservation granule is 32B (or use lcd of all cores)
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// one reservation per thread
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// reservation is set before core receives reload data
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wire stcx_store [0:3];
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wire resv_ra_hit [0:3];
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wire resv_set [0:3];
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wire resv_rst [0:3];
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wire [27:0] resv_q [0:3]; // v, @31:5
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wire [27:0] resv_d [0:3];
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// sync ops
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// cache ops
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// tlb ops
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endmodule |