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72 lines
1.8 KiB
Verilog
72 lines
1.8 KiB
Verilog
// a2wb defines
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`define CORE_TYPE_NONE 4'h0
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`define CORE_TYPE_A2L2 4'h1
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`define CORE_TYPE_WB1 4'h2
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`define CORE_TYPE_WB2 4'h3
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`define BUS_TYPE_NONE 4'h0
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`define BUS_TYPE_WB1 4'h1
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`define BUS_TYPE_WB2 4'h2
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// starting bits for core in/out subvectors
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// out's are core out/bridge in
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`define WB1_WB_OUT_START 383
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`define WB1_EXT_OUT_START `WB1_WB_OUT_START-128
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`define WB2_WB_OUT_START 383
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`define WB2_I_WB_OUT_START 383
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`define WB2_D_WB_OUT_START `WB2_I_WB_OUT_START-128
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`define WB2_EXT_OUT_START `WB2_D_WB_OUT_START-128
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// in's are bridge out/core in
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`define WB1_WB_IN_START 383
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`define WB1_EXT_IN_START `WB1_WB_IN_START-128
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`define WB2_WB_IN_START 383
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`define WB2_I_WB_IN_START 383
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`define WB2_D_WB_IN_START `WB2_I_WB_IN_START-128
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`define WB2_EXT_IN_START `WB2_D_WB_IN_START-128
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// starting bits for bus in/out subvectors
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`define BUS_WB1_OUT_START 127
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`define BUS_WB1_IN_START 127
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`define BUS_WB2_OUT_START 255
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`define BUS_WB2_I_OUT_START 255
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`define BUS_WB2_D_OUT_START 127
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`define BUS_WB2_IN_START 127
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`define BUS_WB2_I_IN_START 127
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`define BUS_WB2_D_IN_START 63
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// internal
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`define CMD_SIZE 77
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`define CMD_VALID `CMD_SIZE-1
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`define CMD_CORE_ID `CMD_SIZE-2:`CMD_SIZE-3
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`define CMD_RSVD_0 `CMD_SIZE-4
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`define CMD_RSVD_1 `CMD_SIZE-5
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`define CMD_TAKEN `CMD_SIZE-6
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`define CMD_RSVD_2 `CMD_SIZE-7
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`define CMD_RSVD_3 `CMD_SIZE-8
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`define CMD_WE `CMD_SIZE-9
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`define CMD_SEL `CMD_SIZE-10:`CMD_SIZE-13
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`define CMD_ADR `CMD_SIZE-14:`CMD_SIZE-45
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`define CMD_DATW `CMD_SIZE-46:`CMD_SIZE-77
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`define RSP_SIZE 64
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`define RSP_VALID `RSP_SIZE-1
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`define RSP_CORE_ID `RSP_SIZE-2:`RSP_SIZE-3
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`define RSP_RSVD_0 `RSP_SIZE-4:`RSP_SIZE-8
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`define RSP_DATA `RSP_SIZE-9:`RSP_SIZE-40
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// main bus
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`define WB1_BUS_OUT_START 127
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`define WB1_BUS_IN_START 127
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