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15 lines
301 B
Verilog
15 lines
301 B
Verilog
// a2l2 default: allow 1 ld, 1 st credit and use 2 dedicated queues
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`include "defs.v"
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reg [77:0] cmd_queue_q[0:3][0:1];
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wire [77:0] cmd_queue_d[0:3][0:1];
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wire [77:0] cmd_queue_in[0:3][0:1];
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wire [71:0] cmd_queue_out[0:3];
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module cmd_wb #(
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parameter CORE_TYPE = CORE_TYPE_A2L2
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) (
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);
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endmodule |