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184 lines
6.5 KiB
Verilog
184 lines
6.5 KiB
Verilog
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module bus_wb2 # (
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) (
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input clk,
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input rst,
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output rdy_i,
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output rdy_d,
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input [`CMD_SIZE-1:0] cmd_i,
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input [`CMD_SIZE-1:0] cmd_d,
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output [`RSP_SIZE-1:0] rsp_i,
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output [`RSP_SIZE-1:0] rsp_d,
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output i_wb_stb,
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output i_wb_cyc,
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output [31:0] i_wb_adr,
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input i_wb_ack,
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input [31:0] i_wb_datr,
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output d_wb_stb,
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output d_wb_cyc,
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output d_wb_we,
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output [3:0] d_wb_sel,
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output [31:0] d_wb_adr,
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output [31:0] d_wb_datw,
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input d_wb_ack,
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input [31:0] d_wb_datr
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);
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reg [`CMD_SIZE-1:0] cmd_i_q;
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wire [`CMD_SIZE-1:0] cmd_i_d;
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reg [`CMD_SIZE-1:0] cmd_d_q;
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wire [`CMD_SIZE-1:0] cmd_d_d;
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reg [1:0] cmdseq_i_q;
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wire [1:0] cmdseq_i_d;
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reg [1:0] cmdseq_d_q;
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wire [1:0] cmdseq_d_d;
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wire idle_i;
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wire cmd_val_i;
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wire ld_cmd_i;
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wire rsp_val_i;
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wire idle_d;
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wire cmd_val_d;
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wire ld_cmd_d;
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wire rsp_val_d;
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// FF
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always @(posedge clk) begin
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if (rst) begin
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cmdseq_i_q = 2'b11;
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cmdseq_d_q = 2'b11;
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cmd_i_q = 'h0;
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cmd_d_q = 'h0;
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end else begin
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cmdseq_i_q = cmdseq_i_d;
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cmdseq_d_q = cmdseq_d_d;
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cmd_i_q = cmd_i_d;
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cmd_d_q = cmd_d_d;
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end
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end
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// super-simple; latch cmd -> send req -> rtn rsp
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assign cmd_val_i = cmd_i[`CMD_SIZE-1];
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//tbl cmdseq_i
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//n cmdseq_i_q cmdseq_i_d
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//n | cmd_val_i | ld_cmd_i
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//n | | i_wb_ack | |
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//n | | | | |
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//n | | | | |
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//n | | | | | idle_i
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//n | | | | | |
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//n | | | | | |
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//b 10 | | 10 | |
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//t ii i i oo o o
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//*------------------------------------------------
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//* Idle ******************************************
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//s 11 - - -- - 1
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//s 11 0 - 11 0 - * ...zzz...
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//s 11 1 - 01 1 -
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//* Request Pending *******************************
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//s 01 - 0 01 0 0
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//s 01 - 1 11 0 0
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//*------------------------------------------------
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//tbl cmdseq_i
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assign cmd_i_d = ld_cmd_i ? cmd_i : {cmd_i_q[`CMD_VALID] & ~i_wb_ack, cmd_i_q[`CMD_VALID-1:0]};
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assign i_wb_stb = cmd_i_q[`CMD_VALID];
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assign i_wb_cyc = cmd_i_q[`CMD_VALID];
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assign i_wb_adr = cmd_i_q[`CMD_ADR];
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assign rdy_i = idle_i;
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assign rsp_i[`RSP_VALID] = i_wb_ack;
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assign rsp_i[`RSP_CORE_ID] = cmd_i_q[`CMD_CORE_ID];
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assign rsp_i[`RSP_DATA] = i_wb_datr;
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//wtf eventually move this to config unit; it will respond and block cmd val to bus unit
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// use adr compare to return coreid for d-read
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wire adr_coreid;
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assign adr_coreid = ~cmd_d_q[`CMD_WE] & (cmd_d_q[`CMD_ADR] == 32'b0); //wtf why is the adr cmp part segving verilator?????
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assign cmd_val_d = cmd_d[`CMD_VALID];
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//tbl cmdseq_d
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//n cmdseq_d_q cmdseq_d_d
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//n | cmd_val_d | ld_cmd_d
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//n | | rsp_d_complete | |
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//n | | | | |
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//n | | | | |
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//n | | | | | idle_d
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//n | | | | | |
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//n | | | | | |
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//b 10 | | 10 | |
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//t ii i i oo o o
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//*------------------------------------------------
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//* Idle ******************************************
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//s 11 - - -- - 1
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//s 11 0 - 11 0 - * ...zzz...
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//s 11 1 - 01 1 -
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//* Request Pending *******************************
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//s 01 - 0 01 0 0
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//s 01 - 1 11 0 0
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//*------------------------------------------------
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//tbl cmdseq_d
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//assign cmd_d_d = ld_cmd_d ? cmd_d : {cmd_d_q[`CMD_VALID] & ~d_wb_ack, cmd_d_q[`CMD_VALID-1:0]};
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assign cmd_d_d = ld_cmd_d ? cmd_d : {cmd_d_q[`CMD_VALID] & ~rsp_d_complete, cmd_d_q[`CMD_VALID-1:0]};
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//assign d_wb_cyc = cmd_d_q[`CMD_VALID];
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//assign d_wb_stb = cmd_d_q[`CMD_VALID];
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assign d_wb_cyc = cmd_d_q[`CMD_VALID] & ~adr_coreid;
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assign d_wb_stb = cmd_d_q[`CMD_VALID] & ~adr_coreid;
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assign d_wb_we = cmd_d_q[`CMD_WE];
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assign d_wb_sel = cmd_d_q[`CMD_SEL];
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assign d_wb_adr = cmd_d_q[`CMD_ADR];
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assign d_wb_datw = cmd_d_q[`CMD_DATW];
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assign rdy_d = idle_d;
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//assign rsp_d[`RSP_VALID] = d_wb_ack;
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wire rsp_d_complete;
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assign rsp_d_complete = d_wb_ack | (cmd_d_q[`CMD_VALID] & adr_coreid);
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assign rsp_d[`RSP_VALID] = rsp_d_complete;
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assign rsp_d[`RSP_CORE_ID] = cmd_d_q[`CMD_CORE_ID];
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//assign rsp_d[`RSP_DATA] = d_wb_datr;
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assign rsp_d[`RSP_DATA] = adr_coreid ? {6'b0, cmd_d_q[`CMD_CORE_ID], 24'b0} : d_wb_datr; // byte 3 = core_id
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// Generated...
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//vtable cmdseq_i
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assign cmdseq_i_d[1] =
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(cmdseq_i_q[1] & cmdseq_i_q[0] & ~cmd_val_i) +
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(~cmdseq_i_q[1] & cmdseq_i_q[0] & i_wb_ack);
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assign cmdseq_i_d[0] =
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(cmdseq_i_q[1] & cmdseq_i_q[0] & ~cmd_val_i) +
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(cmdseq_i_q[1] & cmdseq_i_q[0] & cmd_val_i) +
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(~cmdseq_i_q[1] & cmdseq_i_q[0] & ~i_wb_ack) +
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(~cmdseq_i_q[1] & cmdseq_i_q[0] & i_wb_ack);
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assign ld_cmd_i =
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(cmdseq_i_q[1] & cmdseq_i_q[0] & cmd_val_i);
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assign idle_i =
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(cmdseq_i_q[1] & cmdseq_i_q[0]);
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//vtable cmdseq_i
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//vtable cmdseq_d
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assign cmdseq_d_d[1] =
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(cmdseq_d_q[1] & cmdseq_d_q[0] & ~cmd_val_d) +
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(~cmdseq_d_q[1] & cmdseq_d_q[0] & rsp_d_complete);
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assign cmdseq_d_d[0] =
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(cmdseq_d_q[1] & cmdseq_d_q[0] & ~cmd_val_d) +
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(cmdseq_d_q[1] & cmdseq_d_q[0] & cmd_val_d) +
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(~cmdseq_d_q[1] & cmdseq_d_q[0] & ~rsp_d_complete) +
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(~cmdseq_d_q[1] & cmdseq_d_q[0] & rsp_d_complete);
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assign ld_cmd_d =
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(cmdseq_d_q[1] & cmdseq_d_q[0] & cmd_val_d);
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assign idle_d =
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(cmdseq_d_q[1] & cmdseq_d_q[0]);
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//vtable cmdseq_d
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endmodule
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