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278 lines
10 KiB
Python
278 lines
10 KiB
Python
#!/usr/bin/env python3
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# A2P Test
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# python3 a2p_cmod7.py --csr-csv csr.csv --no-compile-software --build
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#
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import os
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import argparse
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from migen import *
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# local platform
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from platforms import cmod7
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# local core
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import sys
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binPath = os.path.dirname(os.path.realpath(__file__))
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sys.path.append(os.path.join(binPath, 'a2p'))
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from a2p import A2P
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from litex.soc.cores import cpu
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cpu.CPUS['a2p'] = A2P # add to litex dict
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# local modules
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sys.path.append(os.path.join(binPath, 'modules'))
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import colorer
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.interconnect import wishbone
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from litex.soc.cores import uart
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from litex.soc.cores.uart import UART
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from litex.soc.cores.uart import UARTPHY
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeAnalyzer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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#wtf no idea how to modify the reset signal later (add btn0)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk12"), 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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from litex.soc.interconnect import wishbone
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def _to_signal(obj):
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return obj.raw_bits() if isinstance(obj, Record) else obj
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6),
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with_analyzer=False,
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uart_baudrate=115200,
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**kwargs):
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coreUART = True
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platform = cmod7.Platform()
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SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
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with_uart=coreUART, integrated_sram_size=0, integrated_rom_size=0,
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ident="A2P", ident_version=True, uart_baudrate=uart_baudrate,
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cpu_type='a2p')
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#wtf no irq yet
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self.add_constant("UART_POLLING")
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#wtf this appears to be how to set up fixed csr order but not sure it works this way.
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#SoCCore.csr_map
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#self.csr_map = {**SoCCore.csr_map, **{
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#self.csr_map = {
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# "ctrl": 0,
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# "dna" : 1,
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# "uart": 2,
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# "i2c": 3,
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# "leds": 4
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#}}
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#interrupt_map = {**soc_cls.interrupt_map, **{
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# "uart": 0,
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# "timer0": 1,
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#}}
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# rom, sram are referenced by code linker so names must match!!!
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self.mem_map = {
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"csr": 0xFFF00000,
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"sram": 0x00100000,
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"rom": 0x00000000
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}
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# UART -------------------------------------------------------------------------------------
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if not coreUART:
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self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
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self.add_wb_master(self.serial_bridge.wishbone)
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#self.add_uartbone('serial', sys_clk_freq, baudrate=115200)
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# ON-BOARD MEM ------------------------------------------------------------------------------
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rom_size = 0x10000
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with open('rom.init', 'r') as file:
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hexdata = file.read().replace('\n', '')
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outFile = open('mem_1.init', 'w') # write data immediately so available even if not building (sim)
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bytedata = []
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for i in range(0, len(hexdata), 8):
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data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE
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bytedata.append(data)
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outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n')
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romdata = bytedata
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outFile.close()
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if len(romdata)*4 > rom_size:
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self.logger.info('ROM {} {} {}.'.format(
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colorer('Read', color='red'),
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colorer(len(romdata)*4, color='red'),
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colorer('bytes for preload. Too big!', color='red')))
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quit(-100)
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else:
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self.logger.info('ROM {} {} {}.'.format(
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colorer('Read', color='bright'),
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colorer(len(romdata)*4, color='cyan'),
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colorer('bytes for preload. Wrote mem_1.init.', color='bright')))
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self.add_rom("rom", origin=self.mem_map["rom"], size=rom_size, contents=romdata)
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# Internal SRAM (64K) -----------------------------------------------------------------------
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#self.add_ram("sram", origin=self.mem_map["sram"], size=0x10000)
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# External SRAM (512K) -----------------------------------------------------------------------
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from issiram import ISSIRam
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platform.add_source("./modules/issiram.v")
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sram_bus = wishbone.Interface()
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pins = platform.request('issiram')
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mem = {
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'ce': pins.cen,
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'oe': pins.oen,
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'we': pins.wen,
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'adr': pins.addr,
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'dat': pins.data
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}
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sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, mem)
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self.submodules.sram = sram
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self.bus.add_slave('sram', sram_bus,
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SoCRegion(origin=self.mem_map['sram'], size=sram.size))
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self.logger.info("SRAM {} {} {}.".format(
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colorer('sram'),
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colorer("added", color="green"),
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self.bus.regions['sram']))
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# FPGA identification ------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.add_csr("dna")
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# FPGA temperature/voltage -------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.add_csr("xadc")
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# Leds ---------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq
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)
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self.add_csr("leds")
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# Buttons ------------------------------------------------------------------------------------
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self.submodules.buttons = GPIOIn(
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pads = platform.request_all("user_btn")
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)
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self.add_csr("buttons")
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# GPIO I2C -----------------------------------------------------------------------------------
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i2c_0 = Record([("scl", 1), ("sda", 1)])
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i2c_0.scl = platform.request('pmod', 0) # P1
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i2c_0.sda = platform.request('pmod', 1) # P2
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#wtf needs to be 'i2c' for bios for now
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self.submodules.i2c = I2CMaster(i2c_0)
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self.add_csr('i2c')
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# GPIO UARTs ---------------------------------------------------------------------------------
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#wtf someday
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# GPIO Custom Serial -------------------------------------------------------------------------
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#wtf attach to
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self.submodules.dshot_0 = GPIOOut(
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pads = platform.request("digital", 43) # P48
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)
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self.add_csr("dshot_0")
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#wtf need to try...
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# Analyzer -----------------------------------------------------------------------------------
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if with_analyzer:
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analyzer_signals = [
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# IBus
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self.cpu.ibus.stb,
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self.cpu.ibus.cyc,
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self.cpu.ibus.adr,
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self.cpu.ibus.we,
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self.cpu.ibus.ack,
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self.cpu.ibus.sel,
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self.cpu.ibus.dat_w,
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self.cpu.ibus.dat_r,
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# DBus
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self.cpu.dbus.stb,
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self.cpu.dbus.cyc,
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self.cpu.dbus.adr,
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self.cpu.dbus.we,
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self.cpu.dbus.ack,
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self.cpu.dbus.sel,
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self.cpu.dbus.dat_w,
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self.cpu.dbus.dat_r,
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]
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 512,
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clock_domain = "sys",
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csr_csv = "analyzer.csv")
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self.add_csr("analyzer")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="A2P/cmod7")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--with-analyzer", action="store_true", help="Include analyzer")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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print(args)
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_analyzer = args.with_analyzer,
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**soc_sdram_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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#wtf needs openocd!!!
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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