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231 lines
6.6 KiB
Verilog
231 lines
6.6 KiB
Verilog
// A2 Core Bridge
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// adapt cores and buses with generic module
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// one thread/core for now; multithread needs thread tag, deeper queues
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`include "defs.v"
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module A2WB #(
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parameter [0:15] CORE_TYPES = {`CORE_TYPE_WB2, `CORE_TYPE_NONE, `CORE_TYPE_NONE, `CORE_TYPE_NONE},
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parameter [0:3] BUS_TYPE = `BUS_TYPE_WB2
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) (
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input clk,
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input rst,
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input [0:3] core_in,
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output [0:3] core_out,
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input bus_in,
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output bus_out
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);
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integer NUMCORES = 0;
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genvar i;
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// ------------------------------------------------------------------------------------------------
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// I/O Connections
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// cores must be contiguous, starting at 0
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wire i_wb_cyc [0:3];
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wire i_wb_stb [0:3];
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wire [31:2] i_wb_adr[0:3] ;
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wire i_wb_ack [0:3];
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wire [31:0] i_wb_datr[0:3];
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wire d_wb_cyc [0:3];
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wire d_wb_stb [0:3];
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wire d_wb_we [0:3];
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wire [3:0] d_wb_sel [0:3];
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wire [31:0] d_wb_adr [0:3];
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wire [31:0] d_wb_datw [0:3];
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wire d_wb_ack [0:3];
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wire [31:0] d_wb_datr[0:3];
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wire [7:0] ext_cmd [0:3];
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wire [7:0] ext_rsp [0:3];
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generate
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for (i = 0; i < 4; i++) begin
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case (CORE_TYPES[i*4:i*4+3])
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`CORE_TYPE_NONE: begin
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end
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`CORE_TYPE_A2L2: begin
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assign NUMCORES = NUMCORES + 1;
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// a2l2
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end
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`CORE_TYPE_WB1: begin
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assign NUMCORES = NUMCORES + 1;
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wire [78:0] core_0_in;
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wire [32:0] core_out[i];
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assign d_wb_cyc[i] = core_in[i][78];
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assign d_wb_stb[i] = core_in[i][77];
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assign d_wb_we[i] = core_in[i][76];
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assign d_wb_sel[i] = core_in[i][75:72];
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assign d_wb_adr[i] = core_in[i][71:40];
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assign d_wb_datw[i] = core_in[i][39:8];
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assign ext_cmd[i] = core_in[i][7:0];
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assign core_out[i][32] = d_wb_ack[i];
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assign core_out[i][31:0] = d_wb_datr[i];
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end
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`CORE_TYPE_WB2: begin
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assign NUMCORES = NUMCORES + 1;
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wire [110:0] core_in[i];
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wire [65:0] core_out[i];
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assign i_wb_cyc[i] = core_in[i][110];
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assign i_wb_stb[i] = core_in[i][109];
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assign i_wb_adr[i] = core_in[i][108:79];
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assign d_wb_cyc[i] = core_in[i][78];
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assign d_wb_stb[i] = core_in[i][77];
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assign d_wb_we[i] = core_in[i][76];
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assign d_wb_sel[i] = core_in[i][75:72];
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assign d_wb_adr[i] = core_in[i][71:40];
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assign d_wb_datw[i] = core_in[i][39:8];
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assign ext_cmd[i] = core_in[i][7:0];
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assign core_out[i][65] = i_wb_ack[i];
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assign core_out[i][64:33] = i_wb_datr[i];
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assign core_out[i][32] = d_wb_ack[i];
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assign core_out[i][31:0] = d_wb_datr[i];
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end
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endcase
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Command Interfaces
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//
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generate
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for (i = 0; i < 4; i++) begin
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case (CORE_TYPES[i*4:i*4+3])
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`CORE_TYPE_NONE: begin
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end
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`CORE_TYPE_A2L2: begin
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// convert a2l2 to internal format
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end
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`CORE_TYPE_WB1: begin
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cmd_wb #(.CORE_TYPE(CORE_TYPES[i*4:i*4+3]), .BUS_TYPE(BUS_TYPE)) core_in (
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.clk(clk),
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.rst(rst),
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.i_wb_cyc('b0),
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.i_wb_stb('b0),
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.i_wb_adr('h0),
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.d_wb_cyc(d_wb_cyc[i]),
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.d_wb_stb(d_wb_stb[i]),
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.d_wb_we(d_wb_we[i]),
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.d_wb_sel(d_wb_sel[i]),
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.d_wb_adr(d_wb_adr[i]),
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.d_wb_datw(d_wb_datw[i]),
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.ext_cmd(ext_cmd[i]),
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.cmd_taken('b0),
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.cmd_out_0(),
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.cmd_out_1()
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);
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end
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`CORE_TYPE_WB2: begin
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cmd_wb #(.CORE_TYPE(CORE_TYPES[i*4:i*4+3]), .BUS_TYPE(BUS_TYPE)) core_in (
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.clk(clk),
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.rst(rst),
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.i_wb_cyc(i_wb_cyc[i]),
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.i_wb_stb(i_wb_stb[i]),
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.i_wb_adr(i_wb_adr[i]),
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.d_wb_cyc(d_wb_cyc[i]),
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.d_wb_stb(d_wb_stb[i]),
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.d_wb_we(d_wb_we[i]),
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.d_wb_sel(d_wb_sel[i]),
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.d_wb_adr(d_wb_adr[i]),
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.d_wb_datw(d_wb_datw[i]),
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.ext_cmd(ext_cmd[i]),
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.cmd_taken('b0),
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.cmd_out_0(),
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.cmd_out_1()
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);
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end
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endcase
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Arbitration
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//
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// LRU, etc. select from pending cmds; also needs smp to stall some/all cmds
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// do addr cmp here, if necessary? or could do in smp
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arb #() arb (
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);
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// ------------------------------------------------------------------------------------------------
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// SMP
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// special ops: track resv, stall pending cmds, gen rsp
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smp #() smp (
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);
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// ------------------------------------------------------------------------------------------------
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// Bus Out
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// commands to main bus
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generate
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case(BUS_TYPE)
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`BUS_TYPE_WB1: begin
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end
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`BUS_TYPE_WB2: begin
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wire [101:0] bus_out;
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wire bus_i_wb_stb;
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assign bus_out[101] = bus_i_wb_stb;
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wire [31:2] bus_i_wb_adr;
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assign bus_out[100:71] = bus_i_wb_adr;
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wire bus_d_wb_cyc;
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assign bus_out[70] = bus_d_wb_cyc;
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wire bus_d_wb_stb;
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assign bus_out[69] = bus_d_wb_stb;
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wire bus_d_wb_we;
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assign bus_out[68] = bus_d_wb_we;
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wire [3:0] bus_d_wb_sel;
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assign bus_out[67:64] = bus_d_wb_sel;
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wire [31:0] bus_d_wb_adr;
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assign bus_out[63:32] = bus_d_wb_adr;
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wire [31:0] bus_d_wb_datw;
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assign bus_out[31:0] = bus_d_wb_datw;
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end
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endcase
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Bus In
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// responses from main bus
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generate
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case(BUS_TYPE)
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`BUS_TYPE_WB1: begin
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end
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`BUS_TYPE_WB2: begin
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wire [65:0] bus_in;
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wire bus_i_wb_ack = bus_in[65];
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wire [31:0] bus_i_wb_datr = bus_in[64:33];
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wire bus_d_wb_ack = bus_in[32];
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wire [31:0] bus_d_wb_datr = bus_in[31:0];
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end
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endcase
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Response Queues
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// responses for cores
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Misc/Errors/Debug
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// stuff
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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endmodule |