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1959 lines
87 KiB
Verilog
1959 lines
87 KiB
Verilog
// -----------------------------------------------------------------------------
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// Auto-Generated by: __ _ __ _ __
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// / / (_) /____ | |/_/
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// / /__/ / __/ -_)> <
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// /____/_/\__/\__/_/|_|
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// Build your hardware, easily!
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// https://github.com/enjoy-digital/litex
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//
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// Filename : cmod7.v
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// Device : xc7a35t-CPG236-1
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// LiteX sha1 : 33ae301d
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// Date : 2022-08-23 17:08:47
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Module
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//------------------------------------------------------------------------------
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module soc (
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output reg serial_tx,
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input wire serial_rx,
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(* dont_touch = "true" *) input wire clk12,
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output wire user_led0,
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output wire user_led1,
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input wire user_btn0,
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input wire user_btn1
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);
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//------------------------------------------------------------------------------
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// Signals
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//------------------------------------------------------------------------------
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reg main_basesoc_soc_rst = 1'd0;
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wire main_basesoc_cpu_rst;
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reg [1:0] main_basesoc_reset_storage = 2'd0;
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reg main_basesoc_reset_re = 1'd0;
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reg [31:0] main_basesoc_scratch_storage = 32'd305419896;
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reg main_basesoc_scratch_re = 1'd0;
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wire [31:0] main_basesoc_bus_errors_status;
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wire main_basesoc_bus_errors_we;
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reg main_basesoc_bus_errors_re = 1'd0;
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wire main_basesoc_bus_error;
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reg [31:0] main_basesoc_bus_errors = 32'd0;
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wire main_basesoc_reset;
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reg [31:0] main_basesoc_interrupt = 32'd0;
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reg main_basesoc_interruptS = 1'd0;
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wire [29:0] main_basesoc_ibus_adr;
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wire [31:0] main_basesoc_ibus_dat_w;
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wire [31:0] main_basesoc_ibus_dat_r;
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wire [3:0] main_basesoc_ibus_sel;
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wire main_basesoc_ibus_cyc;
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wire main_basesoc_ibus_stb;
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wire main_basesoc_ibus_ack;
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wire main_basesoc_ibus_we;
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wire [2:0] main_basesoc_ibus_cti;
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wire [1:0] main_basesoc_ibus_bte;
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wire main_basesoc_ibus_err;
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wire [29:0] main_basesoc_dbus_adr;
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wire [31:0] main_basesoc_dbus_dat_w;
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wire [31:0] main_basesoc_dbus_dat_r;
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wire [3:0] main_basesoc_dbus_sel;
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wire main_basesoc_dbus_cyc;
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wire main_basesoc_dbus_stb;
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wire main_basesoc_dbus_ack;
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wire main_basesoc_dbus_we;
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wire [2:0] main_basesoc_dbus_cti;
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wire [1:0] main_basesoc_dbus_bte;
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wire main_basesoc_dbus_err;
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reg [31:0] main_basesoc_a2p = 32'd0;
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wire main_basesoc_tx_sink_valid;
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reg main_basesoc_tx_sink_ready = 1'd0;
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wire main_basesoc_tx_sink_first;
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wire main_basesoc_tx_sink_last;
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wire [7:0] main_basesoc_tx_sink_payload_data;
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reg [7:0] main_basesoc_tx_data = 8'd0;
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reg [3:0] main_basesoc_tx_count = 4'd0;
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reg main_basesoc_tx_enable = 1'd0;
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reg main_basesoc_tx_tick = 1'd0;
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reg [31:0] main_basesoc_tx_phase = 32'd0;
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reg main_basesoc_rx_source_valid = 1'd0;
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wire main_basesoc_rx_source_ready;
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reg main_basesoc_rx_source_first = 1'd0;
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reg main_basesoc_rx_source_last = 1'd0;
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reg [7:0] main_basesoc_rx_source_payload_data = 8'd0;
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reg [7:0] main_basesoc_rx_data = 8'd0;
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reg [3:0] main_basesoc_rx_count = 4'd0;
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reg main_basesoc_rx_enable = 1'd0;
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reg main_basesoc_rx_tick = 1'd0;
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reg [31:0] main_basesoc_rx_phase = 32'd0;
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wire main_basesoc_rx_rx;
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reg main_basesoc_rx_rx_d = 1'd0;
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reg main_basesoc_uart_rxtx_re = 1'd0;
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wire [7:0] main_basesoc_uart_rxtx_r;
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reg main_basesoc_uart_rxtx_we = 1'd0;
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wire [7:0] main_basesoc_uart_rxtx_w;
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wire main_basesoc_uart_txfull_status;
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wire main_basesoc_uart_txfull_we;
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reg main_basesoc_uart_txfull_re = 1'd0;
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wire main_basesoc_uart_rxempty_status;
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wire main_basesoc_uart_rxempty_we;
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reg main_basesoc_uart_rxempty_re = 1'd0;
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wire main_basesoc_uart_irq;
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wire main_basesoc_uart_tx_status;
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reg main_basesoc_uart_tx_pending = 1'd0;
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wire main_basesoc_uart_tx_trigger;
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reg main_basesoc_uart_tx_clear = 1'd0;
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reg main_basesoc_uart_tx_trigger_d = 1'd0;
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wire main_basesoc_uart_rx_status;
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reg main_basesoc_uart_rx_pending = 1'd0;
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wire main_basesoc_uart_rx_trigger;
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reg main_basesoc_uart_rx_clear = 1'd0;
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reg main_basesoc_uart_rx_trigger_d = 1'd0;
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wire main_basesoc_uart_tx0;
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wire main_basesoc_uart_rx0;
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reg [1:0] main_basesoc_uart_status_status = 2'd0;
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wire main_basesoc_uart_status_we;
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reg main_basesoc_uart_status_re = 1'd0;
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wire main_basesoc_uart_tx1;
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wire main_basesoc_uart_rx1;
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reg [1:0] main_basesoc_uart_pending_status = 2'd0;
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wire main_basesoc_uart_pending_we;
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reg main_basesoc_uart_pending_re = 1'd0;
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reg [1:0] main_basesoc_uart_pending_r = 2'd0;
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wire main_basesoc_uart_tx2;
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wire main_basesoc_uart_rx2;
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reg [1:0] main_basesoc_uart_enable_storage = 2'd0;
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reg main_basesoc_uart_enable_re = 1'd0;
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wire main_basesoc_uart_txempty_status;
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wire main_basesoc_uart_txempty_we;
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reg main_basesoc_uart_txempty_re = 1'd0;
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wire main_basesoc_uart_rxfull_status;
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wire main_basesoc_uart_rxfull_we;
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reg main_basesoc_uart_rxfull_re = 1'd0;
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wire main_basesoc_uart_uart_sink_valid;
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wire main_basesoc_uart_uart_sink_ready;
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wire main_basesoc_uart_uart_sink_first;
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wire main_basesoc_uart_uart_sink_last;
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wire [7:0] main_basesoc_uart_uart_sink_payload_data;
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wire main_basesoc_uart_uart_source_valid;
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wire main_basesoc_uart_uart_source_ready;
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wire main_basesoc_uart_uart_source_first;
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wire main_basesoc_uart_uart_source_last;
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wire [7:0] main_basesoc_uart_uart_source_payload_data;
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wire main_basesoc_uart_tx_fifo_sink_valid;
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wire main_basesoc_uart_tx_fifo_sink_ready;
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reg main_basesoc_uart_tx_fifo_sink_first = 1'd0;
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reg main_basesoc_uart_tx_fifo_sink_last = 1'd0;
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wire [7:0] main_basesoc_uart_tx_fifo_sink_payload_data;
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wire main_basesoc_uart_tx_fifo_source_valid;
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wire main_basesoc_uart_tx_fifo_source_ready;
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wire main_basesoc_uart_tx_fifo_source_first;
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wire main_basesoc_uart_tx_fifo_source_last;
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wire [7:0] main_basesoc_uart_tx_fifo_source_payload_data;
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wire main_basesoc_uart_tx_fifo_re;
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reg main_basesoc_uart_tx_fifo_readable = 1'd0;
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wire main_basesoc_uart_tx_fifo_syncfifo_we;
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wire main_basesoc_uart_tx_fifo_syncfifo_writable;
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wire main_basesoc_uart_tx_fifo_syncfifo_re;
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wire main_basesoc_uart_tx_fifo_syncfifo_readable;
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wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_din;
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wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_dout;
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reg [4:0] main_basesoc_uart_tx_fifo_level0 = 5'd0;
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reg main_basesoc_uart_tx_fifo_replace = 1'd0;
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reg [3:0] main_basesoc_uart_tx_fifo_produce = 4'd0;
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reg [3:0] main_basesoc_uart_tx_fifo_consume = 4'd0;
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reg [3:0] main_basesoc_uart_tx_fifo_wrport_adr = 4'd0;
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wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_r;
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wire main_basesoc_uart_tx_fifo_wrport_we;
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wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_w;
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wire main_basesoc_uart_tx_fifo_do_read;
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wire [3:0] main_basesoc_uart_tx_fifo_rdport_adr;
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wire [9:0] main_basesoc_uart_tx_fifo_rdport_dat_r;
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wire main_basesoc_uart_tx_fifo_rdport_re;
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wire [4:0] main_basesoc_uart_tx_fifo_level1;
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wire [7:0] main_basesoc_uart_tx_fifo_fifo_in_payload_data;
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wire main_basesoc_uart_tx_fifo_fifo_in_first;
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wire main_basesoc_uart_tx_fifo_fifo_in_last;
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wire [7:0] main_basesoc_uart_tx_fifo_fifo_out_payload_data;
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wire main_basesoc_uart_tx_fifo_fifo_out_first;
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wire main_basesoc_uart_tx_fifo_fifo_out_last;
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wire main_basesoc_uart_rx_fifo_sink_valid;
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wire main_basesoc_uart_rx_fifo_sink_ready;
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wire main_basesoc_uart_rx_fifo_sink_first;
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wire main_basesoc_uart_rx_fifo_sink_last;
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wire [7:0] main_basesoc_uart_rx_fifo_sink_payload_data;
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wire main_basesoc_uart_rx_fifo_source_valid;
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wire main_basesoc_uart_rx_fifo_source_ready;
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wire main_basesoc_uart_rx_fifo_source_first;
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wire main_basesoc_uart_rx_fifo_source_last;
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wire [7:0] main_basesoc_uart_rx_fifo_source_payload_data;
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wire main_basesoc_uart_rx_fifo_re;
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reg main_basesoc_uart_rx_fifo_readable = 1'd0;
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wire main_basesoc_uart_rx_fifo_syncfifo_we;
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wire main_basesoc_uart_rx_fifo_syncfifo_writable;
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wire main_basesoc_uart_rx_fifo_syncfifo_re;
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wire main_basesoc_uart_rx_fifo_syncfifo_readable;
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wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_din;
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wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_dout;
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reg [4:0] main_basesoc_uart_rx_fifo_level0 = 5'd0;
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reg main_basesoc_uart_rx_fifo_replace = 1'd0;
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reg [3:0] main_basesoc_uart_rx_fifo_produce = 4'd0;
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reg [3:0] main_basesoc_uart_rx_fifo_consume = 4'd0;
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reg [3:0] main_basesoc_uart_rx_fifo_wrport_adr = 4'd0;
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wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_r;
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wire main_basesoc_uart_rx_fifo_wrport_we;
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wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_w;
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wire main_basesoc_uart_rx_fifo_do_read;
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wire [3:0] main_basesoc_uart_rx_fifo_rdport_adr;
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wire [9:0] main_basesoc_uart_rx_fifo_rdport_dat_r;
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wire main_basesoc_uart_rx_fifo_rdport_re;
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wire [4:0] main_basesoc_uart_rx_fifo_level1;
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wire [7:0] main_basesoc_uart_rx_fifo_fifo_in_payload_data;
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wire main_basesoc_uart_rx_fifo_fifo_in_first;
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wire main_basesoc_uart_rx_fifo_fifo_in_last;
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wire [7:0] main_basesoc_uart_rx_fifo_fifo_out_payload_data;
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wire main_basesoc_uart_rx_fifo_fifo_out_first;
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wire main_basesoc_uart_rx_fifo_fifo_out_last;
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reg [31:0] main_basesoc_timer_load_storage = 32'd0;
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reg main_basesoc_timer_load_re = 1'd0;
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reg [31:0] main_basesoc_timer_reload_storage = 32'd0;
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reg main_basesoc_timer_reload_re = 1'd0;
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reg main_basesoc_timer_en_storage = 1'd0;
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reg main_basesoc_timer_en_re = 1'd0;
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reg main_basesoc_timer_update_value_storage = 1'd0;
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reg main_basesoc_timer_update_value_re = 1'd0;
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reg [31:0] main_basesoc_timer_value_status = 32'd0;
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wire main_basesoc_timer_value_we;
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reg main_basesoc_timer_value_re = 1'd0;
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wire main_basesoc_timer_irq;
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wire main_basesoc_timer_zero_status;
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reg main_basesoc_timer_zero_pending = 1'd0;
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wire main_basesoc_timer_zero_trigger;
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reg main_basesoc_timer_zero_clear = 1'd0;
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reg main_basesoc_timer_zero_trigger_d = 1'd0;
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wire main_basesoc_timer_zero0;
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wire main_basesoc_timer_status_status;
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wire main_basesoc_timer_status_we;
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reg main_basesoc_timer_status_re = 1'd0;
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wire main_basesoc_timer_zero1;
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wire main_basesoc_timer_pending_status;
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wire main_basesoc_timer_pending_we;
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reg main_basesoc_timer_pending_re = 1'd0;
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reg main_basesoc_timer_pending_r = 1'd0;
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wire main_basesoc_timer_zero2;
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reg main_basesoc_timer_enable_storage = 1'd0;
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reg main_basesoc_timer_enable_re = 1'd0;
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reg [31:0] main_basesoc_timer_value = 32'd0;
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reg main_crg_rst = 1'd0;
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(* dont_touch = "true" *) wire sys_clk;
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wire sys_rst;
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wire sys2x_clk;
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wire idelay_clk;
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wire idelay_rst;
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wire main_crg_reset;
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reg main_crg_power_down = 1'd0;
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wire main_crg_locked;
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(* dont_touch = "true" *) wire main_crg_clkin;
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wire main_crg_clkout0;
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wire main_crg_clkout_buf0;
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wire main_crg_clkout1;
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wire main_crg_clkout_buf1;
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wire main_crg_clkout2;
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wire main_crg_clkout_buf2;
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reg [3:0] main_crg_reset_counter = 4'd15;
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reg main_crg_ic_reset = 1'd1;
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wire [29:0] main_basesoc_ram_bus_adr;
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wire [31:0] main_basesoc_ram_bus_dat_w;
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wire [31:0] main_basesoc_ram_bus_dat_r;
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wire [3:0] main_basesoc_ram_bus_sel;
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wire main_basesoc_ram_bus_cyc;
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wire main_basesoc_ram_bus_stb;
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reg main_basesoc_ram_bus_ack = 1'd0;
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wire main_basesoc_ram_bus_we;
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wire [2:0] main_basesoc_ram_bus_cti;
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wire [1:0] main_basesoc_ram_bus_bte;
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reg main_basesoc_ram_bus_err = 1'd0;
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reg main_basesoc_adr_burst = 1'd0;
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wire [13:0] main_basesoc_adr;
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wire [31:0] main_basesoc_dat_r;
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wire [29:0] main_basesoc_interface0_ram_bus_adr;
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wire [31:0] main_basesoc_interface0_ram_bus_dat_w;
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wire [31:0] main_basesoc_interface0_ram_bus_dat_r;
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wire [3:0] main_basesoc_interface0_ram_bus_sel;
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wire main_basesoc_interface0_ram_bus_cyc;
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wire main_basesoc_interface0_ram_bus_stb;
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reg main_basesoc_interface0_ram_bus_ack = 1'd0;
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wire main_basesoc_interface0_ram_bus_we;
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wire [2:0] main_basesoc_interface0_ram_bus_cti;
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wire [1:0] main_basesoc_interface0_ram_bus_bte;
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reg main_basesoc_interface0_ram_bus_err = 1'd0;
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reg main_basesoc_sram0_adr_burst = 1'd0;
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wire [13:0] main_basesoc_sram0_adr;
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wire [31:0] main_basesoc_sram0_dat_r;
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reg [3:0] main_basesoc_sram0_we = 4'd0;
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wire [31:0] main_basesoc_sram0_dat_w;
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wire [29:0] main_basesoc_interface1_ram_bus_adr;
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wire [31:0] main_basesoc_interface1_ram_bus_dat_w;
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wire [31:0] main_basesoc_interface1_ram_bus_dat_r;
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wire [3:0] main_basesoc_interface1_ram_bus_sel;
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wire main_basesoc_interface1_ram_bus_cyc;
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wire main_basesoc_interface1_ram_bus_stb;
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reg main_basesoc_interface1_ram_bus_ack = 1'd0;
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wire main_basesoc_interface1_ram_bus_we;
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wire [2:0] main_basesoc_interface1_ram_bus_cti;
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wire [1:0] main_basesoc_interface1_ram_bus_bte;
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reg main_basesoc_interface1_ram_bus_err = 1'd0;
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reg main_basesoc_sram1_adr_burst = 1'd0;
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wire [21:0] main_basesoc_sram1_adr;
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wire [31:0] main_basesoc_sram1_dat_r;
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reg [3:0] main_basesoc_sram1_we = 4'd0;
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wire [31:0] main_basesoc_sram1_dat_w;
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reg [1:0] main_leds_storage = 2'd0;
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reg main_leds_re = 1'd0;
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reg [1:0] main_leds_chaser = 2'd0;
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reg main_leds_mode = 1'd0;
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wire main_leds_wait;
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wire main_leds_done;
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reg [24:0] main_leds_count = 25'd25000000;
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reg [1:0] main_leds_leds = 2'd0;
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wire [1:0] main_buttons_status;
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wire main_buttons_we;
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reg main_buttons_re = 1'd0;
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reg [13:0] builder_basesoc_adr = 14'd0;
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reg builder_basesoc_we = 1'd0;
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reg [31:0] builder_basesoc_dat_w = 32'd0;
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wire [31:0] builder_basesoc_dat_r;
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wire [29:0] builder_basesoc_wishbone_adr;
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wire [31:0] builder_basesoc_wishbone_dat_w;
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reg [31:0] builder_basesoc_wishbone_dat_r = 32'd0;
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wire [3:0] builder_basesoc_wishbone_sel;
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wire builder_basesoc_wishbone_cyc;
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wire builder_basesoc_wishbone_stb;
|
|
reg builder_basesoc_wishbone_ack = 1'd0;
|
|
wire builder_basesoc_wishbone_we;
|
|
wire [2:0] builder_basesoc_wishbone_cti;
|
|
wire [1:0] builder_basesoc_wishbone_bte;
|
|
reg builder_basesoc_wishbone_err = 1'd0;
|
|
wire [29:0] builder_shared_adr;
|
|
wire [31:0] builder_shared_dat_w;
|
|
reg [31:0] builder_shared_dat_r = 32'd0;
|
|
wire [3:0] builder_shared_sel;
|
|
wire builder_shared_cyc;
|
|
wire builder_shared_stb;
|
|
reg builder_shared_ack = 1'd0;
|
|
wire builder_shared_we;
|
|
wire [2:0] builder_shared_cti;
|
|
wire [1:0] builder_shared_bte;
|
|
wire builder_shared_err;
|
|
wire [1:0] builder_request;
|
|
reg builder_grant = 1'd0;
|
|
reg [3:0] builder_slave_sel = 4'd0;
|
|
reg [3:0] builder_slave_sel_r = 4'd0;
|
|
reg builder_error = 1'd0;
|
|
wire builder_wait;
|
|
wire builder_done;
|
|
reg [19:0] builder_count = 20'd1000000;
|
|
wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr;
|
|
wire builder_csr_bankarray_interface0_bank_bus_we;
|
|
wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w;
|
|
reg [31:0] builder_csr_bankarray_interface0_bank_bus_dat_r = 32'd0;
|
|
reg builder_csr_bankarray_csrbank0_in_re = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank0_in_r;
|
|
reg builder_csr_bankarray_csrbank0_in_we = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank0_in_w;
|
|
wire builder_csr_bankarray_csrbank0_sel;
|
|
wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr;
|
|
wire builder_csr_bankarray_interface1_bank_bus_we;
|
|
wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w;
|
|
reg [31:0] builder_csr_bankarray_interface1_bank_bus_dat_r = 32'd0;
|
|
reg builder_csr_bankarray_csrbank1_reset0_re = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank1_reset0_r;
|
|
reg builder_csr_bankarray_csrbank1_reset0_we = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank1_reset0_w;
|
|
reg builder_csr_bankarray_csrbank1_scratch0_re = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank1_scratch0_r;
|
|
reg builder_csr_bankarray_csrbank1_scratch0_we = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank1_scratch0_w;
|
|
reg builder_csr_bankarray_csrbank1_bus_errors_re = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank1_bus_errors_r;
|
|
reg builder_csr_bankarray_csrbank1_bus_errors_we = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank1_bus_errors_w;
|
|
wire builder_csr_bankarray_csrbank1_sel;
|
|
wire [13:0] builder_csr_bankarray_sram_bus_adr;
|
|
wire builder_csr_bankarray_sram_bus_we;
|
|
wire [31:0] builder_csr_bankarray_sram_bus_dat_w;
|
|
reg [31:0] builder_csr_bankarray_sram_bus_dat_r = 32'd0;
|
|
wire [4:0] builder_csr_bankarray_adr;
|
|
wire [7:0] builder_csr_bankarray_dat_r;
|
|
wire builder_csr_bankarray_sel;
|
|
reg builder_csr_bankarray_sel_r = 1'd0;
|
|
wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr;
|
|
wire builder_csr_bankarray_interface2_bank_bus_we;
|
|
wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w;
|
|
reg [31:0] builder_csr_bankarray_interface2_bank_bus_dat_r = 32'd0;
|
|
reg builder_csr_bankarray_csrbank2_out0_re = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank2_out0_r;
|
|
reg builder_csr_bankarray_csrbank2_out0_we = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank2_out0_w;
|
|
wire builder_csr_bankarray_csrbank2_sel;
|
|
wire [13:0] builder_csr_bankarray_interface3_bank_bus_adr;
|
|
wire builder_csr_bankarray_interface3_bank_bus_we;
|
|
wire [31:0] builder_csr_bankarray_interface3_bank_bus_dat_w;
|
|
reg [31:0] builder_csr_bankarray_interface3_bank_bus_dat_r = 32'd0;
|
|
reg builder_csr_bankarray_csrbank3_load0_re = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank3_load0_r;
|
|
reg builder_csr_bankarray_csrbank3_load0_we = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank3_load0_w;
|
|
reg builder_csr_bankarray_csrbank3_reload0_re = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank3_reload0_r;
|
|
reg builder_csr_bankarray_csrbank3_reload0_we = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank3_reload0_w;
|
|
reg builder_csr_bankarray_csrbank3_en0_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_en0_r;
|
|
reg builder_csr_bankarray_csrbank3_en0_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_en0_w;
|
|
reg builder_csr_bankarray_csrbank3_update_value0_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_update_value0_r;
|
|
reg builder_csr_bankarray_csrbank3_update_value0_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_update_value0_w;
|
|
reg builder_csr_bankarray_csrbank3_value_re = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank3_value_r;
|
|
reg builder_csr_bankarray_csrbank3_value_we = 1'd0;
|
|
wire [31:0] builder_csr_bankarray_csrbank3_value_w;
|
|
reg builder_csr_bankarray_csrbank3_ev_status_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_ev_status_r;
|
|
reg builder_csr_bankarray_csrbank3_ev_status_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_ev_status_w;
|
|
reg builder_csr_bankarray_csrbank3_ev_pending_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_ev_pending_r;
|
|
reg builder_csr_bankarray_csrbank3_ev_pending_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_ev_pending_w;
|
|
reg builder_csr_bankarray_csrbank3_ev_enable0_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_ev_enable0_r;
|
|
reg builder_csr_bankarray_csrbank3_ev_enable0_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank3_ev_enable0_w;
|
|
wire builder_csr_bankarray_csrbank3_sel;
|
|
wire [13:0] builder_csr_bankarray_interface4_bank_bus_adr;
|
|
wire builder_csr_bankarray_interface4_bank_bus_we;
|
|
wire [31:0] builder_csr_bankarray_interface4_bank_bus_dat_w;
|
|
reg [31:0] builder_csr_bankarray_interface4_bank_bus_dat_r = 32'd0;
|
|
reg builder_csr_bankarray_csrbank4_txfull_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_txfull_r;
|
|
reg builder_csr_bankarray_csrbank4_txfull_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_txfull_w;
|
|
reg builder_csr_bankarray_csrbank4_rxempty_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_rxempty_r;
|
|
reg builder_csr_bankarray_csrbank4_rxempty_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_rxempty_w;
|
|
reg builder_csr_bankarray_csrbank4_ev_status_re = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank4_ev_status_r;
|
|
reg builder_csr_bankarray_csrbank4_ev_status_we = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank4_ev_status_w;
|
|
reg builder_csr_bankarray_csrbank4_ev_pending_re = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank4_ev_pending_r;
|
|
reg builder_csr_bankarray_csrbank4_ev_pending_we = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank4_ev_pending_w;
|
|
reg builder_csr_bankarray_csrbank4_ev_enable0_re = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank4_ev_enable0_r;
|
|
reg builder_csr_bankarray_csrbank4_ev_enable0_we = 1'd0;
|
|
wire [1:0] builder_csr_bankarray_csrbank4_ev_enable0_w;
|
|
reg builder_csr_bankarray_csrbank4_txempty_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_txempty_r;
|
|
reg builder_csr_bankarray_csrbank4_txempty_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_txempty_w;
|
|
reg builder_csr_bankarray_csrbank4_rxfull_re = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_rxfull_r;
|
|
reg builder_csr_bankarray_csrbank4_rxfull_we = 1'd0;
|
|
wire builder_csr_bankarray_csrbank4_rxfull_w;
|
|
wire builder_csr_bankarray_csrbank4_sel;
|
|
wire [13:0] builder_csr_interconnect_adr;
|
|
wire builder_csr_interconnect_we;
|
|
wire [31:0] builder_csr_interconnect_dat_w;
|
|
wire [31:0] builder_csr_interconnect_dat_r;
|
|
reg builder_basesoc_rs232phytx_state = 1'd0;
|
|
reg builder_basesoc_rs232phytx_next_state = 1'd0;
|
|
reg [3:0] main_basesoc_tx_count_rs232phytx_next_value0 = 4'd0;
|
|
reg main_basesoc_tx_count_rs232phytx_next_value_ce0 = 1'd0;
|
|
reg main_basesoc_serial_tx_rs232phytx_next_value1 = 1'd0;
|
|
reg main_basesoc_serial_tx_rs232phytx_next_value_ce1 = 1'd0;
|
|
reg [7:0] main_basesoc_tx_data_rs232phytx_next_value2 = 8'd0;
|
|
reg main_basesoc_tx_data_rs232phytx_next_value_ce2 = 1'd0;
|
|
reg builder_basesoc_rs232phyrx_state = 1'd0;
|
|
reg builder_basesoc_rs232phyrx_next_state = 1'd0;
|
|
reg [3:0] main_basesoc_rx_count_rs232phyrx_next_value0 = 4'd0;
|
|
reg main_basesoc_rx_count_rs232phyrx_next_value_ce0 = 1'd0;
|
|
reg [7:0] main_basesoc_rx_data_rs232phyrx_next_value1 = 8'd0;
|
|
reg main_basesoc_rx_data_rs232phyrx_next_value_ce1 = 1'd0;
|
|
wire builder_basesoc_reset0;
|
|
wire builder_basesoc_reset1;
|
|
wire builder_basesoc_reset2;
|
|
wire builder_basesoc_reset3;
|
|
wire builder_basesoc_reset4;
|
|
wire builder_basesoc_reset5;
|
|
wire builder_basesoc_reset6;
|
|
wire builder_basesoc_reset7;
|
|
wire builder_basesoc_mmcm_fb;
|
|
reg builder_basesoc_state = 1'd0;
|
|
reg builder_basesoc_next_state = 1'd0;
|
|
reg [29:0] builder_array_muxed0 = 30'd0;
|
|
reg [31:0] builder_array_muxed1 = 32'd0;
|
|
reg [3:0] builder_array_muxed2 = 4'd0;
|
|
reg builder_array_muxed3 = 1'd0;
|
|
reg builder_array_muxed4 = 1'd0;
|
|
reg builder_array_muxed5 = 1'd0;
|
|
reg [2:0] builder_array_muxed6 = 3'd0;
|
|
reg [1:0] builder_array_muxed7 = 2'd0;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0;
|
|
wire builder_xilinxasyncresetsynchronizerimpl0;
|
|
wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
|
|
wire builder_xilinxasyncresetsynchronizerimpl1;
|
|
wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
|
|
wire builder_xilinxasyncresetsynchronizerimpl1_expr;
|
|
wire builder_xilinxasyncresetsynchronizerimpl2;
|
|
wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
|
|
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] builder_xilinxmultiregimpl1_regs0 = 2'd0;
|
|
(* async_reg = "true", dont_touch = "true" *) reg [1:0] builder_xilinxmultiregimpl1_regs1 = 2'd0;
|
|
wire builder_xilinxmultiregimpl1;
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Combinatorial Logic
|
|
//------------------------------------------------------------------------------
|
|
|
|
assign main_basesoc_reset = (main_basesoc_soc_rst | main_basesoc_cpu_rst);
|
|
always @(*) begin
|
|
main_crg_rst <= 1'd0;
|
|
if (main_basesoc_soc_rst) begin
|
|
main_crg_rst <= 1'd1;
|
|
end
|
|
end
|
|
assign main_basesoc_bus_error = builder_error;
|
|
always @(*) begin
|
|
main_basesoc_interrupt <= 32'd0;
|
|
main_basesoc_interrupt[1] <= main_basesoc_timer_irq;
|
|
main_basesoc_interrupt[0] <= main_basesoc_uart_irq;
|
|
end
|
|
assign main_basesoc_bus_errors_status = main_basesoc_bus_errors;
|
|
always @(*) begin
|
|
main_basesoc_serial_tx_rs232phytx_next_value1 <= 1'd0;
|
|
main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd0;
|
|
main_basesoc_tx_sink_ready <= 1'd0;
|
|
main_basesoc_tx_data_rs232phytx_next_value2 <= 8'd0;
|
|
main_basesoc_tx_data_rs232phytx_next_value_ce2 <= 1'd0;
|
|
main_basesoc_tx_enable <= 1'd0;
|
|
builder_basesoc_rs232phytx_next_state <= 1'd0;
|
|
main_basesoc_tx_count_rs232phytx_next_value0 <= 4'd0;
|
|
main_basesoc_tx_count_rs232phytx_next_value_ce0 <= 1'd0;
|
|
builder_basesoc_rs232phytx_next_state <= builder_basesoc_rs232phytx_state;
|
|
case (builder_basesoc_rs232phytx_state)
|
|
1'd1: begin
|
|
main_basesoc_tx_enable <= 1'd1;
|
|
if (main_basesoc_tx_tick) begin
|
|
main_basesoc_serial_tx_rs232phytx_next_value1 <= main_basesoc_tx_data;
|
|
main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
|
|
main_basesoc_tx_count_rs232phytx_next_value0 <= (main_basesoc_tx_count + 1'd1);
|
|
main_basesoc_tx_count_rs232phytx_next_value_ce0 <= 1'd1;
|
|
main_basesoc_tx_data_rs232phytx_next_value2 <= {1'd1, main_basesoc_tx_data[7:1]};
|
|
main_basesoc_tx_data_rs232phytx_next_value_ce2 <= 1'd1;
|
|
if ((main_basesoc_tx_count == 4'd9)) begin
|
|
main_basesoc_tx_sink_ready <= 1'd1;
|
|
builder_basesoc_rs232phytx_next_state <= 1'd0;
|
|
end
|
|
end
|
|
end
|
|
default: begin
|
|
main_basesoc_tx_count_rs232phytx_next_value0 <= 1'd0;
|
|
main_basesoc_tx_count_rs232phytx_next_value_ce0 <= 1'd1;
|
|
main_basesoc_serial_tx_rs232phytx_next_value1 <= 1'd1;
|
|
main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
|
|
if (main_basesoc_tx_sink_valid) begin
|
|
main_basesoc_serial_tx_rs232phytx_next_value1 <= 1'd0;
|
|
main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
|
|
main_basesoc_tx_data_rs232phytx_next_value2 <= main_basesoc_tx_sink_payload_data;
|
|
main_basesoc_tx_data_rs232phytx_next_value_ce2 <= 1'd1;
|
|
builder_basesoc_rs232phytx_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
main_basesoc_rx_count_rs232phyrx_next_value_ce0 <= 1'd0;
|
|
main_basesoc_rx_data_rs232phyrx_next_value1 <= 8'd0;
|
|
main_basesoc_rx_source_valid <= 1'd0;
|
|
main_basesoc_rx_data_rs232phyrx_next_value_ce1 <= 1'd0;
|
|
main_basesoc_rx_source_payload_data <= 8'd0;
|
|
main_basesoc_rx_enable <= 1'd0;
|
|
builder_basesoc_rs232phyrx_next_state <= 1'd0;
|
|
main_basesoc_rx_count_rs232phyrx_next_value0 <= 4'd0;
|
|
builder_basesoc_rs232phyrx_next_state <= builder_basesoc_rs232phyrx_state;
|
|
case (builder_basesoc_rs232phyrx_state)
|
|
1'd1: begin
|
|
main_basesoc_rx_enable <= 1'd1;
|
|
if (main_basesoc_rx_tick) begin
|
|
main_basesoc_rx_count_rs232phyrx_next_value0 <= (main_basesoc_rx_count + 1'd1);
|
|
main_basesoc_rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
|
|
main_basesoc_rx_data_rs232phyrx_next_value1 <= {main_basesoc_rx_rx, main_basesoc_rx_data[7:1]};
|
|
main_basesoc_rx_data_rs232phyrx_next_value_ce1 <= 1'd1;
|
|
if ((main_basesoc_rx_count == 4'd9)) begin
|
|
main_basesoc_rx_source_valid <= (main_basesoc_rx_rx == 1'd1);
|
|
main_basesoc_rx_source_payload_data <= main_basesoc_rx_data;
|
|
builder_basesoc_rs232phyrx_next_state <= 1'd0;
|
|
end
|
|
end
|
|
end
|
|
default: begin
|
|
main_basesoc_rx_count_rs232phyrx_next_value0 <= 1'd0;
|
|
main_basesoc_rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
|
|
if (((main_basesoc_rx_rx == 1'd0) & (main_basesoc_rx_rx_d == 1'd1))) begin
|
|
builder_basesoc_rs232phyrx_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign main_basesoc_uart_uart_sink_valid = main_basesoc_rx_source_valid;
|
|
assign main_basesoc_rx_source_ready = main_basesoc_uart_uart_sink_ready;
|
|
assign main_basesoc_uart_uart_sink_first = main_basesoc_rx_source_first;
|
|
assign main_basesoc_uart_uart_sink_last = main_basesoc_rx_source_last;
|
|
assign main_basesoc_uart_uart_sink_payload_data = main_basesoc_rx_source_payload_data;
|
|
assign main_basesoc_tx_sink_valid = main_basesoc_uart_uart_source_valid;
|
|
assign main_basesoc_uart_uart_source_ready = main_basesoc_tx_sink_ready;
|
|
assign main_basesoc_tx_sink_first = main_basesoc_uart_uart_source_first;
|
|
assign main_basesoc_tx_sink_last = main_basesoc_uart_uart_source_last;
|
|
assign main_basesoc_tx_sink_payload_data = main_basesoc_uart_uart_source_payload_data;
|
|
assign main_basesoc_uart_tx_fifo_sink_valid = main_basesoc_uart_rxtx_re;
|
|
assign main_basesoc_uart_tx_fifo_sink_payload_data = main_basesoc_uart_rxtx_r;
|
|
assign main_basesoc_uart_uart_source_valid = main_basesoc_uart_tx_fifo_source_valid;
|
|
assign main_basesoc_uart_tx_fifo_source_ready = main_basesoc_uart_uart_source_ready;
|
|
assign main_basesoc_uart_uart_source_first = main_basesoc_uart_tx_fifo_source_first;
|
|
assign main_basesoc_uart_uart_source_last = main_basesoc_uart_tx_fifo_source_last;
|
|
assign main_basesoc_uart_uart_source_payload_data = main_basesoc_uart_tx_fifo_source_payload_data;
|
|
assign main_basesoc_uart_txfull_status = (~main_basesoc_uart_tx_fifo_sink_ready);
|
|
assign main_basesoc_uart_txempty_status = (~main_basesoc_uart_tx_fifo_source_valid);
|
|
assign main_basesoc_uart_tx_trigger = main_basesoc_uart_tx_fifo_sink_ready;
|
|
assign main_basesoc_uart_rx_fifo_sink_valid = main_basesoc_uart_uart_sink_valid;
|
|
assign main_basesoc_uart_uart_sink_ready = main_basesoc_uart_rx_fifo_sink_ready;
|
|
assign main_basesoc_uart_rx_fifo_sink_first = main_basesoc_uart_uart_sink_first;
|
|
assign main_basesoc_uart_rx_fifo_sink_last = main_basesoc_uart_uart_sink_last;
|
|
assign main_basesoc_uart_rx_fifo_sink_payload_data = main_basesoc_uart_uart_sink_payload_data;
|
|
assign main_basesoc_uart_rxtx_w = main_basesoc_uart_rx_fifo_source_payload_data;
|
|
assign main_basesoc_uart_rx_fifo_source_ready = (main_basesoc_uart_rx_clear | (1'd0 & main_basesoc_uart_rxtx_we));
|
|
assign main_basesoc_uart_rxempty_status = (~main_basesoc_uart_rx_fifo_source_valid);
|
|
assign main_basesoc_uart_rxfull_status = (~main_basesoc_uart_rx_fifo_sink_ready);
|
|
assign main_basesoc_uart_rx_trigger = main_basesoc_uart_rx_fifo_source_valid;
|
|
assign main_basesoc_uart_tx0 = main_basesoc_uart_tx_status;
|
|
assign main_basesoc_uart_tx1 = main_basesoc_uart_tx_pending;
|
|
always @(*) begin
|
|
main_basesoc_uart_tx_clear <= 1'd0;
|
|
if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[0])) begin
|
|
main_basesoc_uart_tx_clear <= 1'd1;
|
|
end
|
|
end
|
|
assign main_basesoc_uart_rx0 = main_basesoc_uart_rx_status;
|
|
assign main_basesoc_uart_rx1 = main_basesoc_uart_rx_pending;
|
|
always @(*) begin
|
|
main_basesoc_uart_rx_clear <= 1'd0;
|
|
if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[1])) begin
|
|
main_basesoc_uart_rx_clear <= 1'd1;
|
|
end
|
|
end
|
|
assign main_basesoc_uart_irq = ((main_basesoc_uart_pending_status[0] & main_basesoc_uart_enable_storage[0]) | (main_basesoc_uart_pending_status[1] & main_basesoc_uart_enable_storage[1]));
|
|
assign main_basesoc_uart_tx_status = main_basesoc_uart_tx_trigger;
|
|
assign main_basesoc_uart_rx_status = main_basesoc_uart_rx_trigger;
|
|
assign main_basesoc_uart_tx_fifo_syncfifo_din = {main_basesoc_uart_tx_fifo_fifo_in_last, main_basesoc_uart_tx_fifo_fifo_in_first, main_basesoc_uart_tx_fifo_fifo_in_payload_data};
|
|
assign {main_basesoc_uart_tx_fifo_fifo_out_last, main_basesoc_uart_tx_fifo_fifo_out_first, main_basesoc_uart_tx_fifo_fifo_out_payload_data} = main_basesoc_uart_tx_fifo_syncfifo_dout;
|
|
assign main_basesoc_uart_tx_fifo_sink_ready = main_basesoc_uart_tx_fifo_syncfifo_writable;
|
|
assign main_basesoc_uart_tx_fifo_syncfifo_we = main_basesoc_uart_tx_fifo_sink_valid;
|
|
assign main_basesoc_uart_tx_fifo_fifo_in_first = main_basesoc_uart_tx_fifo_sink_first;
|
|
assign main_basesoc_uart_tx_fifo_fifo_in_last = main_basesoc_uart_tx_fifo_sink_last;
|
|
assign main_basesoc_uart_tx_fifo_fifo_in_payload_data = main_basesoc_uart_tx_fifo_sink_payload_data;
|
|
assign main_basesoc_uart_tx_fifo_source_valid = main_basesoc_uart_tx_fifo_readable;
|
|
assign main_basesoc_uart_tx_fifo_source_first = main_basesoc_uart_tx_fifo_fifo_out_first;
|
|
assign main_basesoc_uart_tx_fifo_source_last = main_basesoc_uart_tx_fifo_fifo_out_last;
|
|
assign main_basesoc_uart_tx_fifo_source_payload_data = main_basesoc_uart_tx_fifo_fifo_out_payload_data;
|
|
assign main_basesoc_uart_tx_fifo_re = main_basesoc_uart_tx_fifo_source_ready;
|
|
assign main_basesoc_uart_tx_fifo_syncfifo_re = (main_basesoc_uart_tx_fifo_syncfifo_readable & ((~main_basesoc_uart_tx_fifo_readable) | main_basesoc_uart_tx_fifo_re));
|
|
assign main_basesoc_uart_tx_fifo_level1 = (main_basesoc_uart_tx_fifo_level0 + main_basesoc_uart_tx_fifo_readable);
|
|
always @(*) begin
|
|
main_basesoc_uart_tx_fifo_wrport_adr <= 4'd0;
|
|
if (main_basesoc_uart_tx_fifo_replace) begin
|
|
main_basesoc_uart_tx_fifo_wrport_adr <= (main_basesoc_uart_tx_fifo_produce - 1'd1);
|
|
end else begin
|
|
main_basesoc_uart_tx_fifo_wrport_adr <= main_basesoc_uart_tx_fifo_produce;
|
|
end
|
|
end
|
|
assign main_basesoc_uart_tx_fifo_wrport_dat_w = main_basesoc_uart_tx_fifo_syncfifo_din;
|
|
assign main_basesoc_uart_tx_fifo_wrport_we = (main_basesoc_uart_tx_fifo_syncfifo_we & (main_basesoc_uart_tx_fifo_syncfifo_writable | main_basesoc_uart_tx_fifo_replace));
|
|
assign main_basesoc_uart_tx_fifo_do_read = (main_basesoc_uart_tx_fifo_syncfifo_readable & main_basesoc_uart_tx_fifo_syncfifo_re);
|
|
assign main_basesoc_uart_tx_fifo_rdport_adr = main_basesoc_uart_tx_fifo_consume;
|
|
assign main_basesoc_uart_tx_fifo_syncfifo_dout = main_basesoc_uart_tx_fifo_rdport_dat_r;
|
|
assign main_basesoc_uart_tx_fifo_rdport_re = main_basesoc_uart_tx_fifo_do_read;
|
|
assign main_basesoc_uart_tx_fifo_syncfifo_writable = (main_basesoc_uart_tx_fifo_level0 != 5'd16);
|
|
assign main_basesoc_uart_tx_fifo_syncfifo_readable = (main_basesoc_uart_tx_fifo_level0 != 1'd0);
|
|
assign main_basesoc_uart_rx_fifo_syncfifo_din = {main_basesoc_uart_rx_fifo_fifo_in_last, main_basesoc_uart_rx_fifo_fifo_in_first, main_basesoc_uart_rx_fifo_fifo_in_payload_data};
|
|
assign {main_basesoc_uart_rx_fifo_fifo_out_last, main_basesoc_uart_rx_fifo_fifo_out_first, main_basesoc_uart_rx_fifo_fifo_out_payload_data} = main_basesoc_uart_rx_fifo_syncfifo_dout;
|
|
assign main_basesoc_uart_rx_fifo_sink_ready = main_basesoc_uart_rx_fifo_syncfifo_writable;
|
|
assign main_basesoc_uart_rx_fifo_syncfifo_we = main_basesoc_uart_rx_fifo_sink_valid;
|
|
assign main_basesoc_uart_rx_fifo_fifo_in_first = main_basesoc_uart_rx_fifo_sink_first;
|
|
assign main_basesoc_uart_rx_fifo_fifo_in_last = main_basesoc_uart_rx_fifo_sink_last;
|
|
assign main_basesoc_uart_rx_fifo_fifo_in_payload_data = main_basesoc_uart_rx_fifo_sink_payload_data;
|
|
assign main_basesoc_uart_rx_fifo_source_valid = main_basesoc_uart_rx_fifo_readable;
|
|
assign main_basesoc_uart_rx_fifo_source_first = main_basesoc_uart_rx_fifo_fifo_out_first;
|
|
assign main_basesoc_uart_rx_fifo_source_last = main_basesoc_uart_rx_fifo_fifo_out_last;
|
|
assign main_basesoc_uart_rx_fifo_source_payload_data = main_basesoc_uart_rx_fifo_fifo_out_payload_data;
|
|
assign main_basesoc_uart_rx_fifo_re = main_basesoc_uart_rx_fifo_source_ready;
|
|
assign main_basesoc_uart_rx_fifo_syncfifo_re = (main_basesoc_uart_rx_fifo_syncfifo_readable & ((~main_basesoc_uart_rx_fifo_readable) | main_basesoc_uart_rx_fifo_re));
|
|
assign main_basesoc_uart_rx_fifo_level1 = (main_basesoc_uart_rx_fifo_level0 + main_basesoc_uart_rx_fifo_readable);
|
|
always @(*) begin
|
|
main_basesoc_uart_rx_fifo_wrport_adr <= 4'd0;
|
|
if (main_basesoc_uart_rx_fifo_replace) begin
|
|
main_basesoc_uart_rx_fifo_wrport_adr <= (main_basesoc_uart_rx_fifo_produce - 1'd1);
|
|
end else begin
|
|
main_basesoc_uart_rx_fifo_wrport_adr <= main_basesoc_uart_rx_fifo_produce;
|
|
end
|
|
end
|
|
assign main_basesoc_uart_rx_fifo_wrport_dat_w = main_basesoc_uart_rx_fifo_syncfifo_din;
|
|
assign main_basesoc_uart_rx_fifo_wrport_we = (main_basesoc_uart_rx_fifo_syncfifo_we & (main_basesoc_uart_rx_fifo_syncfifo_writable | main_basesoc_uart_rx_fifo_replace));
|
|
assign main_basesoc_uart_rx_fifo_do_read = (main_basesoc_uart_rx_fifo_syncfifo_readable & main_basesoc_uart_rx_fifo_syncfifo_re);
|
|
assign main_basesoc_uart_rx_fifo_rdport_adr = main_basesoc_uart_rx_fifo_consume;
|
|
assign main_basesoc_uart_rx_fifo_syncfifo_dout = main_basesoc_uart_rx_fifo_rdport_dat_r;
|
|
assign main_basesoc_uart_rx_fifo_rdport_re = main_basesoc_uart_rx_fifo_do_read;
|
|
assign main_basesoc_uart_rx_fifo_syncfifo_writable = (main_basesoc_uart_rx_fifo_level0 != 5'd16);
|
|
assign main_basesoc_uart_rx_fifo_syncfifo_readable = (main_basesoc_uart_rx_fifo_level0 != 1'd0);
|
|
assign main_basesoc_timer_zero_trigger = (main_basesoc_timer_value == 1'd0);
|
|
assign main_basesoc_timer_zero0 = main_basesoc_timer_zero_status;
|
|
assign main_basesoc_timer_zero1 = main_basesoc_timer_zero_pending;
|
|
always @(*) begin
|
|
main_basesoc_timer_zero_clear <= 1'd0;
|
|
if ((main_basesoc_timer_pending_re & main_basesoc_timer_pending_r)) begin
|
|
main_basesoc_timer_zero_clear <= 1'd1;
|
|
end
|
|
end
|
|
assign main_basesoc_timer_irq = (main_basesoc_timer_pending_status & main_basesoc_timer_enable_storage);
|
|
assign main_basesoc_timer_zero_status = main_basesoc_timer_zero_trigger;
|
|
assign main_crg_reset = main_crg_rst;
|
|
assign main_crg_clkin = clk12;
|
|
assign sys_clk = main_crg_clkout_buf0;
|
|
assign sys2x_clk = main_crg_clkout_buf1;
|
|
assign idelay_clk = main_crg_clkout_buf2;
|
|
assign main_basesoc_adr = main_basesoc_ram_bus_adr[13:0];
|
|
assign main_basesoc_ram_bus_dat_r = main_basesoc_dat_r;
|
|
always @(*) begin
|
|
main_basesoc_sram0_we <= 4'd0;
|
|
main_basesoc_sram0_we[0] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[0]);
|
|
main_basesoc_sram0_we[1] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[1]);
|
|
main_basesoc_sram0_we[2] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[2]);
|
|
main_basesoc_sram0_we[3] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[3]);
|
|
end
|
|
assign main_basesoc_sram0_adr = main_basesoc_interface0_ram_bus_adr[13:0];
|
|
assign main_basesoc_interface0_ram_bus_dat_r = main_basesoc_sram0_dat_r;
|
|
assign main_basesoc_sram0_dat_w = main_basesoc_interface0_ram_bus_dat_w;
|
|
always @(*) begin
|
|
main_basesoc_sram1_we <= 4'd0;
|
|
main_basesoc_sram1_we[0] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[0]);
|
|
main_basesoc_sram1_we[1] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[1]);
|
|
main_basesoc_sram1_we[2] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[2]);
|
|
main_basesoc_sram1_we[3] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[3]);
|
|
end
|
|
assign main_basesoc_sram1_adr = main_basesoc_interface1_ram_bus_adr[21:0];
|
|
assign main_basesoc_interface1_ram_bus_dat_r = main_basesoc_sram1_dat_r;
|
|
assign main_basesoc_sram1_dat_w = main_basesoc_interface1_ram_bus_dat_w;
|
|
assign main_leds_wait = (~main_leds_done);
|
|
always @(*) begin
|
|
main_leds_leds <= 2'd0;
|
|
if ((main_leds_mode == 1'd1)) begin
|
|
main_leds_leds <= main_leds_storage;
|
|
end else begin
|
|
main_leds_leds <= main_leds_chaser;
|
|
end
|
|
end
|
|
assign {user_led1, user_led0} = (main_leds_leds ^ 1'd0);
|
|
assign main_leds_done = (main_leds_count == 1'd0);
|
|
always @(*) begin
|
|
builder_basesoc_we <= 1'd0;
|
|
builder_basesoc_dat_w <= 32'd0;
|
|
builder_basesoc_wishbone_ack <= 1'd0;
|
|
builder_basesoc_wishbone_dat_r <= 32'd0;
|
|
builder_basesoc_next_state <= 1'd0;
|
|
builder_basesoc_adr <= 14'd0;
|
|
builder_basesoc_next_state <= builder_basesoc_state;
|
|
case (builder_basesoc_state)
|
|
1'd1: begin
|
|
builder_basesoc_wishbone_ack <= 1'd1;
|
|
builder_basesoc_wishbone_dat_r <= builder_basesoc_dat_r;
|
|
builder_basesoc_next_state <= 1'd0;
|
|
end
|
|
default: begin
|
|
builder_basesoc_dat_w <= builder_basesoc_wishbone_dat_w;
|
|
if ((builder_basesoc_wishbone_cyc & builder_basesoc_wishbone_stb)) begin
|
|
builder_basesoc_adr <= builder_basesoc_wishbone_adr;
|
|
builder_basesoc_we <= (builder_basesoc_wishbone_we & (builder_basesoc_wishbone_sel != 1'd0));
|
|
builder_basesoc_next_state <= 1'd1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
assign builder_shared_adr = builder_array_muxed0;
|
|
assign builder_shared_dat_w = builder_array_muxed1;
|
|
assign builder_shared_sel = builder_array_muxed2;
|
|
assign builder_shared_cyc = builder_array_muxed3;
|
|
assign builder_shared_stb = builder_array_muxed4;
|
|
assign builder_shared_we = builder_array_muxed5;
|
|
assign builder_shared_cti = builder_array_muxed6;
|
|
assign builder_shared_bte = builder_array_muxed7;
|
|
assign main_basesoc_ibus_dat_r = builder_shared_dat_r;
|
|
assign main_basesoc_dbus_dat_r = builder_shared_dat_r;
|
|
assign main_basesoc_ibus_ack = (builder_shared_ack & (builder_grant == 1'd0));
|
|
assign main_basesoc_dbus_ack = (builder_shared_ack & (builder_grant == 1'd1));
|
|
assign main_basesoc_ibus_err = (builder_shared_err & (builder_grant == 1'd0));
|
|
assign main_basesoc_dbus_err = (builder_shared_err & (builder_grant == 1'd1));
|
|
assign builder_request = {main_basesoc_dbus_cyc, main_basesoc_ibus_cyc};
|
|
always @(*) begin
|
|
builder_slave_sel <= 4'd0;
|
|
builder_slave_sel[0] <= (builder_shared_adr[29:14] == 1'd0);
|
|
builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd1);
|
|
builder_slave_sel[2] <= (builder_shared_adr[29:22] == 1'd1);
|
|
builder_slave_sel[3] <= (builder_shared_adr[29:14] == 16'd65520);
|
|
end
|
|
assign main_basesoc_ram_bus_adr = builder_shared_adr;
|
|
assign main_basesoc_ram_bus_dat_w = builder_shared_dat_w;
|
|
assign main_basesoc_ram_bus_sel = builder_shared_sel;
|
|
assign main_basesoc_ram_bus_stb = builder_shared_stb;
|
|
assign main_basesoc_ram_bus_we = builder_shared_we;
|
|
assign main_basesoc_ram_bus_cti = builder_shared_cti;
|
|
assign main_basesoc_ram_bus_bte = builder_shared_bte;
|
|
assign main_basesoc_interface0_ram_bus_adr = builder_shared_adr;
|
|
assign main_basesoc_interface0_ram_bus_dat_w = builder_shared_dat_w;
|
|
assign main_basesoc_interface0_ram_bus_sel = builder_shared_sel;
|
|
assign main_basesoc_interface0_ram_bus_stb = builder_shared_stb;
|
|
assign main_basesoc_interface0_ram_bus_we = builder_shared_we;
|
|
assign main_basesoc_interface0_ram_bus_cti = builder_shared_cti;
|
|
assign main_basesoc_interface0_ram_bus_bte = builder_shared_bte;
|
|
assign main_basesoc_interface1_ram_bus_adr = builder_shared_adr;
|
|
assign main_basesoc_interface1_ram_bus_dat_w = builder_shared_dat_w;
|
|
assign main_basesoc_interface1_ram_bus_sel = builder_shared_sel;
|
|
assign main_basesoc_interface1_ram_bus_stb = builder_shared_stb;
|
|
assign main_basesoc_interface1_ram_bus_we = builder_shared_we;
|
|
assign main_basesoc_interface1_ram_bus_cti = builder_shared_cti;
|
|
assign main_basesoc_interface1_ram_bus_bte = builder_shared_bte;
|
|
assign builder_basesoc_wishbone_adr = builder_shared_adr;
|
|
assign builder_basesoc_wishbone_dat_w = builder_shared_dat_w;
|
|
assign builder_basesoc_wishbone_sel = builder_shared_sel;
|
|
assign builder_basesoc_wishbone_stb = builder_shared_stb;
|
|
assign builder_basesoc_wishbone_we = builder_shared_we;
|
|
assign builder_basesoc_wishbone_cti = builder_shared_cti;
|
|
assign builder_basesoc_wishbone_bte = builder_shared_bte;
|
|
assign main_basesoc_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]);
|
|
assign main_basesoc_interface0_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[1]);
|
|
assign main_basesoc_interface1_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[2]);
|
|
assign builder_basesoc_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[3]);
|
|
assign builder_shared_err = (((main_basesoc_ram_bus_err | main_basesoc_interface0_ram_bus_err) | main_basesoc_interface1_ram_bus_err) | builder_basesoc_wishbone_err);
|
|
assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
|
|
always @(*) begin
|
|
builder_error <= 1'd0;
|
|
builder_shared_ack <= 1'd0;
|
|
builder_shared_dat_r <= 32'd0;
|
|
builder_shared_ack <= (((main_basesoc_ram_bus_ack | main_basesoc_interface0_ram_bus_ack) | main_basesoc_interface1_ram_bus_ack) | builder_basesoc_wishbone_ack);
|
|
builder_shared_dat_r <= (((({32{builder_slave_sel_r[0]}} & main_basesoc_ram_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & main_basesoc_interface0_ram_bus_dat_r)) | ({32{builder_slave_sel_r[2]}} & main_basesoc_interface1_ram_bus_dat_r)) | ({32{builder_slave_sel_r[3]}} & builder_basesoc_wishbone_dat_r));
|
|
if (builder_done) begin
|
|
builder_shared_dat_r <= 32'd4294967295;
|
|
builder_shared_ack <= 1'd1;
|
|
builder_error <= 1'd1;
|
|
end
|
|
end
|
|
assign builder_done = (builder_count == 1'd0);
|
|
assign builder_csr_bankarray_csrbank0_sel = (builder_csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd4);
|
|
assign builder_csr_bankarray_csrbank0_in_r = builder_csr_bankarray_interface0_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank0_in_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank0_in_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin
|
|
builder_csr_bankarray_csrbank0_in_re <= builder_csr_bankarray_interface0_bank_bus_we;
|
|
builder_csr_bankarray_csrbank0_in_we <= (~builder_csr_bankarray_interface0_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank0_in_w = main_buttons_status[1:0];
|
|
assign main_buttons_we = builder_csr_bankarray_csrbank0_in_we;
|
|
assign builder_csr_bankarray_csrbank1_sel = (builder_csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd5);
|
|
assign builder_csr_bankarray_csrbank1_reset0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank1_reset0_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank1_reset0_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin
|
|
builder_csr_bankarray_csrbank1_reset0_re <= builder_csr_bankarray_interface1_bank_bus_we;
|
|
builder_csr_bankarray_csrbank1_reset0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank1_scratch0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank1_scratch0_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank1_scratch0_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin
|
|
builder_csr_bankarray_csrbank1_scratch0_re <= builder_csr_bankarray_interface1_bank_bus_we;
|
|
builder_csr_bankarray_csrbank1_scratch0_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank1_bus_errors_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank1_bus_errors_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank1_bus_errors_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin
|
|
builder_csr_bankarray_csrbank1_bus_errors_re <= builder_csr_bankarray_interface1_bank_bus_we;
|
|
builder_csr_bankarray_csrbank1_bus_errors_we <= (~builder_csr_bankarray_interface1_bank_bus_we);
|
|
end
|
|
end
|
|
always @(*) begin
|
|
main_basesoc_soc_rst <= 1'd0;
|
|
if (main_basesoc_reset_re) begin
|
|
main_basesoc_soc_rst <= main_basesoc_reset_storage[0];
|
|
end
|
|
end
|
|
assign main_basesoc_cpu_rst = main_basesoc_reset_storage[1];
|
|
assign builder_csr_bankarray_csrbank1_reset0_w = main_basesoc_reset_storage[1:0];
|
|
assign builder_csr_bankarray_csrbank1_scratch0_w = main_basesoc_scratch_storage[31:0];
|
|
assign builder_csr_bankarray_csrbank1_bus_errors_w = main_basesoc_bus_errors_status[31:0];
|
|
assign main_basesoc_bus_errors_we = builder_csr_bankarray_csrbank1_bus_errors_we;
|
|
assign builder_csr_bankarray_sel = (builder_csr_bankarray_sram_bus_adr[13:9] == 3'd6);
|
|
always @(*) begin
|
|
builder_csr_bankarray_sram_bus_dat_r <= 32'd0;
|
|
if (builder_csr_bankarray_sel_r) begin
|
|
builder_csr_bankarray_sram_bus_dat_r <= builder_csr_bankarray_dat_r;
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_adr = builder_csr_bankarray_sram_bus_adr[4:0];
|
|
assign builder_csr_bankarray_csrbank2_sel = (builder_csr_bankarray_interface2_bank_bus_adr[13:9] == 2'd3);
|
|
assign builder_csr_bankarray_csrbank2_out0_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank2_out0_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank2_out0_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin
|
|
builder_csr_bankarray_csrbank2_out0_re <= builder_csr_bankarray_interface2_bank_bus_we;
|
|
builder_csr_bankarray_csrbank2_out0_we <= (~builder_csr_bankarray_interface2_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank2_out0_w = main_leds_storage[1:0];
|
|
assign builder_csr_bankarray_csrbank3_sel = (builder_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd7);
|
|
assign builder_csr_bankarray_csrbank3_load0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_load0_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_load0_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin
|
|
builder_csr_bankarray_csrbank3_load0_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_load0_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_reload0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_reload0_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_reload0_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd1))) begin
|
|
builder_csr_bankarray_csrbank3_reload0_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_reload0_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_en0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_en0_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_en0_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd2))) begin
|
|
builder_csr_bankarray_csrbank3_en0_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_en0_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_update_value0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_update_value0_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_update_value0_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd3))) begin
|
|
builder_csr_bankarray_csrbank3_update_value0_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_update_value0_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_value_r = builder_csr_bankarray_interface3_bank_bus_dat_w[31:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_value_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_value_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd4))) begin
|
|
builder_csr_bankarray_csrbank3_value_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_value_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_ev_status_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_ev_status_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_ev_status_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd5))) begin
|
|
builder_csr_bankarray_csrbank3_ev_status_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_ev_status_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_ev_pending_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_ev_pending_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_ev_pending_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd6))) begin
|
|
builder_csr_bankarray_csrbank3_ev_pending_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_ev_pending_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_ev_enable0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank3_ev_enable0_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank3_ev_enable0_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd7))) begin
|
|
builder_csr_bankarray_csrbank3_ev_enable0_re <= builder_csr_bankarray_interface3_bank_bus_we;
|
|
builder_csr_bankarray_csrbank3_ev_enable0_we <= (~builder_csr_bankarray_interface3_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank3_load0_w = main_basesoc_timer_load_storage[31:0];
|
|
assign builder_csr_bankarray_csrbank3_reload0_w = main_basesoc_timer_reload_storage[31:0];
|
|
assign builder_csr_bankarray_csrbank3_en0_w = main_basesoc_timer_en_storage;
|
|
assign builder_csr_bankarray_csrbank3_update_value0_w = main_basesoc_timer_update_value_storage;
|
|
assign builder_csr_bankarray_csrbank3_value_w = main_basesoc_timer_value_status[31:0];
|
|
assign main_basesoc_timer_value_we = builder_csr_bankarray_csrbank3_value_we;
|
|
assign main_basesoc_timer_status_status = main_basesoc_timer_zero0;
|
|
assign builder_csr_bankarray_csrbank3_ev_status_w = main_basesoc_timer_status_status;
|
|
assign main_basesoc_timer_status_we = builder_csr_bankarray_csrbank3_ev_status_we;
|
|
assign main_basesoc_timer_pending_status = main_basesoc_timer_zero1;
|
|
assign builder_csr_bankarray_csrbank3_ev_pending_w = main_basesoc_timer_pending_status;
|
|
assign main_basesoc_timer_pending_we = builder_csr_bankarray_csrbank3_ev_pending_we;
|
|
assign main_basesoc_timer_zero2 = main_basesoc_timer_enable_storage;
|
|
assign builder_csr_bankarray_csrbank3_ev_enable0_w = main_basesoc_timer_enable_storage;
|
|
assign builder_csr_bankarray_csrbank4_sel = (builder_csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8);
|
|
assign main_basesoc_uart_rxtx_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0];
|
|
always @(*) begin
|
|
main_basesoc_uart_rxtx_we <= 1'd0;
|
|
main_basesoc_uart_rxtx_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin
|
|
main_basesoc_uart_rxtx_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
main_basesoc_uart_rxtx_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_txfull_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_txfull_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_txfull_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin
|
|
builder_csr_bankarray_csrbank4_txfull_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_txfull_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_rxempty_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_rxempty_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_rxempty_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd2))) begin
|
|
builder_csr_bankarray_csrbank4_rxempty_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_rxempty_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_ev_status_r = builder_csr_bankarray_interface4_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_ev_status_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_ev_status_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd3))) begin
|
|
builder_csr_bankarray_csrbank4_ev_status_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_ev_status_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_ev_pending_r = builder_csr_bankarray_interface4_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_ev_pending_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_ev_pending_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd4))) begin
|
|
builder_csr_bankarray_csrbank4_ev_pending_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_ev_pending_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_ev_enable0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[1:0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_ev_enable0_re <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_ev_enable0_we <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd5))) begin
|
|
builder_csr_bankarray_csrbank4_ev_enable0_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_ev_enable0_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_txempty_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_txempty_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_txempty_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd6))) begin
|
|
builder_csr_bankarray_csrbank4_txempty_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_txempty_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_rxfull_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0];
|
|
always @(*) begin
|
|
builder_csr_bankarray_csrbank4_rxfull_we <= 1'd0;
|
|
builder_csr_bankarray_csrbank4_rxfull_re <= 1'd0;
|
|
if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd7))) begin
|
|
builder_csr_bankarray_csrbank4_rxfull_re <= builder_csr_bankarray_interface4_bank_bus_we;
|
|
builder_csr_bankarray_csrbank4_rxfull_we <= (~builder_csr_bankarray_interface4_bank_bus_we);
|
|
end
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_txfull_w = main_basesoc_uart_txfull_status;
|
|
assign main_basesoc_uart_txfull_we = builder_csr_bankarray_csrbank4_txfull_we;
|
|
assign builder_csr_bankarray_csrbank4_rxempty_w = main_basesoc_uart_rxempty_status;
|
|
assign main_basesoc_uart_rxempty_we = builder_csr_bankarray_csrbank4_rxempty_we;
|
|
always @(*) begin
|
|
main_basesoc_uart_status_status <= 2'd0;
|
|
main_basesoc_uart_status_status[0] <= main_basesoc_uart_tx0;
|
|
main_basesoc_uart_status_status[1] <= main_basesoc_uart_rx0;
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_ev_status_w = main_basesoc_uart_status_status[1:0];
|
|
assign main_basesoc_uart_status_we = builder_csr_bankarray_csrbank4_ev_status_we;
|
|
always @(*) begin
|
|
main_basesoc_uart_pending_status <= 2'd0;
|
|
main_basesoc_uart_pending_status[0] <= main_basesoc_uart_tx1;
|
|
main_basesoc_uart_pending_status[1] <= main_basesoc_uart_rx1;
|
|
end
|
|
assign builder_csr_bankarray_csrbank4_ev_pending_w = main_basesoc_uart_pending_status[1:0];
|
|
assign main_basesoc_uart_pending_we = builder_csr_bankarray_csrbank4_ev_pending_we;
|
|
assign main_basesoc_uart_tx2 = main_basesoc_uart_enable_storage[0];
|
|
assign main_basesoc_uart_rx2 = main_basesoc_uart_enable_storage[1];
|
|
assign builder_csr_bankarray_csrbank4_ev_enable0_w = main_basesoc_uart_enable_storage[1:0];
|
|
assign builder_csr_bankarray_csrbank4_txempty_w = main_basesoc_uart_txempty_status;
|
|
assign main_basesoc_uart_txempty_we = builder_csr_bankarray_csrbank4_txempty_we;
|
|
assign builder_csr_bankarray_csrbank4_rxfull_w = main_basesoc_uart_rxfull_status;
|
|
assign main_basesoc_uart_rxfull_we = builder_csr_bankarray_csrbank4_rxfull_we;
|
|
assign builder_csr_interconnect_adr = builder_basesoc_adr;
|
|
assign builder_csr_interconnect_we = builder_basesoc_we;
|
|
assign builder_csr_interconnect_dat_w = builder_basesoc_dat_w;
|
|
assign builder_basesoc_dat_r = builder_csr_interconnect_dat_r;
|
|
assign builder_csr_bankarray_interface0_bank_bus_adr = builder_csr_interconnect_adr;
|
|
assign builder_csr_bankarray_interface1_bank_bus_adr = builder_csr_interconnect_adr;
|
|
assign builder_csr_bankarray_interface2_bank_bus_adr = builder_csr_interconnect_adr;
|
|
assign builder_csr_bankarray_interface3_bank_bus_adr = builder_csr_interconnect_adr;
|
|
assign builder_csr_bankarray_interface4_bank_bus_adr = builder_csr_interconnect_adr;
|
|
assign builder_csr_bankarray_sram_bus_adr = builder_csr_interconnect_adr;
|
|
assign builder_csr_bankarray_interface0_bank_bus_we = builder_csr_interconnect_we;
|
|
assign builder_csr_bankarray_interface1_bank_bus_we = builder_csr_interconnect_we;
|
|
assign builder_csr_bankarray_interface2_bank_bus_we = builder_csr_interconnect_we;
|
|
assign builder_csr_bankarray_interface3_bank_bus_we = builder_csr_interconnect_we;
|
|
assign builder_csr_bankarray_interface4_bank_bus_we = builder_csr_interconnect_we;
|
|
assign builder_csr_bankarray_sram_bus_we = builder_csr_interconnect_we;
|
|
assign builder_csr_bankarray_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
|
|
assign builder_csr_bankarray_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
|
|
assign builder_csr_bankarray_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
|
|
assign builder_csr_bankarray_interface3_bank_bus_dat_w = builder_csr_interconnect_dat_w;
|
|
assign builder_csr_bankarray_interface4_bank_bus_dat_w = builder_csr_interconnect_dat_w;
|
|
assign builder_csr_bankarray_sram_bus_dat_w = builder_csr_interconnect_dat_w;
|
|
assign builder_csr_interconnect_dat_r = (((((builder_csr_bankarray_interface0_bank_bus_dat_r | builder_csr_bankarray_interface1_bank_bus_dat_r) | builder_csr_bankarray_interface2_bank_bus_dat_r) | builder_csr_bankarray_interface3_bank_bus_dat_r) | builder_csr_bankarray_interface4_bank_bus_dat_r) | builder_csr_bankarray_sram_bus_dat_r);
|
|
always @(*) begin
|
|
builder_array_muxed0 <= 30'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed0 <= main_basesoc_ibus_adr;
|
|
end
|
|
default: begin
|
|
builder_array_muxed0 <= main_basesoc_dbus_adr;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed1 <= 32'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed1 <= main_basesoc_ibus_dat_w;
|
|
end
|
|
default: begin
|
|
builder_array_muxed1 <= main_basesoc_dbus_dat_w;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed2 <= 4'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed2 <= main_basesoc_ibus_sel;
|
|
end
|
|
default: begin
|
|
builder_array_muxed2 <= main_basesoc_dbus_sel;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed3 <= 1'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed3 <= main_basesoc_ibus_cyc;
|
|
end
|
|
default: begin
|
|
builder_array_muxed3 <= main_basesoc_dbus_cyc;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed4 <= 1'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed4 <= main_basesoc_ibus_stb;
|
|
end
|
|
default: begin
|
|
builder_array_muxed4 <= main_basesoc_dbus_stb;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed5 <= 1'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed5 <= main_basesoc_ibus_we;
|
|
end
|
|
default: begin
|
|
builder_array_muxed5 <= main_basesoc_dbus_we;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed6 <= 3'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed6 <= main_basesoc_ibus_cti;
|
|
end
|
|
default: begin
|
|
builder_array_muxed6 <= main_basesoc_dbus_cti;
|
|
end
|
|
endcase
|
|
end
|
|
always @(*) begin
|
|
builder_array_muxed7 <= 2'd0;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
builder_array_muxed7 <= main_basesoc_ibus_bte;
|
|
end
|
|
default: begin
|
|
builder_array_muxed7 <= main_basesoc_dbus_bte;
|
|
end
|
|
endcase
|
|
end
|
|
assign main_basesoc_rx_rx = builder_xilinxmultiregimpl0_regs1;
|
|
assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_crg_locked);
|
|
assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_crg_locked);
|
|
assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_crg_locked);
|
|
assign main_buttons_status = builder_xilinxmultiregimpl1_regs1;
|
|
assign builder_xilinxmultiregimpl1 = {user_btn1, user_btn0};
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Synchronous Logic
|
|
//------------------------------------------------------------------------------
|
|
|
|
always @(posedge idelay_clk) begin
|
|
if ((main_crg_reset_counter != 1'd0)) begin
|
|
main_crg_reset_counter <= (main_crg_reset_counter - 1'd1);
|
|
end else begin
|
|
main_crg_ic_reset <= 1'd0;
|
|
end
|
|
if (idelay_rst) begin
|
|
main_crg_reset_counter <= 4'd15;
|
|
main_crg_ic_reset <= 1'd1;
|
|
end
|
|
end
|
|
|
|
always @(posedge sys_clk) begin
|
|
if ((main_basesoc_bus_errors != 32'd4294967295)) begin
|
|
if (main_basesoc_bus_error) begin
|
|
main_basesoc_bus_errors <= (main_basesoc_bus_errors + 1'd1);
|
|
end
|
|
end
|
|
{main_basesoc_tx_tick, main_basesoc_tx_phase} <= 23'd4947802;
|
|
if (main_basesoc_tx_enable) begin
|
|
{main_basesoc_tx_tick, main_basesoc_tx_phase} <= (main_basesoc_tx_phase + 23'd4947802);
|
|
end
|
|
builder_basesoc_rs232phytx_state <= builder_basesoc_rs232phytx_next_state;
|
|
if (main_basesoc_tx_count_rs232phytx_next_value_ce0) begin
|
|
main_basesoc_tx_count <= main_basesoc_tx_count_rs232phytx_next_value0;
|
|
end
|
|
if (main_basesoc_serial_tx_rs232phytx_next_value_ce1) begin
|
|
serial_tx <= main_basesoc_serial_tx_rs232phytx_next_value1;
|
|
end
|
|
if (main_basesoc_tx_data_rs232phytx_next_value_ce2) begin
|
|
main_basesoc_tx_data <= main_basesoc_tx_data_rs232phytx_next_value2;
|
|
end
|
|
main_basesoc_rx_rx_d <= main_basesoc_rx_rx;
|
|
{main_basesoc_rx_tick, main_basesoc_rx_phase} <= 32'd2147483648;
|
|
if (main_basesoc_rx_enable) begin
|
|
{main_basesoc_rx_tick, main_basesoc_rx_phase} <= (main_basesoc_rx_phase + 23'd4947802);
|
|
end
|
|
builder_basesoc_rs232phyrx_state <= builder_basesoc_rs232phyrx_next_state;
|
|
if (main_basesoc_rx_count_rs232phyrx_next_value_ce0) begin
|
|
main_basesoc_rx_count <= main_basesoc_rx_count_rs232phyrx_next_value0;
|
|
end
|
|
if (main_basesoc_rx_data_rs232phyrx_next_value_ce1) begin
|
|
main_basesoc_rx_data <= main_basesoc_rx_data_rs232phyrx_next_value1;
|
|
end
|
|
if (main_basesoc_uart_tx_clear) begin
|
|
main_basesoc_uart_tx_pending <= 1'd0;
|
|
end
|
|
main_basesoc_uart_tx_trigger_d <= main_basesoc_uart_tx_trigger;
|
|
if ((main_basesoc_uart_tx_trigger & (~main_basesoc_uart_tx_trigger_d))) begin
|
|
main_basesoc_uart_tx_pending <= 1'd1;
|
|
end
|
|
if (main_basesoc_uart_rx_clear) begin
|
|
main_basesoc_uart_rx_pending <= 1'd0;
|
|
end
|
|
main_basesoc_uart_rx_trigger_d <= main_basesoc_uart_rx_trigger;
|
|
if ((main_basesoc_uart_rx_trigger & (~main_basesoc_uart_rx_trigger_d))) begin
|
|
main_basesoc_uart_rx_pending <= 1'd1;
|
|
end
|
|
if (main_basesoc_uart_tx_fifo_syncfifo_re) begin
|
|
main_basesoc_uart_tx_fifo_readable <= 1'd1;
|
|
end else begin
|
|
if (main_basesoc_uart_tx_fifo_re) begin
|
|
main_basesoc_uart_tx_fifo_readable <= 1'd0;
|
|
end
|
|
end
|
|
if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin
|
|
main_basesoc_uart_tx_fifo_produce <= (main_basesoc_uart_tx_fifo_produce + 1'd1);
|
|
end
|
|
if (main_basesoc_uart_tx_fifo_do_read) begin
|
|
main_basesoc_uart_tx_fifo_consume <= (main_basesoc_uart_tx_fifo_consume + 1'd1);
|
|
end
|
|
if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin
|
|
if ((~main_basesoc_uart_tx_fifo_do_read)) begin
|
|
main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 + 1'd1);
|
|
end
|
|
end else begin
|
|
if (main_basesoc_uart_tx_fifo_do_read) begin
|
|
main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 - 1'd1);
|
|
end
|
|
end
|
|
if (main_basesoc_uart_rx_fifo_syncfifo_re) begin
|
|
main_basesoc_uart_rx_fifo_readable <= 1'd1;
|
|
end else begin
|
|
if (main_basesoc_uart_rx_fifo_re) begin
|
|
main_basesoc_uart_rx_fifo_readable <= 1'd0;
|
|
end
|
|
end
|
|
if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin
|
|
main_basesoc_uart_rx_fifo_produce <= (main_basesoc_uart_rx_fifo_produce + 1'd1);
|
|
end
|
|
if (main_basesoc_uart_rx_fifo_do_read) begin
|
|
main_basesoc_uart_rx_fifo_consume <= (main_basesoc_uart_rx_fifo_consume + 1'd1);
|
|
end
|
|
if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin
|
|
if ((~main_basesoc_uart_rx_fifo_do_read)) begin
|
|
main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 + 1'd1);
|
|
end
|
|
end else begin
|
|
if (main_basesoc_uart_rx_fifo_do_read) begin
|
|
main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 - 1'd1);
|
|
end
|
|
end
|
|
if (main_basesoc_timer_en_storage) begin
|
|
if ((main_basesoc_timer_value == 1'd0)) begin
|
|
main_basesoc_timer_value <= main_basesoc_timer_reload_storage;
|
|
end else begin
|
|
main_basesoc_timer_value <= (main_basesoc_timer_value - 1'd1);
|
|
end
|
|
end else begin
|
|
main_basesoc_timer_value <= main_basesoc_timer_load_storage;
|
|
end
|
|
if (main_basesoc_timer_update_value_re) begin
|
|
main_basesoc_timer_value_status <= main_basesoc_timer_value;
|
|
end
|
|
if (main_basesoc_timer_zero_clear) begin
|
|
main_basesoc_timer_zero_pending <= 1'd0;
|
|
end
|
|
main_basesoc_timer_zero_trigger_d <= main_basesoc_timer_zero_trigger;
|
|
if ((main_basesoc_timer_zero_trigger & (~main_basesoc_timer_zero_trigger_d))) begin
|
|
main_basesoc_timer_zero_pending <= 1'd1;
|
|
end
|
|
main_basesoc_ram_bus_ack <= 1'd0;
|
|
if (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & ((~main_basesoc_ram_bus_ack) | main_basesoc_adr_burst))) begin
|
|
main_basesoc_ram_bus_ack <= 1'd1;
|
|
end
|
|
main_basesoc_interface0_ram_bus_ack <= 1'd0;
|
|
if (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & ((~main_basesoc_interface0_ram_bus_ack) | main_basesoc_sram0_adr_burst))) begin
|
|
main_basesoc_interface0_ram_bus_ack <= 1'd1;
|
|
end
|
|
main_basesoc_interface1_ram_bus_ack <= 1'd0;
|
|
if (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & ((~main_basesoc_interface1_ram_bus_ack) | main_basesoc_sram1_adr_burst))) begin
|
|
main_basesoc_interface1_ram_bus_ack <= 1'd1;
|
|
end
|
|
if (main_leds_done) begin
|
|
main_leds_chaser <= {main_leds_chaser, (~main_leds_chaser[1])};
|
|
end
|
|
if (main_leds_re) begin
|
|
main_leds_mode <= 1'd1;
|
|
end
|
|
if (main_leds_wait) begin
|
|
if ((~main_leds_done)) begin
|
|
main_leds_count <= (main_leds_count - 1'd1);
|
|
end
|
|
end else begin
|
|
main_leds_count <= 25'd25000000;
|
|
end
|
|
builder_basesoc_state <= builder_basesoc_next_state;
|
|
case (builder_grant)
|
|
1'd0: begin
|
|
if ((~builder_request[0])) begin
|
|
if (builder_request[1]) begin
|
|
builder_grant <= 1'd1;
|
|
end
|
|
end
|
|
end
|
|
1'd1: begin
|
|
if ((~builder_request[1])) begin
|
|
if (builder_request[0]) begin
|
|
builder_grant <= 1'd0;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
builder_slave_sel_r <= builder_slave_sel;
|
|
if (builder_wait) begin
|
|
if ((~builder_done)) begin
|
|
builder_count <= (builder_count - 1'd1);
|
|
end
|
|
end else begin
|
|
builder_count <= 20'd1000000;
|
|
end
|
|
builder_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0;
|
|
if (builder_csr_bankarray_csrbank0_sel) begin
|
|
case (builder_csr_bankarray_interface0_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_in_w;
|
|
end
|
|
endcase
|
|
end
|
|
main_buttons_re <= builder_csr_bankarray_csrbank0_in_re;
|
|
builder_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0;
|
|
if (builder_csr_bankarray_csrbank1_sel) begin
|
|
case (builder_csr_bankarray_interface1_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_reset0_w;
|
|
end
|
|
1'd1: begin
|
|
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_scratch0_w;
|
|
end
|
|
2'd2: begin
|
|
builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_bus_errors_w;
|
|
end
|
|
endcase
|
|
end
|
|
if (builder_csr_bankarray_csrbank1_reset0_re) begin
|
|
main_basesoc_reset_storage[1:0] <= builder_csr_bankarray_csrbank1_reset0_r;
|
|
end
|
|
main_basesoc_reset_re <= builder_csr_bankarray_csrbank1_reset0_re;
|
|
if (builder_csr_bankarray_csrbank1_scratch0_re) begin
|
|
main_basesoc_scratch_storage[31:0] <= builder_csr_bankarray_csrbank1_scratch0_r;
|
|
end
|
|
main_basesoc_scratch_re <= builder_csr_bankarray_csrbank1_scratch0_re;
|
|
main_basesoc_bus_errors_re <= builder_csr_bankarray_csrbank1_bus_errors_re;
|
|
builder_csr_bankarray_sel_r <= builder_csr_bankarray_sel;
|
|
builder_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0;
|
|
if (builder_csr_bankarray_csrbank2_sel) begin
|
|
case (builder_csr_bankarray_interface2_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_out0_w;
|
|
end
|
|
endcase
|
|
end
|
|
if (builder_csr_bankarray_csrbank2_out0_re) begin
|
|
main_leds_storage[1:0] <= builder_csr_bankarray_csrbank2_out0_r;
|
|
end
|
|
main_leds_re <= builder_csr_bankarray_csrbank2_out0_re;
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0;
|
|
if (builder_csr_bankarray_csrbank3_sel) begin
|
|
case (builder_csr_bankarray_interface3_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_load0_w;
|
|
end
|
|
1'd1: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_reload0_w;
|
|
end
|
|
2'd2: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_en0_w;
|
|
end
|
|
2'd3: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_update_value0_w;
|
|
end
|
|
3'd4: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_value_w;
|
|
end
|
|
3'd5: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_ev_status_w;
|
|
end
|
|
3'd6: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_ev_pending_w;
|
|
end
|
|
3'd7: begin
|
|
builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_ev_enable0_w;
|
|
end
|
|
endcase
|
|
end
|
|
if (builder_csr_bankarray_csrbank3_load0_re) begin
|
|
main_basesoc_timer_load_storage[31:0] <= builder_csr_bankarray_csrbank3_load0_r;
|
|
end
|
|
main_basesoc_timer_load_re <= builder_csr_bankarray_csrbank3_load0_re;
|
|
if (builder_csr_bankarray_csrbank3_reload0_re) begin
|
|
main_basesoc_timer_reload_storage[31:0] <= builder_csr_bankarray_csrbank3_reload0_r;
|
|
end
|
|
main_basesoc_timer_reload_re <= builder_csr_bankarray_csrbank3_reload0_re;
|
|
if (builder_csr_bankarray_csrbank3_en0_re) begin
|
|
main_basesoc_timer_en_storage <= builder_csr_bankarray_csrbank3_en0_r;
|
|
end
|
|
main_basesoc_timer_en_re <= builder_csr_bankarray_csrbank3_en0_re;
|
|
if (builder_csr_bankarray_csrbank3_update_value0_re) begin
|
|
main_basesoc_timer_update_value_storage <= builder_csr_bankarray_csrbank3_update_value0_r;
|
|
end
|
|
main_basesoc_timer_update_value_re <= builder_csr_bankarray_csrbank3_update_value0_re;
|
|
main_basesoc_timer_value_re <= builder_csr_bankarray_csrbank3_value_re;
|
|
main_basesoc_timer_status_re <= builder_csr_bankarray_csrbank3_ev_status_re;
|
|
if (builder_csr_bankarray_csrbank3_ev_pending_re) begin
|
|
main_basesoc_timer_pending_r <= builder_csr_bankarray_csrbank3_ev_pending_r;
|
|
end
|
|
main_basesoc_timer_pending_re <= builder_csr_bankarray_csrbank3_ev_pending_re;
|
|
if (builder_csr_bankarray_csrbank3_ev_enable0_re) begin
|
|
main_basesoc_timer_enable_storage <= builder_csr_bankarray_csrbank3_ev_enable0_r;
|
|
end
|
|
main_basesoc_timer_enable_re <= builder_csr_bankarray_csrbank3_ev_enable0_re;
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0;
|
|
if (builder_csr_bankarray_csrbank4_sel) begin
|
|
case (builder_csr_bankarray_interface4_bank_bus_adr[8:0])
|
|
1'd0: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= main_basesoc_uart_rxtx_w;
|
|
end
|
|
1'd1: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_txfull_w;
|
|
end
|
|
2'd2: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_rxempty_w;
|
|
end
|
|
2'd3: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_status_w;
|
|
end
|
|
3'd4: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_pending_w;
|
|
end
|
|
3'd5: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_enable0_w;
|
|
end
|
|
3'd6: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_txempty_w;
|
|
end
|
|
3'd7: begin
|
|
builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_rxfull_w;
|
|
end
|
|
endcase
|
|
end
|
|
main_basesoc_uart_txfull_re <= builder_csr_bankarray_csrbank4_txfull_re;
|
|
main_basesoc_uart_rxempty_re <= builder_csr_bankarray_csrbank4_rxempty_re;
|
|
main_basesoc_uart_status_re <= builder_csr_bankarray_csrbank4_ev_status_re;
|
|
if (builder_csr_bankarray_csrbank4_ev_pending_re) begin
|
|
main_basesoc_uart_pending_r[1:0] <= builder_csr_bankarray_csrbank4_ev_pending_r;
|
|
end
|
|
main_basesoc_uart_pending_re <= builder_csr_bankarray_csrbank4_ev_pending_re;
|
|
if (builder_csr_bankarray_csrbank4_ev_enable0_re) begin
|
|
main_basesoc_uart_enable_storage[1:0] <= builder_csr_bankarray_csrbank4_ev_enable0_r;
|
|
end
|
|
main_basesoc_uart_enable_re <= builder_csr_bankarray_csrbank4_ev_enable0_re;
|
|
main_basesoc_uart_txempty_re <= builder_csr_bankarray_csrbank4_txempty_re;
|
|
main_basesoc_uart_rxfull_re <= builder_csr_bankarray_csrbank4_rxfull_re;
|
|
if (sys_rst) begin
|
|
main_basesoc_reset_storage <= 2'd0;
|
|
main_basesoc_reset_re <= 1'd0;
|
|
main_basesoc_scratch_storage <= 32'd305419896;
|
|
main_basesoc_scratch_re <= 1'd0;
|
|
main_basesoc_bus_errors_re <= 1'd0;
|
|
main_basesoc_bus_errors <= 32'd0;
|
|
serial_tx <= 1'd1;
|
|
main_basesoc_tx_tick <= 1'd0;
|
|
main_basesoc_rx_tick <= 1'd0;
|
|
main_basesoc_rx_rx_d <= 1'd0;
|
|
main_basesoc_uart_txfull_re <= 1'd0;
|
|
main_basesoc_uart_rxempty_re <= 1'd0;
|
|
main_basesoc_uart_tx_pending <= 1'd0;
|
|
main_basesoc_uart_tx_trigger_d <= 1'd0;
|
|
main_basesoc_uart_rx_pending <= 1'd0;
|
|
main_basesoc_uart_rx_trigger_d <= 1'd0;
|
|
main_basesoc_uart_status_re <= 1'd0;
|
|
main_basesoc_uart_pending_re <= 1'd0;
|
|
main_basesoc_uart_pending_r <= 2'd0;
|
|
main_basesoc_uart_enable_storage <= 2'd0;
|
|
main_basesoc_uart_enable_re <= 1'd0;
|
|
main_basesoc_uart_txempty_re <= 1'd0;
|
|
main_basesoc_uart_rxfull_re <= 1'd0;
|
|
main_basesoc_uart_tx_fifo_readable <= 1'd0;
|
|
main_basesoc_uart_tx_fifo_level0 <= 5'd0;
|
|
main_basesoc_uart_tx_fifo_produce <= 4'd0;
|
|
main_basesoc_uart_tx_fifo_consume <= 4'd0;
|
|
main_basesoc_uart_rx_fifo_readable <= 1'd0;
|
|
main_basesoc_uart_rx_fifo_level0 <= 5'd0;
|
|
main_basesoc_uart_rx_fifo_produce <= 4'd0;
|
|
main_basesoc_uart_rx_fifo_consume <= 4'd0;
|
|
main_basesoc_timer_load_storage <= 32'd0;
|
|
main_basesoc_timer_load_re <= 1'd0;
|
|
main_basesoc_timer_reload_storage <= 32'd0;
|
|
main_basesoc_timer_reload_re <= 1'd0;
|
|
main_basesoc_timer_en_storage <= 1'd0;
|
|
main_basesoc_timer_en_re <= 1'd0;
|
|
main_basesoc_timer_update_value_storage <= 1'd0;
|
|
main_basesoc_timer_update_value_re <= 1'd0;
|
|
main_basesoc_timer_value_status <= 32'd0;
|
|
main_basesoc_timer_value_re <= 1'd0;
|
|
main_basesoc_timer_zero_pending <= 1'd0;
|
|
main_basesoc_timer_zero_trigger_d <= 1'd0;
|
|
main_basesoc_timer_status_re <= 1'd0;
|
|
main_basesoc_timer_pending_re <= 1'd0;
|
|
main_basesoc_timer_pending_r <= 1'd0;
|
|
main_basesoc_timer_enable_storage <= 1'd0;
|
|
main_basesoc_timer_enable_re <= 1'd0;
|
|
main_basesoc_timer_value <= 32'd0;
|
|
main_basesoc_ram_bus_ack <= 1'd0;
|
|
main_basesoc_interface0_ram_bus_ack <= 1'd0;
|
|
main_basesoc_interface1_ram_bus_ack <= 1'd0;
|
|
main_leds_storage <= 2'd0;
|
|
main_leds_re <= 1'd0;
|
|
main_leds_chaser <= 2'd0;
|
|
main_leds_mode <= 1'd0;
|
|
main_leds_count <= 25'd25000000;
|
|
main_buttons_re <= 1'd0;
|
|
builder_grant <= 1'd0;
|
|
builder_slave_sel_r <= 4'd0;
|
|
builder_count <= 20'd1000000;
|
|
builder_csr_bankarray_sel_r <= 1'd0;
|
|
builder_basesoc_rs232phytx_state <= 1'd0;
|
|
builder_basesoc_rs232phyrx_state <= 1'd0;
|
|
builder_basesoc_state <= 1'd0;
|
|
end
|
|
builder_xilinxmultiregimpl0_regs0 <= serial_rx;
|
|
builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0;
|
|
builder_xilinxmultiregimpl1_regs0 <= {user_btn1, user_btn0};
|
|
builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0;
|
|
end
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Specialized Logic
|
|
//------------------------------------------------------------------------------
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Memory mem: 24-words x 8-bit
|
|
//------------------------------------------------------------------------------
|
|
// Port 0 | Read: Sync | Write: ---- |
|
|
reg [7:0] mem[0:23];
|
|
initial begin
|
|
$readmemh("cmod7_mem.init", mem);
|
|
end
|
|
reg [4:0] mem_adr0;
|
|
always @(posedge sys_clk) begin
|
|
mem_adr0 <= builder_csr_bankarray_adr;
|
|
end
|
|
assign builder_csr_bankarray_dat_r = mem[mem_adr0];
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Memory storage: 16-words x 10-bit
|
|
//------------------------------------------------------------------------------
|
|
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
|
|
// Port 1 | Read: Sync | Write: ---- |
|
|
reg [9:0] storage[0:15];
|
|
reg [9:0] storage_dat0;
|
|
reg [9:0] storage_dat1;
|
|
always @(posedge sys_clk) begin
|
|
if (main_basesoc_uart_tx_fifo_wrport_we)
|
|
storage[main_basesoc_uart_tx_fifo_wrport_adr] <= main_basesoc_uart_tx_fifo_wrport_dat_w;
|
|
storage_dat0 <= storage[main_basesoc_uart_tx_fifo_wrport_adr];
|
|
end
|
|
always @(posedge sys_clk) begin
|
|
if (main_basesoc_uart_tx_fifo_rdport_re)
|
|
storage_dat1 <= storage[main_basesoc_uart_tx_fifo_rdport_adr];
|
|
end
|
|
assign main_basesoc_uart_tx_fifo_wrport_dat_r = storage_dat0;
|
|
assign main_basesoc_uart_tx_fifo_rdport_dat_r = storage_dat1;
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Memory storage_1: 16-words x 10-bit
|
|
//------------------------------------------------------------------------------
|
|
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
|
|
// Port 1 | Read: Sync | Write: ---- |
|
|
reg [9:0] storage_1[0:15];
|
|
reg [9:0] storage_1_dat0;
|
|
reg [9:0] storage_1_dat1;
|
|
always @(posedge sys_clk) begin
|
|
if (main_basesoc_uart_rx_fifo_wrport_we)
|
|
storage_1[main_basesoc_uart_rx_fifo_wrport_adr] <= main_basesoc_uart_rx_fifo_wrport_dat_w;
|
|
storage_1_dat0 <= storage_1[main_basesoc_uart_rx_fifo_wrport_adr];
|
|
end
|
|
always @(posedge sys_clk) begin
|
|
if (main_basesoc_uart_rx_fifo_rdport_re)
|
|
storage_1_dat1 <= storage_1[main_basesoc_uart_rx_fifo_rdport_adr];
|
|
end
|
|
assign main_basesoc_uart_rx_fifo_wrport_dat_r = storage_1_dat0;
|
|
assign main_basesoc_uart_rx_fifo_rdport_dat_r = storage_1_dat1;
|
|
|
|
|
|
BUFG BUFG(
|
|
.I(main_crg_clkout0),
|
|
.O(main_crg_clkout_buf0)
|
|
);
|
|
|
|
BUFG BUFG_1(
|
|
.I(main_crg_clkout1),
|
|
.O(main_crg_clkout_buf1)
|
|
);
|
|
|
|
BUFG BUFG_2(
|
|
.I(main_crg_clkout2),
|
|
.O(main_crg_clkout_buf2)
|
|
);
|
|
|
|
IDELAYCTRL IDELAYCTRL(
|
|
.REFCLK(idelay_clk),
|
|
.RST(main_crg_ic_reset)
|
|
);
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Memory rom: 16384-words x 32-bit
|
|
//------------------------------------------------------------------------------
|
|
// Port 0 | Read: Sync | Write: ---- |
|
|
reg [31:0] rom[0:16383];
|
|
initial begin
|
|
$readmemh("cmod7_rom.init", rom);
|
|
end
|
|
reg [31:0] rom_dat0;
|
|
always @(posedge sys_clk) begin
|
|
rom_dat0 <= rom[main_basesoc_adr];
|
|
end
|
|
assign main_basesoc_dat_r = rom_dat0;
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Memory sram: 16384-words x 32-bit
|
|
//------------------------------------------------------------------------------
|
|
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
|
|
reg [31:0] sram[0:16383];
|
|
initial begin
|
|
$readmemh("cmod7_sram.init", sram);
|
|
end
|
|
reg [13:0] sram_adr0;
|
|
always @(posedge sys_clk) begin
|
|
if (main_basesoc_sram0_we[0])
|
|
sram[main_basesoc_sram0_adr][7:0] <= main_basesoc_sram0_dat_w[7:0];
|
|
if (main_basesoc_sram0_we[1])
|
|
sram[main_basesoc_sram0_adr][15:8] <= main_basesoc_sram0_dat_w[15:8];
|
|
if (main_basesoc_sram0_we[2])
|
|
sram[main_basesoc_sram0_adr][23:16] <= main_basesoc_sram0_dat_w[23:16];
|
|
if (main_basesoc_sram0_we[3])
|
|
sram[main_basesoc_sram0_adr][31:24] <= main_basesoc_sram0_dat_w[31:24];
|
|
sram_adr0 <= main_basesoc_sram0_adr;
|
|
end
|
|
assign main_basesoc_sram0_dat_r = sram[sram_adr0];
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Memory main_ram: 4194304-words x 32-bit
|
|
//------------------------------------------------------------------------------
|
|
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
|
|
reg [31:0] main_ram[0:4194303];
|
|
initial begin
|
|
$readmemh("cmod7_main_ram.init", main_ram);
|
|
end
|
|
reg [21:0] main_ram_adr0;
|
|
always @(posedge sys_clk) begin
|
|
if (main_basesoc_sram1_we[0])
|
|
main_ram[main_basesoc_sram1_adr][7:0] <= main_basesoc_sram1_dat_w[7:0];
|
|
if (main_basesoc_sram1_we[1])
|
|
main_ram[main_basesoc_sram1_adr][15:8] <= main_basesoc_sram1_dat_w[15:8];
|
|
if (main_basesoc_sram1_we[2])
|
|
main_ram[main_basesoc_sram1_adr][23:16] <= main_basesoc_sram1_dat_w[23:16];
|
|
if (main_basesoc_sram1_we[3])
|
|
main_ram[main_basesoc_sram1_adr][31:24] <= main_basesoc_sram1_dat_w[31:24];
|
|
main_ram_adr0 <= main_basesoc_sram1_adr;
|
|
end
|
|
assign main_basesoc_sram1_dat_r = main_ram[main_ram_adr0];
|
|
|
|
|
|
A2P_WB A2P_WB(
|
|
.clk(sys_clk),
|
|
.dBusWB_ACK(main_basesoc_dbus_ack),
|
|
.dBusWB_DAT_MISO(main_basesoc_dbus_dat_r),
|
|
.dBusWB_ERR(main_basesoc_dbus_err),
|
|
.externalInterrupt(main_basesoc_interrupt[0]),
|
|
.externalInterruptS(main_basesoc_interruptS),
|
|
.externalResetVector(main_basesoc_a2p),
|
|
.iBusWB_ACK(main_basesoc_ibus_ack),
|
|
.iBusWB_DAT_MISO(main_basesoc_ibus_dat_r),
|
|
.iBusWB_ERR(main_basesoc_ibus_err),
|
|
.reset((sys_rst | main_basesoc_reset)),
|
|
.softwareInterrupt(1'd0),
|
|
.timerInterrupt(1'd0),
|
|
.dBusWB_ADR(main_basesoc_dbus_adr),
|
|
.dBusWB_BTE(main_basesoc_dbus_bte),
|
|
.dBusWB_CTI(main_basesoc_dbus_cti),
|
|
.dBusWB_CYC(main_basesoc_dbus_cyc),
|
|
.dBusWB_DAT_MOSI(main_basesoc_dbus_dat_w),
|
|
.dBusWB_SEL(main_basesoc_dbus_sel),
|
|
.dBusWB_STB(main_basesoc_dbus_stb),
|
|
.dBusWB_WE(main_basesoc_dbus_we),
|
|
.iBusWB_ADR(main_basesoc_ibus_adr),
|
|
.iBusWB_BTE(main_basesoc_ibus_bte),
|
|
.iBusWB_CTI(main_basesoc_ibus_cti),
|
|
.iBusWB_CYC(main_basesoc_ibus_cyc),
|
|
.iBusWB_DAT_MOSI(main_basesoc_ibus_dat_w),
|
|
.iBusWB_SEL(main_basesoc_ibus_sel),
|
|
.iBusWB_STB(main_basesoc_ibus_stb),
|
|
.iBusWB_WE(main_basesoc_ibus_we)
|
|
);
|
|
|
|
FDCE FDCE(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(main_crg_reset),
|
|
.Q(builder_basesoc_reset0)
|
|
);
|
|
|
|
FDCE FDCE_1(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset0),
|
|
.Q(builder_basesoc_reset1)
|
|
);
|
|
|
|
FDCE FDCE_2(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset1),
|
|
.Q(builder_basesoc_reset2)
|
|
);
|
|
|
|
FDCE FDCE_3(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset2),
|
|
.Q(builder_basesoc_reset3)
|
|
);
|
|
|
|
FDCE FDCE_4(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset3),
|
|
.Q(builder_basesoc_reset4)
|
|
);
|
|
|
|
FDCE FDCE_5(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset4),
|
|
.Q(builder_basesoc_reset5)
|
|
);
|
|
|
|
FDCE FDCE_6(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset5),
|
|
.Q(builder_basesoc_reset6)
|
|
);
|
|
|
|
FDCE FDCE_7(
|
|
.C(main_crg_clkin),
|
|
.CE(1'd1),
|
|
.CLR(1'd0),
|
|
.D(builder_basesoc_reset6),
|
|
.Q(builder_basesoc_reset7)
|
|
);
|
|
|
|
MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"),
|
|
.CLKFBOUT_MULT_F(6'd50),
|
|
.CLKIN1_PERIOD(83.33333333333333),
|
|
.CLKOUT0_DIVIDE_F(3'd6),
|
|
.CLKOUT0_PHASE(1'd0),
|
|
.CLKOUT1_DIVIDE(2'd3),
|
|
.CLKOUT1_PHASE(1'd0),
|
|
.CLKOUT2_DIVIDE(2'd3),
|
|
.CLKOUT2_PHASE(1'd0),
|
|
.DIVCLK_DIVIDE(1'd1),
|
|
.REF_JITTER1(0.01)
|
|
) MMCME2_ADV (
|
|
.CLKFBIN(builder_basesoc_mmcm_fb),
|
|
.CLKIN1(main_crg_clkin),
|
|
.PWRDWN(main_crg_power_down),
|
|
.RST(builder_basesoc_reset7),
|
|
.CLKFBOUT(builder_basesoc_mmcm_fb),
|
|
.CLKOUT0(main_crg_clkout0),
|
|
.CLKOUT1(main_crg_clkout1),
|
|
.CLKOUT2(main_crg_clkout2),
|
|
.LOCKED(main_crg_locked)
|
|
);
|
|
|
|
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE (
|
|
.C(sys_clk),
|
|
.CE(1'd1),
|
|
.D(1'd0),
|
|
.PRE(builder_xilinxasyncresetsynchronizerimpl0),
|
|
.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
|
|
);
|
|
|
|
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_1 (
|
|
.C(sys_clk),
|
|
.CE(1'd1),
|
|
.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
|
|
.PRE(builder_xilinxasyncresetsynchronizerimpl0),
|
|
.Q(sys_rst)
|
|
);
|
|
|
|
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_2 (
|
|
.C(sys2x_clk),
|
|
.CE(1'd1),
|
|
.D(1'd0),
|
|
.PRE(builder_xilinxasyncresetsynchronizerimpl1),
|
|
.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
|
|
);
|
|
|
|
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_3 (
|
|
.C(sys2x_clk),
|
|
.CE(1'd1),
|
|
.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
|
|
.PRE(builder_xilinxasyncresetsynchronizerimpl1),
|
|
.Q(builder_xilinxasyncresetsynchronizerimpl1_expr)
|
|
);
|
|
|
|
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_4 (
|
|
.C(idelay_clk),
|
|
.CE(1'd1),
|
|
.D(1'd0),
|
|
.PRE(builder_xilinxasyncresetsynchronizerimpl2),
|
|
.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
|
|
);
|
|
|
|
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
|
|
.INIT(1'd1)
|
|
) FDPE_5 (
|
|
.C(idelay_clk),
|
|
.CE(1'd1),
|
|
.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
|
|
.PRE(builder_xilinxasyncresetsynchronizerimpl2),
|
|
.Q(idelay_rst)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Auto-Generated by LiteX on 2022-08-23 17:08:47.
|
|
//------------------------------------------------------------------------------
|