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455 lines
14 KiB
C++
455 lines
14 KiB
C++
// simple verilator top
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// litex soc w/a2p
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#ifndef NO_TRACE
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#define TRACING
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#endif
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// old public access method
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//#define OLD_PUBLIC
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#include <cstddef>
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#include <unordered_map>
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#include "verilated.h"
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#include "Vsoc.h"
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#ifndef OLD_PUBLIC
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// internal nets
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#include "Vsoc___024root.h"
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#endif
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#include "Vsoc_soc.h"
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#include "Vsoc_A2P_WB.h"
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#ifdef TRACING
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#include "verilated_vcd_c.h"
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VerilatedVcdC *t;
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#else
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unsigned int t = 0;
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#endif
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// using https://github.com/ZipCPU/wbuart32 sim driver
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// how does cpp get compiled in without this? can verilator be told to add more cpp? see a2p!
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// UART=port
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// 0xA20 = 2592
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// A2P = 2593
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#ifdef UART
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#include "wbuart32/bench/cpp/uartsim.h"
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#include "wbuart32/bench/cpp/uartsim.cpp"
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#endif
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Vsoc* m;
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#ifdef OLD_PUBLIC
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Vsoc* root;
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#else
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Vsoc___024root* root;
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#endif
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vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override
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double sc_time_stamp() { // $time in verilog
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return main_time;
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}
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const char* tbName = "tb_litex_soc";
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const int resetCycle = 10;
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const int threadRunCycle = resetCycle + 5;
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const int runCycles = 1000000000;
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const int hbCycles = 500;
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const int quiesceCycles = 50;
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const int threads = 1;
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const std::string testFile = "";
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const unsigned int bootAdr = 0x00000000;
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const bool failMaxCycles = true;
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const unsigned int stopOnHang = 500;
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const unsigned int stopOnLoop = 20;
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const unsigned long iarPass = 0x7F0;
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const unsigned long iarFail = 0x7F4;
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const bool debugWB = true;
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const bool debugWBReq = false;
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// Cythonize this and use it for cocotb too...
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class Memory {
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std::unordered_map<unsigned int, unsigned int> mem;
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public:
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bool le;
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bool logStores;
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int defaultVal;
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Memory();
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void loadFile(std::string filename, unsigned int adr=0, bool le=false, std::string format="ascii");
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int read(unsigned int adr);
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void write(unsigned int adr, unsigned int dat);
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void write(unsigned int adr, unsigned int be, unsigned int dat);
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};
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Memory::Memory() {
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this->defaultVal = 0;
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this->le = false;
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this->logStores = true;
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}
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void Memory::loadFile(std::string filename, unsigned int adr, bool le, std::string format) {
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unsigned int dat;
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std::ifstream f;
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f.open(filename, std::fstream::in);
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// "ascii"
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//while (f.peek()!=EOF) {
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//f >> std::hex >> dat;
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// f >> dat;
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while (f >> std::hex >> dat) {
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this->write(adr, dat);
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adr += 4;
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}
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}
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// adr is word-aligned byte address
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int Memory::read(unsigned int adr) {
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if (this->mem.find(adr) != this->mem.end()) {
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return this->mem[adr];
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} else {
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return this->defaultVal;
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}
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}
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// adr is word-aligned byte address
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void Memory::write(unsigned int adr, unsigned int dat) {
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unsigned int startDat = this->read(adr);
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this->write(adr, 0xF, dat);
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}
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void Memory::write(unsigned int adr, unsigned int be, unsigned int dat) {
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if (be == 0) return;
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int mask = 0, startDat;
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if (be >= 8) {
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be = be - 8;
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mask = 0xFF000000;
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} else {
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mask = 0;
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}
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if (be >= 4) {
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be = be - 4;
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mask |= 0x00FF0000;
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}
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if (be >= 2) {
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be = be - 2;
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mask |= 0x0000FF00;
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}
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if (be = 1) {
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mask |= 0x000000FF;
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}
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startDat = this->read(adr);
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this->mem[adr] = (startDat & ~mask) | (dat & mask);
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if (this->logStores) {
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std::cout << " * Mem Update @" << std::setw(8) << std::setfill('0') << std::uppercase << std::hex << adr <<
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" " <<std::setw(8) << std::setfill('0') << std::uppercase << std::hex << startDat <<
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"->" <<std::setw(8) << std::setfill('0') << std::uppercase << std::hex << this->read(adr) << std::endl;
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}
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}
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Memory mem;
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int main(int argc, char **argv) {
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using namespace std;
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cout << setfill('0');
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Verilated::commandArgs(argc, argv);
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m = new Vsoc;
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#ifdef OLD_PUBLIC
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root = m;
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#else
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root = m->rootp;
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#endif
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#ifdef TRACING
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Verilated::traceEverOn(true);
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t = new VerilatedVcdC;
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m->trace(t, 99);
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t->open("a2plitex.vcd");
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cout << "Tracing enabled." << endl;
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#endif
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unsigned int i, v;
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bool ok = true;
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bool done = false;
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bool resetDone = false;
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bool booted = false;
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unsigned int quiesceCount = 0;
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unsigned int threadStop = 0x3;
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unsigned int tick = 0;
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unsigned int cycle = 1;
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unsigned int readPending = 0;
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unsigned int readAddr = 0;
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unsigned int readTag = 0;
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unsigned int readTID = 0;
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unsigned int countReads = 0;
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unsigned int lastCompCycle = 0;
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unsigned int lastCompSame = 0;
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unsigned int lastCompIAR = 0x0000001;
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unsigned int gpr[32];
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bool wbRdPending = false, wbWrPending = false;
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// memory setup
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//mem.write(0xFFFFFFFC, 0x48000002);
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//mem.loadFile(testFile);
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// uart setup
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/*
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// i_setup[30] True if we are not using hardware flow control. This bit
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// is ignored within this module, as any receive hardware flow
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// control will need to be implemented elsewhere.
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//
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// for a six bit word, or 2'b11 for a five bit word.
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//
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// Set this to one to expect two stop bits, zero for one.
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//
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// i_setup[26] Indicates whether or not a parity bit exists. Set this
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// to 1'b1 to include parity.
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//
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// i_setup[25] Indicates whether or not the parity bit is fixed. Set
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// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
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// parity to be set based upon data. (Both assume the parity
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// enable value is set.)
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//
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// i_setup[24] This bit is ignored if parity is not used. Otherwise,
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// in the case of a fixed parity bit, this bit indicates whether
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// mark (1'b1) or space (1'b0) parity is used. Likewise if the
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// parity is not fixed, a 1'b1 selects even parity, and 1'b0
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// selects odd.
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//
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// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
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// So, for example, if you have a 200 MHz clock and wish to
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// run your UART at 9600 baud, you would take 200 MHz and divide
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// by 9600 to set this value to 24'd20834. Likewise if you wished
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// to run this serial port at 115200 baud from a 200 MHz clock,
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// you would set the value to 24'd1736
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*/
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/*
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m_baud_counts = (isetup & 0x0ffffff);
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m_nbits = 8-((isetup >> 28)&0x03);
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m_nstop =((isetup >> 27)&1)+1;
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m_nparity = (isetup >> 26)&1;
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m_fixdp = (isetup >> 25)&1;
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m_evenp = (isetup >> 24)&1;
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*/
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// 100MHz, 115200 = 868
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#ifdef UART
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UARTSIM *uart;
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int uartPort = UART; // 0-stdin/stdout
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//unsigned uartConfig = 1736;
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unsigned uartConfig = 868;
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//unsigned uartConfig = 434;
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//unsigned uartConfig = 217;
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//unsigned uartConfig = 217;
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cout << "Initializing UART on port " << uartPort << " with config=" << hex << setw(8) << setfill('0') << uartConfig << endl;
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uart = new UARTSIM(uartPort);
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uart->setup(uartConfig);
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cout << "litex_term socket://localhost:" << uartPort << " in a console, then hit enter here...." << endl;
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cin.get();
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#endif
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// do something
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for (i = 0; i < 32; i++) {
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gpr[i] = 0;
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}
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//just use hardware reset
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//root->soc->main_basesoc_soc_rst = 1;
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//cout << dec << setw(8) << cycle << " Resetting..." << endl;
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const int clocks[2] = {0x1, 0x0}; // 1x
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const int ticks1x = 2;
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while (!Verilated::gotFinish() && (ok | quiesceCount > 0) && cycle <= runCycles && !done) {
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if (!resetDone && (cycle > resetCycle)) {
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//root->soc->main_basesoc_soc_rst = 0;
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//cout << dec << setw(8) << cycle << " Releasing reset." << endl;
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resetDone = true;
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}
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if (threadStop && (cycle > threadRunCycle)) {
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//threadStop = 0x0;
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//m->an_ac_pm_thread_stop = threadStop;
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//cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl;
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}
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m->clk12 = clocks[tick % ticks1x];
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m->eval();
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// 1x clock
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if ((tick % ticks1x) == 0) {
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// core
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// completion
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if (root->soc->A2P_WB->lastStageIsFiring) {
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v = root->soc->A2P_WB->lastStagePc;
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " C0: CP";
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cout << " 0:" << setw(6) << setfill('0') << hex << v;
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cout << " [" << setw(6) << setfill('0') << hex << root->soc->A2P_WB->lastStageInstruction << "]" << endl;
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if (quiesceCount > 0) {
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/* skip remaining checks */
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} else if (v == iarPass) {
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cout << "*** Passing IAR detected ***" << endl;
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quiesceCount = 5;
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} else if (v == iarFail) {
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cout << "*** Failing IAR detected ***" << endl;
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ok = false;
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quiesceCount = 5;
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} else if (v == lastCompIAR) {
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lastCompSame++;
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if (stopOnLoop && (lastCompSame == stopOnLoop)) {
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ok = false;
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cout << "*** Loop detected for " << dec << stopOnLoop << " iterations ***" << endl;
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}
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} else {
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lastCompIAR = v;
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lastCompSame = 0;
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}
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}
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// gpr change - really need to use these (to detect write w/same data)
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//reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
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//reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
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//wire UpdateRegFileWrite_valid /* verilator public */ ;
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//wire UpdateRegFileWrite_payload_valid /* verilator public */ ;
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//wire [4:0] UpdateRegFileWrite_payload_address /* verilator public */ ;
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//wire [31:0] UpdateRegFileWrite_payload_data /* verilator public */ ;
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for (i = 0; i < 32; i++) {
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v = root->soc->A2P_WB->RegFilePlugin_regFile[i];
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if (v != gpr[i]) {
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gpr[i] = v;
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cout << dec << setw(8) << setfill('0') << cycle << " C0: GPR Update: R";
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cout << dec << setw(2) << setfill('0') << i << "=";
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cout << hex << setw(8) << setfill('0') << uppercase << v << " ";
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cout << endl;
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}
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}
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// completion
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// wb - soc can monitor-only
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if (wbRdPending) {
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if (root->soc->A2P_WB->dBusWB_ACK)
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if (debugWB)
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
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" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MISO << endl;
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wbRdPending = false;
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} else if (wbWrPending) {
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if (root->soc->A2P_WB->dBusWB_ACK)
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if (debugWB)
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
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" SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)root->soc->A2P_WB->dBusWB_SEL <<
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" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl;
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wbWrPending = false;
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} else if (root->soc->A2P_WB->dBusWB_CYC && root->soc->A2P_WB->dBusWB_STB) {
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if (!root->soc->A2P_WB->dBusWB_WE) {
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if (root->soc->A2P_WB->dBusWB_ACK) {
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if (debugWB)
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
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" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MISO << endl;
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} else if (!wbRdPending && debugWBReq) {
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << endl;
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wbRdPending = true;
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}
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} else {
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if (debugWB) {
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
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" SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)root->soc->A2P_WB->dBusWB_SEL <<
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" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl;
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} else if (!wbWrPending && debugWBReq) {
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
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" SEL=" << root->soc->A2P_WB->dBusWB_SEL << " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl;
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wbWrPending = true;
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}
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}
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}
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// leds, btns, mem, etc.
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} else {
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if (resetDone) {
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#ifdef UART
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m->serial_rx = (*uart)(m->serial_tx);
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#endif
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}
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}
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m->eval(); // NEED THIS!!!!
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// finish clock stuff
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if ((tick % ticks1x) == 0) {
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cycle++;
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if ((cycle % hbCycles) == 0) {
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cout << dec << setw(8) << setfill('0') << cycle << " ...tick..." << endl;
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}
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if (failMaxCycles && (cycle == runCycles)) {
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cout << "*** Max cycles reached ***" << endl;
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ok = false;
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}
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}
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tick++;
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#ifdef TRACING
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t->dump(tick);
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t->flush();
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#endif
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// check for fails
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if (!ok && quiesceCount == 0) {
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quiesceCount = quiesceCycles;
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cout << "Quiescing..." << endl;
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} else if (quiesceCount > 0) {
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quiesceCount--;
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if (ok && quiesceCount == 0) {
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done = true;
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}
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}
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}
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#ifdef TRACING
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t->close();
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#endif
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m->final();
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cout << endl << endl << tbName << endl;
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cout << endl << "Cycles run=" << dec << cycle << endl << endl;
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if (!ok) {
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cout << "You are worthless and weak." << endl;
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exit(EXIT_FAILURE);
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} else {
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cout << "You has opulence." << endl;
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exit(EXIT_SUCCESS);
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}
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} |