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128 lines
4.1 KiB
Tcl
128 lines
4.1 KiB
Tcl
if {![info exists standalone] || $standalone} {
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# Read lef
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read_lef $::env(TECH_LEF)
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read_lef $::env(SC_LEF)
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if {[info exist ::env(ADDITIONAL_LEFS)]} {
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foreach lef $::env(ADDITIONAL_LEFS) {
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read_lef $lef
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}
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}
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# Read liberty files
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foreach libFile $::env(LIB_FILES) {
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read_liberty $libFile
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}
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# Read verilog
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read_verilog $::env(RESULTS_DIR)/1_synth.v
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link_design $::env(DESIGN_NAME)
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read_sdc $::env(RESULTS_DIR)/1_synth.sdc
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if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
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source $::env(PLATFORM_DIR)/derate.tcl
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}
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set num_instances [llength [get_cells -hier *]]
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puts "number instances in verilog is $num_instances"
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} else {
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puts "Starting floorplan"
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}
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# Initialize floorplan using ICeWall FOOTPRINT
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# ----------------------------------------------------------------------------
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if {[info exists ::env(FOOTPRINT)]} {
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ICeWall load_footprint $env(FOOTPRINT)
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initialize_floorplan \
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-die_area [ICeWall get_die_area] \
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-core_area [ICeWall get_core_area] \
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-site $::env(PLACE_SITE)
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ICeWall init_footprint $env(SIG_MAP_FILE)
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# Initialize floorplan using CORE_UTILIZATION
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# ----------------------------------------------------------------------------
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} elseif {[info exists ::env(CORE_UTILIZATION)] && $::env(CORE_UTILIZATION) != "" } {
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initialize_floorplan -utilization $::env(CORE_UTILIZATION) \
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-aspect_ratio $::env(CORE_ASPECT_RATIO) \
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-core_space $::env(CORE_MARGIN) \
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-site $::env(PLACE_SITE)
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# Initialize floorplan using DIE_AREA/CORE_AREA
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# ----------------------------------------------------------------------------
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} elseif {[info exists ::env(CORE_AREA)]} {
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initialize_floorplan -die_area $::env(DIE_AREA) \
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-core_area $::env(CORE_AREA) \
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-site $::env(PLACE_SITE)
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# Initialize floorplan using DIE_AREA wtf-doesnt work; requires core_area parm
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# ----------------------------------------------------------------------------
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} else {
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initialize_floorplan -die_area $::env(DIE_AREA) \
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-site $::env(PLACE_SITE)
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}
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if { [info exists ::env(MAKE_TRACKS)] } {
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source $::env(MAKE_TRACKS)
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} else {
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source $::env(PLATFORM_DIR)/make_tracks.tcl
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}
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# If wrappers defined replace macros with their wrapped version
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# # ----------------------------------------------------------------------------
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if {[info exists ::env(MACRO_WRAPPERS)]} {
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source $::env(MACRO_WRAPPERS)
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set wrapped_macros [dict keys [dict get $wrapper around]]
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set db [ord::get_db]
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set block [ord::get_db_block]
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foreach inst [$block getInsts] {
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if {[lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1} {
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set new_master [dict get $wrapper around [[$inst getMaster] getName]]
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puts "Replacing [[$inst getMaster] getName] with $new_master for [$inst getName]"
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$inst swapMaster [$db findMaster $new_master]
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}
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}
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}
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#puts "wtf"
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#parray ::env
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# pre report
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puts "\n=========================================================================="
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puts "report_checks"
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puts "--------------------------------------------------------------------------"
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report_checks -digits 3 -fields {fo input slew capacitance} -format full_clock_expanded
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report_clock_properties
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puts "\n=========================================================================="
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puts "report_tns"
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puts "--------------------------------------------------------------------------"
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report_tns -digits 3
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puts "\n=========================================================================="
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puts "report_wns"
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puts "--------------------------------------------------------------------------"
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report_wns
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report_worst_slack -digits 3
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puts "\n=========================================================================="
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puts "report_design_area"
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puts "--------------------------------------------------------------------------"
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report_design_area
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# remove buffers inserted by yosys/abc
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#wtf remove_buffers
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if {![info exists standalone] || $standalone} {
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# write output
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write_def $::env(RESULTS_DIR)/2_1_floorplan.def
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write_verilog $::env(RESULTS_DIR)/2_floorplan.v
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write_sdc $::env(RESULTS_DIR)/2_floorplan.sdc
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exit
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}
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