From 92888a53646435933dd08af72a47afac2a7f4ba0 Mon Sep 17 00:00:00 2001 From: wtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Thu, 11 Nov 2021 09:08:04 -0600 Subject: [PATCH] add uart test --- build/litex/litex-1099/a2p_cmod7_uarts.py | 316 ++ build/litex/litex-1099/master/cmod7.v | 2733 +++++++++++++++++ build/litex/litex-1099/master/csr.csv | 63 + build/litex/litex-1099/master/make-uarts.txt | 1771 +++++++++++ build/litex/litex-1099/no_master/cmod7.v | 2684 ++++++++++++++++ build/litex/litex-1099/no_master/csr.csv | 63 + .../litex/litex-1099/no_master/make-uarts.txt | 1763 +++++++++++ 7 files changed, 9393 insertions(+) create mode 100755 build/litex/litex-1099/a2p_cmod7_uarts.py create mode 100644 build/litex/litex-1099/master/cmod7.v create mode 100644 build/litex/litex-1099/master/csr.csv create mode 100644 build/litex/litex-1099/master/make-uarts.txt create mode 100644 build/litex/litex-1099/no_master/cmod7.v create mode 100644 build/litex/litex-1099/no_master/csr.csv create mode 100644 build/litex/litex-1099/no_master/make-uarts.txt diff --git a/build/litex/litex-1099/a2p_cmod7_uarts.py b/build/litex/litex-1099/a2p_cmod7_uarts.py new file mode 100755 index 0000000..9c10e3a --- /dev/null +++ b/build/litex/litex-1099/a2p_cmod7_uarts.py @@ -0,0 +1,316 @@ +#!/usr/bin/env python3 + +# A2P Test +# python3 a2p_cmod7_uarts.py --csr-csv csr.csv --no-compile-software --build +# + +import os +import argparse + +from migen import * + +# local platform +from platforms import cmod7 + +# local core +import sys +binPath = os.path.dirname(os.path.realpath(__file__)) +sys.path.append(os.path.join(binPath, 'a2p')) +from a2p import A2P +from litex.soc.cores import cpu +cpu.CPUS['a2p'] = A2P # add to litex dict + +# local modules +sys.path.append(os.path.join(binPath, 'modules')) + +from litex.soc.cores.clock import * +from litex.soc.integration.soc import colorer +from litex.soc.integration.soc import SoCRegion +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * + +from litex.soc.cores.led import LedChaser +from litex.soc.cores import dna, xadc +from litex.soc.cores.gpio import GPIOIn +from litex.soc.cores.gpio import GPIOOut +from litex.soc.cores.bitbang import I2CMaster + +from litex.soc.interconnect import wishbone + +from litex.soc.cores import uart +from litex.soc.cores.uart import UART +from litex.soc.cores.uart import UARTPHY +from litex.soc.cores.uart import UARTBone +from litex.soc.cores.uart import UARTWishboneBridge +from litex.soc.cores.uart import UARTCrossover +from litescope import LiteScopeAnalyzer + +from litex.soc.interconnect.csr import * + + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) + self.clock_domains.cd_idelay = ClockDomain() + + self.submodules.pll = pll = S7MMCM(speedgrade=-1) + #wtf no idea how to modify the reset signal later (add btn0) + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(platform.request("clk12"), 12e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_idelay, 200e6) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + +class CSRDirectory(GenericBank, AutoCSR): + def __init__(self, description='CSR Directory', busword=32, ordering='big'): + AutoCSR.__init__(self) + GenericBank.__init__(self, description, busword, ordering) + + +# BaseSoC ------------------------------------------------------------------------------------------ + +from litex.soc.interconnect import wishbone + +def _to_signal(obj): + return obj.raw_bits() if isinstance(obj, Record) else obj + +class BaseSoC(SoCCore): + + def __init__(self, sys_clk_freq=int(50e6), + with_analyzer=False, + uart_baudrate=115200, + **kwargs): + + platform = cmod7.Platform() + + SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32, + #with_uart=True, uart_name='crossover+bridge', integrated_sram_size=0, integrated_rom_size=0, + with_uart=True, integrated_sram_size=0, integrated_rom_size=0, + ident="A2P", ident_version=True, uart_baudrate=uart_baudrate, + cpu_type='a2p') + + #wtf no irq yet + self.add_constant("UART_POLLING") + + # rom, sram are referenced by code linker so names must match!!! + self.mem_map = { + "csr": 0xFFF00000, + "sram": 0x00100000, + "rom": 0x00000000 + } + + self.csr_map = { + 'directory': 6, + 'uart' : 5, + 'ctrl' : 0xFFF02000 + } + + # CRG --------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # CSR Directory ----------------------------------------------------------------------------- + + # goes to csr(0) but dont see reset, and all the csr arent given addresses + # by the time this is done + # also not showing in final csr's + csrDirectory = CSRDirectory([ + # should be this probably, but 'CSRConstant' object has no attribute 'finalize' + #CSRConstant(name='directory', value=0x08675309) + CSRStorage(name='directory', reset=0x08675309), + CSRStorage(name='csr_0800'), + #CSRStorage(name='csr_1000'), + #CSRStorage(name='csr_1800'), + # ... + ], 32, 'big') + self.submodules.directory = csrDirectory + self.add_csr('directory') + + # so can the reset values be set at the end, OR can all but loc 0 be added at the end?? + for c in csrDirectory.simple_csrs: + print(c.name) + + # UART w/crossover -------------------------------------------------------------------------- + # uart_name="crossover+bridge"??? didn't help + # lxserver --uart --uart-port /dev/ttyUSB1 connects + # then litex_cli --regs fails with timeout + # cd build; litex_cli --regs fails with no bases attritute + #self.submodules.uart_xover = UARTCrossover() + + # ON-BOARD MEM ------------------------------------------------------------------------------ + + rom_size = 0x10000 + with open('rom.init', 'r') as file: + hexdata = file.read().replace('\n', '') + + outFile = open('mem_1.init', 'w') # write data immediately so available even if not building (sim) + bytedata = [] + for i in range(0, len(hexdata), 8): + data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE + bytedata.append(data) + outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n') + romdata = bytedata + outFile.close() + if len(romdata)*4 > rom_size: + self.logger.info('ROM {} {} {}.'.format( + colorer('Read', color='red'), + colorer(len(romdata)*4, color='red'), + colorer('bytes for preload. Too big!', color='red'))) + quit(-100) + else: + self.logger.info('ROM {} {} {}.'.format( + colorer('Read', color='bright'), + colorer(len(romdata)*4, color='cyan'), + colorer('bytes for preload. Wrote mem_1.init.', color='bright'))) + + self.add_rom("rom", origin=self.mem_map["rom"], size=rom_size, contents=romdata) + + # Internal SRAM (64K) ----------------------------------------------------------------------- + #self.add_ram("sram", origin=self.mem_map["sram"], size=0x10000) + + # External SRAM (512K) ----------------------------------------------------------------------- + + from issiram import ISSIRam + platform.add_source("./modules/issiram.v") + + sram_bus = wishbone.Interface() + pins = platform.request('issiram') + mem = { + 'ce': pins.cen, + 'oe': pins.oen, + 'we': pins.wen, + 'adr': pins.addr, + 'dat': pins.data + } + sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, mem) + self.submodules.sram = sram + self.bus.add_slave('sram', sram_bus, + SoCRegion(origin=self.mem_map['sram'], size=sram.size)) + self.logger.info("SRAM {} {} {}.".format( + colorer('sram'), + colorer("added", color="green"), + self.bus.regions['sram'])) + + # FPGA identification ------------------------------------------------------------------------ + self.submodules.dna = dna.DNA() + self.add_csr("dna") + + # FPGA temperature/voltage ------------------------------------------------------------------- + self.submodules.xadc = xadc.XADC() + self.add_csr("xadc") + + # Leds --------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq + ) + self.add_csr("leds") + + # Buttons ------------------------------------------------------------------------------------ + self.submodules.buttons = GPIOIn( + pads = platform.request_all("user_btn") + ) + self.add_csr("buttons") + + # GPIO I2C ----------------------------------------------------------------------------------- + i2c_0 = Record([("scl", 1), ("sda", 1)]) + i2c_0.scl = platform.request('pmod', 0) # P1 + i2c_0.sda = platform.request('pmod', 1) # P2 + #wtf needs to be 'i2c' for bios for now + self.submodules.i2c = I2CMaster(i2c_0) + self.add_csr('i2c') + + # GPIO UARTs --------------------------------------------------------------------------------- + pins = Record([("tx", 1), ("rx", 1)]) + pins.tx = platform.request('digital', 10) + pins.rx = platform.request('digital', 11) + #self.submodules.uart_1 = UARTWishboneBridge(pins, sys_clk_freq, baudrate=115200) + #self.add_wb_master(self.uart_1.wishbone) + + #self.submodules.uart_1 = UART(UARTPHY(pins, sys_clk_freq, 115200)) + #self.submodules.uart_1 = UARTBone(UARTPHY(pins, sys_clk_freq, 115200), sys_clk_freq) + #self.add_csr('uart_1') + + self.submodules.uart_1_phy = UARTPHY(pins, sys_clk_freq, 115200) + self.submodules.uart_1 = UARTBone(phy=self.uart_1_phy, clk_freq=sys_clk_freq) + self.bus.add_master(name='uart_1', master=self.uart_1.wishbone) + + # GPIO Custom Serial ------------------------------------------------------------------------- + self.submodules.dshot_0 = GPIOOut( + pads = platform.request("digital", 43) # P48 + ) + self.add_csr("dshot_0") + + #wtf need to try... + # Analyzer ----------------------------------------------------------------------------------- + if with_analyzer: + analyzer_signals = [ + # IBus + self.cpu.ibus.stb, + self.cpu.ibus.cyc, + self.cpu.ibus.adr, + self.cpu.ibus.we, + self.cpu.ibus.ack, + self.cpu.ibus.sel, + self.cpu.ibus.dat_w, + self.cpu.ibus.dat_r, + # DBus + self.cpu.dbus.stb, + self.cpu.dbus.cyc, + self.cpu.dbus.adr, + self.cpu.dbus.we, + self.cpu.dbus.ack, + self.cpu.dbus.sel, + self.cpu.dbus.dat_w, + self.cpu.dbus.dat_r, + ] + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, + depth = 512, + clock_domain = "sys", + csr_csv = "analyzer.csv") + self.add_csr("analyzer") + + # at this point, only 0:6 show up (7:10) show in print after finalization() + # print(self.csr) + # print('\n\n\n\n') + +# Build -------------------------------------------------------------------------------------------- + +def main(): + + parser = argparse.ArgumentParser(description="A2P/cmod7") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") + parser.add_argument("--with-analyzer", action="store_true", help="Include analyzer") + + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + print(args) + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_analyzer = args.with_analyzer, + **soc_sdram_argdict(args) + ) + + builder = Builder(soc, **builder_argdict(args)) + # csrs arent all assigned by here either + #print('wtf',soc.csr) + builder.build(run=args.build) + + #wtf needs openocd!!! + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + +if __name__ == "__main__": + main() diff --git a/build/litex/litex-1099/master/cmod7.v b/build/litex/litex-1099/master/cmod7.v new file mode 100644 index 0000000..dc799e3 --- /dev/null +++ b/build/litex/litex-1099/master/cmod7.v @@ -0,0 +1,2733 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : cmod7.v +// Device : xc7a35t-CPG236-1 +// LiteX sha1 : feca1c47 +// Date : 2021-11-11 08:18:47 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module cmod7 ( + output reg serial_tx, + input wire serial_rx, + (* dont_touch = "true" *) input wire clk12, + output wire [18:0] issiram_addr, + inout wire [7:0] issiram_data, + output wire issiram_oen, + output wire issiram_wen, + output wire issiram_cen, + output reg user_led0, + output reg user_led1, + input wire user_btn0, + input wire user_btn1, + inout wire pmod0, + inout wire pmod1, + output reg digital10, + input wire digital11, + output wire digital43 +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg basesoc_soc_rst = 1'd0; +wire basesoc_cpu_rst; +reg [1:0] basesoc_reset_storage = 2'd0; +reg basesoc_reset_re = 1'd0; +reg [31:0] basesoc_scratch_storage = 32'd305419896; +reg basesoc_scratch_re = 1'd0; +wire [31:0] basesoc_bus_errors_status; +wire basesoc_bus_errors_we; +reg basesoc_bus_errors_re = 1'd0; +wire basesoc_bus_error; +reg [31:0] basesoc_bus_errors = 32'd0; +wire basesoc_reset; +reg [31:0] basesoc_interrupt = 32'd0; +reg basesoc_interruptS = 1'd0; +wire [29:0] basesoc_ibus_adr; +wire [31:0] basesoc_ibus_dat_w; +wire [31:0] basesoc_ibus_dat_r; +wire [3:0] basesoc_ibus_sel; +wire basesoc_ibus_cyc; +wire basesoc_ibus_stb; +wire basesoc_ibus_ack; +wire basesoc_ibus_we; +wire [2:0] basesoc_ibus_cti; +wire [1:0] basesoc_ibus_bte; +wire basesoc_ibus_err; +wire [29:0] basesoc_dbus_adr; +wire [31:0] basesoc_dbus_dat_w; +wire [31:0] basesoc_dbus_dat_r; +wire [3:0] basesoc_dbus_sel; +wire basesoc_dbus_cyc; +wire basesoc_dbus_stb; +wire basesoc_dbus_ack; +wire basesoc_dbus_we; +wire [2:0] basesoc_dbus_cti; +wire [1:0] basesoc_dbus_bte; +wire basesoc_dbus_err; +reg [31:0] basesoc_a2p = 32'd0; +wire basesoc_tx_sink_valid; +reg basesoc_tx_sink_ready = 1'd0; +wire basesoc_tx_sink_first; +wire basesoc_tx_sink_last; +wire [7:0] basesoc_tx_sink_payload_data; +reg [7:0] basesoc_tx_data = 8'd0; +reg [3:0] basesoc_tx_count = 4'd0; +reg basesoc_tx_enable = 1'd0; +reg basesoc_tx_tick = 1'd0; +reg [31:0] basesoc_tx_phase = 32'd0; +reg basesoc_rx_source_valid = 1'd0; +wire basesoc_rx_source_ready; +reg basesoc_rx_source_first = 1'd0; +reg basesoc_rx_source_last = 1'd0; +reg [7:0] basesoc_rx_source_payload_data = 8'd0; +reg [7:0] basesoc_rx_data = 8'd0; +reg [3:0] basesoc_rx_count = 4'd0; +reg basesoc_rx_enable = 1'd0; +reg basesoc_rx_tick = 1'd0; +reg [31:0] basesoc_rx_phase = 32'd0; +wire basesoc_rx_rx; +reg basesoc_rx_rx_d = 1'd0; +reg basesoc_uart_rxtx_re = 1'd0; +wire [7:0] basesoc_uart_rxtx_r; +reg basesoc_uart_rxtx_we = 1'd0; +wire [7:0] basesoc_uart_rxtx_w; +wire basesoc_uart_txfull_status; +wire basesoc_uart_txfull_we; +reg basesoc_uart_txfull_re = 1'd0; +wire basesoc_uart_rxempty_status; +wire basesoc_uart_rxempty_we; +reg basesoc_uart_rxempty_re = 1'd0; +wire basesoc_uart_irq; +wire basesoc_uart_tx_status; +reg basesoc_uart_tx_pending = 1'd0; +wire basesoc_uart_tx_trigger; +reg basesoc_uart_tx_clear = 1'd0; +reg basesoc_uart_tx_trigger_d = 1'd0; +wire basesoc_uart_rx_status; +reg basesoc_uart_rx_pending = 1'd0; +wire basesoc_uart_rx_trigger; +reg basesoc_uart_rx_clear = 1'd0; +reg basesoc_uart_rx_trigger_d = 1'd0; +wire basesoc_uart_tx0; +wire basesoc_uart_rx0; +reg [1:0] basesoc_uart_status_status = 2'd0; +wire basesoc_uart_status_we; +reg basesoc_uart_status_re = 1'd0; +wire basesoc_uart_tx1; +wire basesoc_uart_rx1; +reg [1:0] basesoc_uart_pending_status = 2'd0; +wire basesoc_uart_pending_we; +reg basesoc_uart_pending_re = 1'd0; +reg [1:0] basesoc_uart_pending_r = 2'd0; +wire basesoc_uart_tx2; +wire basesoc_uart_rx2; +reg [1:0] basesoc_uart_enable_storage = 2'd0; +reg basesoc_uart_enable_re = 1'd0; +wire basesoc_uart_txempty_status; +wire basesoc_uart_txempty_we; +reg basesoc_uart_txempty_re = 1'd0; +wire basesoc_uart_rxfull_status; +wire basesoc_uart_rxfull_we; +reg basesoc_uart_rxfull_re = 1'd0; +wire basesoc_uart_uart_sink_valid; +wire basesoc_uart_uart_sink_ready; +wire basesoc_uart_uart_sink_first; +wire basesoc_uart_uart_sink_last; +wire [7:0] basesoc_uart_uart_sink_payload_data; +wire basesoc_uart_uart_source_valid; +wire basesoc_uart_uart_source_ready; +wire basesoc_uart_uart_source_first; +wire basesoc_uart_uart_source_last; +wire [7:0] basesoc_uart_uart_source_payload_data; +wire basesoc_uart_tx_fifo_sink_valid; +wire basesoc_uart_tx_fifo_sink_ready; +reg basesoc_uart_tx_fifo_sink_first = 1'd0; +reg basesoc_uart_tx_fifo_sink_last = 1'd0; +wire [7:0] basesoc_uart_tx_fifo_sink_payload_data; +wire basesoc_uart_tx_fifo_source_valid; +wire basesoc_uart_tx_fifo_source_ready; +wire basesoc_uart_tx_fifo_source_first; +wire basesoc_uart_tx_fifo_source_last; +wire [7:0] basesoc_uart_tx_fifo_source_payload_data; +wire basesoc_uart_tx_fifo_re; +reg basesoc_uart_tx_fifo_readable = 1'd0; +wire basesoc_uart_tx_fifo_syncfifo_we; +wire basesoc_uart_tx_fifo_syncfifo_writable; +wire basesoc_uart_tx_fifo_syncfifo_re; +wire basesoc_uart_tx_fifo_syncfifo_readable; +wire [9:0] basesoc_uart_tx_fifo_syncfifo_din; +wire [9:0] basesoc_uart_tx_fifo_syncfifo_dout; +reg [4:0] basesoc_uart_tx_fifo_level0 = 5'd0; +reg basesoc_uart_tx_fifo_replace = 1'd0; +reg [3:0] basesoc_uart_tx_fifo_produce = 4'd0; +reg [3:0] basesoc_uart_tx_fifo_consume = 4'd0; +reg [3:0] basesoc_uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] basesoc_uart_tx_fifo_wrport_dat_r; +wire basesoc_uart_tx_fifo_wrport_we; +wire [9:0] basesoc_uart_tx_fifo_wrport_dat_w; +wire basesoc_uart_tx_fifo_do_read; +wire [3:0] basesoc_uart_tx_fifo_rdport_adr; +wire [9:0] basesoc_uart_tx_fifo_rdport_dat_r; +wire basesoc_uart_tx_fifo_rdport_re; +wire [4:0] basesoc_uart_tx_fifo_level1; +wire [7:0] basesoc_uart_tx_fifo_fifo_in_payload_data; +wire basesoc_uart_tx_fifo_fifo_in_first; +wire basesoc_uart_tx_fifo_fifo_in_last; +wire [7:0] basesoc_uart_tx_fifo_fifo_out_payload_data; +wire basesoc_uart_tx_fifo_fifo_out_first; +wire basesoc_uart_tx_fifo_fifo_out_last; +wire basesoc_uart_rx_fifo_sink_valid; +wire basesoc_uart_rx_fifo_sink_ready; +wire basesoc_uart_rx_fifo_sink_first; +wire basesoc_uart_rx_fifo_sink_last; +wire [7:0] basesoc_uart_rx_fifo_sink_payload_data; +wire basesoc_uart_rx_fifo_source_valid; +wire basesoc_uart_rx_fifo_source_ready; +wire basesoc_uart_rx_fifo_source_first; +wire basesoc_uart_rx_fifo_source_last; +wire [7:0] basesoc_uart_rx_fifo_source_payload_data; +wire basesoc_uart_rx_fifo_re; +reg basesoc_uart_rx_fifo_readable = 1'd0; +wire basesoc_uart_rx_fifo_syncfifo_we; +wire basesoc_uart_rx_fifo_syncfifo_writable; +wire basesoc_uart_rx_fifo_syncfifo_re; +wire basesoc_uart_rx_fifo_syncfifo_readable; +wire [9:0] basesoc_uart_rx_fifo_syncfifo_din; +wire [9:0] basesoc_uart_rx_fifo_syncfifo_dout; +reg [4:0] basesoc_uart_rx_fifo_level0 = 5'd0; +reg basesoc_uart_rx_fifo_replace = 1'd0; +reg [3:0] basesoc_uart_rx_fifo_produce = 4'd0; +reg [3:0] basesoc_uart_rx_fifo_consume = 4'd0; +reg [3:0] basesoc_uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] basesoc_uart_rx_fifo_wrport_dat_r; +wire basesoc_uart_rx_fifo_wrport_we; +wire [9:0] basesoc_uart_rx_fifo_wrport_dat_w; +wire basesoc_uart_rx_fifo_do_read; +wire [3:0] basesoc_uart_rx_fifo_rdport_adr; +wire [9:0] basesoc_uart_rx_fifo_rdport_dat_r; +wire basesoc_uart_rx_fifo_rdport_re; +wire [4:0] basesoc_uart_rx_fifo_level1; +wire [7:0] basesoc_uart_rx_fifo_fifo_in_payload_data; +wire basesoc_uart_rx_fifo_fifo_in_first; +wire basesoc_uart_rx_fifo_fifo_in_last; +wire [7:0] basesoc_uart_rx_fifo_fifo_out_payload_data; +wire basesoc_uart_rx_fifo_fifo_out_first; +wire basesoc_uart_rx_fifo_fifo_out_last; +reg [31:0] basesoc_timer_load_storage = 32'd0; +reg basesoc_timer_load_re = 1'd0; +reg [31:0] basesoc_timer_reload_storage = 32'd0; +reg basesoc_timer_reload_re = 1'd0; +reg basesoc_timer_en_storage = 1'd0; +reg basesoc_timer_en_re = 1'd0; +reg basesoc_timer_update_value_storage = 1'd0; +reg basesoc_timer_update_value_re = 1'd0; +reg [31:0] basesoc_timer_value_status = 32'd0; +wire basesoc_timer_value_we; +reg basesoc_timer_value_re = 1'd0; +wire basesoc_timer_irq; +wire basesoc_timer_zero_status; +reg basesoc_timer_zero_pending = 1'd0; +wire basesoc_timer_zero_trigger; +reg basesoc_timer_zero_clear = 1'd0; +reg basesoc_timer_zero_trigger_d = 1'd0; +wire basesoc_timer_zero0; +wire basesoc_timer_status_status; +wire basesoc_timer_status_we; +reg basesoc_timer_status_re = 1'd0; +wire basesoc_timer_zero1; +wire basesoc_timer_pending_status; +wire basesoc_timer_pending_we; +reg basesoc_timer_pending_re = 1'd0; +reg basesoc_timer_pending_r = 1'd0; +wire basesoc_timer_zero2; +reg basesoc_timer_enable_storage = 1'd0; +reg basesoc_timer_enable_re = 1'd0; +reg [31:0] basesoc_timer_value = 32'd0; +wire crg_rst; +(* dont_touch = "true" *) wire sys_clk; +wire sys_rst; +wire sys2x_clk; +wire idelay_clk; +wire idelay_rst; +wire crg_reset; +reg crg_power_down = 1'd0; +wire crg_locked; +(* dont_touch = "true" *) wire crg_clkin; +wire crg_clkout0; +wire crg_clkout_buf0; +wire crg_clkout1; +wire crg_clkout_buf1; +wire crg_clkout2; +wire crg_clkout_buf2; +reg [3:0] crg_reset_counter = 4'd15; +reg crg_ic_reset = 1'd1; +reg csrstorage0_storage = 1'd140989193; +reg csrstorage0_re = 1'd0; +reg csrstorage1_storage = 1'd0; +reg csrstorage1_re = 1'd0; +reg directory0_re = 1'd0; +reg directory0_r = 1'd0; +wire directory0_w; +reg csr_08000_re = 1'd0; +reg csr_08000_r = 1'd0; +wire csr_08000_w; +wire [29:0] basesoc_ram_bus_adr; +wire [31:0] basesoc_ram_bus_dat_w; +wire [31:0] basesoc_ram_bus_dat_r; +wire [3:0] basesoc_ram_bus_sel; +wire basesoc_ram_bus_cyc; +wire basesoc_ram_bus_stb; +reg basesoc_ram_bus_ack = 1'd0; +wire basesoc_ram_bus_we; +wire [2:0] basesoc_ram_bus_cti; +wire [1:0] basesoc_ram_bus_bte; +reg basesoc_ram_bus_err = 1'd0; +wire [13:0] basesoc_adr; +wire [31:0] basesoc_dat_r; +wire [29:0] sram_bus_adr; +wire [31:0] sram_bus_dat_w; +wire [31:0] sram_bus_dat_r; +wire [3:0] sram_bus_sel; +wire sram_bus_cyc; +wire sram_bus_stb; +wire sram_bus_ack; +wire sram_bus_we; +wire [2:0] sram_bus_cti; +wire [1:0] sram_bus_bte; +reg sram_bus_err = 1'd0; +reg [56:0] dna_status = 57'd0; +wire dna_we; +reg dna_re = 1'd0; +wire dna_do; +reg [6:0] dna_count = 7'd0; +wire dna_clk; +reg [11:0] xadc_temperature_status = 12'd0; +wire xadc_temperature_we; +reg xadc_temperature_re = 1'd0; +reg [11:0] xadc_vccint_status = 12'd0; +wire xadc_vccint_we; +reg xadc_vccint_re = 1'd0; +reg [11:0] xadc_vccaux_status = 12'd0; +wire xadc_vccaux_we; +reg xadc_vccaux_re = 1'd0; +reg [11:0] xadc_vccbram_status = 12'd0; +wire xadc_vccbram_we; +reg xadc_vccbram_re = 1'd0; +reg xadc_eoc_status = 1'd0; +wire xadc_eoc_we; +reg xadc_eoc_re = 1'd0; +reg xadc_eos_status = 1'd0; +wire xadc_eos_we; +reg xadc_eos_re = 1'd0; +wire [7:0] xadc_alarm; +wire xadc_ot; +wire xadc_busy; +wire [6:0] xadc_channel; +wire xadc_eoc; +wire xadc_eos; +reg xadc_dwe = 1'd0; +reg xadc_den = 1'd0; +wire xadc_drdy; +reg [6:0] xadc_dadr = 7'd0; +reg [15:0] xadc_di = 16'd0; +wire [15:0] xadc_do; +reg xadc_drp_en = 1'd0; +reg [1:0] leds_storage = 2'd0; +reg leds_re = 1'd0; +reg [1:0] leds_chaser = 2'd0; +reg leds_mode = 1'd0; +wire leds_wait; +wire leds_done; +reg [24:0] leds_count = 25'd25000000; +wire [1:0] buttons_status; +wire buttons_we; +reg buttons_re = 1'd0; +wire scl; +wire oe; +wire sda0; +reg [2:0] _w_storage = 3'd0; +reg _w_re = 1'd0; +wire sda1; +wire _r_status; +wire _r_we; +reg _r_re = 1'd0; +reg uart_1_phy_tx_sink_valid = 1'd0; +reg uart_1_phy_tx_sink_ready = 1'd0; +wire uart_1_phy_tx_sink_last; +reg [7:0] uart_1_phy_tx_sink_payload_data = 8'd0; +reg [7:0] uart_1_phy_tx_data = 8'd0; +reg [3:0] uart_1_phy_tx_count = 4'd0; +reg uart_1_phy_tx_enable = 1'd0; +reg uart_1_phy_tx_tick = 1'd0; +reg [31:0] uart_1_phy_tx_phase = 32'd0; +reg uart_1_phy_rx_source_valid = 1'd0; +reg uart_1_phy_rx_source_ready = 1'd0; +reg [7:0] uart_1_phy_rx_source_payload_data = 8'd0; +reg [7:0] uart_1_phy_rx_data = 8'd0; +reg [3:0] uart_1_phy_rx_count = 4'd0; +reg uart_1_phy_rx_enable = 1'd0; +reg uart_1_phy_rx_tick = 1'd0; +reg [31:0] uart_1_phy_rx_phase = 32'd0; +wire uart_1_phy_rx_rx; +reg uart_1_phy_rx_rx_d = 1'd0; +wire [29:0] uart_1_wishbone_adr; +wire [31:0] uart_1_wishbone_dat_w; +wire [31:0] uart_1_wishbone_dat_r; +wire [3:0] uart_1_wishbone_sel; +reg uart_1_wishbone_cyc = 1'd0; +reg uart_1_wishbone_stb = 1'd0; +wire uart_1_wishbone_ack; +reg uart_1_wishbone_we = 1'd0; +reg [2:0] uart_1_wishbone_cti = 3'd0; +reg [1:0] uart_1_wishbone_bte = 2'd0; +wire uart_1_wishbone_err; +reg [7:0] uart_1_cmd = 8'd0; +reg uart_1_incr = 1'd0; +reg [7:0] uart_1_length = 8'd0; +reg [31:0] uart_1_address = 32'd0; +reg [31:0] uart_1_data = 32'd0; +reg [1:0] uart_1_bytes_count = 2'd0; +reg [7:0] uart_1_words_count = 8'd0; +wire uart_1_reset; +wire uart_1_wait; +wire uart_1_done; +reg [23:0] uart_1_count = 24'd10000000; +reg uart_1_is_ongoing = 1'd0; +reg dshot_0_storage = 1'd0; +reg dshot_0_re = 1'd0; +reg subfragments_rs232phytx0_state = 1'd0; +reg subfragments_rs232phytx0_next_state = 1'd0; +reg [3:0] basesoc_tx_count_rs232phytx0_next_value0 = 4'd0; +reg basesoc_tx_count_rs232phytx0_next_value_ce0 = 1'd0; +reg basesoc_serial_tx_rs232phytx0_next_value1 = 1'd0; +reg basesoc_serial_tx_rs232phytx0_next_value_ce1 = 1'd0; +reg [7:0] basesoc_tx_data_rs232phytx0_next_value2 = 8'd0; +reg basesoc_tx_data_rs232phytx0_next_value_ce2 = 1'd0; +reg subfragments_rs232phyrx0_state = 1'd0; +reg subfragments_rs232phyrx0_next_state = 1'd0; +reg [3:0] basesoc_rx_count_rs232phyrx0_next_value0 = 4'd0; +reg basesoc_rx_count_rs232phyrx0_next_value_ce0 = 1'd0; +reg [7:0] basesoc_rx_data_rs232phyrx0_next_value1 = 8'd0; +reg basesoc_rx_data_rs232phyrx0_next_value_ce1 = 1'd0; +wire subfragments_reset0; +wire subfragments_reset1; +wire subfragments_reset2; +wire subfragments_reset3; +wire subfragments_reset4; +wire subfragments_reset5; +wire subfragments_reset6; +wire subfragments_reset7; +wire subfragments_mmcm_fb; +reg subfragments_rs232phytx1_state = 1'd0; +reg subfragments_rs232phytx1_next_state = 1'd0; +reg [3:0] uart_1_phy_tx_count_rs232phytx1_next_value0 = 4'd0; +reg uart_1_phy_tx_count_rs232phytx1_next_value_ce0 = 1'd0; +reg tx_obj_rs232phytx1_next_value1 = 1'd0; +reg tx_obj_rs232phytx1_next_value_ce1 = 1'd0; +reg [7:0] uart_1_phy_tx_data_rs232phytx1_next_value2 = 8'd0; +reg uart_1_phy_tx_data_rs232phytx1_next_value_ce2 = 1'd0; +reg subfragments_rs232phyrx1_state = 1'd0; +reg subfragments_rs232phyrx1_next_state = 1'd0; +reg [3:0] uart_1_phy_rx_count_rs232phyrx1_next_value0 = 4'd0; +reg uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 = 1'd0; +reg [7:0] uart_1_phy_rx_data_rs232phyrx1_next_value1 = 8'd0; +reg uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 = 1'd0; +reg [2:0] subfragments_state = 3'd0; +reg [2:0] subfragments_next_state = 3'd0; +reg [1:0] uart_1_bytes_count_next_value0 = 2'd0; +reg uart_1_bytes_count_next_value_ce0 = 1'd0; +reg [7:0] uart_1_words_count_next_value1 = 8'd0; +reg uart_1_words_count_next_value_ce1 = 1'd0; +reg [7:0] uart_1_cmd_next_value2 = 8'd0; +reg uart_1_cmd_next_value_ce2 = 1'd0; +reg [7:0] uart_1_length_next_value3 = 8'd0; +reg uart_1_length_next_value_ce3 = 1'd0; +reg [31:0] uart_1_address_next_value4 = 32'd0; +reg uart_1_address_next_value_ce4 = 1'd0; +reg uart_1_incr_next_value5 = 1'd0; +reg uart_1_incr_next_value_ce5 = 1'd0; +reg [31:0] uart_1_data_next_value6 = 32'd0; +reg uart_1_data_next_value_ce6 = 1'd0; +reg [13:0] basesoc_basesoc_adr = 14'd0; +reg basesoc_basesoc_we = 1'd0; +reg [31:0] basesoc_basesoc_dat_w = 32'd0; +wire [31:0] basesoc_basesoc_dat_r; +wire [29:0] basesoc_basesoc_wishbone_adr; +wire [31:0] basesoc_basesoc_wishbone_dat_w; +reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0; +wire [3:0] basesoc_basesoc_wishbone_sel; +wire basesoc_basesoc_wishbone_cyc; +wire basesoc_basesoc_wishbone_stb; +reg basesoc_basesoc_wishbone_ack = 1'd0; +wire basesoc_basesoc_wishbone_we; +wire [2:0] basesoc_basesoc_wishbone_cti; +wire [1:0] basesoc_basesoc_wishbone_bte; +reg basesoc_basesoc_wishbone_err = 1'd0; +wire [29:0] basesoc_shared_adr; +wire [31:0] basesoc_shared_dat_w; +reg [31:0] basesoc_shared_dat_r = 32'd0; +wire [3:0] basesoc_shared_sel; +wire basesoc_shared_cyc; +wire basesoc_shared_stb; +reg basesoc_shared_ack = 1'd0; +wire basesoc_shared_we; +wire [2:0] basesoc_shared_cti; +wire [1:0] basesoc_shared_bte; +wire basesoc_shared_err; +wire [2:0] basesoc_request; +reg [1:0] basesoc_grant = 2'd0; +reg [2:0] basesoc_slave_sel = 3'd0; +reg [2:0] basesoc_slave_sel_r = 3'd0; +reg basesoc_error = 1'd0; +wire basesoc_wait; +wire basesoc_done; +reg [19:0] basesoc_count = 20'd1000000; +wire [13:0] basesoc_csr_bankarray_interface0_bank_bus_adr; +wire basesoc_csr_bankarray_interface0_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank0_in_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank0_in_r; +reg basesoc_csr_bankarray_csrbank0_in_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank0_in_w; +wire basesoc_csr_bankarray_csrbank0_sel; +wire [13:0] basesoc_csr_bankarray_interface1_bank_bus_adr; +wire basesoc_csr_bankarray_interface1_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank1_reset0_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank1_reset0_r; +reg basesoc_csr_bankarray_csrbank1_reset0_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank1_reset0_w; +reg basesoc_csr_bankarray_csrbank1_scratch0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_scratch0_r; +reg basesoc_csr_bankarray_csrbank1_scratch0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_scratch0_w; +reg basesoc_csr_bankarray_csrbank1_bus_errors_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_bus_errors_r; +reg basesoc_csr_bankarray_csrbank1_bus_errors_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_bus_errors_w; +wire basesoc_csr_bankarray_csrbank1_sel; +wire [13:0] basesoc_csr_bankarray_interface2_bank_bus_adr; +wire basesoc_csr_bankarray_interface2_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank2_id1_re = 1'd0; +wire [24:0] basesoc_csr_bankarray_csrbank2_id1_r; +reg basesoc_csr_bankarray_csrbank2_id1_we = 1'd0; +wire [24:0] basesoc_csr_bankarray_csrbank2_id1_w; +reg basesoc_csr_bankarray_csrbank2_id0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank2_id0_r; +reg basesoc_csr_bankarray_csrbank2_id0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank2_id0_w; +wire basesoc_csr_bankarray_csrbank2_sel; +wire [13:0] basesoc_csr_bankarray_interface3_bank_bus_adr; +wire basesoc_csr_bankarray_interface3_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank3_out0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank3_out0_r; +reg basesoc_csr_bankarray_csrbank3_out0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank3_out0_w; +wire basesoc_csr_bankarray_csrbank3_sel; +wire [13:0] basesoc_csr_bankarray_interface4_bank_bus_adr; +wire basesoc_csr_bankarray_interface4_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank4_w0_re = 1'd0; +wire [2:0] basesoc_csr_bankarray_csrbank4_w0_r; +reg basesoc_csr_bankarray_csrbank4_w0_we = 1'd0; +wire [2:0] basesoc_csr_bankarray_csrbank4_w0_w; +reg basesoc_csr_bankarray_csrbank4_r_re = 1'd0; +wire basesoc_csr_bankarray_csrbank4_r_r; +reg basesoc_csr_bankarray_csrbank4_r_we = 1'd0; +wire basesoc_csr_bankarray_csrbank4_r_w; +wire basesoc_csr_bankarray_csrbank4_sel; +wire [13:0] basesoc_csr_bankarray_sram_bus_adr; +wire basesoc_csr_bankarray_sram_bus_we; +wire [31:0] basesoc_csr_bankarray_sram_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_sram_bus_dat_r = 32'd0; +wire [4:0] basesoc_csr_bankarray_adr; +wire [7:0] basesoc_csr_bankarray_dat_r; +wire basesoc_csr_bankarray_sel; +reg basesoc_csr_bankarray_sel_r = 1'd0; +wire [13:0] basesoc_csr_bankarray_interface5_bank_bus_adr; +wire basesoc_csr_bankarray_interface5_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank5_out0_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank5_out0_r; +reg basesoc_csr_bankarray_csrbank5_out0_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank5_out0_w; +wire basesoc_csr_bankarray_csrbank5_sel; +wire [13:0] basesoc_csr_bankarray_interface6_bank_bus_adr; +wire basesoc_csr_bankarray_interface6_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank6_load0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_load0_r; +reg basesoc_csr_bankarray_csrbank6_load0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_load0_w; +reg basesoc_csr_bankarray_csrbank6_reload0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_reload0_r; +reg basesoc_csr_bankarray_csrbank6_reload0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_reload0_w; +reg basesoc_csr_bankarray_csrbank6_en0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_en0_r; +reg basesoc_csr_bankarray_csrbank6_en0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_en0_w; +reg basesoc_csr_bankarray_csrbank6_update_value0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_update_value0_r; +reg basesoc_csr_bankarray_csrbank6_update_value0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_update_value0_w; +reg basesoc_csr_bankarray_csrbank6_value_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_value_r; +reg basesoc_csr_bankarray_csrbank6_value_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_value_w; +reg basesoc_csr_bankarray_csrbank6_ev_status_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_status_r; +reg basesoc_csr_bankarray_csrbank6_ev_status_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_status_w; +reg basesoc_csr_bankarray_csrbank6_ev_pending_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_pending_r; +reg basesoc_csr_bankarray_csrbank6_ev_pending_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_pending_w; +reg basesoc_csr_bankarray_csrbank6_ev_enable0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_enable0_r; +reg basesoc_csr_bankarray_csrbank6_ev_enable0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_enable0_w; +wire basesoc_csr_bankarray_csrbank6_sel; +wire [13:0] basesoc_csr_bankarray_interface7_bank_bus_adr; +wire basesoc_csr_bankarray_interface7_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank7_txfull_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txfull_r; +reg basesoc_csr_bankarray_csrbank7_txfull_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txfull_w; +reg basesoc_csr_bankarray_csrbank7_rxempty_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxempty_r; +reg basesoc_csr_bankarray_csrbank7_rxempty_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxempty_w; +reg basesoc_csr_bankarray_csrbank7_ev_status_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_status_r; +reg basesoc_csr_bankarray_csrbank7_ev_status_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_status_w; +reg basesoc_csr_bankarray_csrbank7_ev_pending_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_pending_r; +reg basesoc_csr_bankarray_csrbank7_ev_pending_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_pending_w; +reg basesoc_csr_bankarray_csrbank7_ev_enable0_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_enable0_r; +reg basesoc_csr_bankarray_csrbank7_ev_enable0_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_enable0_w; +reg basesoc_csr_bankarray_csrbank7_txempty_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txempty_r; +reg basesoc_csr_bankarray_csrbank7_txempty_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txempty_w; +reg basesoc_csr_bankarray_csrbank7_rxfull_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxfull_r; +reg basesoc_csr_bankarray_csrbank7_rxfull_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxfull_w; +wire basesoc_csr_bankarray_csrbank7_sel; +wire [13:0] basesoc_csr_bankarray_interface8_bank_bus_adr; +wire basesoc_csr_bankarray_interface8_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank8_temperature_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_temperature_r; +reg basesoc_csr_bankarray_csrbank8_temperature_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_temperature_w; +reg basesoc_csr_bankarray_csrbank8_vccint_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccint_r; +reg basesoc_csr_bankarray_csrbank8_vccint_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccint_w; +reg basesoc_csr_bankarray_csrbank8_vccaux_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccaux_r; +reg basesoc_csr_bankarray_csrbank8_vccaux_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccaux_w; +reg basesoc_csr_bankarray_csrbank8_vccbram_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccbram_r; +reg basesoc_csr_bankarray_csrbank8_vccbram_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccbram_w; +reg basesoc_csr_bankarray_csrbank8_eoc_re = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eoc_r; +reg basesoc_csr_bankarray_csrbank8_eoc_we = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eoc_w; +reg basesoc_csr_bankarray_csrbank8_eos_re = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eos_r; +reg basesoc_csr_bankarray_csrbank8_eos_we = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eos_w; +wire basesoc_csr_bankarray_csrbank8_sel; +wire [13:0] basesoc_csr_interconnect_adr; +wire basesoc_csr_interconnect_we; +wire [31:0] basesoc_csr_interconnect_dat_w; +wire [31:0] basesoc_csr_interconnect_dat_r; +reg basesoc_state = 1'd0; +reg basesoc_next_state = 1'd0; +reg [29:0] array_muxed0 = 30'd0; +reg [31:0] array_muxed1 = 32'd0; +reg [3:0] array_muxed2 = 4'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg [2:0] array_muxed6 = 3'd0; +reg [1:0] array_muxed7 = 2'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_expr; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl1_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl1_regs1 = 2'd0; +wire xilinxmultiregimpl1; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign basesoc_reset = (basesoc_soc_rst | basesoc_cpu_rst); +assign crg_rst = basesoc_soc_rst; +assign basesoc_bus_error = basesoc_error; +always @(*) begin + basesoc_interrupt <= 32'd0; + basesoc_interrupt[1] <= basesoc_timer_irq; + basesoc_interrupt[0] <= basesoc_uart_irq; +end +assign basesoc_bus_errors_status = basesoc_bus_errors; +always @(*) begin + subfragments_rs232phytx0_next_state <= 1'd0; + basesoc_tx_count_rs232phytx0_next_value0 <= 4'd0; + basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd0; + basesoc_tx_sink_ready <= 1'd0; + basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd0; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd0; + basesoc_tx_data_rs232phytx0_next_value2 <= 8'd0; + basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd0; + basesoc_tx_enable <= 1'd0; + subfragments_rs232phytx0_next_state <= subfragments_rs232phytx0_state; + case (subfragments_rs232phytx0_state) + 1'd1: begin + basesoc_tx_enable <= 1'd1; + if (basesoc_tx_tick) begin + basesoc_serial_tx_rs232phytx0_next_value1 <= basesoc_tx_data; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1; + basesoc_tx_count_rs232phytx0_next_value0 <= (basesoc_tx_count + 1'd1); + basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd1; + basesoc_tx_data_rs232phytx0_next_value2 <= {1'd1, basesoc_tx_data[7:1]}; + basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd1; + if ((basesoc_tx_count == 4'd9)) begin + basesoc_tx_sink_ready <= 1'd1; + subfragments_rs232phytx0_next_state <= 1'd0; + end + end + end + default: begin + basesoc_tx_count_rs232phytx0_next_value0 <= 1'd0; + basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd1; + basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd1; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1; + if (basesoc_tx_sink_valid) begin + basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd0; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1; + basesoc_tx_data_rs232phytx0_next_value2 <= basesoc_tx_sink_payload_data; + basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd1; + subfragments_rs232phytx0_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + subfragments_rs232phyrx0_next_state <= 1'd0; + basesoc_rx_count_rs232phyrx0_next_value0 <= 4'd0; + basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd0; + basesoc_rx_source_valid <= 1'd0; + basesoc_rx_source_payload_data <= 8'd0; + basesoc_rx_data_rs232phyrx0_next_value1 <= 8'd0; + basesoc_rx_data_rs232phyrx0_next_value_ce1 <= 1'd0; + basesoc_rx_enable <= 1'd0; + subfragments_rs232phyrx0_next_state <= subfragments_rs232phyrx0_state; + case (subfragments_rs232phyrx0_state) + 1'd1: begin + basesoc_rx_enable <= 1'd1; + if (basesoc_rx_tick) begin + basesoc_rx_count_rs232phyrx0_next_value0 <= (basesoc_rx_count + 1'd1); + basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1; + basesoc_rx_data_rs232phyrx0_next_value1 <= {basesoc_rx_rx, basesoc_rx_data[7:1]}; + basesoc_rx_data_rs232phyrx0_next_value_ce1 <= 1'd1; + if ((basesoc_rx_count == 4'd9)) begin + basesoc_rx_source_valid <= (basesoc_rx_rx == 1'd1); + basesoc_rx_source_payload_data <= basesoc_rx_data; + subfragments_rs232phyrx0_next_state <= 1'd0; + end + end + end + default: begin + basesoc_rx_count_rs232phyrx0_next_value0 <= 1'd0; + basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1; + if (((basesoc_rx_rx == 1'd0) & (basesoc_rx_rx_d == 1'd1))) begin + subfragments_rs232phyrx0_next_state <= 1'd1; + end + end + endcase +end +assign basesoc_uart_uart_sink_valid = basesoc_rx_source_valid; +assign basesoc_rx_source_ready = basesoc_uart_uart_sink_ready; +assign basesoc_uart_uart_sink_first = basesoc_rx_source_first; +assign basesoc_uart_uart_sink_last = basesoc_rx_source_last; +assign basesoc_uart_uart_sink_payload_data = basesoc_rx_source_payload_data; +assign basesoc_tx_sink_valid = basesoc_uart_uart_source_valid; +assign basesoc_uart_uart_source_ready = basesoc_tx_sink_ready; +assign basesoc_tx_sink_first = basesoc_uart_uart_source_first; +assign basesoc_tx_sink_last = basesoc_uart_uart_source_last; +assign basesoc_tx_sink_payload_data = basesoc_uart_uart_source_payload_data; +assign basesoc_uart_tx_fifo_sink_valid = basesoc_uart_rxtx_re; +assign basesoc_uart_tx_fifo_sink_payload_data = basesoc_uart_rxtx_r; +assign basesoc_uart_uart_source_valid = basesoc_uart_tx_fifo_source_valid; +assign basesoc_uart_tx_fifo_source_ready = basesoc_uart_uart_source_ready; +assign basesoc_uart_uart_source_first = basesoc_uart_tx_fifo_source_first; +assign basesoc_uart_uart_source_last = basesoc_uart_tx_fifo_source_last; +assign basesoc_uart_uart_source_payload_data = basesoc_uart_tx_fifo_source_payload_data; +assign basesoc_uart_txfull_status = (~basesoc_uart_tx_fifo_sink_ready); +assign basesoc_uart_txempty_status = (~basesoc_uart_tx_fifo_source_valid); +assign basesoc_uart_tx_trigger = basesoc_uart_tx_fifo_sink_ready; +assign basesoc_uart_rx_fifo_sink_valid = basesoc_uart_uart_sink_valid; +assign basesoc_uart_uart_sink_ready = basesoc_uart_rx_fifo_sink_ready; +assign basesoc_uart_rx_fifo_sink_first = basesoc_uart_uart_sink_first; +assign basesoc_uart_rx_fifo_sink_last = basesoc_uart_uart_sink_last; +assign basesoc_uart_rx_fifo_sink_payload_data = basesoc_uart_uart_sink_payload_data; +assign basesoc_uart_rxtx_w = basesoc_uart_rx_fifo_source_payload_data; +assign basesoc_uart_rx_fifo_source_ready = (basesoc_uart_rx_clear | (1'd0 & basesoc_uart_rxtx_we)); +assign basesoc_uart_rxempty_status = (~basesoc_uart_rx_fifo_source_valid); +assign basesoc_uart_rxfull_status = (~basesoc_uart_rx_fifo_sink_ready); +assign basesoc_uart_rx_trigger = basesoc_uart_rx_fifo_source_valid; +assign basesoc_uart_tx0 = basesoc_uart_tx_status; +assign basesoc_uart_tx1 = basesoc_uart_tx_pending; +always @(*) begin + basesoc_uart_tx_clear <= 1'd0; + if ((basesoc_uart_pending_re & basesoc_uart_pending_r[0])) begin + basesoc_uart_tx_clear <= 1'd1; + end +end +assign basesoc_uart_rx0 = basesoc_uart_rx_status; +assign basesoc_uart_rx1 = basesoc_uart_rx_pending; +always @(*) begin + basesoc_uart_rx_clear <= 1'd0; + if ((basesoc_uart_pending_re & basesoc_uart_pending_r[1])) begin + basesoc_uart_rx_clear <= 1'd1; + end +end +assign basesoc_uart_irq = ((basesoc_uart_pending_status[0] & basesoc_uart_enable_storage[0]) | (basesoc_uart_pending_status[1] & basesoc_uart_enable_storage[1])); +assign basesoc_uart_tx_status = basesoc_uart_tx_trigger; +assign basesoc_uart_rx_status = basesoc_uart_rx_trigger; +assign basesoc_uart_tx_fifo_syncfifo_din = {basesoc_uart_tx_fifo_fifo_in_last, basesoc_uart_tx_fifo_fifo_in_first, basesoc_uart_tx_fifo_fifo_in_payload_data}; +assign {basesoc_uart_tx_fifo_fifo_out_last, basesoc_uart_tx_fifo_fifo_out_first, basesoc_uart_tx_fifo_fifo_out_payload_data} = basesoc_uart_tx_fifo_syncfifo_dout; +assign basesoc_uart_tx_fifo_sink_ready = basesoc_uart_tx_fifo_syncfifo_writable; +assign basesoc_uart_tx_fifo_syncfifo_we = basesoc_uart_tx_fifo_sink_valid; +assign basesoc_uart_tx_fifo_fifo_in_first = basesoc_uart_tx_fifo_sink_first; +assign basesoc_uart_tx_fifo_fifo_in_last = basesoc_uart_tx_fifo_sink_last; +assign basesoc_uart_tx_fifo_fifo_in_payload_data = basesoc_uart_tx_fifo_sink_payload_data; +assign basesoc_uart_tx_fifo_source_valid = basesoc_uart_tx_fifo_readable; +assign basesoc_uart_tx_fifo_source_first = basesoc_uart_tx_fifo_fifo_out_first; +assign basesoc_uart_tx_fifo_source_last = basesoc_uart_tx_fifo_fifo_out_last; +assign basesoc_uart_tx_fifo_source_payload_data = basesoc_uart_tx_fifo_fifo_out_payload_data; +assign basesoc_uart_tx_fifo_re = basesoc_uart_tx_fifo_source_ready; +assign basesoc_uart_tx_fifo_syncfifo_re = (basesoc_uart_tx_fifo_syncfifo_readable & ((~basesoc_uart_tx_fifo_readable) | basesoc_uart_tx_fifo_re)); +assign basesoc_uart_tx_fifo_level1 = (basesoc_uart_tx_fifo_level0 + basesoc_uart_tx_fifo_readable); +always @(*) begin + basesoc_uart_tx_fifo_wrport_adr <= 4'd0; + if (basesoc_uart_tx_fifo_replace) begin + basesoc_uart_tx_fifo_wrport_adr <= (basesoc_uart_tx_fifo_produce - 1'd1); + end else begin + basesoc_uart_tx_fifo_wrport_adr <= basesoc_uart_tx_fifo_produce; + end +end +assign basesoc_uart_tx_fifo_wrport_dat_w = basesoc_uart_tx_fifo_syncfifo_din; +assign basesoc_uart_tx_fifo_wrport_we = (basesoc_uart_tx_fifo_syncfifo_we & (basesoc_uart_tx_fifo_syncfifo_writable | basesoc_uart_tx_fifo_replace)); +assign basesoc_uart_tx_fifo_do_read = (basesoc_uart_tx_fifo_syncfifo_readable & basesoc_uart_tx_fifo_syncfifo_re); +assign basesoc_uart_tx_fifo_rdport_adr = basesoc_uart_tx_fifo_consume; +assign basesoc_uart_tx_fifo_syncfifo_dout = basesoc_uart_tx_fifo_rdport_dat_r; +assign basesoc_uart_tx_fifo_rdport_re = basesoc_uart_tx_fifo_do_read; +assign basesoc_uart_tx_fifo_syncfifo_writable = (basesoc_uart_tx_fifo_level0 != 5'd16); +assign basesoc_uart_tx_fifo_syncfifo_readable = (basesoc_uart_tx_fifo_level0 != 1'd0); +assign basesoc_uart_rx_fifo_syncfifo_din = {basesoc_uart_rx_fifo_fifo_in_last, basesoc_uart_rx_fifo_fifo_in_first, basesoc_uart_rx_fifo_fifo_in_payload_data}; +assign {basesoc_uart_rx_fifo_fifo_out_last, basesoc_uart_rx_fifo_fifo_out_first, basesoc_uart_rx_fifo_fifo_out_payload_data} = basesoc_uart_rx_fifo_syncfifo_dout; +assign basesoc_uart_rx_fifo_sink_ready = basesoc_uart_rx_fifo_syncfifo_writable; +assign basesoc_uart_rx_fifo_syncfifo_we = basesoc_uart_rx_fifo_sink_valid; +assign basesoc_uart_rx_fifo_fifo_in_first = basesoc_uart_rx_fifo_sink_first; +assign basesoc_uart_rx_fifo_fifo_in_last = basesoc_uart_rx_fifo_sink_last; +assign basesoc_uart_rx_fifo_fifo_in_payload_data = basesoc_uart_rx_fifo_sink_payload_data; +assign basesoc_uart_rx_fifo_source_valid = basesoc_uart_rx_fifo_readable; +assign basesoc_uart_rx_fifo_source_first = basesoc_uart_rx_fifo_fifo_out_first; +assign basesoc_uart_rx_fifo_source_last = basesoc_uart_rx_fifo_fifo_out_last; +assign basesoc_uart_rx_fifo_source_payload_data = basesoc_uart_rx_fifo_fifo_out_payload_data; +assign basesoc_uart_rx_fifo_re = basesoc_uart_rx_fifo_source_ready; +assign basesoc_uart_rx_fifo_syncfifo_re = (basesoc_uart_rx_fifo_syncfifo_readable & ((~basesoc_uart_rx_fifo_readable) | basesoc_uart_rx_fifo_re)); +assign basesoc_uart_rx_fifo_level1 = (basesoc_uart_rx_fifo_level0 + basesoc_uart_rx_fifo_readable); +always @(*) begin + basesoc_uart_rx_fifo_wrport_adr <= 4'd0; + if (basesoc_uart_rx_fifo_replace) begin + basesoc_uart_rx_fifo_wrport_adr <= (basesoc_uart_rx_fifo_produce - 1'd1); + end else begin + basesoc_uart_rx_fifo_wrport_adr <= basesoc_uart_rx_fifo_produce; + end +end +assign basesoc_uart_rx_fifo_wrport_dat_w = basesoc_uart_rx_fifo_syncfifo_din; +assign basesoc_uart_rx_fifo_wrport_we = (basesoc_uart_rx_fifo_syncfifo_we & (basesoc_uart_rx_fifo_syncfifo_writable | basesoc_uart_rx_fifo_replace)); +assign basesoc_uart_rx_fifo_do_read = (basesoc_uart_rx_fifo_syncfifo_readable & basesoc_uart_rx_fifo_syncfifo_re); +assign basesoc_uart_rx_fifo_rdport_adr = basesoc_uart_rx_fifo_consume; +assign basesoc_uart_rx_fifo_syncfifo_dout = basesoc_uart_rx_fifo_rdport_dat_r; +assign basesoc_uart_rx_fifo_rdport_re = basesoc_uart_rx_fifo_do_read; +assign basesoc_uart_rx_fifo_syncfifo_writable = (basesoc_uart_rx_fifo_level0 != 5'd16); +assign basesoc_uart_rx_fifo_syncfifo_readable = (basesoc_uart_rx_fifo_level0 != 1'd0); +assign basesoc_timer_zero_trigger = (basesoc_timer_value == 1'd0); +assign basesoc_timer_zero0 = basesoc_timer_zero_status; +assign basesoc_timer_zero1 = basesoc_timer_zero_pending; +always @(*) begin + basesoc_timer_zero_clear <= 1'd0; + if ((basesoc_timer_pending_re & basesoc_timer_pending_r)) begin + basesoc_timer_zero_clear <= 1'd1; + end +end +assign basesoc_timer_irq = (basesoc_timer_pending_status & basesoc_timer_enable_storage); +assign basesoc_timer_zero_status = basesoc_timer_zero_trigger; +assign crg_reset = crg_rst; +assign crg_clkin = clk12; +assign sys_clk = crg_clkout_buf0; +assign sys2x_clk = crg_clkout_buf1; +assign idelay_clk = crg_clkout_buf2; +assign directory0_w = csrstorage0_storage; +assign csr_08000_w = csrstorage1_storage; +assign basesoc_adr = basesoc_ram_bus_adr[13:0]; +assign basesoc_ram_bus_dat_r = basesoc_dat_r; +assign dna_clk = dna_count[0]; +always @(*) begin + xadc_den <= 1'd0; + xadc_dadr <= 7'd0; + if ((~xadc_drp_en)) begin + xadc_den <= xadc_eoc; + xadc_dadr <= xadc_channel; + end +end +assign leds_wait = (~leds_done); +always @(*) begin + user_led1 <= 1'd0; + user_led0 <= 1'd0; + if ((leds_mode == 1'd1)) begin + {user_led1, user_led0} <= leds_storage; + end else begin + {user_led1, user_led0} <= leds_chaser; + end +end +assign leds_done = (leds_count == 1'd0); +always @(*) begin + subfragments_rs232phytx1_next_state <= 1'd0; + uart_1_phy_tx_count_rs232phytx1_next_value0 <= 4'd0; + uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd0; + uart_1_phy_tx_enable <= 1'd0; + tx_obj_rs232phytx1_next_value1 <= 1'd0; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd0; + uart_1_phy_tx_data_rs232phytx1_next_value2 <= 8'd0; + uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd0; + uart_1_phy_tx_sink_ready <= 1'd0; + subfragments_rs232phytx1_next_state <= subfragments_rs232phytx1_state; + case (subfragments_rs232phytx1_state) + 1'd1: begin + uart_1_phy_tx_enable <= 1'd1; + if (uart_1_phy_tx_tick) begin + tx_obj_rs232phytx1_next_value1 <= uart_1_phy_tx_data; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd1; + uart_1_phy_tx_count_rs232phytx1_next_value0 <= (uart_1_phy_tx_count + 1'd1); + uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1; + uart_1_phy_tx_data_rs232phytx1_next_value2 <= {1'd1, uart_1_phy_tx_data[7:1]}; + uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd1; + if ((uart_1_phy_tx_count == 4'd9)) begin + uart_1_phy_tx_sink_ready <= 1'd1; + subfragments_rs232phytx1_next_state <= 1'd0; + end + end + end + default: begin + uart_1_phy_tx_count_rs232phytx1_next_value0 <= 1'd0; + uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1; + tx_obj_rs232phytx1_next_value1 <= 1'd1; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd1; + if (uart_1_phy_tx_sink_valid) begin + tx_obj_rs232phytx1_next_value1 <= 1'd0; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd1; + uart_1_phy_tx_data_rs232phytx1_next_value2 <= uart_1_phy_tx_sink_payload_data; + uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd1; + subfragments_rs232phytx1_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + uart_1_phy_rx_source_payload_data <= 8'd0; + subfragments_rs232phyrx1_next_state <= 1'd0; + uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 4'd0; + uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd0; + uart_1_phy_rx_enable <= 1'd0; + uart_1_phy_rx_data_rs232phyrx1_next_value1 <= 8'd0; + uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd0; + uart_1_phy_rx_source_valid <= 1'd0; + subfragments_rs232phyrx1_next_state <= subfragments_rs232phyrx1_state; + case (subfragments_rs232phyrx1_state) + 1'd1: begin + uart_1_phy_rx_enable <= 1'd1; + if (uart_1_phy_rx_tick) begin + uart_1_phy_rx_count_rs232phyrx1_next_value0 <= (uart_1_phy_rx_count + 1'd1); + uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1; + uart_1_phy_rx_data_rs232phyrx1_next_value1 <= {uart_1_phy_rx_rx, uart_1_phy_rx_data[7:1]}; + uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd1; + if ((uart_1_phy_rx_count == 4'd9)) begin + uart_1_phy_rx_source_valid <= (uart_1_phy_rx_rx == 1'd1); + uart_1_phy_rx_source_payload_data <= uart_1_phy_rx_data; + subfragments_rs232phyrx1_next_state <= 1'd0; + end + end + end + default: begin + uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 1'd0; + uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1; + if (((uart_1_phy_rx_rx == 1'd0) & (uart_1_phy_rx_rx_d == 1'd1))) begin + subfragments_rs232phyrx1_next_state <= 1'd1; + end + end + endcase +end +assign uart_1_wait = (~uart_1_is_ongoing); +assign uart_1_reset = uart_1_done; +assign uart_1_wishbone_adr = uart_1_address; +assign uart_1_wishbone_dat_w = uart_1_data; +assign uart_1_wishbone_sel = 4'd15; +always @(*) begin + uart_1_phy_tx_sink_payload_data <= 8'd0; + case (uart_1_bytes_count) + 1'd0: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:24]; + end + 1'd1: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:16]; + end + 2'd2: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:8]; + end + 2'd3: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:0]; + end + endcase +end +assign uart_1_phy_tx_sink_last = ((uart_1_bytes_count == 2'd3) & (uart_1_words_count == (uart_1_length - 1'd1))); +always @(*) begin + subfragments_next_state <= 3'd0; + uart_1_bytes_count_next_value0 <= 2'd0; + uart_1_bytes_count_next_value_ce0 <= 1'd0; + uart_1_words_count_next_value1 <= 8'd0; + uart_1_words_count_next_value_ce1 <= 1'd0; + uart_1_cmd_next_value2 <= 8'd0; + uart_1_cmd_next_value_ce2 <= 1'd0; + uart_1_length_next_value3 <= 8'd0; + uart_1_length_next_value_ce3 <= 1'd0; + uart_1_phy_tx_sink_valid <= 1'd0; + uart_1_address_next_value4 <= 32'd0; + uart_1_address_next_value_ce4 <= 1'd0; + uart_1_is_ongoing <= 1'd0; + uart_1_incr_next_value5 <= 1'd0; + uart_1_incr_next_value_ce5 <= 1'd0; + uart_1_wishbone_cyc <= 1'd0; + uart_1_data_next_value6 <= 32'd0; + uart_1_wishbone_stb <= 1'd0; + uart_1_data_next_value_ce6 <= 1'd0; + uart_1_wishbone_we <= 1'd0; + uart_1_phy_rx_source_ready <= 1'd0; + subfragments_next_state <= subfragments_state; + case (subfragments_state) + 1'd1: begin + uart_1_phy_rx_source_ready <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_length_next_value3 <= uart_1_phy_rx_source_payload_data; + uart_1_length_next_value_ce3 <= 1'd1; + subfragments_next_state <= 2'd2; + end + end + 2'd2: begin + uart_1_phy_rx_source_ready <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_address_next_value4 <= {uart_1_address, uart_1_phy_rx_source_payload_data}; + uart_1_address_next_value_ce4 <= 1'd1; + uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1); + uart_1_bytes_count_next_value_ce0 <= 1'd1; + if ((uart_1_bytes_count == 2'd3)) begin + if (((uart_1_cmd == 1'd1) | (uart_1_cmd == 2'd3))) begin + uart_1_incr_next_value5 <= (uart_1_cmd == 1'd1); + uart_1_incr_next_value_ce5 <= 1'd1; + subfragments_next_state <= 2'd3; + end else begin + if (((uart_1_cmd == 2'd2) | (uart_1_cmd == 3'd4))) begin + uart_1_incr_next_value5 <= (uart_1_cmd == 2'd2); + uart_1_incr_next_value_ce5 <= 1'd1; + subfragments_next_state <= 3'd5; + end else begin + subfragments_next_state <= 1'd0; + end + end + end + end + end + 2'd3: begin + uart_1_phy_rx_source_ready <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_data_next_value6 <= {uart_1_data, uart_1_phy_rx_source_payload_data}; + uart_1_data_next_value_ce6 <= 1'd1; + uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1); + uart_1_bytes_count_next_value_ce0 <= 1'd1; + if ((uart_1_bytes_count == 2'd3)) begin + subfragments_next_state <= 3'd4; + end + end + end + 3'd4: begin + uart_1_phy_rx_source_ready <= 1'd0; + uart_1_wishbone_stb <= 1'd1; + uart_1_wishbone_we <= 1'd1; + uart_1_wishbone_cyc <= 1'd1; + if (uart_1_wishbone_ack) begin + uart_1_words_count_next_value1 <= (uart_1_words_count + 1'd1); + uart_1_words_count_next_value_ce1 <= 1'd1; + uart_1_address_next_value4 <= (uart_1_address + uart_1_incr); + uart_1_address_next_value_ce4 <= 1'd1; + if ((uart_1_words_count == (uart_1_length - 1'd1))) begin + subfragments_next_state <= 1'd0; + end else begin + subfragments_next_state <= 2'd3; + end + end + end + 3'd5: begin + uart_1_phy_rx_source_ready <= 1'd0; + uart_1_wishbone_stb <= 1'd1; + uart_1_wishbone_we <= 1'd0; + uart_1_wishbone_cyc <= 1'd1; + if (uart_1_wishbone_ack) begin + uart_1_data_next_value6 <= uart_1_wishbone_dat_r; + uart_1_data_next_value_ce6 <= 1'd1; + subfragments_next_state <= 3'd6; + end + end + 3'd6: begin + uart_1_phy_rx_source_ready <= 1'd0; + uart_1_phy_tx_sink_valid <= 1'd1; + if (uart_1_phy_tx_sink_ready) begin + uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1); + uart_1_bytes_count_next_value_ce0 <= 1'd1; + if ((uart_1_bytes_count == 2'd3)) begin + uart_1_words_count_next_value1 <= (uart_1_words_count + 1'd1); + uart_1_words_count_next_value_ce1 <= 1'd1; + uart_1_address_next_value4 <= (uart_1_address + uart_1_incr); + uart_1_address_next_value_ce4 <= 1'd1; + if ((uart_1_words_count == (uart_1_length - 1'd1))) begin + subfragments_next_state <= 1'd0; + end else begin + subfragments_next_state <= 3'd5; + end + end + end + end + default: begin + uart_1_is_ongoing <= 1'd1; + uart_1_phy_rx_source_ready <= 1'd1; + uart_1_bytes_count_next_value0 <= 1'd0; + uart_1_bytes_count_next_value_ce0 <= 1'd1; + uart_1_words_count_next_value1 <= 1'd0; + uart_1_words_count_next_value_ce1 <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_cmd_next_value2 <= uart_1_phy_rx_source_payload_data; + uart_1_cmd_next_value_ce2 <= 1'd1; + subfragments_next_state <= 1'd1; + end + end + endcase +end +assign uart_1_done = (uart_1_count == 1'd0); +assign digital43 = dshot_0_storage; +always @(*) begin + basesoc_basesoc_wishbone_dat_r <= 32'd0; + basesoc_basesoc_adr <= 14'd0; + basesoc_basesoc_we <= 1'd0; + basesoc_basesoc_dat_w <= 32'd0; + basesoc_basesoc_wishbone_ack <= 1'd0; + basesoc_next_state <= 1'd0; + basesoc_next_state <= basesoc_state; + case (basesoc_state) + 1'd1: begin + basesoc_basesoc_wishbone_ack <= 1'd1; + basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r; + basesoc_next_state <= 1'd0; + end + default: begin + basesoc_basesoc_dat_w <= basesoc_basesoc_wishbone_dat_w; + if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin + basesoc_basesoc_adr <= basesoc_basesoc_wishbone_adr; + basesoc_basesoc_we <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0)); + basesoc_next_state <= 1'd1; + end + end + endcase +end +assign basesoc_shared_adr = array_muxed0; +assign basesoc_shared_dat_w = array_muxed1; +assign basesoc_shared_sel = array_muxed2; +assign basesoc_shared_cyc = array_muxed3; +assign basesoc_shared_stb = array_muxed4; +assign basesoc_shared_we = array_muxed5; +assign basesoc_shared_cti = array_muxed6; +assign basesoc_shared_bte = array_muxed7; +assign basesoc_ibus_dat_r = basesoc_shared_dat_r; +assign basesoc_dbus_dat_r = basesoc_shared_dat_r; +assign uart_1_wishbone_dat_r = basesoc_shared_dat_r; +assign basesoc_ibus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd0)); +assign basesoc_dbus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd1)); +assign uart_1_wishbone_ack = (basesoc_shared_ack & (basesoc_grant == 2'd2)); +assign basesoc_ibus_err = (basesoc_shared_err & (basesoc_grant == 1'd0)); +assign basesoc_dbus_err = (basesoc_shared_err & (basesoc_grant == 1'd1)); +assign uart_1_wishbone_err = (basesoc_shared_err & (basesoc_grant == 2'd2)); +assign basesoc_request = {uart_1_wishbone_cyc, basesoc_dbus_cyc, basesoc_ibus_cyc}; +always @(*) begin + basesoc_slave_sel <= 3'd0; + basesoc_slave_sel[0] <= (basesoc_shared_adr[29:14] == 1'd0); + basesoc_slave_sel[1] <= (basesoc_shared_adr[29:17] == 2'd2); + basesoc_slave_sel[2] <= (basesoc_shared_adr[29:14] == 16'd65520); +end +assign basesoc_ram_bus_adr = basesoc_shared_adr; +assign basesoc_ram_bus_dat_w = basesoc_shared_dat_w; +assign basesoc_ram_bus_sel = basesoc_shared_sel; +assign basesoc_ram_bus_stb = basesoc_shared_stb; +assign basesoc_ram_bus_we = basesoc_shared_we; +assign basesoc_ram_bus_cti = basesoc_shared_cti; +assign basesoc_ram_bus_bte = basesoc_shared_bte; +assign sram_bus_adr = basesoc_shared_adr; +assign sram_bus_dat_w = basesoc_shared_dat_w; +assign sram_bus_sel = basesoc_shared_sel; +assign sram_bus_stb = basesoc_shared_stb; +assign sram_bus_we = basesoc_shared_we; +assign sram_bus_cti = basesoc_shared_cti; +assign sram_bus_bte = basesoc_shared_bte; +assign basesoc_basesoc_wishbone_adr = basesoc_shared_adr; +assign basesoc_basesoc_wishbone_dat_w = basesoc_shared_dat_w; +assign basesoc_basesoc_wishbone_sel = basesoc_shared_sel; +assign basesoc_basesoc_wishbone_stb = basesoc_shared_stb; +assign basesoc_basesoc_wishbone_we = basesoc_shared_we; +assign basesoc_basesoc_wishbone_cti = basesoc_shared_cti; +assign basesoc_basesoc_wishbone_bte = basesoc_shared_bte; +assign basesoc_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[0]); +assign sram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[1]); +assign basesoc_basesoc_wishbone_cyc = (basesoc_shared_cyc & basesoc_slave_sel[2]); +assign basesoc_shared_err = ((basesoc_ram_bus_err | sram_bus_err) | basesoc_basesoc_wishbone_err); +assign basesoc_wait = ((basesoc_shared_stb & basesoc_shared_cyc) & (~basesoc_shared_ack)); +always @(*) begin + basesoc_shared_ack <= 1'd0; + basesoc_shared_dat_r <= 32'd0; + basesoc_error <= 1'd0; + basesoc_shared_ack <= ((basesoc_ram_bus_ack | sram_bus_ack) | basesoc_basesoc_wishbone_ack); + basesoc_shared_dat_r <= ((({32{basesoc_slave_sel_r[0]}} & basesoc_ram_bus_dat_r) | ({32{basesoc_slave_sel_r[1]}} & sram_bus_dat_r)) | ({32{basesoc_slave_sel_r[2]}} & basesoc_basesoc_wishbone_dat_r)); + if (basesoc_done) begin + basesoc_shared_dat_r <= 32'd4294967295; + basesoc_shared_ack <= 1'd1; + basesoc_error <= 1'd1; + end +end +assign basesoc_done = (basesoc_count == 1'd0); +assign basesoc_csr_bankarray_csrbank0_sel = (basesoc_csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd4); +assign basesoc_csr_bankarray_csrbank0_in_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank0_in_re <= 1'd0; + basesoc_csr_bankarray_csrbank0_in_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank0_sel & (basesoc_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank0_in_re <= basesoc_csr_bankarray_interface0_bank_bus_we; + basesoc_csr_bankarray_csrbank0_in_we <= (~basesoc_csr_bankarray_interface0_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank0_in_w = buttons_status[1:0]; +assign buttons_we = basesoc_csr_bankarray_csrbank0_in_we; +assign basesoc_csr_bankarray_csrbank1_sel = (basesoc_csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd7); +assign basesoc_csr_bankarray_csrbank1_reset0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank1_reset0_re <= 1'd0; + basesoc_csr_bankarray_csrbank1_reset0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank1_reset0_re <= basesoc_csr_bankarray_interface1_bank_bus_we; + basesoc_csr_bankarray_csrbank1_reset0_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank1_scratch0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank1_scratch0_we <= 1'd0; + basesoc_csr_bankarray_csrbank1_scratch0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank1_scratch0_re <= basesoc_csr_bankarray_interface1_bank_bus_we; + basesoc_csr_bankarray_csrbank1_scratch0_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank1_bus_errors_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank1_bus_errors_re <= 1'd0; + basesoc_csr_bankarray_csrbank1_bus_errors_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank1_bus_errors_re <= basesoc_csr_bankarray_interface1_bank_bus_we; + basesoc_csr_bankarray_csrbank1_bus_errors_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we); + end +end +always @(*) begin + basesoc_soc_rst <= 1'd0; + if (basesoc_reset_re) begin + basesoc_soc_rst <= basesoc_reset_storage[0]; + end +end +assign basesoc_cpu_rst = basesoc_reset_storage[1]; +assign basesoc_csr_bankarray_csrbank1_reset0_w = basesoc_reset_storage[1:0]; +assign basesoc_csr_bankarray_csrbank1_scratch0_w = basesoc_scratch_storage[31:0]; +assign basesoc_csr_bankarray_csrbank1_bus_errors_w = basesoc_bus_errors_status[31:0]; +assign basesoc_bus_errors_we = basesoc_csr_bankarray_csrbank1_bus_errors_we; +assign basesoc_csr_bankarray_csrbank2_sel = (basesoc_csr_bankarray_interface2_bank_bus_adr[13:9] == 1'd1); +assign basesoc_csr_bankarray_csrbank2_id1_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[24:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank2_id1_we <= 1'd0; + basesoc_csr_bankarray_csrbank2_id1_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank2_sel & (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank2_id1_re <= basesoc_csr_bankarray_interface2_bank_bus_we; + basesoc_csr_bankarray_csrbank2_id1_we <= (~basesoc_csr_bankarray_interface2_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank2_id0_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank2_id0_re <= 1'd0; + basesoc_csr_bankarray_csrbank2_id0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank2_sel & (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank2_id0_re <= basesoc_csr_bankarray_interface2_bank_bus_we; + basesoc_csr_bankarray_csrbank2_id0_we <= (~basesoc_csr_bankarray_interface2_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank2_id1_w = dna_status[56:32]; +assign basesoc_csr_bankarray_csrbank2_id0_w = dna_status[31:0]; +assign dna_we = basesoc_csr_bankarray_csrbank2_id0_we; +assign basesoc_csr_bankarray_csrbank3_sel = (basesoc_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd6); +assign basesoc_csr_bankarray_csrbank3_out0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank3_out0_we <= 1'd0; + basesoc_csr_bankarray_csrbank3_out0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank3_sel & (basesoc_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank3_out0_re <= basesoc_csr_bankarray_interface3_bank_bus_we; + basesoc_csr_bankarray_csrbank3_out0_we <= (~basesoc_csr_bankarray_interface3_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank3_out0_w = dshot_0_storage; +assign basesoc_csr_bankarray_csrbank4_sel = (basesoc_csr_bankarray_interface4_bank_bus_adr[13:9] == 3'd5); +assign basesoc_csr_bankarray_csrbank4_w0_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[2:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank4_w0_re <= 1'd0; + basesoc_csr_bankarray_csrbank4_w0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank4_sel & (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank4_w0_re <= basesoc_csr_bankarray_interface4_bank_bus_we; + basesoc_csr_bankarray_csrbank4_w0_we <= (~basesoc_csr_bankarray_interface4_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank4_r_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank4_r_re <= 1'd0; + basesoc_csr_bankarray_csrbank4_r_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank4_sel & (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank4_r_re <= basesoc_csr_bankarray_interface4_bank_bus_we; + basesoc_csr_bankarray_csrbank4_r_we <= (~basesoc_csr_bankarray_interface4_bank_bus_we); + end +end +assign scl = _w_storage[0]; +assign oe = _w_storage[1]; +assign sda0 = _w_storage[2]; +assign basesoc_csr_bankarray_csrbank4_w0_w = _w_storage[2:0]; +assign _r_status = sda1; +assign basesoc_csr_bankarray_csrbank4_r_w = _r_status; +assign _r_we = basesoc_csr_bankarray_csrbank4_r_we; +assign basesoc_csr_bankarray_sel = (basesoc_csr_bankarray_sram_bus_adr[13:9] == 4'd8); +always @(*) begin + basesoc_csr_bankarray_sram_bus_dat_r <= 32'd0; + if (basesoc_csr_bankarray_sel_r) begin + basesoc_csr_bankarray_sram_bus_dat_r <= basesoc_csr_bankarray_dat_r; + end +end +assign basesoc_csr_bankarray_adr = basesoc_csr_bankarray_sram_bus_adr[4:0]; +assign basesoc_csr_bankarray_csrbank5_sel = (basesoc_csr_bankarray_interface5_bank_bus_adr[13:9] == 2'd3); +assign basesoc_csr_bankarray_csrbank5_out0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank5_out0_re <= 1'd0; + basesoc_csr_bankarray_csrbank5_out0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank5_sel & (basesoc_csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank5_out0_re <= basesoc_csr_bankarray_interface5_bank_bus_we; + basesoc_csr_bankarray_csrbank5_out0_we <= (~basesoc_csr_bankarray_interface5_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank5_out0_w = leds_storage[1:0]; +assign basesoc_csr_bankarray_csrbank6_sel = (basesoc_csr_bankarray_interface6_bank_bus_adr[13:9] == 4'd9); +assign basesoc_csr_bankarray_csrbank6_load0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_load0_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_load0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank6_load0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_load0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_reload0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_reload0_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_reload0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank6_reload0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_reload0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_en0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_en0_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_en0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank6_en0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_en0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_update_value0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_update_value0_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_update_value0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csr_bankarray_csrbank6_update_value0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_update_value0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_value_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_value_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_value_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csr_bankarray_csrbank6_value_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_value_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_ev_status_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_ev_status_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_ev_status_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csr_bankarray_csrbank6_ev_status_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_ev_status_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_ev_pending_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_ev_pending_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_ev_pending_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd6))) begin + basesoc_csr_bankarray_csrbank6_ev_pending_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_ev_pending_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_ev_enable0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_ev_enable0_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_ev_enable0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd7))) begin + basesoc_csr_bankarray_csrbank6_ev_enable0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_ev_enable0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_load0_w = basesoc_timer_load_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_reload0_w = basesoc_timer_reload_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_en0_w = basesoc_timer_en_storage; +assign basesoc_csr_bankarray_csrbank6_update_value0_w = basesoc_timer_update_value_storage; +assign basesoc_csr_bankarray_csrbank6_value_w = basesoc_timer_value_status[31:0]; +assign basesoc_timer_value_we = basesoc_csr_bankarray_csrbank6_value_we; +assign basesoc_timer_status_status = basesoc_timer_zero0; +assign basesoc_csr_bankarray_csrbank6_ev_status_w = basesoc_timer_status_status; +assign basesoc_timer_status_we = basesoc_csr_bankarray_csrbank6_ev_status_we; +assign basesoc_timer_pending_status = basesoc_timer_zero1; +assign basesoc_csr_bankarray_csrbank6_ev_pending_w = basesoc_timer_pending_status; +assign basesoc_timer_pending_we = basesoc_csr_bankarray_csrbank6_ev_pending_we; +assign basesoc_timer_zero2 = basesoc_timer_enable_storage; +assign basesoc_csr_bankarray_csrbank6_ev_enable0_w = basesoc_timer_enable_storage; +assign basesoc_csr_bankarray_csrbank7_sel = (basesoc_csr_bankarray_interface7_bank_bus_adr[13:9] == 4'd10); +assign basesoc_uart_rxtx_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[7:0]; +always @(*) begin + basesoc_uart_rxtx_we <= 1'd0; + basesoc_uart_rxtx_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_uart_rxtx_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_uart_rxtx_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_txfull_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_txfull_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_txfull_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank7_txfull_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_txfull_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_rxempty_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_rxempty_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_rxempty_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank7_rxempty_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_rxempty_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_ev_status_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_ev_status_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_ev_status_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csr_bankarray_csrbank7_ev_status_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_ev_status_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_ev_pending_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_ev_pending_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_ev_pending_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csr_bankarray_csrbank7_ev_pending_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_ev_pending_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_ev_enable0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_ev_enable0_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_ev_enable0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csr_bankarray_csrbank7_ev_enable0_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_ev_enable0_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_txempty_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_txempty_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_txempty_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd6))) begin + basesoc_csr_bankarray_csrbank7_txempty_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_txempty_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_rxfull_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_rxfull_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_rxfull_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd7))) begin + basesoc_csr_bankarray_csrbank7_rxfull_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_rxfull_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_txfull_w = basesoc_uart_txfull_status; +assign basesoc_uart_txfull_we = basesoc_csr_bankarray_csrbank7_txfull_we; +assign basesoc_csr_bankarray_csrbank7_rxempty_w = basesoc_uart_rxempty_status; +assign basesoc_uart_rxempty_we = basesoc_csr_bankarray_csrbank7_rxempty_we; +always @(*) begin + basesoc_uart_status_status <= 2'd0; + basesoc_uart_status_status[0] <= basesoc_uart_tx0; + basesoc_uart_status_status[1] <= basesoc_uart_rx0; +end +assign basesoc_csr_bankarray_csrbank7_ev_status_w = basesoc_uart_status_status[1:0]; +assign basesoc_uart_status_we = basesoc_csr_bankarray_csrbank7_ev_status_we; +always @(*) begin + basesoc_uart_pending_status <= 2'd0; + basesoc_uart_pending_status[0] <= basesoc_uart_tx1; + basesoc_uart_pending_status[1] <= basesoc_uart_rx1; +end +assign basesoc_csr_bankarray_csrbank7_ev_pending_w = basesoc_uart_pending_status[1:0]; +assign basesoc_uart_pending_we = basesoc_csr_bankarray_csrbank7_ev_pending_we; +assign basesoc_uart_tx2 = basesoc_uart_enable_storage[0]; +assign basesoc_uart_rx2 = basesoc_uart_enable_storage[1]; +assign basesoc_csr_bankarray_csrbank7_ev_enable0_w = basesoc_uart_enable_storage[1:0]; +assign basesoc_csr_bankarray_csrbank7_txempty_w = basesoc_uart_txempty_status; +assign basesoc_uart_txempty_we = basesoc_csr_bankarray_csrbank7_txempty_we; +assign basesoc_csr_bankarray_csrbank7_rxfull_w = basesoc_uart_rxfull_status; +assign basesoc_uart_rxfull_we = basesoc_csr_bankarray_csrbank7_rxfull_we; +assign basesoc_csr_bankarray_csrbank8_sel = (basesoc_csr_bankarray_interface8_bank_bus_adr[13:9] == 2'd2); +assign basesoc_csr_bankarray_csrbank8_temperature_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_temperature_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_temperature_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank8_temperature_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_temperature_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_vccint_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_vccint_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_vccint_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank8_vccint_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_vccint_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_vccaux_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_vccaux_re <= 1'd0; + basesoc_csr_bankarray_csrbank8_vccaux_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank8_vccaux_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_vccaux_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_vccbram_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_vccbram_re <= 1'd0; + basesoc_csr_bankarray_csrbank8_vccbram_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csr_bankarray_csrbank8_vccbram_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_vccbram_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_eoc_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_eoc_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_eoc_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csr_bankarray_csrbank8_eoc_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_eoc_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_eos_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_eos_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_eos_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csr_bankarray_csrbank8_eos_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_eos_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_temperature_w = xadc_temperature_status[11:0]; +assign xadc_temperature_we = basesoc_csr_bankarray_csrbank8_temperature_we; +assign basesoc_csr_bankarray_csrbank8_vccint_w = xadc_vccint_status[11:0]; +assign xadc_vccint_we = basesoc_csr_bankarray_csrbank8_vccint_we; +assign basesoc_csr_bankarray_csrbank8_vccaux_w = xadc_vccaux_status[11:0]; +assign xadc_vccaux_we = basesoc_csr_bankarray_csrbank8_vccaux_we; +assign basesoc_csr_bankarray_csrbank8_vccbram_w = xadc_vccbram_status[11:0]; +assign xadc_vccbram_we = basesoc_csr_bankarray_csrbank8_vccbram_we; +assign basesoc_csr_bankarray_csrbank8_eoc_w = xadc_eoc_status; +assign xadc_eoc_we = basesoc_csr_bankarray_csrbank8_eoc_we; +assign basesoc_csr_bankarray_csrbank8_eos_w = xadc_eos_status; +assign xadc_eos_we = basesoc_csr_bankarray_csrbank8_eos_we; +assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr; +assign basesoc_csr_interconnect_we = basesoc_basesoc_we; +assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w; +assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r; +assign basesoc_csr_bankarray_interface0_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface1_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface2_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface3_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface4_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface5_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface6_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface7_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface8_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_sram_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface0_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface1_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface2_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface3_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface4_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface5_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface6_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface7_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface8_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_sram_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface2_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface3_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface4_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface5_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface6_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface7_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface8_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_sram_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_interconnect_dat_r = (((((((((basesoc_csr_bankarray_interface0_bank_bus_dat_r | basesoc_csr_bankarray_interface1_bank_bus_dat_r) | basesoc_csr_bankarray_interface2_bank_bus_dat_r) | basesoc_csr_bankarray_interface3_bank_bus_dat_r) | basesoc_csr_bankarray_interface4_bank_bus_dat_r) | basesoc_csr_bankarray_interface5_bank_bus_dat_r) | basesoc_csr_bankarray_interface6_bank_bus_dat_r) | basesoc_csr_bankarray_interface7_bank_bus_dat_r) | basesoc_csr_bankarray_interface8_bank_bus_dat_r) | basesoc_csr_bankarray_sram_bus_dat_r); +always @(*) begin + array_muxed0 <= 30'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed0 <= basesoc_ibus_adr; + end + 1'd1: begin + array_muxed0 <= basesoc_dbus_adr; + end + default: begin + array_muxed0 <= uart_1_wishbone_adr; + end + endcase +end +always @(*) begin + array_muxed1 <= 32'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed1 <= basesoc_ibus_dat_w; + end + 1'd1: begin + array_muxed1 <= basesoc_dbus_dat_w; + end + default: begin + array_muxed1 <= uart_1_wishbone_dat_w; + end + endcase +end +always @(*) begin + array_muxed2 <= 4'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed2 <= basesoc_ibus_sel; + end + 1'd1: begin + array_muxed2 <= basesoc_dbus_sel; + end + default: begin + array_muxed2 <= uart_1_wishbone_sel; + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed3 <= basesoc_ibus_cyc; + end + 1'd1: begin + array_muxed3 <= basesoc_dbus_cyc; + end + default: begin + array_muxed3 <= uart_1_wishbone_cyc; + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed4 <= basesoc_ibus_stb; + end + 1'd1: begin + array_muxed4 <= basesoc_dbus_stb; + end + default: begin + array_muxed4 <= uart_1_wishbone_stb; + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed5 <= basesoc_ibus_we; + end + 1'd1: begin + array_muxed5 <= basesoc_dbus_we; + end + default: begin + array_muxed5 <= uart_1_wishbone_we; + end + endcase +end +always @(*) begin + array_muxed6 <= 3'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed6 <= basesoc_ibus_cti; + end + 1'd1: begin + array_muxed6 <= basesoc_dbus_cti; + end + default: begin + array_muxed6 <= uart_1_wishbone_cti; + end + endcase +end +always @(*) begin + array_muxed7 <= 2'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed7 <= basesoc_ibus_bte; + end + 1'd1: begin + array_muxed7 <= basesoc_dbus_bte; + end + default: begin + array_muxed7 <= uart_1_wishbone_bte; + end + endcase +end +assign basesoc_rx_rx = xilinxmultiregimpl0_regs1; +assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked); +assign buttons_status = xilinxmultiregimpl1_regs1; +assign xilinxmultiregimpl1 = {user_btn1, user_btn0}; +assign uart_1_phy_rx_rx = xilinxmultiregimpl2_regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge idelay_clk) begin + if ((crg_reset_counter != 1'd0)) begin + crg_reset_counter <= (crg_reset_counter - 1'd1); + end else begin + crg_ic_reset <= 1'd0; + end + if (idelay_rst) begin + crg_reset_counter <= 4'd15; + crg_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + if ((basesoc_bus_errors != 32'd4294967295)) begin + if (basesoc_bus_error) begin + basesoc_bus_errors <= (basesoc_bus_errors + 1'd1); + end + end + {basesoc_tx_tick, basesoc_tx_phase} <= 23'd4947802; + if (basesoc_tx_enable) begin + {basesoc_tx_tick, basesoc_tx_phase} <= (basesoc_tx_phase + 23'd4947802); + end + subfragments_rs232phytx0_state <= subfragments_rs232phytx0_next_state; + if (basesoc_tx_count_rs232phytx0_next_value_ce0) begin + basesoc_tx_count <= basesoc_tx_count_rs232phytx0_next_value0; + end + if (basesoc_serial_tx_rs232phytx0_next_value_ce1) begin + serial_tx <= basesoc_serial_tx_rs232phytx0_next_value1; + end + if (basesoc_tx_data_rs232phytx0_next_value_ce2) begin + basesoc_tx_data <= basesoc_tx_data_rs232phytx0_next_value2; + end + basesoc_rx_rx_d <= basesoc_rx_rx; + {basesoc_rx_tick, basesoc_rx_phase} <= 32'd2147483648; + if (basesoc_rx_enable) begin + {basesoc_rx_tick, basesoc_rx_phase} <= (basesoc_rx_phase + 23'd4947802); + end + subfragments_rs232phyrx0_state <= subfragments_rs232phyrx0_next_state; + if (basesoc_rx_count_rs232phyrx0_next_value_ce0) begin + basesoc_rx_count <= basesoc_rx_count_rs232phyrx0_next_value0; + end + if (basesoc_rx_data_rs232phyrx0_next_value_ce1) begin + basesoc_rx_data <= basesoc_rx_data_rs232phyrx0_next_value1; + end + if (basesoc_uart_tx_clear) begin + basesoc_uart_tx_pending <= 1'd0; + end + basesoc_uart_tx_trigger_d <= basesoc_uart_tx_trigger; + if ((basesoc_uart_tx_trigger & (~basesoc_uart_tx_trigger_d))) begin + basesoc_uart_tx_pending <= 1'd1; + end + if (basesoc_uart_rx_clear) begin + basesoc_uart_rx_pending <= 1'd0; + end + basesoc_uart_rx_trigger_d <= basesoc_uart_rx_trigger; + if ((basesoc_uart_rx_trigger & (~basesoc_uart_rx_trigger_d))) begin + basesoc_uart_rx_pending <= 1'd1; + end + if (basesoc_uart_tx_fifo_syncfifo_re) begin + basesoc_uart_tx_fifo_readable <= 1'd1; + end else begin + if (basesoc_uart_tx_fifo_re) begin + basesoc_uart_tx_fifo_readable <= 1'd0; + end + end + if (((basesoc_uart_tx_fifo_syncfifo_we & basesoc_uart_tx_fifo_syncfifo_writable) & (~basesoc_uart_tx_fifo_replace))) begin + basesoc_uart_tx_fifo_produce <= (basesoc_uart_tx_fifo_produce + 1'd1); + end + if (basesoc_uart_tx_fifo_do_read) begin + basesoc_uart_tx_fifo_consume <= (basesoc_uart_tx_fifo_consume + 1'd1); + end + if (((basesoc_uart_tx_fifo_syncfifo_we & basesoc_uart_tx_fifo_syncfifo_writable) & (~basesoc_uart_tx_fifo_replace))) begin + if ((~basesoc_uart_tx_fifo_do_read)) begin + basesoc_uart_tx_fifo_level0 <= (basesoc_uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (basesoc_uart_tx_fifo_do_read) begin + basesoc_uart_tx_fifo_level0 <= (basesoc_uart_tx_fifo_level0 - 1'd1); + end + end + if (basesoc_uart_rx_fifo_syncfifo_re) begin + basesoc_uart_rx_fifo_readable <= 1'd1; + end else begin + if (basesoc_uart_rx_fifo_re) begin + basesoc_uart_rx_fifo_readable <= 1'd0; + end + end + if (((basesoc_uart_rx_fifo_syncfifo_we & basesoc_uart_rx_fifo_syncfifo_writable) & (~basesoc_uart_rx_fifo_replace))) begin + basesoc_uart_rx_fifo_produce <= (basesoc_uart_rx_fifo_produce + 1'd1); + end + if (basesoc_uart_rx_fifo_do_read) begin + basesoc_uart_rx_fifo_consume <= (basesoc_uart_rx_fifo_consume + 1'd1); + end + if (((basesoc_uart_rx_fifo_syncfifo_we & basesoc_uart_rx_fifo_syncfifo_writable) & (~basesoc_uart_rx_fifo_replace))) begin + if ((~basesoc_uart_rx_fifo_do_read)) begin + basesoc_uart_rx_fifo_level0 <= (basesoc_uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (basesoc_uart_rx_fifo_do_read) begin + basesoc_uart_rx_fifo_level0 <= (basesoc_uart_rx_fifo_level0 - 1'd1); + end + end + if (basesoc_timer_en_storage) begin + if ((basesoc_timer_value == 1'd0)) begin + basesoc_timer_value <= basesoc_timer_reload_storage; + end else begin + basesoc_timer_value <= (basesoc_timer_value - 1'd1); + end + end else begin + basesoc_timer_value <= basesoc_timer_load_storage; + end + if (basesoc_timer_update_value_re) begin + basesoc_timer_value_status <= basesoc_timer_value; + end + if (basesoc_timer_zero_clear) begin + basesoc_timer_zero_pending <= 1'd0; + end + basesoc_timer_zero_trigger_d <= basesoc_timer_zero_trigger; + if ((basesoc_timer_zero_trigger & (~basesoc_timer_zero_trigger_d))) begin + basesoc_timer_zero_pending <= 1'd1; + end + if (directory0_re) begin + csrstorage0_storage <= directory0_r; + end + csrstorage0_re <= directory0_re; + if (csr_08000_re) begin + csrstorage1_storage <= csr_08000_r; + end + csrstorage1_re <= csr_08000_re; + basesoc_ram_bus_ack <= 1'd0; + if (((basesoc_ram_bus_cyc & basesoc_ram_bus_stb) & (~basesoc_ram_bus_ack))) begin + basesoc_ram_bus_ack <= 1'd1; + end + if ((dna_count < 7'd114)) begin + dna_count <= (dna_count + 1'd1); + if (dna_clk) begin + dna_status <= {dna_status, dna_do}; + end + end + if (xadc_drdy) begin + case (xadc_channel) + 1'd0: begin + xadc_temperature_status <= (xadc_do >>> 3'd4); + end + 1'd1: begin + xadc_vccint_status <= (xadc_do >>> 3'd4); + end + 2'd2: begin + xadc_vccaux_status <= (xadc_do >>> 3'd4); + end + 3'd6: begin + xadc_vccbram_status <= (xadc_do >>> 3'd4); + end + endcase + end + xadc_eoc_status <= ((xadc_eoc_status & (~xadc_eoc_we)) | xadc_eoc); + xadc_eos_status <= ((xadc_eos_status & (~xadc_eos_we)) | xadc_eos); + if (leds_done) begin + leds_chaser <= {leds_chaser, (~leds_chaser[1])}; + end + if (leds_re) begin + leds_mode <= 1'd1; + end + if (leds_wait) begin + if ((~leds_done)) begin + leds_count <= (leds_count - 1'd1); + end + end else begin + leds_count <= 25'd25000000; + end + {uart_1_phy_tx_tick, uart_1_phy_tx_phase} <= 23'd4947802; + if (uart_1_phy_tx_enable) begin + {uart_1_phy_tx_tick, uart_1_phy_tx_phase} <= (uart_1_phy_tx_phase + 23'd4947802); + end + subfragments_rs232phytx1_state <= subfragments_rs232phytx1_next_state; + if (uart_1_phy_tx_count_rs232phytx1_next_value_ce0) begin + uart_1_phy_tx_count <= uart_1_phy_tx_count_rs232phytx1_next_value0; + end + if (tx_obj_rs232phytx1_next_value_ce1) begin + digital10 <= tx_obj_rs232phytx1_next_value1; + end + if (uart_1_phy_tx_data_rs232phytx1_next_value_ce2) begin + uart_1_phy_tx_data <= uart_1_phy_tx_data_rs232phytx1_next_value2; + end + uart_1_phy_rx_rx_d <= uart_1_phy_rx_rx; + {uart_1_phy_rx_tick, uart_1_phy_rx_phase} <= 32'd2147483648; + if (uart_1_phy_rx_enable) begin + {uart_1_phy_rx_tick, uart_1_phy_rx_phase} <= (uart_1_phy_rx_phase + 23'd4947802); + end + subfragments_rs232phyrx1_state <= subfragments_rs232phyrx1_next_state; + if (uart_1_phy_rx_count_rs232phyrx1_next_value_ce0) begin + uart_1_phy_rx_count <= uart_1_phy_rx_count_rs232phyrx1_next_value0; + end + if (uart_1_phy_rx_data_rs232phyrx1_next_value_ce1) begin + uart_1_phy_rx_data <= uart_1_phy_rx_data_rs232phyrx1_next_value1; + end + subfragments_state <= subfragments_next_state; + if (uart_1_bytes_count_next_value_ce0) begin + uart_1_bytes_count <= uart_1_bytes_count_next_value0; + end + if (uart_1_words_count_next_value_ce1) begin + uart_1_words_count <= uart_1_words_count_next_value1; + end + if (uart_1_cmd_next_value_ce2) begin + uart_1_cmd <= uart_1_cmd_next_value2; + end + if (uart_1_length_next_value_ce3) begin + uart_1_length <= uart_1_length_next_value3; + end + if (uart_1_address_next_value_ce4) begin + uart_1_address <= uart_1_address_next_value4; + end + if (uart_1_incr_next_value_ce5) begin + uart_1_incr <= uart_1_incr_next_value5; + end + if (uart_1_data_next_value_ce6) begin + uart_1_data <= uart_1_data_next_value6; + end + if (uart_1_reset) begin + uart_1_incr <= 1'd0; + subfragments_state <= 3'd0; + end + if (uart_1_wait) begin + if ((~uart_1_done)) begin + uart_1_count <= (uart_1_count - 1'd1); + end + end else begin + uart_1_count <= 24'd10000000; + end + basesoc_state <= basesoc_next_state; + case (basesoc_grant) + 1'd0: begin + if ((~basesoc_request[0])) begin + if (basesoc_request[1]) begin + basesoc_grant <= 1'd1; + end else begin + if (basesoc_request[2]) begin + basesoc_grant <= 2'd2; + end + end + end + end + 1'd1: begin + if ((~basesoc_request[1])) begin + if (basesoc_request[2]) begin + basesoc_grant <= 2'd2; + end else begin + if (basesoc_request[0]) begin + basesoc_grant <= 1'd0; + end + end + end + end + 2'd2: begin + if ((~basesoc_request[2])) begin + if (basesoc_request[0]) begin + basesoc_grant <= 1'd0; + end else begin + if (basesoc_request[1]) begin + basesoc_grant <= 1'd1; + end + end + end + end + endcase + basesoc_slave_sel_r <= basesoc_slave_sel; + if (basesoc_wait) begin + if ((~basesoc_done)) begin + basesoc_count <= (basesoc_count - 1'd1); + end + end else begin + basesoc_count <= 20'd1000000; + end + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank0_sel) begin + case (basesoc_csr_bankarray_interface0_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_in_w; + end + endcase + end + buttons_re <= basesoc_csr_bankarray_csrbank0_in_re; + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank1_sel) begin + case (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_reset0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_scratch0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_bus_errors_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank1_reset0_re) begin + basesoc_reset_storage[1:0] <= basesoc_csr_bankarray_csrbank1_reset0_r; + end + basesoc_reset_re <= basesoc_csr_bankarray_csrbank1_reset0_re; + if (basesoc_csr_bankarray_csrbank1_scratch0_re) begin + basesoc_scratch_storage[31:0] <= basesoc_csr_bankarray_csrbank1_scratch0_r; + end + basesoc_scratch_re <= basesoc_csr_bankarray_csrbank1_scratch0_re; + basesoc_bus_errors_re <= basesoc_csr_bankarray_csrbank1_bus_errors_re; + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank2_sel) begin + case (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_id1_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_id0_w; + end + endcase + end + dna_re <= basesoc_csr_bankarray_csrbank2_id0_re; + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank3_sel) begin + case (basesoc_csr_bankarray_interface3_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_out0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank3_out0_re) begin + dshot_0_storage <= basesoc_csr_bankarray_csrbank3_out0_r; + end + dshot_0_re <= basesoc_csr_bankarray_csrbank3_out0_re; + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank4_sel) begin + case (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_w0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_r_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank4_w0_re) begin + _w_storage[2:0] <= basesoc_csr_bankarray_csrbank4_w0_r; + end + _w_re <= basesoc_csr_bankarray_csrbank4_w0_re; + _r_re <= basesoc_csr_bankarray_csrbank4_r_re; + basesoc_csr_bankarray_sel_r <= basesoc_csr_bankarray_sel; + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank5_sel) begin + case (basesoc_csr_bankarray_interface5_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_out0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank5_out0_re) begin + leds_storage[1:0] <= basesoc_csr_bankarray_csrbank5_out0_r; + end + leds_re <= basesoc_csr_bankarray_csrbank5_out0_re; + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank6_sel) begin + case (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_load0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_reload0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_en0_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_update_value0_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_value_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_status_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_pending_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_enable0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank6_load0_re) begin + basesoc_timer_load_storage[31:0] <= basesoc_csr_bankarray_csrbank6_load0_r; + end + basesoc_timer_load_re <= basesoc_csr_bankarray_csrbank6_load0_re; + if (basesoc_csr_bankarray_csrbank6_reload0_re) begin + basesoc_timer_reload_storage[31:0] <= basesoc_csr_bankarray_csrbank6_reload0_r; + end + basesoc_timer_reload_re <= basesoc_csr_bankarray_csrbank6_reload0_re; + if (basesoc_csr_bankarray_csrbank6_en0_re) begin + basesoc_timer_en_storage <= basesoc_csr_bankarray_csrbank6_en0_r; + end + basesoc_timer_en_re <= basesoc_csr_bankarray_csrbank6_en0_re; + if (basesoc_csr_bankarray_csrbank6_update_value0_re) begin + basesoc_timer_update_value_storage <= basesoc_csr_bankarray_csrbank6_update_value0_r; + end + basesoc_timer_update_value_re <= basesoc_csr_bankarray_csrbank6_update_value0_re; + basesoc_timer_value_re <= basesoc_csr_bankarray_csrbank6_value_re; + basesoc_timer_status_re <= basesoc_csr_bankarray_csrbank6_ev_status_re; + if (basesoc_csr_bankarray_csrbank6_ev_pending_re) begin + basesoc_timer_pending_r <= basesoc_csr_bankarray_csrbank6_ev_pending_r; + end + basesoc_timer_pending_re <= basesoc_csr_bankarray_csrbank6_ev_pending_re; + if (basesoc_csr_bankarray_csrbank6_ev_enable0_re) begin + basesoc_timer_enable_storage <= basesoc_csr_bankarray_csrbank6_ev_enable0_r; + end + basesoc_timer_enable_re <= basesoc_csr_bankarray_csrbank6_ev_enable0_re; + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank7_sel) begin + case (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_uart_rxtx_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_txfull_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_rxempty_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_status_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_pending_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_enable0_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_txempty_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_rxfull_w; + end + endcase + end + basesoc_uart_txfull_re <= basesoc_csr_bankarray_csrbank7_txfull_re; + basesoc_uart_rxempty_re <= basesoc_csr_bankarray_csrbank7_rxempty_re; + basesoc_uart_status_re <= basesoc_csr_bankarray_csrbank7_ev_status_re; + if (basesoc_csr_bankarray_csrbank7_ev_pending_re) begin + basesoc_uart_pending_r[1:0] <= basesoc_csr_bankarray_csrbank7_ev_pending_r; + end + basesoc_uart_pending_re <= basesoc_csr_bankarray_csrbank7_ev_pending_re; + if (basesoc_csr_bankarray_csrbank7_ev_enable0_re) begin + basesoc_uart_enable_storage[1:0] <= basesoc_csr_bankarray_csrbank7_ev_enable0_r; + end + basesoc_uart_enable_re <= basesoc_csr_bankarray_csrbank7_ev_enable0_re; + basesoc_uart_txempty_re <= basesoc_csr_bankarray_csrbank7_txempty_re; + basesoc_uart_rxfull_re <= basesoc_csr_bankarray_csrbank7_rxfull_re; + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank8_sel) begin + case (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_temperature_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccint_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccaux_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccbram_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_eoc_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_eos_w; + end + endcase + end + xadc_temperature_re <= basesoc_csr_bankarray_csrbank8_temperature_re; + xadc_vccint_re <= basesoc_csr_bankarray_csrbank8_vccint_re; + xadc_vccaux_re <= basesoc_csr_bankarray_csrbank8_vccaux_re; + xadc_vccbram_re <= basesoc_csr_bankarray_csrbank8_vccbram_re; + xadc_eoc_re <= basesoc_csr_bankarray_csrbank8_eoc_re; + xadc_eos_re <= basesoc_csr_bankarray_csrbank8_eos_re; + if (sys_rst) begin + basesoc_reset_storage <= 2'd0; + basesoc_reset_re <= 1'd0; + basesoc_scratch_storage <= 32'd305419896; + basesoc_scratch_re <= 1'd0; + basesoc_bus_errors_re <= 1'd0; + basesoc_bus_errors <= 32'd0; + serial_tx <= 1'd1; + basesoc_tx_tick <= 1'd0; + basesoc_rx_tick <= 1'd0; + basesoc_rx_rx_d <= 1'd0; + basesoc_uart_txfull_re <= 1'd0; + basesoc_uart_rxempty_re <= 1'd0; + basesoc_uart_tx_pending <= 1'd0; + basesoc_uart_tx_trigger_d <= 1'd0; + basesoc_uart_rx_pending <= 1'd0; + basesoc_uart_rx_trigger_d <= 1'd0; + basesoc_uart_status_re <= 1'd0; + basesoc_uart_pending_re <= 1'd0; + basesoc_uart_pending_r <= 2'd0; + basesoc_uart_enable_storage <= 2'd0; + basesoc_uart_enable_re <= 1'd0; + basesoc_uart_txempty_re <= 1'd0; + basesoc_uart_rxfull_re <= 1'd0; + basesoc_uart_tx_fifo_readable <= 1'd0; + basesoc_uart_tx_fifo_level0 <= 5'd0; + basesoc_uart_tx_fifo_produce <= 4'd0; + basesoc_uart_tx_fifo_consume <= 4'd0; + basesoc_uart_rx_fifo_readable <= 1'd0; + basesoc_uart_rx_fifo_level0 <= 5'd0; + basesoc_uart_rx_fifo_produce <= 4'd0; + basesoc_uart_rx_fifo_consume <= 4'd0; + basesoc_timer_load_storage <= 32'd0; + basesoc_timer_load_re <= 1'd0; + basesoc_timer_reload_storage <= 32'd0; + basesoc_timer_reload_re <= 1'd0; + basesoc_timer_en_storage <= 1'd0; + basesoc_timer_en_re <= 1'd0; + basesoc_timer_update_value_storage <= 1'd0; + basesoc_timer_update_value_re <= 1'd0; + basesoc_timer_value_status <= 32'd0; + basesoc_timer_value_re <= 1'd0; + basesoc_timer_zero_pending <= 1'd0; + basesoc_timer_zero_trigger_d <= 1'd0; + basesoc_timer_status_re <= 1'd0; + basesoc_timer_pending_re <= 1'd0; + basesoc_timer_pending_r <= 1'd0; + basesoc_timer_enable_storage <= 1'd0; + basesoc_timer_enable_re <= 1'd0; + basesoc_timer_value <= 32'd0; + csrstorage0_storage <= 1'd140989193; + csrstorage0_re <= 1'd0; + csrstorage1_storage <= 1'd0; + csrstorage1_re <= 1'd0; + basesoc_ram_bus_ack <= 1'd0; + dna_status <= 57'd0; + dna_re <= 1'd0; + dna_count <= 7'd0; + xadc_temperature_status <= 12'd0; + xadc_temperature_re <= 1'd0; + xadc_vccint_status <= 12'd0; + xadc_vccint_re <= 1'd0; + xadc_vccaux_status <= 12'd0; + xadc_vccaux_re <= 1'd0; + xadc_vccbram_status <= 12'd0; + xadc_vccbram_re <= 1'd0; + xadc_eoc_status <= 1'd0; + xadc_eoc_re <= 1'd0; + xadc_eos_status <= 1'd0; + xadc_eos_re <= 1'd0; + leds_storage <= 2'd0; + leds_re <= 1'd0; + leds_chaser <= 2'd0; + leds_mode <= 1'd0; + leds_count <= 25'd25000000; + buttons_re <= 1'd0; + _w_storage <= 3'd0; + _w_re <= 1'd0; + _r_re <= 1'd0; + digital10 <= 1'd1; + uart_1_phy_tx_tick <= 1'd0; + uart_1_phy_rx_tick <= 1'd0; + uart_1_phy_rx_rx_d <= 1'd0; + uart_1_incr <= 1'd0; + uart_1_count <= 24'd10000000; + dshot_0_storage <= 1'd0; + dshot_0_re <= 1'd0; + subfragments_rs232phytx0_state <= 1'd0; + subfragments_rs232phyrx0_state <= 1'd0; + subfragments_rs232phytx1_state <= 1'd0; + subfragments_rs232phyrx1_state <= 1'd0; + subfragments_state <= 3'd0; + basesoc_grant <= 2'd0; + basesoc_slave_sel_r <= 3'd0; + basesoc_count <= 20'd1000000; + basesoc_csr_bankarray_sel_r <= 1'd0; + basesoc_state <= 1'd0; + end + xilinxmultiregimpl0_regs0 <= serial_rx; + xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; + xilinxmultiregimpl1_regs0 <= {user_btn1, user_btn0}; + xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; + xilinxmultiregimpl2_regs0 <= digital11; + xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory mem: 24-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [7:0] mem[0:23]; +initial begin + $readmemh("mem.init", mem); +end +reg [4:0] mem_adr0; +always @(posedge sys_clk) begin + mem_adr0 <= basesoc_csr_bankarray_adr; +end +assign basesoc_csr_bankarray_dat_r = mem[mem_adr0]; + + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage[0:15]; +reg [9:0] storage_dat0; +reg [9:0] storage_dat1; +always @(posedge sys_clk) begin + if (basesoc_uart_tx_fifo_wrport_we) + storage[basesoc_uart_tx_fifo_wrport_adr] <= basesoc_uart_tx_fifo_wrport_dat_w; + storage_dat0 <= storage[basesoc_uart_tx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (basesoc_uart_tx_fifo_rdport_re) + storage_dat1 <= storage[basesoc_uart_tx_fifo_rdport_adr]; +end +assign basesoc_uart_tx_fifo_wrport_dat_r = storage_dat0; +assign basesoc_uart_tx_fifo_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:15]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (basesoc_uart_rx_fifo_wrport_we) + storage_1[basesoc_uart_rx_fifo_wrport_adr] <= basesoc_uart_rx_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[basesoc_uart_rx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (basesoc_uart_rx_fifo_rdport_re) + storage_1_dat1 <= storage_1[basesoc_uart_rx_fifo_rdport_adr]; +end +assign basesoc_uart_rx_fifo_wrport_dat_r = storage_1_dat0; +assign basesoc_uart_rx_fifo_rdport_dat_r = storage_1_dat1; + + +BUFG BUFG( + .I(crg_clkout0), + .O(crg_clkout_buf0) +); + +BUFG BUFG_1( + .I(crg_clkout1), + .O(crg_clkout_buf1) +); + +BUFG BUFG_2( + .I(crg_clkout2), + .O(crg_clkout_buf2) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(idelay_clk), + .RST(crg_ic_reset) +); + +//------------------------------------------------------------------------------ +// Memory mem_1: 16384-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:16383]; +initial begin + $readmemh("mem_1.init", mem_1); +end +reg [31:0] mem_1_dat0; +always @(posedge sys_clk) begin + mem_1_dat0 <= mem_1[basesoc_adr]; +end +assign basesoc_dat_r = mem_1_dat0; + + +issiram issiram( + .clk(sys_clk), + .rst(sys_rst), + .wbs_adr_i(sram_bus_adr), + .wbs_cyc_i(sram_bus_cyc), + .wbs_dat_i(sram_bus_dat_w), + .wbs_sel_i(sram_bus_sel), + .wbs_stb_i(sram_bus_stb), + .wbs_we_i(sram_bus_we), + .mem_dat(issiram_data), + .mem_adr(issiram_addr), + .mem_ce_n(issiram_cen), + .mem_oe_n(issiram_oen), + .mem_we_n(issiram_wen), + .wbs_ack_o(sram_bus_ack), + .wbs_dat_o(sram_bus_dat_r) +); + +DNA_PORT DNA_PORT( + .CLK(dna_clk), + .DIN(dna_status[56]), + .READ((dna_count < 2'd2)), + .SHIFT(1'd1), + .DOUT(dna_do) +); + +XADC #( + .INIT_40(16'd36864), + .INIT_41(14'd12016), + .INIT_42(11'd1024), + .INIT_48(15'd18177), + .INIT_49(4'd15), + .INIT_4A(15'd18176), + .INIT_4B(1'd0), + .INIT_4C(1'd0), + .INIT_4D(1'd0), + .INIT_4E(1'd0), + .INIT_4F(1'd0), + .INIT_50(16'd46573), + .INIT_51(15'd22937), + .INIT_52(16'd41287), + .INIT_53(16'd56797), + .INIT_54(16'd43322), + .INIT_55(15'd20753), + .INIT_56(16'd37355), + .INIT_57(16'd44622), + .INIT_58(15'd22937), + .INIT_5C(15'd20753) +) XADC ( + .CONVST(1'd0), + .CONVSTCLK(1'd0), + .DADDR(xadc_dadr), + .DCLK(sys_clk), + .DEN(xadc_den), + .DI(xadc_di), + .DWE(xadc_dwe), + .RESET(sys_rst), + .VAUXN(1'd0), + .VAUXP(1'd0), + .VN(1'd0), + .VP(1'd0), + .ALM(xadc_alarm), + .BUSY(xadc_busy), + .CHANNEL(xadc_channel), + .DO(xadc_do), + .DRDY(xadc_drdy), + .EOC(xadc_eoc), + .EOS(xadc_eos), + .OT(xadc_ot) +); + +assign pmod0 = (~scl) ? 1'd0 : 1'bz; + +assign pmod1 = (oe & (~sda0)) ? 1'd0 : 1'bz; +assign sda1 = pmod1; + +A2P_WB A2P_WB( + .clk(sys_clk), + .dBusWB_ACK(basesoc_dbus_ack), + .dBusWB_DAT_MISO(basesoc_dbus_dat_r), + .dBusWB_ERR(basesoc_dbus_err), + .externalInterrupt(basesoc_interrupt[0]), + .externalInterruptS(basesoc_interruptS), + .externalResetVector(basesoc_a2p), + .iBusWB_ACK(basesoc_ibus_ack), + .iBusWB_DAT_MISO(basesoc_ibus_dat_r), + .iBusWB_ERR(basesoc_ibus_err), + .reset((sys_rst | basesoc_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWB_ADR(basesoc_dbus_adr), + .dBusWB_BTE(basesoc_dbus_bte), + .dBusWB_CTI(basesoc_dbus_cti), + .dBusWB_CYC(basesoc_dbus_cyc), + .dBusWB_DAT_MOSI(basesoc_dbus_dat_w), + .dBusWB_SEL(basesoc_dbus_sel), + .dBusWB_STB(basesoc_dbus_stb), + .dBusWB_WE(basesoc_dbus_we), + .iBusWB_ADR(basesoc_ibus_adr), + .iBusWB_BTE(basesoc_ibus_bte), + .iBusWB_CTI(basesoc_ibus_cti), + .iBusWB_CYC(basesoc_ibus_cyc), + .iBusWB_DAT_MOSI(basesoc_ibus_dat_w), + .iBusWB_SEL(basesoc_ibus_sel), + .iBusWB_STB(basesoc_ibus_stb), + .iBusWB_WE(basesoc_ibus_we) +); + +FD FD( + .C(crg_clkin), + .D(crg_reset), + .Q(subfragments_reset0) +); + +FD FD_1( + .C(crg_clkin), + .D(subfragments_reset0), + .Q(subfragments_reset1) +); + +FD FD_2( + .C(crg_clkin), + .D(subfragments_reset1), + .Q(subfragments_reset2) +); + +FD FD_3( + .C(crg_clkin), + .D(subfragments_reset2), + .Q(subfragments_reset3) +); + +FD FD_4( + .C(crg_clkin), + .D(subfragments_reset3), + .Q(subfragments_reset4) +); + +FD FD_5( + .C(crg_clkin), + .D(subfragments_reset4), + .Q(subfragments_reset5) +); + +FD FD_6( + .C(crg_clkin), + .D(subfragments_reset5), + .Q(subfragments_reset6) +); + +FD FD_7( + .C(crg_clkin), + .D(subfragments_reset6), + .Q(subfragments_reset7) +); + +MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(6'd50), + .CLKIN1_PERIOD(83.33333333333333), + .CLKOUT0_DIVIDE_F(3'd6), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(2'd3), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(2'd3), + .CLKOUT2_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01) +) MMCME2_ADV ( + .CLKFBIN(subfragments_mmcm_fb), + .CLKIN1(crg_clkin), + .PWRDWN(crg_power_down), + .RST(subfragments_reset7), + .CLKFBOUT(subfragments_mmcm_fb), + .CLKOUT0(crg_clkout0), + .CLKOUT1(crg_clkout1), + .CLKOUT2(crg_clkout2), + .LOCKED(crg_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys2x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys2x_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(idelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(idelay_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(idelay_rst) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2021-11-11 08:18:47. +//------------------------------------------------------------------------------ diff --git a/build/litex/litex-1099/master/csr.csv b/build/litex/litex-1099/master/csr.csv new file mode 100644 index 0000000..b1f2ae3 --- /dev/null +++ b/build/litex/litex-1099/master/csr.csv @@ -0,0 +1,63 @@ +#-------------------------------------------------------------------------------- +# Auto-generated by Migen (7507a2b) & LiteX (feca1c47) on 2021-11-11 08:18:47 +#-------------------------------------------------------------------------------- +csr_base,dna,0xfff00800,, +csr_base,xadc,0xfff01000,, +csr_base,leds,0xfff01800,, +csr_base,buttons,0xfff02000,, +csr_base,i2c,0xfff02800,, +csr_base,dshot_0,0xfff03000,, +csr_base,ctrl,0xfff03800,, +csr_base,identifier_mem,0xfff04000,, +csr_base,timer0,0xfff04800,, +csr_base,uart,0xfff05000,, +csr_register,dna_id,0xfff00800,2,ro +csr_register,xadc_temperature,0xfff01000,1,ro +csr_register,xadc_vccint,0xfff01004,1,ro +csr_register,xadc_vccaux,0xfff01008,1,ro +csr_register,xadc_vccbram,0xfff0100c,1,ro +csr_register,xadc_eoc,0xfff01010,1,ro +csr_register,xadc_eos,0xfff01014,1,ro +csr_register,leds_out,0xfff01800,1,rw +csr_register,buttons_in,0xfff02000,1,ro +csr_register,i2c_w,0xfff02800,1,rw +csr_register,i2c_r,0xfff02804,1,ro +csr_register,dshot_0_out,0xfff03000,1,rw +csr_register,ctrl_reset,0xfff03800,1,rw +csr_register,ctrl_scratch,0xfff03804,1,rw +csr_register,ctrl_bus_errors,0xfff03808,1,ro +csr_register,timer0_load,0xfff04800,1,rw +csr_register,timer0_reload,0xfff04804,1,rw +csr_register,timer0_en,0xfff04808,1,rw +csr_register,timer0_update_value,0xfff0480c,1,rw +csr_register,timer0_value,0xfff04810,1,ro +csr_register,timer0_ev_status,0xfff04814,1,ro +csr_register,timer0_ev_pending,0xfff04818,1,rw +csr_register,timer0_ev_enable,0xfff0481c,1,rw +csr_register,uart_rxtx,0xfff05000,1,rw +csr_register,uart_txfull,0xfff05004,1,ro +csr_register,uart_rxempty,0xfff05008,1,ro +csr_register,uart_ev_status,0xfff0500c,1,ro +csr_register,uart_ev_pending,0xfff05010,1,rw +csr_register,uart_ev_enable,0xfff05014,1,rw +csr_register,uart_txempty,0xfff05018,1,ro +csr_register,uart_rxfull,0xfff0501c,1,ro +constant,config_clock_frequency,100000000,, +constant,config_cpu_has_interrupt,None,, +constant,config_cpu_reset_addr,0,, +constant,config_cpu_type_a2p,None,, +constant,config_cpu_variant_standard,None,, +constant,config_cpu_human_name,a2p_wb,, +constant,config_cpu_nop,nop,, +constant,config_with_build_time,None,, +constant,uart_polling,None,, +constant,config_csr_data_width,32,, +constant,config_csr_alignment,32,, +constant,config_bus_standard,wishbone,, +constant,config_bus_data_width,32,, +constant,config_bus_address_width,32,, +constant,timer0_interrupt,1,, +constant,uart_interrupt,0,, +memory_region,rom,0x00000000,65536,cached +memory_region,sram,0x00100000,524288,cached +memory_region,csr,0xfff00000,65536,io diff --git a/build/litex/litex-1099/master/make-uarts.txt b/build/litex/litex-1099/master/make-uarts.txt new file mode 100644 index 0000000..0e146c8 --- /dev/null +++ b/build/litex/litex-1099/master/make-uarts.txt @@ -0,0 +1,1771 @@ +Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :) +Namespace(build=True, bus_address_width=32, bus_data_width=32, bus_standard='wishbone', bus_timeout=1000000.0, cpu_cfu=None, cpu_reset_address=None, cpu_type=None, cpu_variant=None, csr_address_width=14, csr_csv='csr.csv', csr_data_width=None, csr_json=None, csr_ordering='big', csr_paging=2048, csr_svd=None, doc=False, gateware_dir=None, generated_dir=None, ident=None, ident_version=None, include_dir=None, integrated_main_ram_size=None, integrated_rom_init=None, integrated_rom_size=131072, integrated_sram_size=8192, l2_size=8192, load=False, memory_x=None, no_compile_gateware=False, no_compile_software=True, no_ctrl=False, no_timer=False, no_uart=False, output_dir=None, software_dir=None, sys_clk_freq=100000000.0, timer_uptime=False, uart_baudrate=None, uart_fifo_depth=16, uart_name='serial', with_analyzer=False) +directory0 +csr_08000 + +****** Vivado v2020.2 (64-bit) + **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 + **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 + ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + +source cmod7.tcl +# create_project -force -name cmod7 -part xc7a35t-CPG236-1 +# set_msg_config -id {Common 17-55} -new_severity {Warning} +# read_verilog {/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v} +# read_verilog {/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v} +# read_verilog {/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v} +# read_xdc cmod7.xdc +# set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc] +# synth_design -directive default -top cmod7 -part xc7a35t-CPG236-1 +Command: synth_design -directive default -top cmod7 -part xc7a35t-CPG236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 558463 +WARNING: [Synth 8-2292] literal value truncated to fit in 1 bits [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:278] +WARNING: [Synth 8-2292] literal value truncated to fit in 1 bits [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2336] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 342 ; free virtual = 10273 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'cmod7' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:20] +INFO: [Synth 8-3876] $readmem data file 'mem.init' is read successfully [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2403] +INFO: [Synth 8-3876] $readmem data file 'mem_1.init' is read successfully [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2480] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1942] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2032] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2077] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2086] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2109] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2121] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2133] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2150] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2162] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2217] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2259] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2469] +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060] + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (2#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060] +WARNING: [Synth 8-7071] port 'RDY' of module 'IDELAYCTRL' is unconnected for instance 'IDELAYCTRL' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2469] +WARNING: [Synth 8-7023] instance 'IDELAYCTRL' of module 'IDELAYCTRL' has 3 connections declared, but only 2 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2469] +INFO: [Synth 8-6157] synthesizing module 'issiram' [/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v:41] + Parameter WB_BITWIDTH bound to: 32 - type: integer + Parameter RAM_BITWIDTH bound to: 8 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'issiram' (3#1) [/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v:41] +INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:11984] + Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (4#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:11984] +INFO: [Synth 8-6157] synthesizing module 'XADC' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:82182] + Parameter INIT_40 bound to: 16'b1001000000000000 + Parameter INIT_41 bound to: 16'b0010111011110000 + Parameter INIT_42 bound to: 16'b0000010000000000 + Parameter INIT_43 bound to: 16'b0000000000000000 + Parameter INIT_44 bound to: 16'b0000000000000000 + Parameter INIT_45 bound to: 16'b0000000000000000 + Parameter INIT_46 bound to: 16'b0000000000000000 + Parameter INIT_47 bound to: 16'b0000000000000000 + Parameter INIT_48 bound to: 16'b0100011100000001 + Parameter INIT_49 bound to: 16'b0000000000001111 + Parameter INIT_4A bound to: 16'b0100011100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101100110011001 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1101110111011101 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101000100010001 + Parameter INIT_56 bound to: 16'b1001000111101011 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_59 bound to: 16'b0000000000000000 + Parameter INIT_5A bound to: 16'b0000000000000000 + Parameter INIT_5B bound to: 16'b0000000000000000 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter INIT_5D bound to: 16'b0000000000000000 + Parameter INIT_5E bound to: 16'b0000000000000000 + Parameter INIT_5F bound to: 16'b0000000000000000 + Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 + Parameter IS_DCLK_INVERTED bound to: 1'b0 + Parameter SIM_DEVICE bound to: 7SERIES - type: string + Parameter SIM_MONITOR_FILE bound to: design.txt - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (5#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:82182] +WARNING: [Synth 8-689] width (7) of port connection 'CHANNEL' does not match port width (5) of module 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2552] +WARNING: [Synth 8-7071] port 'JTAGBUSY' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537] +WARNING: [Synth 8-7071] port 'JTAGLOCKED' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537] +WARNING: [Synth 8-7071] port 'JTAGMODIFIED' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537] +WARNING: [Synth 8-7071] port 'MUXADDR' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537] +WARNING: [Synth 8-7023] instance 'XADC' of module 'XADC' has 24 connections declared, but only 20 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537] +INFO: [Synth 8-6157] synthesizing module 'A2P_WB' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:1183] +INFO: [Synth 8-6157] synthesizing module 'InstructionCache' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:164] +INFO: [Synth 8-6155] done synthesizing module 'InstructionCache' (6#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:164] +INFO: [Synth 8-6157] synthesizing module 'DataCache' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:465] +INFO: [Synth 8-6155] done synthesizing module 'DataCache' (7#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:465] +INFO: [Synth 8-6155] done synthesizing module 'A2P_WB' (8#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:1183] +INFO: [Synth 8-6157] synthesizing module 'FD' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13483] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-6155] done synthesizing module 'FD' (9#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13483] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 50.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 83.333333 - type: double + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 3 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (10#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DO' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DRDY' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'PSDONE' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKIN2' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'CLKINSEL' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DADDR' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DCLK' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DEN' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DI' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'DWE' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'PSCLK' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'PSEN' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7071] port 'PSINCDEC' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +WARNING: [Synth 8-7023] instance 'MMCME2_ADV' of module 'MMCME2_ADV' has 33 connections declared, but only 9 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657] +INFO: [Synth 8-6157] synthesizing module 'FDPE' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13664] + Parameter INIT bound to: 1'b1 + Parameter IS_C_INVERTED bound to: 1'b0 + Parameter IS_D_INVERTED bound to: 1'b0 + Parameter IS_PRE_INVERTED bound to: 1'b0 +INFO: [Synth 8-6155] done synthesizing module 'FDPE' (11#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'cmod7' (12#1) [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:20] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1055 ; free virtual = 10988 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1070 ; free virtual = 11003 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1070 ; free virtual = 11003 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1054 ; free virtual = 10987 +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +WARNING: [Vivado 12-507] No nets matched 'clk12'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:211] +CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_nets clk12]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:211] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets sys_clk]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Verify the create_clock command was called to create the clock object before it is referenced. +INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets crg_clkin]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Verify the create_clock command was called to create the clock object before it is referenced. +INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets sys_clk]]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets crg_clkin]]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Finished Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/cmod7_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/cmod7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2406.531 ; gain = 0.000 ; free physical = 955 ; free virtual = 10888 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 8 instances were transformed. + FD => FDRE: 8 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2406.531 ; gain = 0.000 ; free physical = 955 ; free virtual = 10888 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1054 ; free virtual = 10987 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1054 ; free virtual = 10987 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1054 ; free virtual = 10987 +--------------------------------------------------------------------------------- +INFO: [Synth 8-3971] The signal "A2P_WB:/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template. +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1033 ; free virtual = 10969 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 64 Bit Adders := 1 + 3 Input 52 Bit Adders := 1 + 3 Input 33 Bit Adders := 2 + 2 Input 33 Bit Adders := 5 + 2 Input 32 Bit Adders := 11 + 2 Input 10 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 2 + 31 Input 6 Bit Adders := 1 + 2 Input 5 Bit Adders := 2 + 7 Input 4 Bit Adders := 4 + 2 Input 4 Bit Adders := 11 + 2 Input 3 Bit Adders := 5 + 2 Input 2 Bit Adders := 6 + 4 Input 2 Bit Adders := 2 + 16 Input 1 Bit Adders := 2 + 8 Input 1 Bit Adders := 1 + 12 Input 1 Bit Adders := 2 + 13 Input 1 Bit Adders := 1 + 15 Input 1 Bit Adders := 1 + 19 Input 1 Bit Adders := 1 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 11 Input 1 Bit Adders := 1 + 2 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 2 + 2 Input 1 Bit XORs := 6 + 4 Input 1 Bit XORs := 1 ++---Registers : + 65 Bit Registers := 1 + 57 Bit Registers := 1 + 54 Bit Registers := 1 + 52 Bit Registers := 1 + 34 Bit Registers := 1 + 33 Bit Registers := 1 + 32 Bit Registers := 76 + 22 Bit Registers := 2 + 20 Bit Registers := 2 + 19 Bit Registers := 1 + 12 Bit Registers := 4 + 11 Bit Registers := 2 + 10 Bit Registers := 1 + 8 Bit Registers := 19 + 7 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 21 + 4 Bit Registers := 18 + 3 Bit Registers := 14 + 2 Bit Registers := 28 + 1 Bit Registers := 213 ++---RAMs : + 54K Bit (1024 X 54 bit) RAMs := 1 + 32K Bit (1024 X 32 bit) RAMs := 1 + 8K Bit (1024 X 8 bit) RAMs := 4 + 2K Bit (128 X 22 bit) RAMs := 2 + 1024 Bit (32 X 32 bit) RAMs := 1 + 160 Bit (16 X 10 bit) RAMs := 2 ++---ROMs : + ROMs := 1 ++---Muxes : + 2 Input 33 Bit Muxes := 3 + 2 Input 32 Bit Muxes := 144 + 3 Input 32 Bit Muxes := 1 + 4 Input 32 Bit Muxes := 7 + 8 Input 32 Bit Muxes := 5 + 20 Input 32 Bit Muxes := 1 + 6 Input 32 Bit Muxes := 2 + 7 Input 32 Bit Muxes := 2 + 2 Input 31 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 2 + 2 Input 26 Bit Muxes := 3 + 2 Input 20 Bit Muxes := 1 + 2 Input 19 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 5 + 2 Input 14 Bit Muxes := 2 + 18 Input 12 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 3 + 3 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 4 + 4 Input 8 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 23 + 3 Input 8 Bit Muxes := 5 + 7 Input 8 Bit Muxes := 3 + 5 Input 8 Bit Muxes := 2 + 25 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 9 + 2 Input 6 Bit Muxes := 6 + 7 Input 5 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 15 + 3 Input 5 Bit Muxes := 1 + 8 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 23 + 8 Input 4 Bit Muxes := 9 + 3 Input 4 Bit Muxes := 1 + 3 Input 3 Bit Muxes := 2 + 2 Input 3 Bit Muxes := 6 + 20 Input 3 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 10 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 10 + 4 Input 2 Bit Muxes := 2 + 7 Input 2 Bit Muxes := 1 + 6 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 298 + 5 Input 1 Bit Muxes := 9 + 8 Input 1 Bit Muxes := 4 + 7 Input 1 Bit Muxes := 14 + 20 Input 1 Bit Muxes := 2 + 32 Input 1 Bit Muxes := 1 + 6 Input 1 Bit Muxes := 6 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +DSP Report: Generating DSP memory_to_writeBack_MUL_HH_reg, operation Mode is: (A*B)'. +DSP Report: register memory_to_writeBack_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg. +DSP Report: register execute_to_memory_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg. +DSP Report: operator execute_MUL_HH is absorbed into DSP memory_to_writeBack_MUL_HH_reg. +DSP Report: Generating DSP execute_to_memory_MUL_LH_reg, operation Mode is: (A*B)'. +DSP Report: register execute_to_memory_MUL_LH_reg is absorbed into DSP execute_to_memory_MUL_LH_reg. +DSP Report: operator execute_MUL_LH is absorbed into DSP execute_to_memory_MUL_LH_reg. +DSP Report: Generating DSP execute_to_memory_MUL_HL_reg, operation Mode is: (A*B)'. +DSP Report: register execute_to_memory_MUL_HL_reg is absorbed into DSP execute_to_memory_MUL_HL_reg. +DSP Report: operator execute_MUL_HL is absorbed into DSP execute_to_memory_MUL_HL_reg. +DSP Report: Generating DSP execute_to_memory_MUL_LL_reg, operation Mode is: (A*B)'. +DSP Report: register execute_to_memory_MUL_LL_reg is absorbed into DSP execute_to_memory_MUL_LL_reg. +DSP Report: operator execute_MUL_LL is absorbed into DSP execute_to_memory_MUL_LL_reg. +INFO: [Synth 8-3971] The signal "A2P_WB/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:23 ; elapsed = 00:01:25 . Memory (MB): peak = 2443.516 ; gain = 144.730 ; free physical = 996 ; free virtual = 10945 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------+----------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------+----------------+---------------+----------------+ +|cmod7 | mem_1_dat0_reg | 16384x32 | Block RAM | ++------------+----------------+---------------+----------------+ + + +Block RAM: Preliminary Mapping Report (see note below) ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|A2P_WB/IBusCachedPlugin_cache | ways_0_datas_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|A2P_WB/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB | IBusCachedPlugin_predictor_history_reg | 1 K x 54(READ_FIRST) | W | | 1 K x 54(WRITE_FIRST) | | R | Port A and B | 1 | 1 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------+-----------+----------------------+-------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------+-----------+----------------------+-------------+ +|cmod7 | storage_1_reg | Implied | 16 x 8 | RAM32M x 2 | +|cmod7 | storage_reg | Implied | 16 x 8 | RAM32M x 2 | ++------------+---------------+-----------+----------------------+-------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below) ++------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|A2P_WB | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 1 | +|A2P_WB | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 | +|A2P_WB | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 | +|A2P_WB | (A*B)' | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 1 | 0 | ++------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:31 ; elapsed = 00:01:33 . Memory (MB): peak = 2443.516 ; gain = 144.730 ; free physical = 732 ; free virtual = 10701 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 2443.516 ; gain = 144.730 ; free physical = 788 ; free virtual = 10756 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|A2P_WB/IBusCachedPlugin_cache | ways_0_datas_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|A2P_WB/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB | IBusCachedPlugin_predictor_history_reg | 1 K x 54(READ_FIRST) | W | | 1 K x 54(WRITE_FIRST) | | R | Port A and B | 1 | 1 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++------------+---------------+-----------+----------------------+-------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------+-----------+----------------------+-------------+ +|cmod7 | storage_1_reg | Implied | 16 x 8 | RAM32M x 2 | +|cmod7 | storage_reg | Implied | 16 x 8 | RAM32M x 2 | ++------------+---------------+-----------+----------------------+-------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/dataCache_1_/DC_DIR_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_10 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_11 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_12 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_13 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_14 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_15 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 736 ; free virtual = 10727 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13035] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8733] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651] +INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 726 ; free virtual = 10702 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 726 ; free virtual = 10702 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 725 ; free virtual = 10701 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 724 ; free virtual = 10701 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 720 ; free virtual = 10697 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 721 ; free virtual = 10698 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 4| +|2 |CARRY4 | 255| +|3 |DNA_PORT | 1| +|4 |DSP48E1 | 4| +|6 |IDELAYCTRL | 1| +|7 |LUT1 | 304| +|8 |LUT2 | 348| +|9 |LUT3 | 882| +|10 |LUT4 | 855| +|11 |LUT5 | 962| +|12 |LUT6 | 2468| +|13 |MMCME2_ADV | 1| +|14 |MUXF7 | 35| +|15 |RAM32M | 4| +|16 |RAMB18E1 | 10| +|19 |RAMB36E1 | 18| +|37 |XADC | 1| +|38 |FD | 8| +|39 |FDCE | 283| +|40 |FDPE | 7| +|41 |FDRE | 2513| +|42 |FDSE | 93| +|43 |IBUF | 5| +|44 |IOBUF | 9| +|45 |OBUF | 27| +|46 |OBUFT | 1| ++------+-----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 722 ; free virtual = 10698 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 2939 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:36 ; elapsed = 00:01:39 . Memory (MB): peak = 2496.523 ; gain = 89.992 ; free physical = 781 ; free virtual = 10757 +Synthesis Optimization Complete : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.531 ; gain = 197.738 ; free physical = 781 ; free virtual = 10757 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2496.531 ; gain = 0.000 ; free physical = 866 ; free virtual = 10842 +INFO: [Netlist 29-17] Analyzing 345 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +INFO: [Timing 38-2] Deriving generated clocks [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +WARNING: [Vivado 12-3521] Clock specified in more than one group: crg_clkout0 [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Finished Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2840.547 ; gain = 0.000 ; free physical = 555 ; free virtual = 10522 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 21 instances were transformed. + FD => FDRE: 8 instances + IOBUF => IOBUF (IBUF, OBUFT): 9 instances + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 4 instances + +INFO: [Common 17-83] Releasing license: Synthesis +82 Infos, 140 Warnings, 6 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:55 ; elapsed = 00:01:52 . Memory (MB): peak = 2840.547 ; gain = 541.859 ; free physical = 726 ; free virtual = 10693 +# report_timing_summary -file cmod7_timing_synth.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt +# report_utilization -file cmod7_utilization_synth.rpt +# opt_design -directive default +Command: opt_design -directive default +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port pmod0 expects both input and output buffering but the buffers are incomplete. +INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2911.605 ; gain = 64.031 ; free physical = 695 ; free virtual = 10660 + +Starting Cache Timing Information Task +Ending Cache Timing Information Task | Checksum: 16ae10926 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 695 ; free virtual = 10660 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: f3d65e6d + +Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 597 ; free virtual = 10562 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 55 cells +INFO: [Opt 31-1021] In phase Retarget, 6 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 153537fc4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 599 ; free virtual = 10562 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 1 cells +INFO: [Opt 31-1021] In phase Constant propagation, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 3 Sweep +Phase 3 Sweep | Checksum: cd080f35 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Sweep, 20 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: cd080f35 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.92 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. +INFO: [Opt 31-1021] In phase BUFG optimization, 3 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: cd080f35 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: cd080f35 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 55 | 6 | +| Constant propagation | 0 | 1 | 2 | +| Sweep | 0 | 19 | 20 | +| BUFG optimization | 0 | 0 | 3 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 1 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562 +Ending Logic Optimization Task | Checksum: f008ea69 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +INFO: [Power 33-23] Power model is not available for DNA_PORT +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 28 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports +Number of BRAM Ports augmented: 1 newly gated: 1 Total Ports: 56 +Ending PowerOpt Patch Enables Task | Checksum: a01ec7fc + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 728 ; free virtual = 10687 +Ending Power Optimization Task | Checksum: a01ec7fc + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3172.551 ; gain = 260.945 ; free physical = 736 ; free virtual = 10694 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: a01ec7fc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 736 ; free virtual = 10694 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 735 ; free virtual = 10694 +Ending Netlist Obfuscation Task | Checksum: e791bb43 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 735 ; free virtual = 10694 +INFO: [Common 17-83] Releasing license: Implementation +28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3172.551 ; gain = 324.977 ; free physical = 734 ; free virtual = 10693 +# place_design -directive default +Command: place_design -directive default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[5] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[0]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[6] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[1]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[7] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[2]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port pmod0 expects both input and output buffering but the buffers are incomplete. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 43 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 46-5] The placer was invoked with the 'default' directive. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 87f2f39c + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +WARNING: [Place 30-568] A LUT 'clk12_inst' is driving clock pin of 8 registers. This could lead to large hold time violations. First few involved registers are: + FD_4 {FDRE} + FD {FDRE} + FD_2 {FDRE} + FD_1 {FDRE} + FD_3 {FDRE} +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ba0c756b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.72 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 743 ; free virtual = 10702 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 29b4df3bb + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 739 ; free virtual = 10699 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 29b4df3bb + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 739 ; free virtual = 10699 +Phase 1 Placer Initialization | Checksum: 29b4df3bb + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 739 ; free virtual = 10699 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 25d7745f4 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 732 ; free virtual = 10691 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fb083423 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 732 ; free virtual = 10691 + +Phase 2.3 Global Placement Core + +Phase 2.3.1 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 122 LUTNM shape to break, 192 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 87, two critical 35, total 122, new lutff created 1 +INFO: [Physopt 32-775] End 1 Pass. Optimized 187 nets or cells. Created 122 new cells, deleted 65 existing cells and moved 0 existing cell +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-64] No nets found for fanout-optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][6] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_6 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/lastStageRegFileWrite_payload_data[20] could not be optimized because driver A2P_WB/dataCache_1_/RegFilePlugin_regFile_reg_1_i_38 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/lastStageRegFileWrite_payload_data[30] could not be optimized because driver A2P_WB/dataCache_1_/RegFilePlugin_regFile_reg_1_i_28 could not be replicated +INFO: [Physopt 32-68] No nets found for critical-cell optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-527] Pass 1: Identified 3 candidate cells for BRAM register optimization +INFO: [Physopt 32-666] Processed cell A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg. No change. +INFO: [Physopt 32-665] Processed cell A2P_WB/dataCache_1_/DC_DIR_data_symbol1_reg. 8 registers were pushed out. +INFO: [Physopt 32-665] Processed cell A2P_WB/dataCache_1_/DC_DIR_data_symbol3_reg. 8 registers were pushed out. +INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 16 new cells, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 714 ; free virtual = 10673 +INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 714 ; free virtual = 10674 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 122 | 65 | 187 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| BRAM Register | 16 | 0 | 2 | 0 | 1 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 138 | 65 | 189 | 0 | 10 | 00:00:01 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1a341b5d2 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 715 ; free virtual = 10674 +Phase 2.3 Global Placement Core | Checksum: 1aa8e06dd + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 714 ; free virtual = 10673 +Phase 2 Global Placement | Checksum: 1aa8e06dd + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 719 ; free virtual = 10678 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1f20bb7a9 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:11 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 719 ; free virtual = 10678 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ece0d326 + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10677 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 2065d7a66 + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10676 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 2991add41 + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10676 + +Phase 3.5 Fast Optimization +Phase 3.5 Fast Optimization | Checksum: 2a8da495d + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 716 ; free virtual = 10675 + +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: 20e8bd739 + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:16 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 715 ; free virtual = 10673 + +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 1d656ef4e + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:17 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 716 ; free virtual = 10674 + +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 108f68281 + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:17 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 716 ; free virtual = 10674 + +Phase 3.9 Fast Optimization +Phase 3.9 Fast Optimization | Checksum: 137b6925a + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 712 ; free virtual = 10671 +Phase 3 Detail Placement | Checksum: 137b6925a + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 712 ; free virtual = 10671 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: ffb54392 + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.486 | TNS=-10.492 | +Phase 1 Physical Synthesis Initialization | Checksum: 12be2a25c + +Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 709 ; free virtual = 10667 +INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. +Ending Physical Synthesis Task | Checksum: b80880be + +Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10665 +Phase 4.1.1.1 BUFG Insertion | Checksum: ffb54392 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:23 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10665 +INFO: [Place 30-746] Post Placement Timing Summary WNS=0.503. For the most accurate timing information please run report_timing. + +Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666 +Phase 4.1 Post Commit Optimization | Checksum: e5c2f70b + +Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: e5c2f70b + +Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 4x4| +|___________|___________________|___________________| +| South| 1x1| 2x2| +|___________|___________________|___________________| +| East| 1x1| 4x4| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: e5c2f70b + +Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665 +Phase 4.3 Placer Reporting | Checksum: e5c2f70b + +Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665 + +Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 16e2ac428 + +Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 705 ; free virtual = 10664 +Ending Placer Task | Checksum: 14f2dee0a + +Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 705 ; free virtual = 10664 +INFO: [Common 17-83] Releasing license: Implementation +47 Infos, 44 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:01:01 ; elapsed = 00:00:30 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 720 ; free virtual = 10679 +# report_utilization -hierarchical -file cmod7_utilization_hierarchical_place.rpt +# report_utilization -file cmod7_utilization_place.rpt +# report_io -file cmod7_io.rpt +report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 713 ; free virtual = 10672 +# report_control_sets -verbose -file cmod7_control_sets.rpt +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10677 +# report_clock_utilization -file cmod7_clock_utilization.rpt +# route_design -directive default +Command: route_design -directive default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'default'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs +Checksum: PlaceDB: 7c90c02d ConstDB: 0 ShapeSum: d29d2ddd RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: b88298ea + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 587 ; free virtual = 10553 +Post Restoration Checksum: NetGraph: adea1a45 NumContArr: a987ea5 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: b88298ea + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 589 ; free virtual = 10556 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: b88298ea + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 558 ; free virtual = 10525 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: b88298ea + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 558 ; free virtual = 10524 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 203a8934b + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 566 ; free virtual = 10529 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.660 | TNS=0.000 | WHS=-0.215 | THS=-46.957| + +Phase 2 Router Initialization | Checksum: 25ab15ee4 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 565 ; free virtual = 10528 + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00191342 % + Global Horizontal Routing Utilization = 0.00143155 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 7823 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 7822 + Number of Partially Routed Nets = 1 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 25ab15ee4 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 564 ; free virtual = 10527 +Phase 3 Initial Routing | Checksum: 8cae6c5c + +Time (s): cpu = 00:00:27 ; elapsed = 00:00:14 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 562 ; free virtual = 10525 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 4313 + Number of Nodes with overlaps = 2004 + Number of Nodes with overlaps = 1086 + Number of Nodes with overlaps = 553 + Number of Nodes with overlaps = 291 + Number of Nodes with overlaps = 147 + Number of Nodes with overlaps = 49 + Number of Nodes with overlaps = 20 + Number of Nodes with overlaps = 19 + Number of Nodes with overlaps = 10 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.339 | TNS=-4.313 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 1609ee9c0 + +Time (s): cpu = 00:02:11 ; elapsed = 00:00:43 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 565 ; free virtual = 10523 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 533 + Number of Nodes with overlaps = 386 + Number of Nodes with overlaps = 177 + Number of Nodes with overlaps = 138 + Number of Nodes with overlaps = 55 + Number of Nodes with overlaps = 32 + Number of Nodes with overlaps = 20 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.026 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 1bcfc8674 + +Time (s): cpu = 00:02:47 ; elapsed = 00:01:01 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 587 ; free virtual = 10545 + +Phase 4.3 Global Iteration 2 + Number of Nodes with overlaps = 390 + Number of Nodes with overlaps = 275 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 97 + Number of Nodes with overlaps = 57 + Number of Nodes with overlaps = 25 + Number of Nodes with overlaps = 13 + Number of Nodes with overlaps = 24 + Number of Nodes with overlaps = 16 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.169 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.3 Global Iteration 2 | Checksum: 1138b2815 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 587 ; free virtual = 10545 +Phase 4 Rip-up And Reroute | Checksum: 1138b2815 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 1138b2815 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 1138b2815 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544 +Phase 5 Delay and Skew Optimization | Checksum: 1138b2815 + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 14f05eee6 + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10545 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.181 | TNS=0.000 | WHS=0.008 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 136d40aef + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 585 ; free virtual = 10544 +Phase 6 Post Hold Fix | Checksum: 136d40aef + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 585 ; free virtual = 10544 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 4.60249 % + Global Horizontal Routing Utilization = 5.68961 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: f3d8b232 + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 585 ; free virtual = 10544 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: f3d8b232 + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 584 ; free virtual = 10543 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1873629a4 + +Time (s): cpu = 00:03:23 ; elapsed = 00:01:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 583 ; free virtual = 10542 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=0.181 | TNS=0.000 | WHS=0.008 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 1873629a4 + +Time (s): cpu = 00:03:23 ; elapsed = 00:01:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 583 ; free virtual = 10542 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:03:23 ; elapsed = 00:01:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 622 ; free virtual = 10581 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:03:30 ; elapsed = 00:01:23 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 622 ; free virtual = 10581 +# phys_opt_design -directive default +Command: phys_opt_design -directive default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed) +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: default +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +# write_checkpoint -force cmod7_route.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 583 ; free virtual = 10555 +INFO: [Common 17-1381] The checkpoint '/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7_route.dcp' has been generated. +# report_timing_summary -no_header -no_detailed_paths +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (1) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (2) +5. checking no_input_delay (13) +6. checking no_output_delay (36) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (1) +------------------------ + There is 1 register/latch pin with no clock driven by root clock pin: dna_count_reg[0]/Q (HIGH) + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (2) +------------------------------------------------ + There are 2 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (13) +------------------------------- + There are 13 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (36) +-------------------------------- + There are 36 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.181 0.000 0 7495 0.007 0.000 0 7495 3.750 0.000 0 2991 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk12 {0.000 41.666} 83.333 12.000 + crg_clkout0 {0.000 5.000} 10.000 100.000 + subfragments_mmcm_fb {0.000 41.666} 83.333 12.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk12 81.512 0.000 0 7 0.160 0.000 0 7 16.667 0.000 0 10 + crg_clkout0 0.181 0.000 0 7202 0.007 0.000 0 7202 3.750 0.000 0 2979 + subfragments_mmcm_fb 16.667 0.000 0 2 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** crg_clkout0 crg_clkout0 2.432 0.000 0 286 0.811 0.000 0 286 + + +# report_route_status -file cmod7_route_status.rpt +# report_drc -file cmod7_drc.rpt +Command: report_drc -file cmod7_drc.rpt +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7_drc.rpt. +report_drc completed successfully +# report_timing_summary -datasheet -max_paths 10 -file cmod7_timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# report_power -file cmod7_power.rpt +Command: report_power -file cmod7_power.rpt +INFO: [Power 33-23] Power model is not available for DNA_PORT +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. +Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. +1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +# write_bitstream -force cmod7.bit +Command: write_bitstream -force cmod7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg input A2P_WB/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg input A2P_WB/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg input A2P_WB/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg input A2P_WB/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg input A2P_WB/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg input A2P_WB/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/memory_to_writeBack_MUL_HH_reg input A2P_WB/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/memory_to_writeBack_MUL_HH_reg input A2P_WB/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg multiplier stage A2P_WB/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg multiplier stage A2P_WB/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg multiplier stage A2P_WB/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC PDRC-153] Gated clock check: Net crg_clkin is a gated clock net sourced by a combinational pin clk12_inst/O, cell clk12_inst. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT clk12_inst is driving clock pin of 8 cells. This could lead to large hold time violations. Involved cells are: +FD, FD_1, FD_2, FD_3, FD_4, FD_5, FD_6, and FD_7 +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[5] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[0]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[6] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[1]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[7] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[2]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 56 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./cmod7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Nov 11 08:23:23 2021. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html. +INFO: [Common 17-83] Releasing license: Implementation +10 Infos, 56 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:16 . Memory (MB): peak = 3247.566 ; gain = 75.016 ; free physical = 557 ; free virtual = 10516 +# quit +INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 08:23:23 2021... +Copying .v and .bit, and programming... + + + +****** Vivado v2020.2 (64-bit) + **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 + **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 + ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + +source pgmfpga.tcl +# open_hw_manager +# connect_hw_server +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2020.2 + **** Build date : Nov 18 2020 at 09:50:49 + ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2020.2 + ****** Build date : Nov 03 2020-15:02:56 + **** Build number : 2020.2.1604437376 + ** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved. + + + +# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*] +# open_hw_target +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210328B04819A +# set dev [lindex [get_hw_devices] 0] +# current_hw_device $dev +# refresh_hw_device -update_hw_probes false $dev +INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +# set_property PROGRAM.FILE {./cmod7.bit} $dev +# program_hw_devices $dev +INFO: [Labtools 27-3164] End of startup status: HIGH +# refresh_hw_device $dev +INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +# puts "Device programmed." +Device programmed. +# quit +INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 08:23:40 2021... + + +Done. diff --git a/build/litex/litex-1099/no_master/cmod7.v b/build/litex/litex-1099/no_master/cmod7.v new file mode 100644 index 0000000..3ab6aa2 --- /dev/null +++ b/build/litex/litex-1099/no_master/cmod7.v @@ -0,0 +1,2684 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : cmod7.v +// Device : xc7a35t-CPG236-1 +// LiteX sha1 : feca1c47 +// Date : 2021-11-11 08:35:18 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module cmod7 ( + output reg serial_tx, + input wire serial_rx, + (* dont_touch = "true" *) input wire clk12, + output wire [18:0] issiram_addr, + inout wire [7:0] issiram_data, + output wire issiram_oen, + output wire issiram_wen, + output wire issiram_cen, + output reg user_led0, + output reg user_led1, + input wire user_btn0, + input wire user_btn1, + inout wire pmod0, + inout wire pmod1, + output reg digital10, + input wire digital11, + output wire digital43 +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg basesoc_soc_rst = 1'd0; +wire basesoc_cpu_rst; +reg [1:0] basesoc_reset_storage = 2'd0; +reg basesoc_reset_re = 1'd0; +reg [31:0] basesoc_scratch_storage = 32'd305419896; +reg basesoc_scratch_re = 1'd0; +wire [31:0] basesoc_bus_errors_status; +wire basesoc_bus_errors_we; +reg basesoc_bus_errors_re = 1'd0; +wire basesoc_bus_error; +reg [31:0] basesoc_bus_errors = 32'd0; +wire basesoc_reset; +reg [31:0] basesoc_interrupt = 32'd0; +reg basesoc_interruptS = 1'd0; +wire [29:0] basesoc_ibus_adr; +wire [31:0] basesoc_ibus_dat_w; +wire [31:0] basesoc_ibus_dat_r; +wire [3:0] basesoc_ibus_sel; +wire basesoc_ibus_cyc; +wire basesoc_ibus_stb; +wire basesoc_ibus_ack; +wire basesoc_ibus_we; +wire [2:0] basesoc_ibus_cti; +wire [1:0] basesoc_ibus_bte; +wire basesoc_ibus_err; +wire [29:0] basesoc_dbus_adr; +wire [31:0] basesoc_dbus_dat_w; +wire [31:0] basesoc_dbus_dat_r; +wire [3:0] basesoc_dbus_sel; +wire basesoc_dbus_cyc; +wire basesoc_dbus_stb; +wire basesoc_dbus_ack; +wire basesoc_dbus_we; +wire [2:0] basesoc_dbus_cti; +wire [1:0] basesoc_dbus_bte; +wire basesoc_dbus_err; +reg [31:0] basesoc_a2p = 32'd0; +wire basesoc_tx_sink_valid; +reg basesoc_tx_sink_ready = 1'd0; +wire basesoc_tx_sink_first; +wire basesoc_tx_sink_last; +wire [7:0] basesoc_tx_sink_payload_data; +reg [7:0] basesoc_tx_data = 8'd0; +reg [3:0] basesoc_tx_count = 4'd0; +reg basesoc_tx_enable = 1'd0; +reg basesoc_tx_tick = 1'd0; +reg [31:0] basesoc_tx_phase = 32'd0; +reg basesoc_rx_source_valid = 1'd0; +wire basesoc_rx_source_ready; +reg basesoc_rx_source_first = 1'd0; +reg basesoc_rx_source_last = 1'd0; +reg [7:0] basesoc_rx_source_payload_data = 8'd0; +reg [7:0] basesoc_rx_data = 8'd0; +reg [3:0] basesoc_rx_count = 4'd0; +reg basesoc_rx_enable = 1'd0; +reg basesoc_rx_tick = 1'd0; +reg [31:0] basesoc_rx_phase = 32'd0; +wire basesoc_rx_rx; +reg basesoc_rx_rx_d = 1'd0; +reg basesoc_uart_rxtx_re = 1'd0; +wire [7:0] basesoc_uart_rxtx_r; +reg basesoc_uart_rxtx_we = 1'd0; +wire [7:0] basesoc_uart_rxtx_w; +wire basesoc_uart_txfull_status; +wire basesoc_uart_txfull_we; +reg basesoc_uart_txfull_re = 1'd0; +wire basesoc_uart_rxempty_status; +wire basesoc_uart_rxempty_we; +reg basesoc_uart_rxempty_re = 1'd0; +wire basesoc_uart_irq; +wire basesoc_uart_tx_status; +reg basesoc_uart_tx_pending = 1'd0; +wire basesoc_uart_tx_trigger; +reg basesoc_uart_tx_clear = 1'd0; +reg basesoc_uart_tx_trigger_d = 1'd0; +wire basesoc_uart_rx_status; +reg basesoc_uart_rx_pending = 1'd0; +wire basesoc_uart_rx_trigger; +reg basesoc_uart_rx_clear = 1'd0; +reg basesoc_uart_rx_trigger_d = 1'd0; +wire basesoc_uart_tx0; +wire basesoc_uart_rx0; +reg [1:0] basesoc_uart_status_status = 2'd0; +wire basesoc_uart_status_we; +reg basesoc_uart_status_re = 1'd0; +wire basesoc_uart_tx1; +wire basesoc_uart_rx1; +reg [1:0] basesoc_uart_pending_status = 2'd0; +wire basesoc_uart_pending_we; +reg basesoc_uart_pending_re = 1'd0; +reg [1:0] basesoc_uart_pending_r = 2'd0; +wire basesoc_uart_tx2; +wire basesoc_uart_rx2; +reg [1:0] basesoc_uart_enable_storage = 2'd0; +reg basesoc_uart_enable_re = 1'd0; +wire basesoc_uart_txempty_status; +wire basesoc_uart_txempty_we; +reg basesoc_uart_txempty_re = 1'd0; +wire basesoc_uart_rxfull_status; +wire basesoc_uart_rxfull_we; +reg basesoc_uart_rxfull_re = 1'd0; +wire basesoc_uart_uart_sink_valid; +wire basesoc_uart_uart_sink_ready; +wire basesoc_uart_uart_sink_first; +wire basesoc_uart_uart_sink_last; +wire [7:0] basesoc_uart_uart_sink_payload_data; +wire basesoc_uart_uart_source_valid; +wire basesoc_uart_uart_source_ready; +wire basesoc_uart_uart_source_first; +wire basesoc_uart_uart_source_last; +wire [7:0] basesoc_uart_uart_source_payload_data; +wire basesoc_uart_tx_fifo_sink_valid; +wire basesoc_uart_tx_fifo_sink_ready; +reg basesoc_uart_tx_fifo_sink_first = 1'd0; +reg basesoc_uart_tx_fifo_sink_last = 1'd0; +wire [7:0] basesoc_uart_tx_fifo_sink_payload_data; +wire basesoc_uart_tx_fifo_source_valid; +wire basesoc_uart_tx_fifo_source_ready; +wire basesoc_uart_tx_fifo_source_first; +wire basesoc_uart_tx_fifo_source_last; +wire [7:0] basesoc_uart_tx_fifo_source_payload_data; +wire basesoc_uart_tx_fifo_re; +reg basesoc_uart_tx_fifo_readable = 1'd0; +wire basesoc_uart_tx_fifo_syncfifo_we; +wire basesoc_uart_tx_fifo_syncfifo_writable; +wire basesoc_uart_tx_fifo_syncfifo_re; +wire basesoc_uart_tx_fifo_syncfifo_readable; +wire [9:0] basesoc_uart_tx_fifo_syncfifo_din; +wire [9:0] basesoc_uart_tx_fifo_syncfifo_dout; +reg [4:0] basesoc_uart_tx_fifo_level0 = 5'd0; +reg basesoc_uart_tx_fifo_replace = 1'd0; +reg [3:0] basesoc_uart_tx_fifo_produce = 4'd0; +reg [3:0] basesoc_uart_tx_fifo_consume = 4'd0; +reg [3:0] basesoc_uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] basesoc_uart_tx_fifo_wrport_dat_r; +wire basesoc_uart_tx_fifo_wrport_we; +wire [9:0] basesoc_uart_tx_fifo_wrport_dat_w; +wire basesoc_uart_tx_fifo_do_read; +wire [3:0] basesoc_uart_tx_fifo_rdport_adr; +wire [9:0] basesoc_uart_tx_fifo_rdport_dat_r; +wire basesoc_uart_tx_fifo_rdport_re; +wire [4:0] basesoc_uart_tx_fifo_level1; +wire [7:0] basesoc_uart_tx_fifo_fifo_in_payload_data; +wire basesoc_uart_tx_fifo_fifo_in_first; +wire basesoc_uart_tx_fifo_fifo_in_last; +wire [7:0] basesoc_uart_tx_fifo_fifo_out_payload_data; +wire basesoc_uart_tx_fifo_fifo_out_first; +wire basesoc_uart_tx_fifo_fifo_out_last; +wire basesoc_uart_rx_fifo_sink_valid; +wire basesoc_uart_rx_fifo_sink_ready; +wire basesoc_uart_rx_fifo_sink_first; +wire basesoc_uart_rx_fifo_sink_last; +wire [7:0] basesoc_uart_rx_fifo_sink_payload_data; +wire basesoc_uart_rx_fifo_source_valid; +wire basesoc_uart_rx_fifo_source_ready; +wire basesoc_uart_rx_fifo_source_first; +wire basesoc_uart_rx_fifo_source_last; +wire [7:0] basesoc_uart_rx_fifo_source_payload_data; +wire basesoc_uart_rx_fifo_re; +reg basesoc_uart_rx_fifo_readable = 1'd0; +wire basesoc_uart_rx_fifo_syncfifo_we; +wire basesoc_uart_rx_fifo_syncfifo_writable; +wire basesoc_uart_rx_fifo_syncfifo_re; +wire basesoc_uart_rx_fifo_syncfifo_readable; +wire [9:0] basesoc_uart_rx_fifo_syncfifo_din; +wire [9:0] basesoc_uart_rx_fifo_syncfifo_dout; +reg [4:0] basesoc_uart_rx_fifo_level0 = 5'd0; +reg basesoc_uart_rx_fifo_replace = 1'd0; +reg [3:0] basesoc_uart_rx_fifo_produce = 4'd0; +reg [3:0] basesoc_uart_rx_fifo_consume = 4'd0; +reg [3:0] basesoc_uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] basesoc_uart_rx_fifo_wrport_dat_r; +wire basesoc_uart_rx_fifo_wrport_we; +wire [9:0] basesoc_uart_rx_fifo_wrport_dat_w; +wire basesoc_uart_rx_fifo_do_read; +wire [3:0] basesoc_uart_rx_fifo_rdport_adr; +wire [9:0] basesoc_uart_rx_fifo_rdport_dat_r; +wire basesoc_uart_rx_fifo_rdport_re; +wire [4:0] basesoc_uart_rx_fifo_level1; +wire [7:0] basesoc_uart_rx_fifo_fifo_in_payload_data; +wire basesoc_uart_rx_fifo_fifo_in_first; +wire basesoc_uart_rx_fifo_fifo_in_last; +wire [7:0] basesoc_uart_rx_fifo_fifo_out_payload_data; +wire basesoc_uart_rx_fifo_fifo_out_first; +wire basesoc_uart_rx_fifo_fifo_out_last; +reg [31:0] basesoc_timer_load_storage = 32'd0; +reg basesoc_timer_load_re = 1'd0; +reg [31:0] basesoc_timer_reload_storage = 32'd0; +reg basesoc_timer_reload_re = 1'd0; +reg basesoc_timer_en_storage = 1'd0; +reg basesoc_timer_en_re = 1'd0; +reg basesoc_timer_update_value_storage = 1'd0; +reg basesoc_timer_update_value_re = 1'd0; +reg [31:0] basesoc_timer_value_status = 32'd0; +wire basesoc_timer_value_we; +reg basesoc_timer_value_re = 1'd0; +wire basesoc_timer_irq; +wire basesoc_timer_zero_status; +reg basesoc_timer_zero_pending = 1'd0; +wire basesoc_timer_zero_trigger; +reg basesoc_timer_zero_clear = 1'd0; +reg basesoc_timer_zero_trigger_d = 1'd0; +wire basesoc_timer_zero0; +wire basesoc_timer_status_status; +wire basesoc_timer_status_we; +reg basesoc_timer_status_re = 1'd0; +wire basesoc_timer_zero1; +wire basesoc_timer_pending_status; +wire basesoc_timer_pending_we; +reg basesoc_timer_pending_re = 1'd0; +reg basesoc_timer_pending_r = 1'd0; +wire basesoc_timer_zero2; +reg basesoc_timer_enable_storage = 1'd0; +reg basesoc_timer_enable_re = 1'd0; +reg [31:0] basesoc_timer_value = 32'd0; +wire crg_rst; +(* dont_touch = "true" *) wire sys_clk; +wire sys_rst; +wire sys2x_clk; +wire idelay_clk; +wire idelay_rst; +wire crg_reset; +reg crg_power_down = 1'd0; +wire crg_locked; +(* dont_touch = "true" *) wire crg_clkin; +wire crg_clkout0; +wire crg_clkout_buf0; +wire crg_clkout1; +wire crg_clkout_buf1; +wire crg_clkout2; +wire crg_clkout_buf2; +reg [3:0] crg_reset_counter = 4'd15; +reg crg_ic_reset = 1'd1; +reg csrstorage0_storage = 1'd140989193; +reg csrstorage0_re = 1'd0; +reg csrstorage1_storage = 1'd0; +reg csrstorage1_re = 1'd0; +reg directory0_re = 1'd0; +reg directory0_r = 1'd0; +wire directory0_w; +reg csr_08000_re = 1'd0; +reg csr_08000_r = 1'd0; +wire csr_08000_w; +wire [29:0] basesoc_ram_bus_adr; +wire [31:0] basesoc_ram_bus_dat_w; +wire [31:0] basesoc_ram_bus_dat_r; +wire [3:0] basesoc_ram_bus_sel; +wire basesoc_ram_bus_cyc; +wire basesoc_ram_bus_stb; +reg basesoc_ram_bus_ack = 1'd0; +wire basesoc_ram_bus_we; +wire [2:0] basesoc_ram_bus_cti; +wire [1:0] basesoc_ram_bus_bte; +reg basesoc_ram_bus_err = 1'd0; +wire [13:0] basesoc_adr; +wire [31:0] basesoc_dat_r; +wire [29:0] sram_bus_adr; +wire [31:0] sram_bus_dat_w; +wire [31:0] sram_bus_dat_r; +wire [3:0] sram_bus_sel; +wire sram_bus_cyc; +wire sram_bus_stb; +wire sram_bus_ack; +wire sram_bus_we; +wire [2:0] sram_bus_cti; +wire [1:0] sram_bus_bte; +reg sram_bus_err = 1'd0; +reg [56:0] dna_status = 57'd0; +wire dna_we; +reg dna_re = 1'd0; +wire dna_do; +reg [6:0] dna_count = 7'd0; +wire dna_clk; +reg [11:0] xadc_temperature_status = 12'd0; +wire xadc_temperature_we; +reg xadc_temperature_re = 1'd0; +reg [11:0] xadc_vccint_status = 12'd0; +wire xadc_vccint_we; +reg xadc_vccint_re = 1'd0; +reg [11:0] xadc_vccaux_status = 12'd0; +wire xadc_vccaux_we; +reg xadc_vccaux_re = 1'd0; +reg [11:0] xadc_vccbram_status = 12'd0; +wire xadc_vccbram_we; +reg xadc_vccbram_re = 1'd0; +reg xadc_eoc_status = 1'd0; +wire xadc_eoc_we; +reg xadc_eoc_re = 1'd0; +reg xadc_eos_status = 1'd0; +wire xadc_eos_we; +reg xadc_eos_re = 1'd0; +wire [7:0] xadc_alarm; +wire xadc_ot; +wire xadc_busy; +wire [6:0] xadc_channel; +wire xadc_eoc; +wire xadc_eos; +reg xadc_dwe = 1'd0; +reg xadc_den = 1'd0; +wire xadc_drdy; +reg [6:0] xadc_dadr = 7'd0; +reg [15:0] xadc_di = 16'd0; +wire [15:0] xadc_do; +reg xadc_drp_en = 1'd0; +reg [1:0] leds_storage = 2'd0; +reg leds_re = 1'd0; +reg [1:0] leds_chaser = 2'd0; +reg leds_mode = 1'd0; +wire leds_wait; +wire leds_done; +reg [24:0] leds_count = 25'd25000000; +wire [1:0] buttons_status; +wire buttons_we; +reg buttons_re = 1'd0; +wire scl; +wire oe; +wire sda0; +reg [2:0] _w_storage = 3'd0; +reg _w_re = 1'd0; +wire sda1; +wire _r_status; +wire _r_we; +reg _r_re = 1'd0; +reg uart_1_phy_tx_sink_valid = 1'd0; +reg uart_1_phy_tx_sink_ready = 1'd0; +wire uart_1_phy_tx_sink_last; +reg [7:0] uart_1_phy_tx_sink_payload_data = 8'd0; +reg [7:0] uart_1_phy_tx_data = 8'd0; +reg [3:0] uart_1_phy_tx_count = 4'd0; +reg uart_1_phy_tx_enable = 1'd0; +reg uart_1_phy_tx_tick = 1'd0; +reg [31:0] uart_1_phy_tx_phase = 32'd0; +reg uart_1_phy_rx_source_valid = 1'd0; +reg uart_1_phy_rx_source_ready = 1'd0; +reg [7:0] uart_1_phy_rx_source_payload_data = 8'd0; +reg [7:0] uart_1_phy_rx_data = 8'd0; +reg [3:0] uart_1_phy_rx_count = 4'd0; +reg uart_1_phy_rx_enable = 1'd0; +reg uart_1_phy_rx_tick = 1'd0; +reg [31:0] uart_1_phy_rx_phase = 32'd0; +wire uart_1_phy_rx_rx; +reg uart_1_phy_rx_rx_d = 1'd0; +wire [29:0] uart_1_wishbone_adr; +wire [31:0] uart_1_wishbone_dat_w; +reg [31:0] uart_1_wishbone_dat_r = 32'd0; +wire [3:0] uart_1_wishbone_sel; +reg uart_1_wishbone_cyc = 1'd0; +reg uart_1_wishbone_stb = 1'd0; +reg uart_1_wishbone_ack = 1'd0; +reg uart_1_wishbone_we = 1'd0; +reg [7:0] uart_1_cmd = 8'd0; +reg uart_1_incr = 1'd0; +reg [7:0] uart_1_length = 8'd0; +reg [31:0] uart_1_address = 32'd0; +reg [31:0] uart_1_data = 32'd0; +reg [1:0] uart_1_bytes_count = 2'd0; +reg [7:0] uart_1_words_count = 8'd0; +wire uart_1_reset; +wire uart_1_wait; +wire uart_1_done; +reg [23:0] uart_1_count = 24'd10000000; +reg uart_1_is_ongoing = 1'd0; +reg dshot_0_storage = 1'd0; +reg dshot_0_re = 1'd0; +reg subfragments_rs232phytx0_state = 1'd0; +reg subfragments_rs232phytx0_next_state = 1'd0; +reg [3:0] basesoc_tx_count_rs232phytx0_next_value0 = 4'd0; +reg basesoc_tx_count_rs232phytx0_next_value_ce0 = 1'd0; +reg basesoc_serial_tx_rs232phytx0_next_value1 = 1'd0; +reg basesoc_serial_tx_rs232phytx0_next_value_ce1 = 1'd0; +reg [7:0] basesoc_tx_data_rs232phytx0_next_value2 = 8'd0; +reg basesoc_tx_data_rs232phytx0_next_value_ce2 = 1'd0; +reg subfragments_rs232phyrx0_state = 1'd0; +reg subfragments_rs232phyrx0_next_state = 1'd0; +reg [3:0] basesoc_rx_count_rs232phyrx0_next_value0 = 4'd0; +reg basesoc_rx_count_rs232phyrx0_next_value_ce0 = 1'd0; +reg [7:0] basesoc_rx_data_rs232phyrx0_next_value1 = 8'd0; +reg basesoc_rx_data_rs232phyrx0_next_value_ce1 = 1'd0; +wire subfragments_reset0; +wire subfragments_reset1; +wire subfragments_reset2; +wire subfragments_reset3; +wire subfragments_reset4; +wire subfragments_reset5; +wire subfragments_reset6; +wire subfragments_reset7; +wire subfragments_mmcm_fb; +reg subfragments_rs232phytx1_state = 1'd0; +reg subfragments_rs232phytx1_next_state = 1'd0; +reg [3:0] uart_1_phy_tx_count_rs232phytx1_next_value0 = 4'd0; +reg uart_1_phy_tx_count_rs232phytx1_next_value_ce0 = 1'd0; +reg tx_obj_rs232phytx1_next_value1 = 1'd0; +reg tx_obj_rs232phytx1_next_value_ce1 = 1'd0; +reg [7:0] uart_1_phy_tx_data_rs232phytx1_next_value2 = 8'd0; +reg uart_1_phy_tx_data_rs232phytx1_next_value_ce2 = 1'd0; +reg subfragments_rs232phyrx1_state = 1'd0; +reg subfragments_rs232phyrx1_next_state = 1'd0; +reg [3:0] uart_1_phy_rx_count_rs232phyrx1_next_value0 = 4'd0; +reg uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 = 1'd0; +reg [7:0] uart_1_phy_rx_data_rs232phyrx1_next_value1 = 8'd0; +reg uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 = 1'd0; +reg [2:0] subfragments_state = 3'd0; +reg [2:0] subfragments_next_state = 3'd0; +reg [1:0] uart_1_bytes_count_next_value0 = 2'd0; +reg uart_1_bytes_count_next_value_ce0 = 1'd0; +reg [7:0] uart_1_words_count_next_value1 = 8'd0; +reg uart_1_words_count_next_value_ce1 = 1'd0; +reg [7:0] uart_1_cmd_next_value2 = 8'd0; +reg uart_1_cmd_next_value_ce2 = 1'd0; +reg [7:0] uart_1_length_next_value3 = 8'd0; +reg uart_1_length_next_value_ce3 = 1'd0; +reg [31:0] uart_1_address_next_value4 = 32'd0; +reg uart_1_address_next_value_ce4 = 1'd0; +reg uart_1_incr_next_value5 = 1'd0; +reg uart_1_incr_next_value_ce5 = 1'd0; +reg [31:0] uart_1_data_next_value6 = 32'd0; +reg uart_1_data_next_value_ce6 = 1'd0; +reg [13:0] basesoc_basesoc_adr = 14'd0; +reg basesoc_basesoc_we = 1'd0; +reg [31:0] basesoc_basesoc_dat_w = 32'd0; +wire [31:0] basesoc_basesoc_dat_r; +wire [29:0] basesoc_basesoc_wishbone_adr; +wire [31:0] basesoc_basesoc_wishbone_dat_w; +reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0; +wire [3:0] basesoc_basesoc_wishbone_sel; +wire basesoc_basesoc_wishbone_cyc; +wire basesoc_basesoc_wishbone_stb; +reg basesoc_basesoc_wishbone_ack = 1'd0; +wire basesoc_basesoc_wishbone_we; +wire [2:0] basesoc_basesoc_wishbone_cti; +wire [1:0] basesoc_basesoc_wishbone_bte; +reg basesoc_basesoc_wishbone_err = 1'd0; +wire [29:0] basesoc_shared_adr; +wire [31:0] basesoc_shared_dat_w; +reg [31:0] basesoc_shared_dat_r = 32'd0; +wire [3:0] basesoc_shared_sel; +wire basesoc_shared_cyc; +wire basesoc_shared_stb; +reg basesoc_shared_ack = 1'd0; +wire basesoc_shared_we; +wire [2:0] basesoc_shared_cti; +wire [1:0] basesoc_shared_bte; +wire basesoc_shared_err; +wire [1:0] basesoc_request; +reg basesoc_grant = 1'd0; +reg [2:0] basesoc_slave_sel = 3'd0; +reg [2:0] basesoc_slave_sel_r = 3'd0; +reg basesoc_error = 1'd0; +wire basesoc_wait; +wire basesoc_done; +reg [19:0] basesoc_count = 20'd1000000; +wire [13:0] basesoc_csr_bankarray_interface0_bank_bus_adr; +wire basesoc_csr_bankarray_interface0_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface0_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank0_in_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank0_in_r; +reg basesoc_csr_bankarray_csrbank0_in_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank0_in_w; +wire basesoc_csr_bankarray_csrbank0_sel; +wire [13:0] basesoc_csr_bankarray_interface1_bank_bus_adr; +wire basesoc_csr_bankarray_interface1_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface1_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank1_reset0_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank1_reset0_r; +reg basesoc_csr_bankarray_csrbank1_reset0_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank1_reset0_w; +reg basesoc_csr_bankarray_csrbank1_scratch0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_scratch0_r; +reg basesoc_csr_bankarray_csrbank1_scratch0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_scratch0_w; +reg basesoc_csr_bankarray_csrbank1_bus_errors_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_bus_errors_r; +reg basesoc_csr_bankarray_csrbank1_bus_errors_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank1_bus_errors_w; +wire basesoc_csr_bankarray_csrbank1_sel; +wire [13:0] basesoc_csr_bankarray_interface2_bank_bus_adr; +wire basesoc_csr_bankarray_interface2_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface2_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank2_id1_re = 1'd0; +wire [24:0] basesoc_csr_bankarray_csrbank2_id1_r; +reg basesoc_csr_bankarray_csrbank2_id1_we = 1'd0; +wire [24:0] basesoc_csr_bankarray_csrbank2_id1_w; +reg basesoc_csr_bankarray_csrbank2_id0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank2_id0_r; +reg basesoc_csr_bankarray_csrbank2_id0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank2_id0_w; +wire basesoc_csr_bankarray_csrbank2_sel; +wire [13:0] basesoc_csr_bankarray_interface3_bank_bus_adr; +wire basesoc_csr_bankarray_interface3_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface3_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank3_out0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank3_out0_r; +reg basesoc_csr_bankarray_csrbank3_out0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank3_out0_w; +wire basesoc_csr_bankarray_csrbank3_sel; +wire [13:0] basesoc_csr_bankarray_interface4_bank_bus_adr; +wire basesoc_csr_bankarray_interface4_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface4_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank4_w0_re = 1'd0; +wire [2:0] basesoc_csr_bankarray_csrbank4_w0_r; +reg basesoc_csr_bankarray_csrbank4_w0_we = 1'd0; +wire [2:0] basesoc_csr_bankarray_csrbank4_w0_w; +reg basesoc_csr_bankarray_csrbank4_r_re = 1'd0; +wire basesoc_csr_bankarray_csrbank4_r_r; +reg basesoc_csr_bankarray_csrbank4_r_we = 1'd0; +wire basesoc_csr_bankarray_csrbank4_r_w; +wire basesoc_csr_bankarray_csrbank4_sel; +wire [13:0] basesoc_csr_bankarray_sram_bus_adr; +wire basesoc_csr_bankarray_sram_bus_we; +wire [31:0] basesoc_csr_bankarray_sram_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_sram_bus_dat_r = 32'd0; +wire [4:0] basesoc_csr_bankarray_adr; +wire [7:0] basesoc_csr_bankarray_dat_r; +wire basesoc_csr_bankarray_sel; +reg basesoc_csr_bankarray_sel_r = 1'd0; +wire [13:0] basesoc_csr_bankarray_interface5_bank_bus_adr; +wire basesoc_csr_bankarray_interface5_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface5_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank5_out0_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank5_out0_r; +reg basesoc_csr_bankarray_csrbank5_out0_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank5_out0_w; +wire basesoc_csr_bankarray_csrbank5_sel; +wire [13:0] basesoc_csr_bankarray_interface6_bank_bus_adr; +wire basesoc_csr_bankarray_interface6_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface6_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank6_load0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_load0_r; +reg basesoc_csr_bankarray_csrbank6_load0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_load0_w; +reg basesoc_csr_bankarray_csrbank6_reload0_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_reload0_r; +reg basesoc_csr_bankarray_csrbank6_reload0_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_reload0_w; +reg basesoc_csr_bankarray_csrbank6_en0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_en0_r; +reg basesoc_csr_bankarray_csrbank6_en0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_en0_w; +reg basesoc_csr_bankarray_csrbank6_update_value0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_update_value0_r; +reg basesoc_csr_bankarray_csrbank6_update_value0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_update_value0_w; +reg basesoc_csr_bankarray_csrbank6_value_re = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_value_r; +reg basesoc_csr_bankarray_csrbank6_value_we = 1'd0; +wire [31:0] basesoc_csr_bankarray_csrbank6_value_w; +reg basesoc_csr_bankarray_csrbank6_ev_status_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_status_r; +reg basesoc_csr_bankarray_csrbank6_ev_status_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_status_w; +reg basesoc_csr_bankarray_csrbank6_ev_pending_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_pending_r; +reg basesoc_csr_bankarray_csrbank6_ev_pending_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_pending_w; +reg basesoc_csr_bankarray_csrbank6_ev_enable0_re = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_enable0_r; +reg basesoc_csr_bankarray_csrbank6_ev_enable0_we = 1'd0; +wire basesoc_csr_bankarray_csrbank6_ev_enable0_w; +wire basesoc_csr_bankarray_csrbank6_sel; +wire [13:0] basesoc_csr_bankarray_interface7_bank_bus_adr; +wire basesoc_csr_bankarray_interface7_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface7_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank7_txfull_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txfull_r; +reg basesoc_csr_bankarray_csrbank7_txfull_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txfull_w; +reg basesoc_csr_bankarray_csrbank7_rxempty_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxempty_r; +reg basesoc_csr_bankarray_csrbank7_rxempty_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxempty_w; +reg basesoc_csr_bankarray_csrbank7_ev_status_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_status_r; +reg basesoc_csr_bankarray_csrbank7_ev_status_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_status_w; +reg basesoc_csr_bankarray_csrbank7_ev_pending_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_pending_r; +reg basesoc_csr_bankarray_csrbank7_ev_pending_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_pending_w; +reg basesoc_csr_bankarray_csrbank7_ev_enable0_re = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_enable0_r; +reg basesoc_csr_bankarray_csrbank7_ev_enable0_we = 1'd0; +wire [1:0] basesoc_csr_bankarray_csrbank7_ev_enable0_w; +reg basesoc_csr_bankarray_csrbank7_txempty_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txempty_r; +reg basesoc_csr_bankarray_csrbank7_txempty_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_txempty_w; +reg basesoc_csr_bankarray_csrbank7_rxfull_re = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxfull_r; +reg basesoc_csr_bankarray_csrbank7_rxfull_we = 1'd0; +wire basesoc_csr_bankarray_csrbank7_rxfull_w; +wire basesoc_csr_bankarray_csrbank7_sel; +wire [13:0] basesoc_csr_bankarray_interface8_bank_bus_adr; +wire basesoc_csr_bankarray_interface8_bank_bus_we; +wire [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_w; +reg [31:0] basesoc_csr_bankarray_interface8_bank_bus_dat_r = 32'd0; +reg basesoc_csr_bankarray_csrbank8_temperature_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_temperature_r; +reg basesoc_csr_bankarray_csrbank8_temperature_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_temperature_w; +reg basesoc_csr_bankarray_csrbank8_vccint_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccint_r; +reg basesoc_csr_bankarray_csrbank8_vccint_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccint_w; +reg basesoc_csr_bankarray_csrbank8_vccaux_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccaux_r; +reg basesoc_csr_bankarray_csrbank8_vccaux_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccaux_w; +reg basesoc_csr_bankarray_csrbank8_vccbram_re = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccbram_r; +reg basesoc_csr_bankarray_csrbank8_vccbram_we = 1'd0; +wire [11:0] basesoc_csr_bankarray_csrbank8_vccbram_w; +reg basesoc_csr_bankarray_csrbank8_eoc_re = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eoc_r; +reg basesoc_csr_bankarray_csrbank8_eoc_we = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eoc_w; +reg basesoc_csr_bankarray_csrbank8_eos_re = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eos_r; +reg basesoc_csr_bankarray_csrbank8_eos_we = 1'd0; +wire basesoc_csr_bankarray_csrbank8_eos_w; +wire basesoc_csr_bankarray_csrbank8_sel; +wire [13:0] basesoc_csr_interconnect_adr; +wire basesoc_csr_interconnect_we; +wire [31:0] basesoc_csr_interconnect_dat_w; +wire [31:0] basesoc_csr_interconnect_dat_r; +reg basesoc_state = 1'd0; +reg basesoc_next_state = 1'd0; +reg [29:0] array_muxed0 = 30'd0; +reg [31:0] array_muxed1 = 32'd0; +reg [3:0] array_muxed2 = 4'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg [2:0] array_muxed6 = 3'd0; +reg [1:0] array_muxed7 = 2'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_expr; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl1_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] xilinxmultiregimpl1_regs1 = 2'd0; +wire xilinxmultiregimpl1; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign basesoc_reset = (basesoc_soc_rst | basesoc_cpu_rst); +assign crg_rst = basesoc_soc_rst; +assign basesoc_bus_error = basesoc_error; +always @(*) begin + basesoc_interrupt <= 32'd0; + basesoc_interrupt[1] <= basesoc_timer_irq; + basesoc_interrupt[0] <= basesoc_uart_irq; +end +assign basesoc_bus_errors_status = basesoc_bus_errors; +always @(*) begin + subfragments_rs232phytx0_next_state <= 1'd0; + basesoc_tx_count_rs232phytx0_next_value0 <= 4'd0; + basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd0; + basesoc_tx_sink_ready <= 1'd0; + basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd0; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd0; + basesoc_tx_data_rs232phytx0_next_value2 <= 8'd0; + basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd0; + basesoc_tx_enable <= 1'd0; + subfragments_rs232phytx0_next_state <= subfragments_rs232phytx0_state; + case (subfragments_rs232phytx0_state) + 1'd1: begin + basesoc_tx_enable <= 1'd1; + if (basesoc_tx_tick) begin + basesoc_serial_tx_rs232phytx0_next_value1 <= basesoc_tx_data; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1; + basesoc_tx_count_rs232phytx0_next_value0 <= (basesoc_tx_count + 1'd1); + basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd1; + basesoc_tx_data_rs232phytx0_next_value2 <= {1'd1, basesoc_tx_data[7:1]}; + basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd1; + if ((basesoc_tx_count == 4'd9)) begin + basesoc_tx_sink_ready <= 1'd1; + subfragments_rs232phytx0_next_state <= 1'd0; + end + end + end + default: begin + basesoc_tx_count_rs232phytx0_next_value0 <= 1'd0; + basesoc_tx_count_rs232phytx0_next_value_ce0 <= 1'd1; + basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd1; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1; + if (basesoc_tx_sink_valid) begin + basesoc_serial_tx_rs232phytx0_next_value1 <= 1'd0; + basesoc_serial_tx_rs232phytx0_next_value_ce1 <= 1'd1; + basesoc_tx_data_rs232phytx0_next_value2 <= basesoc_tx_sink_payload_data; + basesoc_tx_data_rs232phytx0_next_value_ce2 <= 1'd1; + subfragments_rs232phytx0_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + subfragments_rs232phyrx0_next_state <= 1'd0; + basesoc_rx_count_rs232phyrx0_next_value0 <= 4'd0; + basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd0; + basesoc_rx_source_valid <= 1'd0; + basesoc_rx_source_payload_data <= 8'd0; + basesoc_rx_data_rs232phyrx0_next_value1 <= 8'd0; + basesoc_rx_data_rs232phyrx0_next_value_ce1 <= 1'd0; + basesoc_rx_enable <= 1'd0; + subfragments_rs232phyrx0_next_state <= subfragments_rs232phyrx0_state; + case (subfragments_rs232phyrx0_state) + 1'd1: begin + basesoc_rx_enable <= 1'd1; + if (basesoc_rx_tick) begin + basesoc_rx_count_rs232phyrx0_next_value0 <= (basesoc_rx_count + 1'd1); + basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1; + basesoc_rx_data_rs232phyrx0_next_value1 <= {basesoc_rx_rx, basesoc_rx_data[7:1]}; + basesoc_rx_data_rs232phyrx0_next_value_ce1 <= 1'd1; + if ((basesoc_rx_count == 4'd9)) begin + basesoc_rx_source_valid <= (basesoc_rx_rx == 1'd1); + basesoc_rx_source_payload_data <= basesoc_rx_data; + subfragments_rs232phyrx0_next_state <= 1'd0; + end + end + end + default: begin + basesoc_rx_count_rs232phyrx0_next_value0 <= 1'd0; + basesoc_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1; + if (((basesoc_rx_rx == 1'd0) & (basesoc_rx_rx_d == 1'd1))) begin + subfragments_rs232phyrx0_next_state <= 1'd1; + end + end + endcase +end +assign basesoc_uart_uart_sink_valid = basesoc_rx_source_valid; +assign basesoc_rx_source_ready = basesoc_uart_uart_sink_ready; +assign basesoc_uart_uart_sink_first = basesoc_rx_source_first; +assign basesoc_uart_uart_sink_last = basesoc_rx_source_last; +assign basesoc_uart_uart_sink_payload_data = basesoc_rx_source_payload_data; +assign basesoc_tx_sink_valid = basesoc_uart_uart_source_valid; +assign basesoc_uart_uart_source_ready = basesoc_tx_sink_ready; +assign basesoc_tx_sink_first = basesoc_uart_uart_source_first; +assign basesoc_tx_sink_last = basesoc_uart_uart_source_last; +assign basesoc_tx_sink_payload_data = basesoc_uart_uart_source_payload_data; +assign basesoc_uart_tx_fifo_sink_valid = basesoc_uart_rxtx_re; +assign basesoc_uart_tx_fifo_sink_payload_data = basesoc_uart_rxtx_r; +assign basesoc_uart_uart_source_valid = basesoc_uart_tx_fifo_source_valid; +assign basesoc_uart_tx_fifo_source_ready = basesoc_uart_uart_source_ready; +assign basesoc_uart_uart_source_first = basesoc_uart_tx_fifo_source_first; +assign basesoc_uart_uart_source_last = basesoc_uart_tx_fifo_source_last; +assign basesoc_uart_uart_source_payload_data = basesoc_uart_tx_fifo_source_payload_data; +assign basesoc_uart_txfull_status = (~basesoc_uart_tx_fifo_sink_ready); +assign basesoc_uart_txempty_status = (~basesoc_uart_tx_fifo_source_valid); +assign basesoc_uart_tx_trigger = basesoc_uart_tx_fifo_sink_ready; +assign basesoc_uart_rx_fifo_sink_valid = basesoc_uart_uart_sink_valid; +assign basesoc_uart_uart_sink_ready = basesoc_uart_rx_fifo_sink_ready; +assign basesoc_uart_rx_fifo_sink_first = basesoc_uart_uart_sink_first; +assign basesoc_uart_rx_fifo_sink_last = basesoc_uart_uart_sink_last; +assign basesoc_uart_rx_fifo_sink_payload_data = basesoc_uart_uart_sink_payload_data; +assign basesoc_uart_rxtx_w = basesoc_uart_rx_fifo_source_payload_data; +assign basesoc_uart_rx_fifo_source_ready = (basesoc_uart_rx_clear | (1'd0 & basesoc_uart_rxtx_we)); +assign basesoc_uart_rxempty_status = (~basesoc_uart_rx_fifo_source_valid); +assign basesoc_uart_rxfull_status = (~basesoc_uart_rx_fifo_sink_ready); +assign basesoc_uart_rx_trigger = basesoc_uart_rx_fifo_source_valid; +assign basesoc_uart_tx0 = basesoc_uart_tx_status; +assign basesoc_uart_tx1 = basesoc_uart_tx_pending; +always @(*) begin + basesoc_uart_tx_clear <= 1'd0; + if ((basesoc_uart_pending_re & basesoc_uart_pending_r[0])) begin + basesoc_uart_tx_clear <= 1'd1; + end +end +assign basesoc_uart_rx0 = basesoc_uart_rx_status; +assign basesoc_uart_rx1 = basesoc_uart_rx_pending; +always @(*) begin + basesoc_uart_rx_clear <= 1'd0; + if ((basesoc_uart_pending_re & basesoc_uart_pending_r[1])) begin + basesoc_uart_rx_clear <= 1'd1; + end +end +assign basesoc_uart_irq = ((basesoc_uart_pending_status[0] & basesoc_uart_enable_storage[0]) | (basesoc_uart_pending_status[1] & basesoc_uart_enable_storage[1])); +assign basesoc_uart_tx_status = basesoc_uart_tx_trigger; +assign basesoc_uart_rx_status = basesoc_uart_rx_trigger; +assign basesoc_uart_tx_fifo_syncfifo_din = {basesoc_uart_tx_fifo_fifo_in_last, basesoc_uart_tx_fifo_fifo_in_first, basesoc_uart_tx_fifo_fifo_in_payload_data}; +assign {basesoc_uart_tx_fifo_fifo_out_last, basesoc_uart_tx_fifo_fifo_out_first, basesoc_uart_tx_fifo_fifo_out_payload_data} = basesoc_uart_tx_fifo_syncfifo_dout; +assign basesoc_uart_tx_fifo_sink_ready = basesoc_uart_tx_fifo_syncfifo_writable; +assign basesoc_uart_tx_fifo_syncfifo_we = basesoc_uart_tx_fifo_sink_valid; +assign basesoc_uart_tx_fifo_fifo_in_first = basesoc_uart_tx_fifo_sink_first; +assign basesoc_uart_tx_fifo_fifo_in_last = basesoc_uart_tx_fifo_sink_last; +assign basesoc_uart_tx_fifo_fifo_in_payload_data = basesoc_uart_tx_fifo_sink_payload_data; +assign basesoc_uart_tx_fifo_source_valid = basesoc_uart_tx_fifo_readable; +assign basesoc_uart_tx_fifo_source_first = basesoc_uart_tx_fifo_fifo_out_first; +assign basesoc_uart_tx_fifo_source_last = basesoc_uart_tx_fifo_fifo_out_last; +assign basesoc_uart_tx_fifo_source_payload_data = basesoc_uart_tx_fifo_fifo_out_payload_data; +assign basesoc_uart_tx_fifo_re = basesoc_uart_tx_fifo_source_ready; +assign basesoc_uart_tx_fifo_syncfifo_re = (basesoc_uart_tx_fifo_syncfifo_readable & ((~basesoc_uart_tx_fifo_readable) | basesoc_uart_tx_fifo_re)); +assign basesoc_uart_tx_fifo_level1 = (basesoc_uart_tx_fifo_level0 + basesoc_uart_tx_fifo_readable); +always @(*) begin + basesoc_uart_tx_fifo_wrport_adr <= 4'd0; + if (basesoc_uart_tx_fifo_replace) begin + basesoc_uart_tx_fifo_wrport_adr <= (basesoc_uart_tx_fifo_produce - 1'd1); + end else begin + basesoc_uart_tx_fifo_wrport_adr <= basesoc_uart_tx_fifo_produce; + end +end +assign basesoc_uart_tx_fifo_wrport_dat_w = basesoc_uart_tx_fifo_syncfifo_din; +assign basesoc_uart_tx_fifo_wrport_we = (basesoc_uart_tx_fifo_syncfifo_we & (basesoc_uart_tx_fifo_syncfifo_writable | basesoc_uart_tx_fifo_replace)); +assign basesoc_uart_tx_fifo_do_read = (basesoc_uart_tx_fifo_syncfifo_readable & basesoc_uart_tx_fifo_syncfifo_re); +assign basesoc_uart_tx_fifo_rdport_adr = basesoc_uart_tx_fifo_consume; +assign basesoc_uart_tx_fifo_syncfifo_dout = basesoc_uart_tx_fifo_rdport_dat_r; +assign basesoc_uart_tx_fifo_rdport_re = basesoc_uart_tx_fifo_do_read; +assign basesoc_uart_tx_fifo_syncfifo_writable = (basesoc_uart_tx_fifo_level0 != 5'd16); +assign basesoc_uart_tx_fifo_syncfifo_readable = (basesoc_uart_tx_fifo_level0 != 1'd0); +assign basesoc_uart_rx_fifo_syncfifo_din = {basesoc_uart_rx_fifo_fifo_in_last, basesoc_uart_rx_fifo_fifo_in_first, basesoc_uart_rx_fifo_fifo_in_payload_data}; +assign {basesoc_uart_rx_fifo_fifo_out_last, basesoc_uart_rx_fifo_fifo_out_first, basesoc_uart_rx_fifo_fifo_out_payload_data} = basesoc_uart_rx_fifo_syncfifo_dout; +assign basesoc_uart_rx_fifo_sink_ready = basesoc_uart_rx_fifo_syncfifo_writable; +assign basesoc_uart_rx_fifo_syncfifo_we = basesoc_uart_rx_fifo_sink_valid; +assign basesoc_uart_rx_fifo_fifo_in_first = basesoc_uart_rx_fifo_sink_first; +assign basesoc_uart_rx_fifo_fifo_in_last = basesoc_uart_rx_fifo_sink_last; +assign basesoc_uart_rx_fifo_fifo_in_payload_data = basesoc_uart_rx_fifo_sink_payload_data; +assign basesoc_uart_rx_fifo_source_valid = basesoc_uart_rx_fifo_readable; +assign basesoc_uart_rx_fifo_source_first = basesoc_uart_rx_fifo_fifo_out_first; +assign basesoc_uart_rx_fifo_source_last = basesoc_uart_rx_fifo_fifo_out_last; +assign basesoc_uart_rx_fifo_source_payload_data = basesoc_uart_rx_fifo_fifo_out_payload_data; +assign basesoc_uart_rx_fifo_re = basesoc_uart_rx_fifo_source_ready; +assign basesoc_uart_rx_fifo_syncfifo_re = (basesoc_uart_rx_fifo_syncfifo_readable & ((~basesoc_uart_rx_fifo_readable) | basesoc_uart_rx_fifo_re)); +assign basesoc_uart_rx_fifo_level1 = (basesoc_uart_rx_fifo_level0 + basesoc_uart_rx_fifo_readable); +always @(*) begin + basesoc_uart_rx_fifo_wrport_adr <= 4'd0; + if (basesoc_uart_rx_fifo_replace) begin + basesoc_uart_rx_fifo_wrport_adr <= (basesoc_uart_rx_fifo_produce - 1'd1); + end else begin + basesoc_uart_rx_fifo_wrport_adr <= basesoc_uart_rx_fifo_produce; + end +end +assign basesoc_uart_rx_fifo_wrport_dat_w = basesoc_uart_rx_fifo_syncfifo_din; +assign basesoc_uart_rx_fifo_wrport_we = (basesoc_uart_rx_fifo_syncfifo_we & (basesoc_uart_rx_fifo_syncfifo_writable | basesoc_uart_rx_fifo_replace)); +assign basesoc_uart_rx_fifo_do_read = (basesoc_uart_rx_fifo_syncfifo_readable & basesoc_uart_rx_fifo_syncfifo_re); +assign basesoc_uart_rx_fifo_rdport_adr = basesoc_uart_rx_fifo_consume; +assign basesoc_uart_rx_fifo_syncfifo_dout = basesoc_uart_rx_fifo_rdport_dat_r; +assign basesoc_uart_rx_fifo_rdport_re = basesoc_uart_rx_fifo_do_read; +assign basesoc_uart_rx_fifo_syncfifo_writable = (basesoc_uart_rx_fifo_level0 != 5'd16); +assign basesoc_uart_rx_fifo_syncfifo_readable = (basesoc_uart_rx_fifo_level0 != 1'd0); +assign basesoc_timer_zero_trigger = (basesoc_timer_value == 1'd0); +assign basesoc_timer_zero0 = basesoc_timer_zero_status; +assign basesoc_timer_zero1 = basesoc_timer_zero_pending; +always @(*) begin + basesoc_timer_zero_clear <= 1'd0; + if ((basesoc_timer_pending_re & basesoc_timer_pending_r)) begin + basesoc_timer_zero_clear <= 1'd1; + end +end +assign basesoc_timer_irq = (basesoc_timer_pending_status & basesoc_timer_enable_storage); +assign basesoc_timer_zero_status = basesoc_timer_zero_trigger; +assign crg_reset = crg_rst; +assign crg_clkin = clk12; +assign sys_clk = crg_clkout_buf0; +assign sys2x_clk = crg_clkout_buf1; +assign idelay_clk = crg_clkout_buf2; +assign directory0_w = csrstorage0_storage; +assign csr_08000_w = csrstorage1_storage; +assign basesoc_adr = basesoc_ram_bus_adr[13:0]; +assign basesoc_ram_bus_dat_r = basesoc_dat_r; +assign dna_clk = dna_count[0]; +always @(*) begin + xadc_den <= 1'd0; + xadc_dadr <= 7'd0; + if ((~xadc_drp_en)) begin + xadc_den <= xadc_eoc; + xadc_dadr <= xadc_channel; + end +end +assign leds_wait = (~leds_done); +always @(*) begin + user_led1 <= 1'd0; + user_led0 <= 1'd0; + if ((leds_mode == 1'd1)) begin + {user_led1, user_led0} <= leds_storage; + end else begin + {user_led1, user_led0} <= leds_chaser; + end +end +assign leds_done = (leds_count == 1'd0); +always @(*) begin + subfragments_rs232phytx1_next_state <= 1'd0; + uart_1_phy_tx_count_rs232phytx1_next_value0 <= 4'd0; + uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd0; + uart_1_phy_tx_enable <= 1'd0; + tx_obj_rs232phytx1_next_value1 <= 1'd0; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd0; + uart_1_phy_tx_data_rs232phytx1_next_value2 <= 8'd0; + uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd0; + uart_1_phy_tx_sink_ready <= 1'd0; + subfragments_rs232phytx1_next_state <= subfragments_rs232phytx1_state; + case (subfragments_rs232phytx1_state) + 1'd1: begin + uart_1_phy_tx_enable <= 1'd1; + if (uart_1_phy_tx_tick) begin + tx_obj_rs232phytx1_next_value1 <= uart_1_phy_tx_data; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd1; + uart_1_phy_tx_count_rs232phytx1_next_value0 <= (uart_1_phy_tx_count + 1'd1); + uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1; + uart_1_phy_tx_data_rs232phytx1_next_value2 <= {1'd1, uart_1_phy_tx_data[7:1]}; + uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd1; + if ((uart_1_phy_tx_count == 4'd9)) begin + uart_1_phy_tx_sink_ready <= 1'd1; + subfragments_rs232phytx1_next_state <= 1'd0; + end + end + end + default: begin + uart_1_phy_tx_count_rs232phytx1_next_value0 <= 1'd0; + uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1; + tx_obj_rs232phytx1_next_value1 <= 1'd1; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd1; + if (uart_1_phy_tx_sink_valid) begin + tx_obj_rs232phytx1_next_value1 <= 1'd0; + tx_obj_rs232phytx1_next_value_ce1 <= 1'd1; + uart_1_phy_tx_data_rs232phytx1_next_value2 <= uart_1_phy_tx_sink_payload_data; + uart_1_phy_tx_data_rs232phytx1_next_value_ce2 <= 1'd1; + subfragments_rs232phytx1_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + uart_1_phy_rx_source_payload_data <= 8'd0; + subfragments_rs232phyrx1_next_state <= 1'd0; + uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 4'd0; + uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd0; + uart_1_phy_rx_enable <= 1'd0; + uart_1_phy_rx_data_rs232phyrx1_next_value1 <= 8'd0; + uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd0; + uart_1_phy_rx_source_valid <= 1'd0; + subfragments_rs232phyrx1_next_state <= subfragments_rs232phyrx1_state; + case (subfragments_rs232phyrx1_state) + 1'd1: begin + uart_1_phy_rx_enable <= 1'd1; + if (uart_1_phy_rx_tick) begin + uart_1_phy_rx_count_rs232phyrx1_next_value0 <= (uart_1_phy_rx_count + 1'd1); + uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1; + uart_1_phy_rx_data_rs232phyrx1_next_value1 <= {uart_1_phy_rx_rx, uart_1_phy_rx_data[7:1]}; + uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd1; + if ((uart_1_phy_rx_count == 4'd9)) begin + uart_1_phy_rx_source_valid <= (uart_1_phy_rx_rx == 1'd1); + uart_1_phy_rx_source_payload_data <= uart_1_phy_rx_data; + subfragments_rs232phyrx1_next_state <= 1'd0; + end + end + end + default: begin + uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 1'd0; + uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1; + if (((uart_1_phy_rx_rx == 1'd0) & (uart_1_phy_rx_rx_d == 1'd1))) begin + subfragments_rs232phyrx1_next_state <= 1'd1; + end + end + endcase +end +assign uart_1_wait = (~uart_1_is_ongoing); +assign uart_1_reset = uart_1_done; +assign uart_1_wishbone_adr = uart_1_address; +assign uart_1_wishbone_dat_w = uart_1_data; +assign uart_1_wishbone_sel = 4'd15; +always @(*) begin + uart_1_phy_tx_sink_payload_data <= 8'd0; + case (uart_1_bytes_count) + 1'd0: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:24]; + end + 1'd1: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:16]; + end + 2'd2: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:8]; + end + 2'd3: begin + uart_1_phy_tx_sink_payload_data <= uart_1_data[31:0]; + end + endcase +end +assign uart_1_phy_tx_sink_last = ((uart_1_bytes_count == 2'd3) & (uart_1_words_count == (uart_1_length - 1'd1))); +always @(*) begin + subfragments_next_state <= 3'd0; + uart_1_bytes_count_next_value0 <= 2'd0; + uart_1_bytes_count_next_value_ce0 <= 1'd0; + uart_1_words_count_next_value1 <= 8'd0; + uart_1_words_count_next_value_ce1 <= 1'd0; + uart_1_cmd_next_value2 <= 8'd0; + uart_1_cmd_next_value_ce2 <= 1'd0; + uart_1_length_next_value3 <= 8'd0; + uart_1_length_next_value_ce3 <= 1'd0; + uart_1_phy_tx_sink_valid <= 1'd0; + uart_1_address_next_value4 <= 32'd0; + uart_1_address_next_value_ce4 <= 1'd0; + uart_1_is_ongoing <= 1'd0; + uart_1_incr_next_value5 <= 1'd0; + uart_1_incr_next_value_ce5 <= 1'd0; + uart_1_wishbone_cyc <= 1'd0; + uart_1_data_next_value6 <= 32'd0; + uart_1_wishbone_stb <= 1'd0; + uart_1_data_next_value_ce6 <= 1'd0; + uart_1_wishbone_we <= 1'd0; + uart_1_phy_rx_source_ready <= 1'd0; + subfragments_next_state <= subfragments_state; + case (subfragments_state) + 1'd1: begin + uart_1_phy_rx_source_ready <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_length_next_value3 <= uart_1_phy_rx_source_payload_data; + uart_1_length_next_value_ce3 <= 1'd1; + subfragments_next_state <= 2'd2; + end + end + 2'd2: begin + uart_1_phy_rx_source_ready <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_address_next_value4 <= {uart_1_address, uart_1_phy_rx_source_payload_data}; + uart_1_address_next_value_ce4 <= 1'd1; + uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1); + uart_1_bytes_count_next_value_ce0 <= 1'd1; + if ((uart_1_bytes_count == 2'd3)) begin + if (((uart_1_cmd == 1'd1) | (uart_1_cmd == 2'd3))) begin + uart_1_incr_next_value5 <= (uart_1_cmd == 1'd1); + uart_1_incr_next_value_ce5 <= 1'd1; + subfragments_next_state <= 2'd3; + end else begin + if (((uart_1_cmd == 2'd2) | (uart_1_cmd == 3'd4))) begin + uart_1_incr_next_value5 <= (uart_1_cmd == 2'd2); + uart_1_incr_next_value_ce5 <= 1'd1; + subfragments_next_state <= 3'd5; + end else begin + subfragments_next_state <= 1'd0; + end + end + end + end + end + 2'd3: begin + uart_1_phy_rx_source_ready <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_data_next_value6 <= {uart_1_data, uart_1_phy_rx_source_payload_data}; + uart_1_data_next_value_ce6 <= 1'd1; + uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1); + uart_1_bytes_count_next_value_ce0 <= 1'd1; + if ((uart_1_bytes_count == 2'd3)) begin + subfragments_next_state <= 3'd4; + end + end + end + 3'd4: begin + uart_1_phy_rx_source_ready <= 1'd0; + uart_1_wishbone_stb <= 1'd1; + uart_1_wishbone_we <= 1'd1; + uart_1_wishbone_cyc <= 1'd1; + if (uart_1_wishbone_ack) begin + uart_1_words_count_next_value1 <= (uart_1_words_count + 1'd1); + uart_1_words_count_next_value_ce1 <= 1'd1; + uart_1_address_next_value4 <= (uart_1_address + uart_1_incr); + uart_1_address_next_value_ce4 <= 1'd1; + if ((uart_1_words_count == (uart_1_length - 1'd1))) begin + subfragments_next_state <= 1'd0; + end else begin + subfragments_next_state <= 2'd3; + end + end + end + 3'd5: begin + uart_1_phy_rx_source_ready <= 1'd0; + uart_1_wishbone_stb <= 1'd1; + uart_1_wishbone_we <= 1'd0; + uart_1_wishbone_cyc <= 1'd1; + if (uart_1_wishbone_ack) begin + uart_1_data_next_value6 <= uart_1_wishbone_dat_r; + uart_1_data_next_value_ce6 <= 1'd1; + subfragments_next_state <= 3'd6; + end + end + 3'd6: begin + uart_1_phy_rx_source_ready <= 1'd0; + uart_1_phy_tx_sink_valid <= 1'd1; + if (uart_1_phy_tx_sink_ready) begin + uart_1_bytes_count_next_value0 <= (uart_1_bytes_count + 1'd1); + uart_1_bytes_count_next_value_ce0 <= 1'd1; + if ((uart_1_bytes_count == 2'd3)) begin + uart_1_words_count_next_value1 <= (uart_1_words_count + 1'd1); + uart_1_words_count_next_value_ce1 <= 1'd1; + uart_1_address_next_value4 <= (uart_1_address + uart_1_incr); + uart_1_address_next_value_ce4 <= 1'd1; + if ((uart_1_words_count == (uart_1_length - 1'd1))) begin + subfragments_next_state <= 1'd0; + end else begin + subfragments_next_state <= 3'd5; + end + end + end + end + default: begin + uart_1_is_ongoing <= 1'd1; + uart_1_phy_rx_source_ready <= 1'd1; + uart_1_bytes_count_next_value0 <= 1'd0; + uart_1_bytes_count_next_value_ce0 <= 1'd1; + uart_1_words_count_next_value1 <= 1'd0; + uart_1_words_count_next_value_ce1 <= 1'd1; + if (uart_1_phy_rx_source_valid) begin + uart_1_cmd_next_value2 <= uart_1_phy_rx_source_payload_data; + uart_1_cmd_next_value_ce2 <= 1'd1; + subfragments_next_state <= 1'd1; + end + end + endcase +end +assign uart_1_done = (uart_1_count == 1'd0); +assign digital43 = dshot_0_storage; +always @(*) begin + basesoc_basesoc_wishbone_dat_r <= 32'd0; + basesoc_basesoc_adr <= 14'd0; + basesoc_basesoc_we <= 1'd0; + basesoc_basesoc_dat_w <= 32'd0; + basesoc_basesoc_wishbone_ack <= 1'd0; + basesoc_next_state <= 1'd0; + basesoc_next_state <= basesoc_state; + case (basesoc_state) + 1'd1: begin + basesoc_basesoc_wishbone_ack <= 1'd1; + basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r; + basesoc_next_state <= 1'd0; + end + default: begin + basesoc_basesoc_dat_w <= basesoc_basesoc_wishbone_dat_w; + if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin + basesoc_basesoc_adr <= basesoc_basesoc_wishbone_adr; + basesoc_basesoc_we <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0)); + basesoc_next_state <= 1'd1; + end + end + endcase +end +assign basesoc_shared_adr = array_muxed0; +assign basesoc_shared_dat_w = array_muxed1; +assign basesoc_shared_sel = array_muxed2; +assign basesoc_shared_cyc = array_muxed3; +assign basesoc_shared_stb = array_muxed4; +assign basesoc_shared_we = array_muxed5; +assign basesoc_shared_cti = array_muxed6; +assign basesoc_shared_bte = array_muxed7; +assign basesoc_ibus_dat_r = basesoc_shared_dat_r; +assign basesoc_dbus_dat_r = basesoc_shared_dat_r; +assign basesoc_ibus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd0)); +assign basesoc_dbus_ack = (basesoc_shared_ack & (basesoc_grant == 1'd1)); +assign basesoc_ibus_err = (basesoc_shared_err & (basesoc_grant == 1'd0)); +assign basesoc_dbus_err = (basesoc_shared_err & (basesoc_grant == 1'd1)); +assign basesoc_request = {basesoc_dbus_cyc, basesoc_ibus_cyc}; +always @(*) begin + basesoc_slave_sel <= 3'd0; + basesoc_slave_sel[0] <= (basesoc_shared_adr[29:14] == 1'd0); + basesoc_slave_sel[1] <= (basesoc_shared_adr[29:17] == 2'd2); + basesoc_slave_sel[2] <= (basesoc_shared_adr[29:14] == 16'd65520); +end +assign basesoc_ram_bus_adr = basesoc_shared_adr; +assign basesoc_ram_bus_dat_w = basesoc_shared_dat_w; +assign basesoc_ram_bus_sel = basesoc_shared_sel; +assign basesoc_ram_bus_stb = basesoc_shared_stb; +assign basesoc_ram_bus_we = basesoc_shared_we; +assign basesoc_ram_bus_cti = basesoc_shared_cti; +assign basesoc_ram_bus_bte = basesoc_shared_bte; +assign sram_bus_adr = basesoc_shared_adr; +assign sram_bus_dat_w = basesoc_shared_dat_w; +assign sram_bus_sel = basesoc_shared_sel; +assign sram_bus_stb = basesoc_shared_stb; +assign sram_bus_we = basesoc_shared_we; +assign sram_bus_cti = basesoc_shared_cti; +assign sram_bus_bte = basesoc_shared_bte; +assign basesoc_basesoc_wishbone_adr = basesoc_shared_adr; +assign basesoc_basesoc_wishbone_dat_w = basesoc_shared_dat_w; +assign basesoc_basesoc_wishbone_sel = basesoc_shared_sel; +assign basesoc_basesoc_wishbone_stb = basesoc_shared_stb; +assign basesoc_basesoc_wishbone_we = basesoc_shared_we; +assign basesoc_basesoc_wishbone_cti = basesoc_shared_cti; +assign basesoc_basesoc_wishbone_bte = basesoc_shared_bte; +assign basesoc_ram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[0]); +assign sram_bus_cyc = (basesoc_shared_cyc & basesoc_slave_sel[1]); +assign basesoc_basesoc_wishbone_cyc = (basesoc_shared_cyc & basesoc_slave_sel[2]); +assign basesoc_shared_err = ((basesoc_ram_bus_err | sram_bus_err) | basesoc_basesoc_wishbone_err); +assign basesoc_wait = ((basesoc_shared_stb & basesoc_shared_cyc) & (~basesoc_shared_ack)); +always @(*) begin + basesoc_shared_ack <= 1'd0; + basesoc_shared_dat_r <= 32'd0; + basesoc_error <= 1'd0; + basesoc_shared_ack <= ((basesoc_ram_bus_ack | sram_bus_ack) | basesoc_basesoc_wishbone_ack); + basesoc_shared_dat_r <= ((({32{basesoc_slave_sel_r[0]}} & basesoc_ram_bus_dat_r) | ({32{basesoc_slave_sel_r[1]}} & sram_bus_dat_r)) | ({32{basesoc_slave_sel_r[2]}} & basesoc_basesoc_wishbone_dat_r)); + if (basesoc_done) begin + basesoc_shared_dat_r <= 32'd4294967295; + basesoc_shared_ack <= 1'd1; + basesoc_error <= 1'd1; + end +end +assign basesoc_done = (basesoc_count == 1'd0); +assign basesoc_csr_bankarray_csrbank0_sel = (basesoc_csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd4); +assign basesoc_csr_bankarray_csrbank0_in_r = basesoc_csr_bankarray_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank0_in_re <= 1'd0; + basesoc_csr_bankarray_csrbank0_in_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank0_sel & (basesoc_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank0_in_re <= basesoc_csr_bankarray_interface0_bank_bus_we; + basesoc_csr_bankarray_csrbank0_in_we <= (~basesoc_csr_bankarray_interface0_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank0_in_w = buttons_status[1:0]; +assign buttons_we = basesoc_csr_bankarray_csrbank0_in_we; +assign basesoc_csr_bankarray_csrbank1_sel = (basesoc_csr_bankarray_interface1_bank_bus_adr[13:9] == 4'd8); +assign basesoc_csr_bankarray_csrbank1_reset0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank1_reset0_re <= 1'd0; + basesoc_csr_bankarray_csrbank1_reset0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank1_reset0_re <= basesoc_csr_bankarray_interface1_bank_bus_we; + basesoc_csr_bankarray_csrbank1_reset0_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank1_scratch0_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank1_scratch0_we <= 1'd0; + basesoc_csr_bankarray_csrbank1_scratch0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank1_scratch0_re <= basesoc_csr_bankarray_interface1_bank_bus_we; + basesoc_csr_bankarray_csrbank1_scratch0_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank1_bus_errors_r = basesoc_csr_bankarray_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank1_bus_errors_we <= 1'd0; + basesoc_csr_bankarray_csrbank1_bus_errors_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank1_sel & (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank1_bus_errors_re <= basesoc_csr_bankarray_interface1_bank_bus_we; + basesoc_csr_bankarray_csrbank1_bus_errors_we <= (~basesoc_csr_bankarray_interface1_bank_bus_we); + end +end +always @(*) begin + basesoc_soc_rst <= 1'd0; + if (basesoc_reset_re) begin + basesoc_soc_rst <= basesoc_reset_storage[0]; + end +end +assign basesoc_cpu_rst = basesoc_reset_storage[1]; +assign basesoc_csr_bankarray_csrbank1_reset0_w = basesoc_reset_storage[1:0]; +assign basesoc_csr_bankarray_csrbank1_scratch0_w = basesoc_scratch_storage[31:0]; +assign basesoc_csr_bankarray_csrbank1_bus_errors_w = basesoc_bus_errors_status[31:0]; +assign basesoc_bus_errors_we = basesoc_csr_bankarray_csrbank1_bus_errors_we; +assign basesoc_csr_bankarray_csrbank2_sel = (basesoc_csr_bankarray_interface2_bank_bus_adr[13:9] == 1'd1); +assign basesoc_csr_bankarray_csrbank2_id1_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[24:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank2_id1_we <= 1'd0; + basesoc_csr_bankarray_csrbank2_id1_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank2_sel & (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank2_id1_re <= basesoc_csr_bankarray_interface2_bank_bus_we; + basesoc_csr_bankarray_csrbank2_id1_we <= (~basesoc_csr_bankarray_interface2_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank2_id0_r = basesoc_csr_bankarray_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank2_id0_we <= 1'd0; + basesoc_csr_bankarray_csrbank2_id0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank2_sel & (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank2_id0_re <= basesoc_csr_bankarray_interface2_bank_bus_we; + basesoc_csr_bankarray_csrbank2_id0_we <= (~basesoc_csr_bankarray_interface2_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank2_id1_w = dna_status[56:32]; +assign basesoc_csr_bankarray_csrbank2_id0_w = dna_status[31:0]; +assign dna_we = basesoc_csr_bankarray_csrbank2_id0_we; +assign basesoc_csr_bankarray_csrbank3_sel = (basesoc_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd7); +assign basesoc_csr_bankarray_csrbank3_out0_r = basesoc_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank3_out0_we <= 1'd0; + basesoc_csr_bankarray_csrbank3_out0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank3_sel & (basesoc_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank3_out0_re <= basesoc_csr_bankarray_interface3_bank_bus_we; + basesoc_csr_bankarray_csrbank3_out0_we <= (~basesoc_csr_bankarray_interface3_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank3_out0_w = dshot_0_storage; +assign basesoc_csr_bankarray_csrbank4_sel = (basesoc_csr_bankarray_interface4_bank_bus_adr[13:9] == 3'd5); +assign basesoc_csr_bankarray_csrbank4_w0_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[2:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank4_w0_we <= 1'd0; + basesoc_csr_bankarray_csrbank4_w0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank4_sel & (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank4_w0_re <= basesoc_csr_bankarray_interface4_bank_bus_we; + basesoc_csr_bankarray_csrbank4_w0_we <= (~basesoc_csr_bankarray_interface4_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank4_r_r = basesoc_csr_bankarray_interface4_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank4_r_re <= 1'd0; + basesoc_csr_bankarray_csrbank4_r_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank4_sel & (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank4_r_re <= basesoc_csr_bankarray_interface4_bank_bus_we; + basesoc_csr_bankarray_csrbank4_r_we <= (~basesoc_csr_bankarray_interface4_bank_bus_we); + end +end +assign scl = _w_storage[0]; +assign oe = _w_storage[1]; +assign sda0 = _w_storage[2]; +assign basesoc_csr_bankarray_csrbank4_w0_w = _w_storage[2:0]; +assign _r_status = sda1; +assign basesoc_csr_bankarray_csrbank4_r_w = _r_status; +assign _r_we = basesoc_csr_bankarray_csrbank4_r_we; +assign basesoc_csr_bankarray_sel = (basesoc_csr_bankarray_sram_bus_adr[13:9] == 4'd9); +always @(*) begin + basesoc_csr_bankarray_sram_bus_dat_r <= 32'd0; + if (basesoc_csr_bankarray_sel_r) begin + basesoc_csr_bankarray_sram_bus_dat_r <= basesoc_csr_bankarray_dat_r; + end +end +assign basesoc_csr_bankarray_adr = basesoc_csr_bankarray_sram_bus_adr[4:0]; +assign basesoc_csr_bankarray_csrbank5_sel = (basesoc_csr_bankarray_interface5_bank_bus_adr[13:9] == 2'd3); +assign basesoc_csr_bankarray_csrbank5_out0_r = basesoc_csr_bankarray_interface5_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank5_out0_we <= 1'd0; + basesoc_csr_bankarray_csrbank5_out0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank5_sel & (basesoc_csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank5_out0_re <= basesoc_csr_bankarray_interface5_bank_bus_we; + basesoc_csr_bankarray_csrbank5_out0_we <= (~basesoc_csr_bankarray_interface5_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank5_out0_w = leds_storage[1:0]; +assign basesoc_csr_bankarray_csrbank6_sel = (basesoc_csr_bankarray_interface6_bank_bus_adr[13:9] == 4'd10); +assign basesoc_csr_bankarray_csrbank6_load0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_load0_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_load0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank6_load0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_load0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_reload0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_reload0_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_reload0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank6_reload0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_reload0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_en0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_en0_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_en0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank6_en0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_en0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_update_value0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_update_value0_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_update_value0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csr_bankarray_csrbank6_update_value0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_update_value0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_value_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_value_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_value_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csr_bankarray_csrbank6_value_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_value_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_ev_status_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_ev_status_we <= 1'd0; + basesoc_csr_bankarray_csrbank6_ev_status_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csr_bankarray_csrbank6_ev_status_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_ev_status_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_ev_pending_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_ev_pending_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_ev_pending_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd6))) begin + basesoc_csr_bankarray_csrbank6_ev_pending_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_ev_pending_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_ev_enable0_r = basesoc_csr_bankarray_interface6_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank6_ev_enable0_re <= 1'd0; + basesoc_csr_bankarray_csrbank6_ev_enable0_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank6_sel & (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0] == 3'd7))) begin + basesoc_csr_bankarray_csrbank6_ev_enable0_re <= basesoc_csr_bankarray_interface6_bank_bus_we; + basesoc_csr_bankarray_csrbank6_ev_enable0_we <= (~basesoc_csr_bankarray_interface6_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank6_load0_w = basesoc_timer_load_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_reload0_w = basesoc_timer_reload_storage[31:0]; +assign basesoc_csr_bankarray_csrbank6_en0_w = basesoc_timer_en_storage; +assign basesoc_csr_bankarray_csrbank6_update_value0_w = basesoc_timer_update_value_storage; +assign basesoc_csr_bankarray_csrbank6_value_w = basesoc_timer_value_status[31:0]; +assign basesoc_timer_value_we = basesoc_csr_bankarray_csrbank6_value_we; +assign basesoc_timer_status_status = basesoc_timer_zero0; +assign basesoc_csr_bankarray_csrbank6_ev_status_w = basesoc_timer_status_status; +assign basesoc_timer_status_we = basesoc_csr_bankarray_csrbank6_ev_status_we; +assign basesoc_timer_pending_status = basesoc_timer_zero1; +assign basesoc_csr_bankarray_csrbank6_ev_pending_w = basesoc_timer_pending_status; +assign basesoc_timer_pending_we = basesoc_csr_bankarray_csrbank6_ev_pending_we; +assign basesoc_timer_zero2 = basesoc_timer_enable_storage; +assign basesoc_csr_bankarray_csrbank6_ev_enable0_w = basesoc_timer_enable_storage; +assign basesoc_csr_bankarray_csrbank7_sel = (basesoc_csr_bankarray_interface7_bank_bus_adr[13:9] == 4'd11); +assign basesoc_uart_rxtx_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[7:0]; +always @(*) begin + basesoc_uart_rxtx_we <= 1'd0; + basesoc_uart_rxtx_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_uart_rxtx_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_uart_rxtx_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_txfull_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_txfull_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_txfull_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank7_txfull_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_txfull_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_rxempty_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_rxempty_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_rxempty_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank7_rxempty_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_rxempty_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_ev_status_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_ev_status_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_ev_status_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csr_bankarray_csrbank7_ev_status_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_ev_status_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_ev_pending_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_ev_pending_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_ev_pending_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csr_bankarray_csrbank7_ev_pending_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_ev_pending_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_ev_enable0_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_ev_enable0_we <= 1'd0; + basesoc_csr_bankarray_csrbank7_ev_enable0_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csr_bankarray_csrbank7_ev_enable0_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_ev_enable0_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_txempty_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_txempty_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_txempty_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd6))) begin + basesoc_csr_bankarray_csrbank7_txempty_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_txempty_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_rxfull_r = basesoc_csr_bankarray_interface7_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank7_rxfull_re <= 1'd0; + basesoc_csr_bankarray_csrbank7_rxfull_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank7_sel & (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0] == 3'd7))) begin + basesoc_csr_bankarray_csrbank7_rxfull_re <= basesoc_csr_bankarray_interface7_bank_bus_we; + basesoc_csr_bankarray_csrbank7_rxfull_we <= (~basesoc_csr_bankarray_interface7_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank7_txfull_w = basesoc_uart_txfull_status; +assign basesoc_uart_txfull_we = basesoc_csr_bankarray_csrbank7_txfull_we; +assign basesoc_csr_bankarray_csrbank7_rxempty_w = basesoc_uart_rxempty_status; +assign basesoc_uart_rxempty_we = basesoc_csr_bankarray_csrbank7_rxempty_we; +always @(*) begin + basesoc_uart_status_status <= 2'd0; + basesoc_uart_status_status[0] <= basesoc_uart_tx0; + basesoc_uart_status_status[1] <= basesoc_uart_rx0; +end +assign basesoc_csr_bankarray_csrbank7_ev_status_w = basesoc_uart_status_status[1:0]; +assign basesoc_uart_status_we = basesoc_csr_bankarray_csrbank7_ev_status_we; +always @(*) begin + basesoc_uart_pending_status <= 2'd0; + basesoc_uart_pending_status[0] <= basesoc_uart_tx1; + basesoc_uart_pending_status[1] <= basesoc_uart_rx1; +end +assign basesoc_csr_bankarray_csrbank7_ev_pending_w = basesoc_uart_pending_status[1:0]; +assign basesoc_uart_pending_we = basesoc_csr_bankarray_csrbank7_ev_pending_we; +assign basesoc_uart_tx2 = basesoc_uart_enable_storage[0]; +assign basesoc_uart_rx2 = basesoc_uart_enable_storage[1]; +assign basesoc_csr_bankarray_csrbank7_ev_enable0_w = basesoc_uart_enable_storage[1:0]; +assign basesoc_csr_bankarray_csrbank7_txempty_w = basesoc_uart_txempty_status; +assign basesoc_uart_txempty_we = basesoc_csr_bankarray_csrbank7_txempty_we; +assign basesoc_csr_bankarray_csrbank7_rxfull_w = basesoc_uart_rxfull_status; +assign basesoc_uart_rxfull_we = basesoc_csr_bankarray_csrbank7_rxfull_we; +assign basesoc_csr_bankarray_csrbank8_sel = (basesoc_csr_bankarray_interface8_bank_bus_adr[13:9] == 2'd2); +assign basesoc_csr_bankarray_csrbank8_temperature_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_temperature_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_temperature_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csr_bankarray_csrbank8_temperature_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_temperature_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_vccint_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_vccint_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_vccint_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csr_bankarray_csrbank8_vccint_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_vccint_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_vccaux_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_vccaux_re <= 1'd0; + basesoc_csr_bankarray_csrbank8_vccaux_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csr_bankarray_csrbank8_vccaux_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_vccaux_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_vccbram_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[11:0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_vccbram_re <= 1'd0; + basesoc_csr_bankarray_csrbank8_vccbram_we <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csr_bankarray_csrbank8_vccbram_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_vccbram_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_eoc_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_eoc_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_eoc_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csr_bankarray_csrbank8_eoc_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_eoc_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_eos_r = basesoc_csr_bankarray_interface8_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csr_bankarray_csrbank8_eos_we <= 1'd0; + basesoc_csr_bankarray_csrbank8_eos_re <= 1'd0; + if ((basesoc_csr_bankarray_csrbank8_sel & (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csr_bankarray_csrbank8_eos_re <= basesoc_csr_bankarray_interface8_bank_bus_we; + basesoc_csr_bankarray_csrbank8_eos_we <= (~basesoc_csr_bankarray_interface8_bank_bus_we); + end +end +assign basesoc_csr_bankarray_csrbank8_temperature_w = xadc_temperature_status[11:0]; +assign xadc_temperature_we = basesoc_csr_bankarray_csrbank8_temperature_we; +assign basesoc_csr_bankarray_csrbank8_vccint_w = xadc_vccint_status[11:0]; +assign xadc_vccint_we = basesoc_csr_bankarray_csrbank8_vccint_we; +assign basesoc_csr_bankarray_csrbank8_vccaux_w = xadc_vccaux_status[11:0]; +assign xadc_vccaux_we = basesoc_csr_bankarray_csrbank8_vccaux_we; +assign basesoc_csr_bankarray_csrbank8_vccbram_w = xadc_vccbram_status[11:0]; +assign xadc_vccbram_we = basesoc_csr_bankarray_csrbank8_vccbram_we; +assign basesoc_csr_bankarray_csrbank8_eoc_w = xadc_eoc_status; +assign xadc_eoc_we = basesoc_csr_bankarray_csrbank8_eoc_we; +assign basesoc_csr_bankarray_csrbank8_eos_w = xadc_eos_status; +assign xadc_eos_we = basesoc_csr_bankarray_csrbank8_eos_we; +assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr; +assign basesoc_csr_interconnect_we = basesoc_basesoc_we; +assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w; +assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r; +assign basesoc_csr_bankarray_interface0_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface1_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface2_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface3_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface4_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface5_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface6_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface7_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface8_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_sram_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_csr_bankarray_interface0_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface1_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface2_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface3_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface4_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface5_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface6_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface7_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface8_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_sram_bus_we = basesoc_csr_interconnect_we; +assign basesoc_csr_bankarray_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface2_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface3_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface4_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface5_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface6_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface7_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_interface8_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_bankarray_sram_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_interconnect_dat_r = (((((((((basesoc_csr_bankarray_interface0_bank_bus_dat_r | basesoc_csr_bankarray_interface1_bank_bus_dat_r) | basesoc_csr_bankarray_interface2_bank_bus_dat_r) | basesoc_csr_bankarray_interface3_bank_bus_dat_r) | basesoc_csr_bankarray_interface4_bank_bus_dat_r) | basesoc_csr_bankarray_interface5_bank_bus_dat_r) | basesoc_csr_bankarray_interface6_bank_bus_dat_r) | basesoc_csr_bankarray_interface7_bank_bus_dat_r) | basesoc_csr_bankarray_interface8_bank_bus_dat_r) | basesoc_csr_bankarray_sram_bus_dat_r); +always @(*) begin + array_muxed0 <= 30'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed0 <= basesoc_ibus_adr; + end + default: begin + array_muxed0 <= basesoc_dbus_adr; + end + endcase +end +always @(*) begin + array_muxed1 <= 32'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed1 <= basesoc_ibus_dat_w; + end + default: begin + array_muxed1 <= basesoc_dbus_dat_w; + end + endcase +end +always @(*) begin + array_muxed2 <= 4'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed2 <= basesoc_ibus_sel; + end + default: begin + array_muxed2 <= basesoc_dbus_sel; + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed3 <= basesoc_ibus_cyc; + end + default: begin + array_muxed3 <= basesoc_dbus_cyc; + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed4 <= basesoc_ibus_stb; + end + default: begin + array_muxed4 <= basesoc_dbus_stb; + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed5 <= basesoc_ibus_we; + end + default: begin + array_muxed5 <= basesoc_dbus_we; + end + endcase +end +always @(*) begin + array_muxed6 <= 3'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed6 <= basesoc_ibus_cti; + end + default: begin + array_muxed6 <= basesoc_dbus_cti; + end + endcase +end +always @(*) begin + array_muxed7 <= 2'd0; + case (basesoc_grant) + 1'd0: begin + array_muxed7 <= basesoc_ibus_bte; + end + default: begin + array_muxed7 <= basesoc_dbus_bte; + end + endcase +end +assign basesoc_rx_rx = xilinxmultiregimpl0_regs1; +assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked); +assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked); +assign buttons_status = xilinxmultiregimpl1_regs1; +assign xilinxmultiregimpl1 = {user_btn1, user_btn0}; +assign uart_1_phy_rx_rx = xilinxmultiregimpl2_regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge idelay_clk) begin + if ((crg_reset_counter != 1'd0)) begin + crg_reset_counter <= (crg_reset_counter - 1'd1); + end else begin + crg_ic_reset <= 1'd0; + end + if (idelay_rst) begin + crg_reset_counter <= 4'd15; + crg_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + if ((basesoc_bus_errors != 32'd4294967295)) begin + if (basesoc_bus_error) begin + basesoc_bus_errors <= (basesoc_bus_errors + 1'd1); + end + end + {basesoc_tx_tick, basesoc_tx_phase} <= 23'd4947802; + if (basesoc_tx_enable) begin + {basesoc_tx_tick, basesoc_tx_phase} <= (basesoc_tx_phase + 23'd4947802); + end + subfragments_rs232phytx0_state <= subfragments_rs232phytx0_next_state; + if (basesoc_tx_count_rs232phytx0_next_value_ce0) begin + basesoc_tx_count <= basesoc_tx_count_rs232phytx0_next_value0; + end + if (basesoc_serial_tx_rs232phytx0_next_value_ce1) begin + serial_tx <= basesoc_serial_tx_rs232phytx0_next_value1; + end + if (basesoc_tx_data_rs232phytx0_next_value_ce2) begin + basesoc_tx_data <= basesoc_tx_data_rs232phytx0_next_value2; + end + basesoc_rx_rx_d <= basesoc_rx_rx; + {basesoc_rx_tick, basesoc_rx_phase} <= 32'd2147483648; + if (basesoc_rx_enable) begin + {basesoc_rx_tick, basesoc_rx_phase} <= (basesoc_rx_phase + 23'd4947802); + end + subfragments_rs232phyrx0_state <= subfragments_rs232phyrx0_next_state; + if (basesoc_rx_count_rs232phyrx0_next_value_ce0) begin + basesoc_rx_count <= basesoc_rx_count_rs232phyrx0_next_value0; + end + if (basesoc_rx_data_rs232phyrx0_next_value_ce1) begin + basesoc_rx_data <= basesoc_rx_data_rs232phyrx0_next_value1; + end + if (basesoc_uart_tx_clear) begin + basesoc_uart_tx_pending <= 1'd0; + end + basesoc_uart_tx_trigger_d <= basesoc_uart_tx_trigger; + if ((basesoc_uart_tx_trigger & (~basesoc_uart_tx_trigger_d))) begin + basesoc_uart_tx_pending <= 1'd1; + end + if (basesoc_uart_rx_clear) begin + basesoc_uart_rx_pending <= 1'd0; + end + basesoc_uart_rx_trigger_d <= basesoc_uart_rx_trigger; + if ((basesoc_uart_rx_trigger & (~basesoc_uart_rx_trigger_d))) begin + basesoc_uart_rx_pending <= 1'd1; + end + if (basesoc_uart_tx_fifo_syncfifo_re) begin + basesoc_uart_tx_fifo_readable <= 1'd1; + end else begin + if (basesoc_uart_tx_fifo_re) begin + basesoc_uart_tx_fifo_readable <= 1'd0; + end + end + if (((basesoc_uart_tx_fifo_syncfifo_we & basesoc_uart_tx_fifo_syncfifo_writable) & (~basesoc_uart_tx_fifo_replace))) begin + basesoc_uart_tx_fifo_produce <= (basesoc_uart_tx_fifo_produce + 1'd1); + end + if (basesoc_uart_tx_fifo_do_read) begin + basesoc_uart_tx_fifo_consume <= (basesoc_uart_tx_fifo_consume + 1'd1); + end + if (((basesoc_uart_tx_fifo_syncfifo_we & basesoc_uart_tx_fifo_syncfifo_writable) & (~basesoc_uart_tx_fifo_replace))) begin + if ((~basesoc_uart_tx_fifo_do_read)) begin + basesoc_uart_tx_fifo_level0 <= (basesoc_uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (basesoc_uart_tx_fifo_do_read) begin + basesoc_uart_tx_fifo_level0 <= (basesoc_uart_tx_fifo_level0 - 1'd1); + end + end + if (basesoc_uart_rx_fifo_syncfifo_re) begin + basesoc_uart_rx_fifo_readable <= 1'd1; + end else begin + if (basesoc_uart_rx_fifo_re) begin + basesoc_uart_rx_fifo_readable <= 1'd0; + end + end + if (((basesoc_uart_rx_fifo_syncfifo_we & basesoc_uart_rx_fifo_syncfifo_writable) & (~basesoc_uart_rx_fifo_replace))) begin + basesoc_uart_rx_fifo_produce <= (basesoc_uart_rx_fifo_produce + 1'd1); + end + if (basesoc_uart_rx_fifo_do_read) begin + basesoc_uart_rx_fifo_consume <= (basesoc_uart_rx_fifo_consume + 1'd1); + end + if (((basesoc_uart_rx_fifo_syncfifo_we & basesoc_uart_rx_fifo_syncfifo_writable) & (~basesoc_uart_rx_fifo_replace))) begin + if ((~basesoc_uart_rx_fifo_do_read)) begin + basesoc_uart_rx_fifo_level0 <= (basesoc_uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (basesoc_uart_rx_fifo_do_read) begin + basesoc_uart_rx_fifo_level0 <= (basesoc_uart_rx_fifo_level0 - 1'd1); + end + end + if (basesoc_timer_en_storage) begin + if ((basesoc_timer_value == 1'd0)) begin + basesoc_timer_value <= basesoc_timer_reload_storage; + end else begin + basesoc_timer_value <= (basesoc_timer_value - 1'd1); + end + end else begin + basesoc_timer_value <= basesoc_timer_load_storage; + end + if (basesoc_timer_update_value_re) begin + basesoc_timer_value_status <= basesoc_timer_value; + end + if (basesoc_timer_zero_clear) begin + basesoc_timer_zero_pending <= 1'd0; + end + basesoc_timer_zero_trigger_d <= basesoc_timer_zero_trigger; + if ((basesoc_timer_zero_trigger & (~basesoc_timer_zero_trigger_d))) begin + basesoc_timer_zero_pending <= 1'd1; + end + if (directory0_re) begin + csrstorage0_storage <= directory0_r; + end + csrstorage0_re <= directory0_re; + if (csr_08000_re) begin + csrstorage1_storage <= csr_08000_r; + end + csrstorage1_re <= csr_08000_re; + basesoc_ram_bus_ack <= 1'd0; + if (((basesoc_ram_bus_cyc & basesoc_ram_bus_stb) & (~basesoc_ram_bus_ack))) begin + basesoc_ram_bus_ack <= 1'd1; + end + if ((dna_count < 7'd114)) begin + dna_count <= (dna_count + 1'd1); + if (dna_clk) begin + dna_status <= {dna_status, dna_do}; + end + end + if (xadc_drdy) begin + case (xadc_channel) + 1'd0: begin + xadc_temperature_status <= (xadc_do >>> 3'd4); + end + 1'd1: begin + xadc_vccint_status <= (xadc_do >>> 3'd4); + end + 2'd2: begin + xadc_vccaux_status <= (xadc_do >>> 3'd4); + end + 3'd6: begin + xadc_vccbram_status <= (xadc_do >>> 3'd4); + end + endcase + end + xadc_eoc_status <= ((xadc_eoc_status & (~xadc_eoc_we)) | xadc_eoc); + xadc_eos_status <= ((xadc_eos_status & (~xadc_eos_we)) | xadc_eos); + if (leds_done) begin + leds_chaser <= {leds_chaser, (~leds_chaser[1])}; + end + if (leds_re) begin + leds_mode <= 1'd1; + end + if (leds_wait) begin + if ((~leds_done)) begin + leds_count <= (leds_count - 1'd1); + end + end else begin + leds_count <= 25'd25000000; + end + {uart_1_phy_tx_tick, uart_1_phy_tx_phase} <= 23'd4947802; + if (uart_1_phy_tx_enable) begin + {uart_1_phy_tx_tick, uart_1_phy_tx_phase} <= (uart_1_phy_tx_phase + 23'd4947802); + end + subfragments_rs232phytx1_state <= subfragments_rs232phytx1_next_state; + if (uart_1_phy_tx_count_rs232phytx1_next_value_ce0) begin + uart_1_phy_tx_count <= uart_1_phy_tx_count_rs232phytx1_next_value0; + end + if (tx_obj_rs232phytx1_next_value_ce1) begin + digital10 <= tx_obj_rs232phytx1_next_value1; + end + if (uart_1_phy_tx_data_rs232phytx1_next_value_ce2) begin + uart_1_phy_tx_data <= uart_1_phy_tx_data_rs232phytx1_next_value2; + end + uart_1_phy_rx_rx_d <= uart_1_phy_rx_rx; + {uart_1_phy_rx_tick, uart_1_phy_rx_phase} <= 32'd2147483648; + if (uart_1_phy_rx_enable) begin + {uart_1_phy_rx_tick, uart_1_phy_rx_phase} <= (uart_1_phy_rx_phase + 23'd4947802); + end + subfragments_rs232phyrx1_state <= subfragments_rs232phyrx1_next_state; + if (uart_1_phy_rx_count_rs232phyrx1_next_value_ce0) begin + uart_1_phy_rx_count <= uart_1_phy_rx_count_rs232phyrx1_next_value0; + end + if (uart_1_phy_rx_data_rs232phyrx1_next_value_ce1) begin + uart_1_phy_rx_data <= uart_1_phy_rx_data_rs232phyrx1_next_value1; + end + subfragments_state <= subfragments_next_state; + if (uart_1_bytes_count_next_value_ce0) begin + uart_1_bytes_count <= uart_1_bytes_count_next_value0; + end + if (uart_1_words_count_next_value_ce1) begin + uart_1_words_count <= uart_1_words_count_next_value1; + end + if (uart_1_cmd_next_value_ce2) begin + uart_1_cmd <= uart_1_cmd_next_value2; + end + if (uart_1_length_next_value_ce3) begin + uart_1_length <= uart_1_length_next_value3; + end + if (uart_1_address_next_value_ce4) begin + uart_1_address <= uart_1_address_next_value4; + end + if (uart_1_incr_next_value_ce5) begin + uart_1_incr <= uart_1_incr_next_value5; + end + if (uart_1_data_next_value_ce6) begin + uart_1_data <= uart_1_data_next_value6; + end + if (uart_1_reset) begin + uart_1_incr <= 1'd0; + subfragments_state <= 3'd0; + end + if (uart_1_wait) begin + if ((~uart_1_done)) begin + uart_1_count <= (uart_1_count - 1'd1); + end + end else begin + uart_1_count <= 24'd10000000; + end + basesoc_state <= basesoc_next_state; + case (basesoc_grant) + 1'd0: begin + if ((~basesoc_request[0])) begin + if (basesoc_request[1]) begin + basesoc_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~basesoc_request[1])) begin + if (basesoc_request[0]) begin + basesoc_grant <= 1'd0; + end + end + end + endcase + basesoc_slave_sel_r <= basesoc_slave_sel; + if (basesoc_wait) begin + if ((~basesoc_done)) begin + basesoc_count <= (basesoc_count - 1'd1); + end + end else begin + basesoc_count <= 20'd1000000; + end + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank0_sel) begin + case (basesoc_csr_bankarray_interface0_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface0_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank0_in_w; + end + endcase + end + buttons_re <= basesoc_csr_bankarray_csrbank0_in_re; + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank1_sel) begin + case (basesoc_csr_bankarray_interface1_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_reset0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_scratch0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface1_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank1_bus_errors_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank1_reset0_re) begin + basesoc_reset_storage[1:0] <= basesoc_csr_bankarray_csrbank1_reset0_r; + end + basesoc_reset_re <= basesoc_csr_bankarray_csrbank1_reset0_re; + if (basesoc_csr_bankarray_csrbank1_scratch0_re) begin + basesoc_scratch_storage[31:0] <= basesoc_csr_bankarray_csrbank1_scratch0_r; + end + basesoc_scratch_re <= basesoc_csr_bankarray_csrbank1_scratch0_re; + basesoc_bus_errors_re <= basesoc_csr_bankarray_csrbank1_bus_errors_re; + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank2_sel) begin + case (basesoc_csr_bankarray_interface2_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_id1_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface2_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank2_id0_w; + end + endcase + end + dna_re <= basesoc_csr_bankarray_csrbank2_id0_re; + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank3_sel) begin + case (basesoc_csr_bankarray_interface3_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface3_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank3_out0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank3_out0_re) begin + dshot_0_storage <= basesoc_csr_bankarray_csrbank3_out0_r; + end + dshot_0_re <= basesoc_csr_bankarray_csrbank3_out0_re; + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank4_sel) begin + case (basesoc_csr_bankarray_interface4_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_w0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface4_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank4_r_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank4_w0_re) begin + _w_storage[2:0] <= basesoc_csr_bankarray_csrbank4_w0_r; + end + _w_re <= basesoc_csr_bankarray_csrbank4_w0_re; + _r_re <= basesoc_csr_bankarray_csrbank4_r_re; + basesoc_csr_bankarray_sel_r <= basesoc_csr_bankarray_sel; + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank5_sel) begin + case (basesoc_csr_bankarray_interface5_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface5_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank5_out0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank5_out0_re) begin + leds_storage[1:0] <= basesoc_csr_bankarray_csrbank5_out0_r; + end + leds_re <= basesoc_csr_bankarray_csrbank5_out0_re; + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank6_sel) begin + case (basesoc_csr_bankarray_interface6_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_load0_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_reload0_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_en0_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_update_value0_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_value_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_status_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_pending_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface6_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank6_ev_enable0_w; + end + endcase + end + if (basesoc_csr_bankarray_csrbank6_load0_re) begin + basesoc_timer_load_storage[31:0] <= basesoc_csr_bankarray_csrbank6_load0_r; + end + basesoc_timer_load_re <= basesoc_csr_bankarray_csrbank6_load0_re; + if (basesoc_csr_bankarray_csrbank6_reload0_re) begin + basesoc_timer_reload_storage[31:0] <= basesoc_csr_bankarray_csrbank6_reload0_r; + end + basesoc_timer_reload_re <= basesoc_csr_bankarray_csrbank6_reload0_re; + if (basesoc_csr_bankarray_csrbank6_en0_re) begin + basesoc_timer_en_storage <= basesoc_csr_bankarray_csrbank6_en0_r; + end + basesoc_timer_en_re <= basesoc_csr_bankarray_csrbank6_en0_re; + if (basesoc_csr_bankarray_csrbank6_update_value0_re) begin + basesoc_timer_update_value_storage <= basesoc_csr_bankarray_csrbank6_update_value0_r; + end + basesoc_timer_update_value_re <= basesoc_csr_bankarray_csrbank6_update_value0_re; + basesoc_timer_value_re <= basesoc_csr_bankarray_csrbank6_value_re; + basesoc_timer_status_re <= basesoc_csr_bankarray_csrbank6_ev_status_re; + if (basesoc_csr_bankarray_csrbank6_ev_pending_re) begin + basesoc_timer_pending_r <= basesoc_csr_bankarray_csrbank6_ev_pending_r; + end + basesoc_timer_pending_re <= basesoc_csr_bankarray_csrbank6_ev_pending_re; + if (basesoc_csr_bankarray_csrbank6_ev_enable0_re) begin + basesoc_timer_enable_storage <= basesoc_csr_bankarray_csrbank6_ev_enable0_r; + end + basesoc_timer_enable_re <= basesoc_csr_bankarray_csrbank6_ev_enable0_re; + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank7_sel) begin + case (basesoc_csr_bankarray_interface7_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_uart_rxtx_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_txfull_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_rxempty_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_status_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_pending_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_ev_enable0_w; + end + 3'd6: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_txempty_w; + end + 3'd7: begin + basesoc_csr_bankarray_interface7_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank7_rxfull_w; + end + endcase + end + basesoc_uart_txfull_re <= basesoc_csr_bankarray_csrbank7_txfull_re; + basesoc_uart_rxempty_re <= basesoc_csr_bankarray_csrbank7_rxempty_re; + basesoc_uart_status_re <= basesoc_csr_bankarray_csrbank7_ev_status_re; + if (basesoc_csr_bankarray_csrbank7_ev_pending_re) begin + basesoc_uart_pending_r[1:0] <= basesoc_csr_bankarray_csrbank7_ev_pending_r; + end + basesoc_uart_pending_re <= basesoc_csr_bankarray_csrbank7_ev_pending_re; + if (basesoc_csr_bankarray_csrbank7_ev_enable0_re) begin + basesoc_uart_enable_storage[1:0] <= basesoc_csr_bankarray_csrbank7_ev_enable0_r; + end + basesoc_uart_enable_re <= basesoc_csr_bankarray_csrbank7_ev_enable0_re; + basesoc_uart_txempty_re <= basesoc_csr_bankarray_csrbank7_txempty_re; + basesoc_uart_rxfull_re <= basesoc_csr_bankarray_csrbank7_rxfull_re; + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= 1'd0; + if (basesoc_csr_bankarray_csrbank8_sel) begin + case (basesoc_csr_bankarray_interface8_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_temperature_w; + end + 1'd1: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccint_w; + end + 2'd2: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccaux_w; + end + 2'd3: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_vccbram_w; + end + 3'd4: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_eoc_w; + end + 3'd5: begin + basesoc_csr_bankarray_interface8_bank_bus_dat_r <= basesoc_csr_bankarray_csrbank8_eos_w; + end + endcase + end + xadc_temperature_re <= basesoc_csr_bankarray_csrbank8_temperature_re; + xadc_vccint_re <= basesoc_csr_bankarray_csrbank8_vccint_re; + xadc_vccaux_re <= basesoc_csr_bankarray_csrbank8_vccaux_re; + xadc_vccbram_re <= basesoc_csr_bankarray_csrbank8_vccbram_re; + xadc_eoc_re <= basesoc_csr_bankarray_csrbank8_eoc_re; + xadc_eos_re <= basesoc_csr_bankarray_csrbank8_eos_re; + if (sys_rst) begin + basesoc_reset_storage <= 2'd0; + basesoc_reset_re <= 1'd0; + basesoc_scratch_storage <= 32'd305419896; + basesoc_scratch_re <= 1'd0; + basesoc_bus_errors_re <= 1'd0; + basesoc_bus_errors <= 32'd0; + serial_tx <= 1'd1; + basesoc_tx_tick <= 1'd0; + basesoc_rx_tick <= 1'd0; + basesoc_rx_rx_d <= 1'd0; + basesoc_uart_txfull_re <= 1'd0; + basesoc_uart_rxempty_re <= 1'd0; + basesoc_uart_tx_pending <= 1'd0; + basesoc_uart_tx_trigger_d <= 1'd0; + basesoc_uart_rx_pending <= 1'd0; + basesoc_uart_rx_trigger_d <= 1'd0; + basesoc_uart_status_re <= 1'd0; + basesoc_uart_pending_re <= 1'd0; + basesoc_uart_pending_r <= 2'd0; + basesoc_uart_enable_storage <= 2'd0; + basesoc_uart_enable_re <= 1'd0; + basesoc_uart_txempty_re <= 1'd0; + basesoc_uart_rxfull_re <= 1'd0; + basesoc_uart_tx_fifo_readable <= 1'd0; + basesoc_uart_tx_fifo_level0 <= 5'd0; + basesoc_uart_tx_fifo_produce <= 4'd0; + basesoc_uart_tx_fifo_consume <= 4'd0; + basesoc_uart_rx_fifo_readable <= 1'd0; + basesoc_uart_rx_fifo_level0 <= 5'd0; + basesoc_uart_rx_fifo_produce <= 4'd0; + basesoc_uart_rx_fifo_consume <= 4'd0; + basesoc_timer_load_storage <= 32'd0; + basesoc_timer_load_re <= 1'd0; + basesoc_timer_reload_storage <= 32'd0; + basesoc_timer_reload_re <= 1'd0; + basesoc_timer_en_storage <= 1'd0; + basesoc_timer_en_re <= 1'd0; + basesoc_timer_update_value_storage <= 1'd0; + basesoc_timer_update_value_re <= 1'd0; + basesoc_timer_value_status <= 32'd0; + basesoc_timer_value_re <= 1'd0; + basesoc_timer_zero_pending <= 1'd0; + basesoc_timer_zero_trigger_d <= 1'd0; + basesoc_timer_status_re <= 1'd0; + basesoc_timer_pending_re <= 1'd0; + basesoc_timer_pending_r <= 1'd0; + basesoc_timer_enable_storage <= 1'd0; + basesoc_timer_enable_re <= 1'd0; + basesoc_timer_value <= 32'd0; + csrstorage0_storage <= 1'd140989193; + csrstorage0_re <= 1'd0; + csrstorage1_storage <= 1'd0; + csrstorage1_re <= 1'd0; + basesoc_ram_bus_ack <= 1'd0; + dna_status <= 57'd0; + dna_re <= 1'd0; + dna_count <= 7'd0; + xadc_temperature_status <= 12'd0; + xadc_temperature_re <= 1'd0; + xadc_vccint_status <= 12'd0; + xadc_vccint_re <= 1'd0; + xadc_vccaux_status <= 12'd0; + xadc_vccaux_re <= 1'd0; + xadc_vccbram_status <= 12'd0; + xadc_vccbram_re <= 1'd0; + xadc_eoc_status <= 1'd0; + xadc_eoc_re <= 1'd0; + xadc_eos_status <= 1'd0; + xadc_eos_re <= 1'd0; + leds_storage <= 2'd0; + leds_re <= 1'd0; + leds_chaser <= 2'd0; + leds_mode <= 1'd0; + leds_count <= 25'd25000000; + buttons_re <= 1'd0; + _w_storage <= 3'd0; + _w_re <= 1'd0; + _r_re <= 1'd0; + digital10 <= 1'd1; + uart_1_phy_tx_tick <= 1'd0; + uart_1_phy_rx_tick <= 1'd0; + uart_1_phy_rx_rx_d <= 1'd0; + uart_1_incr <= 1'd0; + uart_1_count <= 24'd10000000; + dshot_0_storage <= 1'd0; + dshot_0_re <= 1'd0; + subfragments_rs232phytx0_state <= 1'd0; + subfragments_rs232phyrx0_state <= 1'd0; + subfragments_rs232phytx1_state <= 1'd0; + subfragments_rs232phyrx1_state <= 1'd0; + subfragments_state <= 3'd0; + basesoc_grant <= 1'd0; + basesoc_slave_sel_r <= 3'd0; + basesoc_count <= 20'd1000000; + basesoc_csr_bankarray_sel_r <= 1'd0; + basesoc_state <= 1'd0; + end + xilinxmultiregimpl0_regs0 <= serial_rx; + xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; + xilinxmultiregimpl1_regs0 <= {user_btn1, user_btn0}; + xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; + xilinxmultiregimpl2_regs0 <= digital11; + xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory mem: 24-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [7:0] mem[0:23]; +initial begin + $readmemh("mem.init", mem); +end +reg [4:0] mem_adr0; +always @(posedge sys_clk) begin + mem_adr0 <= basesoc_csr_bankarray_adr; +end +assign basesoc_csr_bankarray_dat_r = mem[mem_adr0]; + + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage[0:15]; +reg [9:0] storage_dat0; +reg [9:0] storage_dat1; +always @(posedge sys_clk) begin + if (basesoc_uart_tx_fifo_wrport_we) + storage[basesoc_uart_tx_fifo_wrport_adr] <= basesoc_uart_tx_fifo_wrport_dat_w; + storage_dat0 <= storage[basesoc_uart_tx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (basesoc_uart_tx_fifo_rdport_re) + storage_dat1 <= storage[basesoc_uart_tx_fifo_rdport_adr]; +end +assign basesoc_uart_tx_fifo_wrport_dat_r = storage_dat0; +assign basesoc_uart_tx_fifo_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:15]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (basesoc_uart_rx_fifo_wrport_we) + storage_1[basesoc_uart_rx_fifo_wrport_adr] <= basesoc_uart_rx_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[basesoc_uart_rx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (basesoc_uart_rx_fifo_rdport_re) + storage_1_dat1 <= storage_1[basesoc_uart_rx_fifo_rdport_adr]; +end +assign basesoc_uart_rx_fifo_wrport_dat_r = storage_1_dat0; +assign basesoc_uart_rx_fifo_rdport_dat_r = storage_1_dat1; + + +BUFG BUFG( + .I(crg_clkout0), + .O(crg_clkout_buf0) +); + +BUFG BUFG_1( + .I(crg_clkout1), + .O(crg_clkout_buf1) +); + +BUFG BUFG_2( + .I(crg_clkout2), + .O(crg_clkout_buf2) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(idelay_clk), + .RST(crg_ic_reset) +); + +//------------------------------------------------------------------------------ +// Memory mem_1: 16384-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:16383]; +initial begin + $readmemh("mem_1.init", mem_1); +end +reg [31:0] mem_1_dat0; +always @(posedge sys_clk) begin + mem_1_dat0 <= mem_1[basesoc_adr]; +end +assign basesoc_dat_r = mem_1_dat0; + + +issiram issiram( + .clk(sys_clk), + .rst(sys_rst), + .wbs_adr_i(sram_bus_adr), + .wbs_cyc_i(sram_bus_cyc), + .wbs_dat_i(sram_bus_dat_w), + .wbs_sel_i(sram_bus_sel), + .wbs_stb_i(sram_bus_stb), + .wbs_we_i(sram_bus_we), + .mem_dat(issiram_data), + .mem_adr(issiram_addr), + .mem_ce_n(issiram_cen), + .mem_oe_n(issiram_oen), + .mem_we_n(issiram_wen), + .wbs_ack_o(sram_bus_ack), + .wbs_dat_o(sram_bus_dat_r) +); + +DNA_PORT DNA_PORT( + .CLK(dna_clk), + .DIN(dna_status[56]), + .READ((dna_count < 2'd2)), + .SHIFT(1'd1), + .DOUT(dna_do) +); + +XADC #( + .INIT_40(16'd36864), + .INIT_41(14'd12016), + .INIT_42(11'd1024), + .INIT_48(15'd18177), + .INIT_49(4'd15), + .INIT_4A(15'd18176), + .INIT_4B(1'd0), + .INIT_4C(1'd0), + .INIT_4D(1'd0), + .INIT_4E(1'd0), + .INIT_4F(1'd0), + .INIT_50(16'd46573), + .INIT_51(15'd22937), + .INIT_52(16'd41287), + .INIT_53(16'd56797), + .INIT_54(16'd43322), + .INIT_55(15'd20753), + .INIT_56(16'd37355), + .INIT_57(16'd44622), + .INIT_58(15'd22937), + .INIT_5C(15'd20753) +) XADC ( + .CONVST(1'd0), + .CONVSTCLK(1'd0), + .DADDR(xadc_dadr), + .DCLK(sys_clk), + .DEN(xadc_den), + .DI(xadc_di), + .DWE(xadc_dwe), + .RESET(sys_rst), + .VAUXN(1'd0), + .VAUXP(1'd0), + .VN(1'd0), + .VP(1'd0), + .ALM(xadc_alarm), + .BUSY(xadc_busy), + .CHANNEL(xadc_channel), + .DO(xadc_do), + .DRDY(xadc_drdy), + .EOC(xadc_eoc), + .EOS(xadc_eos), + .OT(xadc_ot) +); + +assign pmod0 = (~scl) ? 1'd0 : 1'bz; + +assign pmod1 = (oe & (~sda0)) ? 1'd0 : 1'bz; +assign sda1 = pmod1; + +A2P_WB A2P_WB( + .clk(sys_clk), + .dBusWB_ACK(basesoc_dbus_ack), + .dBusWB_DAT_MISO(basesoc_dbus_dat_r), + .dBusWB_ERR(basesoc_dbus_err), + .externalInterrupt(basesoc_interrupt[0]), + .externalInterruptS(basesoc_interruptS), + .externalResetVector(basesoc_a2p), + .iBusWB_ACK(basesoc_ibus_ack), + .iBusWB_DAT_MISO(basesoc_ibus_dat_r), + .iBusWB_ERR(basesoc_ibus_err), + .reset((sys_rst | basesoc_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWB_ADR(basesoc_dbus_adr), + .dBusWB_BTE(basesoc_dbus_bte), + .dBusWB_CTI(basesoc_dbus_cti), + .dBusWB_CYC(basesoc_dbus_cyc), + .dBusWB_DAT_MOSI(basesoc_dbus_dat_w), + .dBusWB_SEL(basesoc_dbus_sel), + .dBusWB_STB(basesoc_dbus_stb), + .dBusWB_WE(basesoc_dbus_we), + .iBusWB_ADR(basesoc_ibus_adr), + .iBusWB_BTE(basesoc_ibus_bte), + .iBusWB_CTI(basesoc_ibus_cti), + .iBusWB_CYC(basesoc_ibus_cyc), + .iBusWB_DAT_MOSI(basesoc_ibus_dat_w), + .iBusWB_SEL(basesoc_ibus_sel), + .iBusWB_STB(basesoc_ibus_stb), + .iBusWB_WE(basesoc_ibus_we) +); + +FD FD( + .C(crg_clkin), + .D(crg_reset), + .Q(subfragments_reset0) +); + +FD FD_1( + .C(crg_clkin), + .D(subfragments_reset0), + .Q(subfragments_reset1) +); + +FD FD_2( + .C(crg_clkin), + .D(subfragments_reset1), + .Q(subfragments_reset2) +); + +FD FD_3( + .C(crg_clkin), + .D(subfragments_reset2), + .Q(subfragments_reset3) +); + +FD FD_4( + .C(crg_clkin), + .D(subfragments_reset3), + .Q(subfragments_reset4) +); + +FD FD_5( + .C(crg_clkin), + .D(subfragments_reset4), + .Q(subfragments_reset5) +); + +FD FD_6( + .C(crg_clkin), + .D(subfragments_reset5), + .Q(subfragments_reset6) +); + +FD FD_7( + .C(crg_clkin), + .D(subfragments_reset6), + .Q(subfragments_reset7) +); + +MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(6'd50), + .CLKIN1_PERIOD(83.33333333333333), + .CLKOUT0_DIVIDE_F(3'd6), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(2'd3), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(2'd3), + .CLKOUT2_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01) +) MMCME2_ADV ( + .CLKFBIN(subfragments_mmcm_fb), + .CLKIN1(crg_clkin), + .PWRDWN(crg_power_down), + .RST(subfragments_reset7), + .CLKFBOUT(subfragments_mmcm_fb), + .CLKOUT0(crg_clkout0), + .CLKOUT1(crg_clkout1), + .CLKOUT2(crg_clkout2), + .LOCKED(crg_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys2x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys2x_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(idelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(idelay_clk), + .CE(1'd1), + .D(xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(idelay_rst) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2021-11-11 08:35:18. +//------------------------------------------------------------------------------ diff --git a/build/litex/litex-1099/no_master/csr.csv b/build/litex/litex-1099/no_master/csr.csv new file mode 100644 index 0000000..d924305 --- /dev/null +++ b/build/litex/litex-1099/no_master/csr.csv @@ -0,0 +1,63 @@ +#-------------------------------------------------------------------------------- +# Auto-generated by Migen (7507a2b) & LiteX (feca1c47) on 2021-11-11 08:35:18 +#-------------------------------------------------------------------------------- +csr_base,dna,0xfff00800,, +csr_base,xadc,0xfff01000,, +csr_base,leds,0xfff01800,, +csr_base,buttons,0xfff02000,, +csr_base,i2c,0xfff02800,, +csr_base,dshot_0,0xfff03800,, +csr_base,ctrl,0xfff04000,, +csr_base,identifier_mem,0xfff04800,, +csr_base,timer0,0xfff05000,, +csr_base,uart,0xfff05800,, +csr_register,dna_id,0xfff00800,2,ro +csr_register,xadc_temperature,0xfff01000,1,ro +csr_register,xadc_vccint,0xfff01004,1,ro +csr_register,xadc_vccaux,0xfff01008,1,ro +csr_register,xadc_vccbram,0xfff0100c,1,ro +csr_register,xadc_eoc,0xfff01010,1,ro +csr_register,xadc_eos,0xfff01014,1,ro +csr_register,leds_out,0xfff01800,1,rw +csr_register,buttons_in,0xfff02000,1,ro +csr_register,i2c_w,0xfff02800,1,rw +csr_register,i2c_r,0xfff02804,1,ro +csr_register,dshot_0_out,0xfff03800,1,rw +csr_register,ctrl_reset,0xfff04000,1,rw +csr_register,ctrl_scratch,0xfff04004,1,rw +csr_register,ctrl_bus_errors,0xfff04008,1,ro +csr_register,timer0_load,0xfff05000,1,rw +csr_register,timer0_reload,0xfff05004,1,rw +csr_register,timer0_en,0xfff05008,1,rw +csr_register,timer0_update_value,0xfff0500c,1,rw +csr_register,timer0_value,0xfff05010,1,ro +csr_register,timer0_ev_status,0xfff05014,1,ro +csr_register,timer0_ev_pending,0xfff05018,1,rw +csr_register,timer0_ev_enable,0xfff0501c,1,rw +csr_register,uart_rxtx,0xfff05800,1,rw +csr_register,uart_txfull,0xfff05804,1,ro +csr_register,uart_rxempty,0xfff05808,1,ro +csr_register,uart_ev_status,0xfff0580c,1,ro +csr_register,uart_ev_pending,0xfff05810,1,rw +csr_register,uart_ev_enable,0xfff05814,1,rw +csr_register,uart_txempty,0xfff05818,1,ro +csr_register,uart_rxfull,0xfff0581c,1,ro +constant,config_clock_frequency,100000000,, +constant,config_cpu_has_interrupt,None,, +constant,config_cpu_reset_addr,0,, +constant,config_cpu_type_a2p,None,, +constant,config_cpu_variant_standard,None,, +constant,config_cpu_human_name,a2p_wb,, +constant,config_cpu_nop,nop,, +constant,config_with_build_time,None,, +constant,uart_polling,None,, +constant,config_csr_data_width,32,, +constant,config_csr_alignment,32,, +constant,config_bus_standard,wishbone,, +constant,config_bus_data_width,32,, +constant,config_bus_address_width,32,, +constant,timer0_interrupt,1,, +constant,uart_interrupt,0,, +memory_region,rom,0x00000000,65536,cached +memory_region,sram,0x00100000,524288,cached +memory_region,csr,0xfff00000,65536,io diff --git a/build/litex/litex-1099/no_master/make-uarts.txt b/build/litex/litex-1099/no_master/make-uarts.txt new file mode 100644 index 0000000..575ad35 --- /dev/null +++ b/build/litex/litex-1099/no_master/make-uarts.txt @@ -0,0 +1,1763 @@ +Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :) +Namespace(build=True, bus_address_width=32, bus_data_width=32, bus_standard='wishbone', bus_timeout=1000000.0, cpu_cfu=None, cpu_reset_address=None, cpu_type=None, cpu_variant=None, csr_address_width=14, csr_csv='csr.csv', csr_data_width=None, csr_json=None, csr_ordering='big', csr_paging=2048, csr_svd=None, doc=False, gateware_dir=None, generated_dir=None, ident=None, ident_version=None, include_dir=None, integrated_main_ram_size=None, integrated_rom_init=None, integrated_rom_size=131072, integrated_sram_size=8192, l2_size=8192, load=False, memory_x=None, no_compile_gateware=False, no_compile_software=True, no_ctrl=False, no_timer=False, no_uart=False, output_dir=None, software_dir=None, sys_clk_freq=100000000.0, timer_uptime=False, uart_baudrate=None, uart_fifo_depth=16, uart_name='serial', with_analyzer=False) +directory0 +csr_08000 + +****** Vivado v2020.2 (64-bit) + **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 + **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 + ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + +source cmod7.tcl +# create_project -force -name cmod7 -part xc7a35t-CPG236-1 +# set_msg_config -id {Common 17-55} -new_severity {Warning} +# read_verilog {/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v} +# read_verilog {/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v} +# read_verilog {/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v} +# read_xdc cmod7.xdc +# set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc] +# synth_design -directive default -top cmod7 -part xc7a35t-CPG236-1 +Command: synth_design -directive default -top cmod7 -part xc7a35t-CPG236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 580129 +WARNING: [Synth 8-2292] literal value truncated to fit in 1 bits [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:278] +WARNING: [Synth 8-2292] literal value truncated to fit in 1 bits [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2287] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 329 ; free virtual = 10263 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'cmod7' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:20] +INFO: [Synth 8-3876] $readmem data file 'mem.init' is read successfully [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2354] +INFO: [Synth 8-3876] $readmem data file 'mem_1.init' is read successfully [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2431] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1912] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2028] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2037] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2060] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2072] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2084] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2101] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2113] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2168] +INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2210] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2420] +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060] + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (2#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060] +WARNING: [Synth 8-7071] port 'RDY' of module 'IDELAYCTRL' is unconnected for instance 'IDELAYCTRL' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2420] +WARNING: [Synth 8-7023] instance 'IDELAYCTRL' of module 'IDELAYCTRL' has 3 connections declared, but only 2 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2420] +INFO: [Synth 8-6157] synthesizing module 'issiram' [/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v:41] + Parameter WB_BITWIDTH bound to: 32 - type: integer + Parameter RAM_BITWIDTH bound to: 8 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'issiram' (3#1) [/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v:41] +INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:11984] + Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (4#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:11984] +INFO: [Synth 8-6157] synthesizing module 'XADC' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:82182] + Parameter INIT_40 bound to: 16'b1001000000000000 + Parameter INIT_41 bound to: 16'b0010111011110000 + Parameter INIT_42 bound to: 16'b0000010000000000 + Parameter INIT_43 bound to: 16'b0000000000000000 + Parameter INIT_44 bound to: 16'b0000000000000000 + Parameter INIT_45 bound to: 16'b0000000000000000 + Parameter INIT_46 bound to: 16'b0000000000000000 + Parameter INIT_47 bound to: 16'b0000000000000000 + Parameter INIT_48 bound to: 16'b0100011100000001 + Parameter INIT_49 bound to: 16'b0000000000001111 + Parameter INIT_4A bound to: 16'b0100011100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101100110011001 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1101110111011101 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101000100010001 + Parameter INIT_56 bound to: 16'b1001000111101011 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_59 bound to: 16'b0000000000000000 + Parameter INIT_5A bound to: 16'b0000000000000000 + Parameter INIT_5B bound to: 16'b0000000000000000 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter INIT_5D bound to: 16'b0000000000000000 + Parameter INIT_5E bound to: 16'b0000000000000000 + Parameter INIT_5F bound to: 16'b0000000000000000 + Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 + Parameter IS_DCLK_INVERTED bound to: 1'b0 + Parameter SIM_DEVICE bound to: 7SERIES - type: string + Parameter SIM_MONITOR_FILE bound to: design.txt - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (5#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:82182] +WARNING: [Synth 8-689] width (7) of port connection 'CHANNEL' does not match port width (5) of module 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2503] +WARNING: [Synth 8-7071] port 'JTAGBUSY' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2488] +WARNING: [Synth 8-7071] port 'JTAGLOCKED' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2488] +WARNING: [Synth 8-7071] port 'JTAGMODIFIED' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2488] +WARNING: [Synth 8-7071] port 'MUXADDR' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2488] +WARNING: [Synth 8-7023] instance 'XADC' of module 'XADC' has 24 connections declared, but only 20 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2488] +INFO: [Synth 8-6157] synthesizing module 'A2P_WB' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:1183] +INFO: [Synth 8-6157] synthesizing module 'InstructionCache' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:164] +INFO: [Synth 8-6155] done synthesizing module 'InstructionCache' (6#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:164] +INFO: [Synth 8-6157] synthesizing module 'DataCache' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:465] +INFO: [Synth 8-6155] done synthesizing module 'DataCache' (7#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:465] +INFO: [Synth 8-6155] done synthesizing module 'A2P_WB' (8#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:1183] +INFO: [Synth 8-6157] synthesizing module 'FD' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13483] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-6155] done synthesizing module 'FD' (9#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13483] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 50.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 83.333333 - type: double + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 3 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (10#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DO' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DRDY' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'PSDONE' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKIN2' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'CLKINSEL' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DADDR' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DCLK' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DEN' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DI' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'DWE' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'PSCLK' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'PSEN' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7071] port 'PSINCDEC' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +WARNING: [Synth 8-7023] instance 'MMCME2_ADV' of module 'MMCME2_ADV' has 33 connections declared, but only 9 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2608] +INFO: [Synth 8-6157] synthesizing module 'FDPE' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13664] + Parameter INIT bound to: 1'b1 + Parameter IS_C_INVERTED bound to: 1'b0 + Parameter IS_D_INVERTED bound to: 1'b0 + Parameter IS_PRE_INVERTED bound to: 1'b0 +INFO: [Synth 8-6155] done synthesizing module 'FDPE' (11#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'cmod7' (12#1) [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:20] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1042 ; free virtual = 10973 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1059 ; free virtual = 10989 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1059 ; free virtual = 10989 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1043 ; free virtual = 10974 +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +WARNING: [Vivado 12-507] No nets matched 'clk12'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:211] +CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_nets clk12]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:211] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets sys_clk]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Verify the create_clock command was called to create the clock object before it is referenced. +INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets crg_clkin]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Verify the create_clock command was called to create the clock object before it is referenced. +INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets sys_clk]]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets crg_clkin]]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +CRITICAL WARNING: [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Finished Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/cmod7_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/cmod7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2411.500 ; gain = 0.000 ; free physical = 944 ; free virtual = 10875 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 8 instances were transformed. + FD => FDRE: 8 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2411.500 ; gain = 0.000 ; free physical = 944 ; free virtual = 10875 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2411.500 ; gain = 112.715 ; free physical = 1043 ; free virtual = 10973 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2411.500 ; gain = 112.715 ; free physical = 1043 ; free virtual = 10973 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2411.500 ; gain = 112.715 ; free physical = 1043 ; free virtual = 10973 +--------------------------------------------------------------------------------- +INFO: [Synth 8-3971] The signal "A2P_WB:/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template. +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2411.500 ; gain = 112.715 ; free physical = 1023 ; free virtual = 10956 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 64 Bit Adders := 1 + 3 Input 52 Bit Adders := 1 + 3 Input 33 Bit Adders := 2 + 2 Input 33 Bit Adders := 5 + 2 Input 32 Bit Adders := 10 + 2 Input 10 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 2 + 31 Input 6 Bit Adders := 1 + 2 Input 5 Bit Adders := 2 + 7 Input 4 Bit Adders := 4 + 2 Input 4 Bit Adders := 11 + 2 Input 3 Bit Adders := 5 + 2 Input 2 Bit Adders := 6 + 4 Input 2 Bit Adders := 2 + 16 Input 1 Bit Adders := 2 + 8 Input 1 Bit Adders := 1 + 12 Input 1 Bit Adders := 2 + 13 Input 1 Bit Adders := 1 + 15 Input 1 Bit Adders := 1 + 19 Input 1 Bit Adders := 1 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 11 Input 1 Bit Adders := 1 + 2 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 2 + 2 Input 1 Bit XORs := 6 + 4 Input 1 Bit XORs := 1 ++---Registers : + 65 Bit Registers := 1 + 57 Bit Registers := 1 + 54 Bit Registers := 1 + 52 Bit Registers := 1 + 34 Bit Registers := 1 + 33 Bit Registers := 1 + 32 Bit Registers := 75 + 22 Bit Registers := 2 + 20 Bit Registers := 2 + 19 Bit Registers := 1 + 12 Bit Registers := 4 + 11 Bit Registers := 2 + 10 Bit Registers := 1 + 8 Bit Registers := 19 + 7 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 21 + 4 Bit Registers := 18 + 3 Bit Registers := 14 + 2 Bit Registers := 27 + 1 Bit Registers := 213 ++---RAMs : + 54K Bit (1024 X 54 bit) RAMs := 1 + 32K Bit (1024 X 32 bit) RAMs := 1 + 8K Bit (1024 X 8 bit) RAMs := 4 + 2K Bit (128 X 22 bit) RAMs := 2 + 1024 Bit (32 X 32 bit) RAMs := 1 + 160 Bit (16 X 10 bit) RAMs := 2 ++---ROMs : + ROMs := 1 ++---Muxes : + 2 Input 33 Bit Muxes := 3 + 2 Input 32 Bit Muxes := 138 + 3 Input 32 Bit Muxes := 1 + 4 Input 32 Bit Muxes := 7 + 8 Input 32 Bit Muxes := 5 + 20 Input 32 Bit Muxes := 1 + 6 Input 32 Bit Muxes := 2 + 7 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 1 + 2 Input 26 Bit Muxes := 3 + 2 Input 20 Bit Muxes := 1 + 2 Input 19 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 5 + 2 Input 14 Bit Muxes := 2 + 18 Input 12 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 3 + 3 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 4 + 4 Input 8 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 22 + 3 Input 8 Bit Muxes := 5 + 5 Input 8 Bit Muxes := 2 + 7 Input 8 Bit Muxes := 3 + 25 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 9 + 2 Input 6 Bit Muxes := 6 + 7 Input 5 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 15 + 3 Input 5 Bit Muxes := 1 + 8 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 22 + 8 Input 4 Bit Muxes := 9 + 3 Input 4 Bit Muxes := 1 + 3 Input 3 Bit Muxes := 2 + 2 Input 3 Bit Muxes := 6 + 20 Input 3 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 10 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 9 + 4 Input 2 Bit Muxes := 2 + 7 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 287 + 5 Input 1 Bit Muxes := 9 + 8 Input 1 Bit Muxes := 4 + 7 Input 1 Bit Muxes := 10 + 20 Input 1 Bit Muxes := 2 + 32 Input 1 Bit Muxes := 1 + 6 Input 1 Bit Muxes := 6 + 4 Input 1 Bit Muxes := 9 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +DSP Report: Generating DSP memory_to_writeBack_MUL_HH_reg, operation Mode is: (A*B)'. +DSP Report: register memory_to_writeBack_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg. +DSP Report: register execute_to_memory_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg. +DSP Report: operator execute_MUL_HH is absorbed into DSP memory_to_writeBack_MUL_HH_reg. +DSP Report: Generating DSP execute_to_memory_MUL_LH_reg, operation Mode is: (A*B)'. +DSP Report: register execute_to_memory_MUL_LH_reg is absorbed into DSP execute_to_memory_MUL_LH_reg. +DSP Report: operator execute_MUL_LH is absorbed into DSP execute_to_memory_MUL_LH_reg. +DSP Report: Generating DSP execute_to_memory_MUL_HL_reg, operation Mode is: (A*B)'. +DSP Report: register execute_to_memory_MUL_HL_reg is absorbed into DSP execute_to_memory_MUL_HL_reg. +DSP Report: operator execute_MUL_HL is absorbed into DSP execute_to_memory_MUL_HL_reg. +DSP Report: Generating DSP execute_to_memory_MUL_LL_reg, operation Mode is: (A*B)'. +DSP Report: register execute_to_memory_MUL_LL_reg is absorbed into DSP execute_to_memory_MUL_LL_reg. +DSP Report: operator execute_MUL_LL is absorbed into DSP execute_to_memory_MUL_LL_reg. +INFO: [Synth 8-3971] The signal "A2P_WB/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:24 ; elapsed = 00:01:26 . Memory (MB): peak = 2434.484 ; gain = 135.699 ; free physical = 981 ; free virtual = 10928 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------+----------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------+----------------+---------------+----------------+ +|cmod7 | mem_1_dat0_reg | 16384x32 | Block RAM | ++------------+----------------+---------------+----------------+ + + +Block RAM: Preliminary Mapping Report (see note below) ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|A2P_WB/IBusCachedPlugin_cache | ways_0_datas_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|A2P_WB/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB | IBusCachedPlugin_predictor_history_reg | 1 K x 54(READ_FIRST) | W | | 1 K x 54(WRITE_FIRST) | | R | Port A and B | 1 | 1 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------+-----------+----------------------+-------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------+-----------+----------------------+-------------+ +|cmod7 | storage_reg | Implied | 16 x 8 | RAM32M x 2 | +|cmod7 | storage_1_reg | Implied | 16 x 8 | RAM32M x 2 | ++------------+---------------+-----------+----------------------+-------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below) ++------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|A2P_WB | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 1 | +|A2P_WB | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 | +|A2P_WB | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 | +|A2P_WB | (A*B)' | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 1 | 0 | ++------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:31 ; elapsed = 00:01:33 . Memory (MB): peak = 2434.484 ; gain = 135.699 ; free physical = 832 ; free virtual = 10778 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 2434.484 ; gain = 135.699 ; free physical = 827 ; free virtual = 10774 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|A2P_WB/IBusCachedPlugin_cache | ways_0_datas_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|A2P_WB/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB/dataCache_1_ | DC_DIR_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|A2P_WB | IBusCachedPlugin_predictor_history_reg | 1 K x 54(READ_FIRST) | W | | 1 K x 54(WRITE_FIRST) | | R | Port A and B | 1 | 1 | ++------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++------------+---------------+-----------+----------------------+-------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------+-----------+----------------------+-------------+ +|cmod7 | storage_reg | Implied | 16 x 8 | RAM32M x 2 | +|cmod7 | storage_1_reg | Implied | 16 x 8 | RAM32M x 2 | ++------------+---------------+-----------+----------------------+-------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/dataCache_1_/DC_DIR_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_10 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_11 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_12 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_13 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_14 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_15 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:35 ; elapsed = 00:01:38 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 811 ; free virtual = 10757 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13035] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8733] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:4098] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1814] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1988] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1973] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1973] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1973] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1973] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1973] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1973] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1979] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1976] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1976] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1976] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1976] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1976] +WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1976] +INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:38 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:38 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 4| +|2 |CARRY4 | 247| +|3 |DNA_PORT | 1| +|4 |DSP48E1 | 4| +|6 |IDELAYCTRL | 1| +|7 |LUT1 | 277| +|8 |LUT2 | 380| +|9 |LUT3 | 891| +|10 |LUT4 | 802| +|11 |LUT5 | 935| +|12 |LUT6 | 2417| +|13 |MMCME2_ADV | 1| +|14 |MUXF7 | 35| +|15 |RAM32M | 4| +|16 |RAMB18E1 | 10| +|19 |RAMB36E1 | 18| +|37 |XADC | 1| +|38 |FD | 8| +|39 |FDCE | 283| +|40 |FDPE | 7| +|41 |FDRE | 2451| +|42 |FDSE | 123| +|43 |IBUF | 5| +|44 |IOBUF | 9| +|45 |OBUF | 27| +|46 |OBUFT | 1| ++------+-----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.492 ; gain = 192.707 ; free physical = 807 ; free virtual = 10753 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 2907 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:35 ; elapsed = 00:01:37 . Memory (MB): peak = 2491.492 ; gain = 79.992 ; free physical = 868 ; free virtual = 10814 +Synthesis Optimization Complete : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2491.500 ; gain = 192.707 ; free physical = 868 ; free virtual = 10814 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2491.500 ; gain = 0.000 ; free physical = 950 ; free virtual = 10897 +INFO: [Netlist 29-17] Analyzing 337 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +INFO: [Timing 38-2] Deriving generated clocks [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +WARNING: [Vivado 12-3521] Clock specified in more than one group: crg_clkout0 [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213] +Finished Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2840.516 ; gain = 0.000 ; free physical = 611 ; free virtual = 10558 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 21 instances were transformed. + FD => FDRE: 8 instances + IOBUF => IOBUF (IBUF, OBUFT): 9 instances + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 4 instances + +INFO: [Common 17-83] Releasing license: Synthesis +81 Infos, 140 Warnings, 6 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:54 ; elapsed = 00:01:52 . Memory (MB): peak = 2840.516 ; gain = 541.828 ; free physical = 782 ; free virtual = 10728 +# report_timing_summary -file cmod7_timing_synth.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt +# report_utilization -file cmod7_utilization_synth.rpt +# opt_design -directive default +Command: opt_design -directive default +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port pmod0 expects both input and output buffering but the buffers are incomplete. +INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2911.574 ; gain = 64.031 ; free physical = 741 ; free virtual = 10688 + +Starting Cache Timing Information Task +Ending Cache Timing Information Task | Checksum: 12978f5b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 741 ; free virtual = 10688 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1d94b6faf + +Time (s): cpu = 00:00:00.90 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 27 cells +INFO: [Opt 31-1021] In phase Retarget, 6 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1f4c0c0d9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 1 cells +INFO: [Opt 31-1021] In phase Constant propagation, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1b055dea7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Sweep, 20 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1b055dea7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.85 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. +INFO: [Opt 31-1021] In phase BUFG optimization, 3 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 1b055dea7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1b055dea7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 27 | 6 | +| Constant propagation | 0 | 1 | 2 | +| Sweep | 0 | 19 | 20 | +| BUFG optimization | 0 | 0 | 3 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 1 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 +Ending Logic Optimization Task | Checksum: 1a34ea084 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2911.574 ; gain = 0.000 ; free physical = 638 ; free virtual = 10585 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +INFO: [Power 33-23] Power model is not available for DNA_PORT +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... + +Finished Running Vector-less Activity Propagation + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 28 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports +Number of BRAM Ports augmented: 1 newly gated: 1 Total Ports: 56 +Ending PowerOpt Patch Enables Task | Checksum: 1825a2c4a + +Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 774 ; free virtual = 10721 +Ending Power Optimization Task | Checksum: 1825a2c4a + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 3170.543 ; gain = 258.969 ; free physical = 779 ; free virtual = 10726 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1825a2c4a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 779 ; free virtual = 10726 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 779 ; free virtual = 10726 +Ending Netlist Obfuscation Task | Checksum: ef4b2e89 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 779 ; free virtual = 10726 +INFO: [Common 17-83] Releasing license: Implementation +28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 3170.543 ; gain = 323.000 ; free physical = 779 ; free virtual = 10726 +# place_design -directive default +Command: place_design -directive default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[5] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[0]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[6] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[1]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[7] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[2]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_inc_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_interrupt_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_140__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_143__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_365__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/dataCache_1__io_mem_cmd_m2sPipe_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_inc_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_interrupt_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_140__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_143__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_365__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/dataCache_1__io_mem_cmd_m2sPipe_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port pmod0 expects both input and output buffering but the buffers are incomplete. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 43 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 46-5] The placer was invoked with the 'default' directive. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 750 ; free virtual = 10697 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b6b9e3cf + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 750 ; free virtual = 10697 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 750 ; free virtual = 10697 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +WARNING: [Place 30-568] A LUT 'clk12_inst' is driving clock pin of 8 registers. This could lead to large hold time violations. First few involved registers are: + FD_5 {FDRE} + FD_1 {FDRE} + FD {FDRE} + FD_3 {FDRE} + FD_2 {FDRE} +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d094301e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 768 ; free virtual = 10715 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 12e594cea + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 766 ; free virtual = 10712 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 12e594cea + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 766 ; free virtual = 10712 +Phase 1 Placer Initialization | Checksum: 12e594cea + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 766 ; free virtual = 10712 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 102370582 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 758 ; free virtual = 10705 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 12aabc56c + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 759 ; free virtual = 10706 + +Phase 2.3 Global Placement Core + +Phase 2.3.1 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 107 LUTNM shape to break, 203 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 77, two critical 30, total 107, new lutff created 1 +INFO: [Physopt 32-775] End 1 Pass. Optimized 182 nets or cells. Created 107 new cells, deleted 75 existing cells and moved 0 existing cell +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-64] No nets found for fanout-optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][1] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_11 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][5] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_7 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][10] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_2 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][3] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_9 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][2] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_10 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][7] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_5 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][8] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_4 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][4] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_8 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][6] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_6 could not be replicated +INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][9] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_3 could not be replicated +INFO: [Physopt 32-68] No nets found for critical-cell optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-527] Pass 1: Identified 3 candidate cells for BRAM register optimization +INFO: [Physopt 32-665] Processed cell A2P_WB/dataCache_1_/DC_DIR_data_symbol3_reg. 8 registers were pushed out. +INFO: [Physopt 32-666] Processed cell A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg. No change. +INFO: [Physopt 32-665] Processed cell A2P_WB/dataCache_1_/DC_DIR_data_symbol2_reg. 8 registers were pushed out. +INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 16 new cells, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 739 ; free virtual = 10686 +INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 739 ; free virtual = 10686 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 107 | 75 | 182 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| BRAM Register | 16 | 0 | 2 | 0 | 1 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 123 | 75 | 184 | 0 | 10 | 00:00:01 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.3.1 Physical Synthesis In Placer | Checksum: 19c653749 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 740 ; free virtual = 10687 +Phase 2.3 Global Placement Core | Checksum: 18c9e46b7 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 740 ; free virtual = 10686 +Phase 2 Global Placement | Checksum: 18c9e46b7 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 743 ; free virtual = 10690 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1c9f1baa9 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:11 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 743 ; free virtual = 10689 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f0337058 + +Time (s): cpu = 00:00:27 ; elapsed = 00:00:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 741 ; free virtual = 10688 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 208d7322e + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 741 ; free virtual = 10688 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 22bd3208c + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 741 ; free virtual = 10688 + +Phase 3.5 Fast Optimization +Phase 3.5 Fast Optimization | Checksum: 230abce19 + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:13 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 740 ; free virtual = 10687 + +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: 21cddc7bf + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:16 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 740 ; free virtual = 10687 + +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 1cd7ad4ed + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:16 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 742 ; free virtual = 10689 + +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 153579b5e + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:16 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 742 ; free virtual = 10689 + +Phase 3.9 Fast Optimization +Phase 3.9 Fast Optimization | Checksum: 1d338a4b9 + +Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 735 ; free virtual = 10682 +Phase 3 Detail Placement | Checksum: 1d338a4b9 + +Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 735 ; free virtual = 10682 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 213358b0e + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.306 | TNS=-1.849 | +Phase 1 Physical Synthesis Initialization | Checksum: 1aef7145f + +Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 731 ; free virtual = 10677 +INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. +Ending Physical Synthesis Task | Checksum: 195647e5d + +Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 731 ; free virtual = 10677 +Phase 4.1.1.1 BUFG Insertion | Checksum: 213358b0e + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:22 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 731 ; free virtual = 10677 +INFO: [Place 30-746] Post Placement Timing Summary WNS=0.510. For the most accurate timing information please run report_timing. + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 +Phase 4.1 Post Commit Optimization | Checksum: 199935b85 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 199935b85 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 1x1| 4x4| +|___________|___________________|___________________| +| East| 1x1| 4x4| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 199935b85 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:24 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 +Phase 4.3 Placer Reporting | Checksum: 199935b85 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:25 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:25 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 10a32b2b4 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:25 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 +Ending Placer Task | Checksum: 61514434 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:25 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 730 ; free virtual = 10676 +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 44 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:27 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 743 ; free virtual = 10689 +# report_utilization -hierarchical -file cmod7_utilization_hierarchical_place.rpt +# report_utilization -file cmod7_utilization_place.rpt +# report_io -file cmod7_io.rpt +report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 739 ; free virtual = 10685 +# report_control_sets -verbose -file cmod7_control_sets.rpt +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 748 ; free virtual = 10695 +# report_clock_utilization -file cmod7_clock_utilization.rpt +# route_design -directive default +Command: route_design -directive default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'default'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs +Checksum: PlaceDB: 17552f95 ConstDB: 0 ShapeSum: 49fc149f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 157ed1690 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 630 ; free virtual = 10578 +Post Restoration Checksum: NetGraph: ef4e428a NumContArr: 689ed406 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 157ed1690 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 633 ; free virtual = 10581 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 157ed1690 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 603 ; free virtual = 10550 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 157ed1690 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 603 ; free virtual = 10550 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 210981e82 + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 590 ; free virtual = 10537 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.653 | TNS=0.000 | WHS=-0.148 | THS=-41.667| + +Phase 2 Router Initialization | Checksum: 1cf3a94d4 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 588 ; free virtual = 10536 + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00741449 % + Global Horizontal Routing Utilization = 0.00507548 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 7690 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 7689 + Number of Partially Routed Nets = 1 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing + +Phase 3.1 Global Routing +Phase 3.1 Global Routing | Checksum: 1cf3a94d4 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 586 ; free virtual = 10533 +Phase 3 Initial Routing | Checksum: 245374c77 + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:14 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 583 ; free virtual = 10531 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 3721 + Number of Nodes with overlaps = 1755 + Number of Nodes with overlaps = 985 + Number of Nodes with overlaps = 613 + Number of Nodes with overlaps = 317 + Number of Nodes with overlaps = 119 + Number of Nodes with overlaps = 127 + Number of Nodes with overlaps = 50 + Number of Nodes with overlaps = 21 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.162 | TNS=-0.284 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 10d4cf58e + +Time (s): cpu = 00:02:12 ; elapsed = 00:00:44 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 585 ; free virtual = 10529 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 592 + Number of Nodes with overlaps = 318 + Number of Nodes with overlaps = 146 + Number of Nodes with overlaps = 84 + Number of Nodes with overlaps = 39 + Number of Nodes with overlaps = 25 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 17 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.007 | TNS=-0.007 | WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 2102603d0 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:59 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 585 ; free virtual = 10529 + +Phase 4.3 Global Iteration 2 + Number of Nodes with overlaps = 268 + Number of Nodes with overlaps = 124 + Number of Nodes with overlaps = 91 + Number of Nodes with overlaps = 68 + Number of Nodes with overlaps = 60 + Number of Nodes with overlaps = 33 + Number of Nodes with overlaps = 34 + Number of Nodes with overlaps = 26 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.138 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.3 Global Iteration 2 | Checksum: 987ca01c + +Time (s): cpu = 00:03:06 ; elapsed = 00:01:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 +Phase 4 Rip-up And Reroute | Checksum: 987ca01c + +Time (s): cpu = 00:03:06 ; elapsed = 00:01:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 987ca01c + +Time (s): cpu = 00:03:06 ; elapsed = 00:01:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 987ca01c + +Time (s): cpu = 00:03:06 ; elapsed = 00:01:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 +Phase 5 Delay and Skew Optimization | Checksum: 987ca01c + +Time (s): cpu = 00:03:06 ; elapsed = 00:01:10 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 12b31b37c + +Time (s): cpu = 00:03:07 ; elapsed = 00:01:11 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.217 | TNS=0.000 | WHS=0.029 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 9af62b6c + +Time (s): cpu = 00:03:08 ; elapsed = 00:01:11 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 +Phase 6 Post Hold Fix | Checksum: 9af62b6c + +Time (s): cpu = 00:03:08 ; elapsed = 00:01:11 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 4.884 % + Global Horizontal Routing Utilization = 5.9145 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 5478b55c + +Time (s): cpu = 00:03:08 ; elapsed = 00:01:11 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 587 ; free virtual = 10531 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 5478b55c + +Time (s): cpu = 00:03:08 ; elapsed = 00:01:11 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 586 ; free virtual = 10530 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e1f9d340 + +Time (s): cpu = 00:03:09 ; elapsed = 00:01:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 585 ; free virtual = 10529 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=0.217 | TNS=0.000 | WHS=0.029 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: e1f9d340 + +Time (s): cpu = 00:03:09 ; elapsed = 00:01:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 585 ; free virtual = 10529 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:03:09 ; elapsed = 00:01:12 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 623 ; free virtual = 10567 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:03:16 ; elapsed = 00:01:14 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 623 ; free virtual = 10567 +# phys_opt_design -directive default +Command: phys_opt_design -directive default +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed) +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: default +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +# write_checkpoint -force cmod7_route.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.72 . Memory (MB): peak = 3170.543 ; gain = 0.000 ; free physical = 605 ; free virtual = 10562 +INFO: [Common 17-1381] The checkpoint '/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7_route.dcp' has been generated. +# report_timing_summary -no_header -no_detailed_paths +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (1) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (2) +5. checking no_input_delay (13) +6. checking no_output_delay (36) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (1) +------------------------ + There is 1 register/latch pin with no clock driven by root clock pin: dna_count_reg[0]/Q (HIGH) + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (2) +------------------------------------------------ + There are 2 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (13) +------------------------------- + There are 13 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (36) +-------------------------------- + There are 36 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.217 0.000 0 7465 0.029 0.000 0 7465 3.750 0.000 0 2959 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk12 {0.000 41.666} 83.333 12.000 + crg_clkout0 {0.000 5.000} 10.000 100.000 + subfragments_mmcm_fb {0.000 41.666} 83.333 12.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk12 80.380 0.000 0 7 0.216 0.000 0 7 16.667 0.000 0 10 + crg_clkout0 0.217 0.000 0 7172 0.029 0.000 0 7172 3.750 0.000 0 2947 + subfragments_mmcm_fb 16.667 0.000 0 2 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** crg_clkout0 crg_clkout0 0.932 0.000 0 286 0.506 0.000 0 286 + + +# report_route_status -file cmod7_route_status.rpt +# report_drc -file cmod7_drc.rpt +Command: report_drc -file cmod7_drc.rpt +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Coretcl 2-168] The results of DRC are in file /home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7_drc.rpt. +report_drc completed successfully +# report_timing_summary -datasheet -max_paths 10 -file cmod7_timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# report_power -file cmod7_power.rpt +Command: report_power -file cmod7_power.rpt +INFO: [Power 33-23] Power model is not available for DNA_PORT +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. +Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. +1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +# write_bitstream -force cmod7.bit +Command: write_bitstream -force cmod7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. +WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg input A2P_WB/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg input A2P_WB/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg input A2P_WB/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg input A2P_WB/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg input A2P_WB/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg input A2P_WB/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/memory_to_writeBack_MUL_HH_reg input A2P_WB/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/memory_to_writeBack_MUL_HH_reg input A2P_WB/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg multiplier stage A2P_WB/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg multiplier stage A2P_WB/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg multiplier stage A2P_WB/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC PDRC-153] Gated clock check: Net crg_clkin is a gated clock net sourced by a combinational pin clk12_inst/O, cell clk12_inst. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT clk12_inst is driving clock pin of 8 cells. This could lead to large hold time violations. Involved cells are: +FD, FD_1, FD_2, FD_3, FD_4, FD_5, FD_6, and FD_7 +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[5] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[0]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[6] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[1]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[7] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[2]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_inc_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_interrupt_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_140__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_143__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_365__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/dataCache_1__io_mem_cmd_m2sPipe_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_inc_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_interrupt_valid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_140__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_143__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_365__reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/dataCache_1__io_mem_cmd_m2sPipe_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 56 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./cmod7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Nov 11 08:39:39 2021. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html. +INFO: [Common 17-83] Releasing license: Implementation +10 Infos, 56 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:16 . Memory (MB): peak = 3247.488 ; gain = 76.945 ; free physical = 584 ; free virtual = 10528 +# quit +INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 08:39:39 2021... +Copying .v and .bit, and programming... + + + +****** Vivado v2020.2 (64-bit) + **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 + **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 + ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + +source pgmfpga.tcl +# open_hw_manager +# connect_hw_server +INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 +INFO: [Labtools 27-2222] Launching hw_server... +INFO: [Labtools 27-2221] Launch Output: + +****** Xilinx hw_server v2020.2 + **** Build date : Nov 18 2020 at 09:50:49 + ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. + + +INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042 +INFO: [Labtools 27-3417] Launching cs_server... +INFO: [Labtools 27-2221] Launch Output: + + +******** Xilinx cs_server v2020.2 + ****** Build date : Nov 03 2020-15:02:56 + **** Build number : 2020.2.1604437376 + ** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved. + + + +# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*] +# open_hw_target +INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210328B04819A +# set dev [lindex [get_hw_devices] 0] +# current_hw_device $dev +# refresh_hw_device -update_hw_probes false $dev +INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +# set_property PROGRAM.FILE {./cmod7.bit} $dev +# program_hw_devices $dev +INFO: [Labtools 27-3164] End of startup status: HIGH +# refresh_hw_device $dev +INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. +# puts "Device programmed." +Device programmed. +# quit +INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 08:39:56 2021... + + +Done.