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@ -17,7 +17,9 @@ some bugs in CR/XER handling.
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* Need to define supported translation modes.
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* SOC builds with Litex; software is built manually and runs from 'ROM' with on-board RAM.
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* SOC builds with Litex; ~~software is built manually and runs from 'ROM' with on-board RAM.~~
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* now running Litex BiOS, coremark, prototype test environment, etc. with async RAM interface on Cmod-A7 ISSI chip.
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* Core and SOC run in Verilator/pyverilator. SOC uses emulated host UART.
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