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gen/run simple.tst

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master
wtf 3 years ago
parent 32586292a4
commit 32f86e291f
7 changed files with 876 additions and 11 deletions
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4
software/arci/arcigen.py
Unescape Escape View File

@ -164,6 +164,7 @@ class Add(Op):
return self

def print(self):
self.addToStream()
lines.append(f'I {self.cia:08X} {self.op}')
for i in range(len(self.res)):
lines.append(f'R {self.res[i][0]:6} {self.res[i][1]:08X} {self.res[i][2]}')
@ -202,6 +203,7 @@ class Add_R(Op):
return self

def print(self):
self.addToStream()
lines.append(f'I {self.cia:08X} {self.op}')
for i in range(len(self.res)):
lines.append(f'R {self.res[i][0]:6} {self.res[i][1]:08X} {self.res[i][2]}')
@ -258,7 +260,7 @@ def genAsm(tplFile, asmFile):
for k,f in facs.items():
if f.spr:
tstData[f'init_{f.rname.lower()}'] = f'0x{f.init:08X}'
tstData[f'expt_{f.rname.lower()}'] = f'0x{f.init:08X}'
tstData[f'expt_{f.rname.lower()}'] = f'0x{f.value:08X}'

for i in range(32):
v = gpr[f'r{i}'].init

338
software/arci/arcirun.c
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@ -0,0 +1,338 @@
/*
© IBM Corp. 2020
Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
repository except in compliance with the License as modified.
You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0

Modified Terms:

1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
the work of authorship in physical form.

2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
under the terms and conditions of the EULA.

Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
governing permissions and limitations under the License.

Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
ISA) here: https://openpowerfoundation.org.

Brief explanation of modifications:

Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
it unambiguously permits a user to make and use the physical chip.

Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received
under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
licenses for the specific Power ISA Core are granted under this modified Apache license.
*/

//wtf fix up int vs pointer

#include <stdio.h>
#include "arcirun.h"

#define DEBUG 1
//#define DEBUG2

//#define SAFESTACK

#define MAGIC 0x08675309

// needs to be here so it's at start address
void main(unsigned int r1, unsigned int r2, unsigned int r3, unsigned int addr) {
unsigned int *inits = &tst_inits;
unsigned int v;

console_set_write_hook(0); // make sure null
printf("Thunderbirds are go!!!\n\n\n");

printf("Invoking test...\n");

// danger! once r1 is whacked, any c code like bad int handler, etc. needs
// to make sure it has a safe stack for calls
asm (
"mr 3,%0\n"
//"lis 4,init_tst@h\n"
//"ori 4,4,init_tst@l\n"
//"mtctr 4\n"
//"bcctr\n"
"b init_tst\n"
: // outputs
: "r"(inits) // inputs
: "r3" // clobbers
);

while(1) {}

}

//void __attribute__((noreturn)) tst_done(unsigned int rc) {
void tst_done(unsigned int rc) {
unsigned int i, ok = 1, done = 0;
char c;
char name[10];
unsigned int r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
unsigned int cr, xer, ctr, lr, tar;
unsigned int op, *cia;

#ifdef DEBUG
asm volatile(
"mr %0,0\n"
"mr %1,1\n"
"mr %2,2\n"
"mr %3,3\n"
"mr %4,4\n"
"mr %5,5\n"
"mr %6,6\n"
"mr %7,7\n"
"mr %8,8\n"
"mr %9,9\n"
"mr %10,10\n"
"mr %11,11\n"
"mr %12,12\n"
"mr %13,13\n"
"mr %14,14\n"
"mr %15,15\n"
: "=r"(r0), "=r"(r1), "=r"(r2), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6), "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11), "=r"(r12), "=r"(r13), "=r"(r14), "=r"(r15) // outputs
: // inputs
: // clobbers
);
#endif

// can't help unless can get rid of preamble! give tst return addr and have it jmp there
#ifdef SAFESTACK
// force stack to be copacetic
unsigned int safestack=0x17FFF0;
asm volatile(
"mr %0,1\n"
"mr 1,%1\n"
: "=r"(r1) // outputs
: "r"(safestack) // inputs
);
printf("SAFETYSTACK'ed %08X->%08X\n\n", r1, safestack);
#endif

#ifdef DEBUG2
printf("GPR\n");
printf(" 00: %08X 01: %08X 02: %08X 03: %08X 04: %08X 05: %08X 06: %08X 07: %08X\n", r0, r1, r2, r3, r4, r5, r6, r7);
printf(" 08: %08X 09: %08X 10: %08X 11: %08X 12: %08X 13: %08X 14: %08X 15: %08X\n", r8, r9, r10, r11, r12, r13, r14, r15);

printf("\n");

asm volatile(
"mfcr %0\n"
"mfxer %1\n"
"mfctr %2\n"
"mflr %3\n"
"mfspr %4,815\n"
: "=r"(cr), "=r"(xer), "=r"(ctr), "=r"(lr), "=r"(tar) // outputs
: // inputs
: // clobbers
);

printf("CR: %08X", cr);
printf(" XER: %08X", xer);
printf(" CTR: %08X", ctr);
printf(" LR: %08X", lr);
printf(" TAR: %08X", tar);
printf("\n\n");

#ifdef SAFESTACK
r1 = safestack;
#endif
printf("Stack\n");
printMem((r1-0x100)&0xFFFFFFF0, (r1+0x100)&0xFFFFFFF0);
printf("\n");

printf("Initsl\n");
printMem(&tst_inits, (int)(&tst_inits)+40*4);
printf("Actual\n");
printMem(&tst_results, (int)(&tst_results)+40*4);
printf("Expected\n");
printMem(&tst_expects, (int)(&tst_expects)+40*4);

printf("\n\n\n");

#endif

printf("Test completed. Checking results...\n\n");

if (rc != MAGIC) {
printf("Huh? rc=%08X\n\n\n", rc);
ok = 0;
}

// ops
printf("Instructions\n");
for (cia = &tst_start; cia < &tst_end; cia++) {
op = *cia;
printf(" %08X: %08X\n", (int)cia, op);
}
printf("\n");

printf("Facilities\n");
// r0:r31
for (i = 0; i < 32; i++) {
sprintf(name, "R%02d", i);
ok = ok && checkResult(i, name);
}

// cr, xer, ctr, lr, tar
ok = ok && checkResult(32, "CR");
ok = ok && checkResult(33, "XER");
ok = ok && checkResult(34, "CTR");
ok = ok && checkResult(35, "LR");
ok = ok && checkResult(36, "TAR");

// msr, srr0, srr1, dar, dsisr

printf("\n\n");
if (ok) {
printf("You has opulence.\n\n");
} else {
printf("You are worthless and weak!\n\n");
}

printf("Here you would run another test automatically, or temp halt, or reboot bios...\n");

while (!done) {
if(uart_read_nonblock()) {
c = uart_read();
if ((c == 'r') || (c == '\e')) {
printf("Rebooting...\n\n\n\n");
asm (
"ba 0\n"
);
} else if (c == 'q') {
done = 1;
} else {
asm (
"b main\n"
);
}
}
}

printf("Hanging...\n");
while(1) {}
}

void printMem(unsigned int start, unsigned int end) {
unsigned int i, j, k, l, *p;
char *c;
unsigned int groupSize = 8, maxLines = 32;

l = 0;
for (i = start; i < end; i += 4*groupSize) {
printf(" %08X:", i);
for (j = 0; j < 4*groupSize; j+=4) {
p = i + j;
printf(" %08X", *p);
}
printf(" ");
for (k = 0; k < 4*groupSize; k++) {
c = i + k;
if ((*c < 32) | (*c > 126)) {
putchar(' ');
} else {
putchar(*c);
}
}
printf("\n");
l++;
if (l == maxLines) {
printf("...\n");
break;
}
}
}

void printGPR(void) {
unsigned int r0, r1, r2, r3, r4, r5, r6, r7;

asm volatile(
"mr %0,0\n"
"mr %1,1\n"
"mr %2,2\n"
"mr %3,3\n"
"mr %4,4\n"
"mr %5,5\n"
"mr %6,6\n"
"mr %7,7\n"
: "=r"(r0), "=r"(r1), "=r"(r2), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6), "=r"(r7) // outputs
: // inputs
: // clobbers
);

printf("GPR\n");
printf(" 00: %08X 01: %08X 02: %08X 03: %08X 04: %08X 05: %08X 06: %08X 07: %08X\n", r0, r1, r2, r3, r4, r5, r6, r7);
printf("\n");
}

void printSPR(void) {
unsigned int cr, xer, ctr, lr, tar;

asm volatile(
"mfcr %0\n"
"mfxer %1\n"
"mfctr %2\n"
"mflr %3\n"
"mfspr %4,815\n"
: "=r"(cr), "=r"(xer), "=r"(ctr), "=r"(lr), "=r"(tar) // outputs
: // inputs
: // clobbers
);

printf("CR: %08X", cr);
printf(" XER: %08X", xer);
printf(" CTR: %08X", ctr);
printf(" LR: %08X", lr);
printf(" TAR: %08X", tar);
printf("\n");

}

void printSPRPriv(void) {
unsigned int srr0, srr1, dar, dsisr;

asm volatile(
"mfspr %0,26\n"
"mfspr %1,27\n"
"mfspr %2,19\n"
"mfspr %3,18\n"
: "=r"(srr0), "=r"(srr1), "=r"(dar), "=r"(dsisr) // outputs
: // inputs
: // clobbers
);

printf("SRR0: %08X", srr0);
printf(" SRR1: %08X", srr1);
printf(" DAR: %08X", dar);
printf(" DSISR: %08X", dsisr);
printf("\n");
}

unsigned int checkResult(unsigned int r, char* name) {
unsigned int init, act, exp, ok = 1;

init = *(&tst_inits + r);
act = *(&tst_results + r);
exp = *(&tst_expects + r);
if (DEBUG || act != exp) {
printf("%6s: %08X %08X %08X ", name, init, act, exp);
if (act != exp) {
printf("* MISCOMPARE\n");
ok = 0;
} else {
printf("\n");
}
}
return ok;
}

16
software/arci/arcitst.tpl
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@ -6,6 +6,8 @@
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects
@ -63,8 +65,6 @@ init_lr: .long $init_lr
init_tar: .long $init_tar

save_r1: .long 0
save_r30: .long 0
save_r31: .long 0

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
@ -73,8 +73,6 @@ init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)
stw r30,(save_r30-tst_inits)(r3)
stw r31,(save_r31-tst_inits)(r3)

# init test regs
lwz r1,(init_cr-tst_inits)(r3)
@ -121,16 +119,17 @@ init_tst:
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

b start_tst
b tst_start

# -------------------------------------------------------------------------------------------------
.align 5
start_tst:
tst_start:

# -------------------------------------------------------------------------------------------------
$stream
# -------------------------------------------------------------------------------------------------

tst_end:
b save_results

# -------------------------------------------------------------------------------------------------
@ -184,12 +183,11 @@ save_results:
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r1,tst_inits@l
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lwz r30,(save_r30-tst_inits)(r3)
lwz r31,(save_r31-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l


146
software/arci/defines.s
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@ -0,0 +1,146 @@
# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

#-----------------------------------------
# Defines
#-----------------------------------------

# Regs

.set r0, 0
.set r1, 1
.set r2, 2
.set r3, 3
.set r4, 4
.set r5, 5
.set r6, 6
.set r7, 7
.set r8, 8
.set r9, 9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31

.set f0, 0
.set f1, 1
.set f2, 2
.set f3, 3
.set f4, 4
.set f5, 5
.set f6, 6
.set f7, 7
.set f8, 8
.set f9, 9
.set f10,10
.set f11,11
.set f12,12
.set f13,13
.set f14,14
.set f15,15
.set f16,16
.set f17,17
.set f18,18
.set f19,19
.set f20,20
.set f21,21
.set f22,22
.set f23,23
.set f24,24
.set f25,25
.set f26,26
.set f27,27
.set f28,28
.set f29,29
.set f30,30
.set f31,31

.set cr0, 0
.set cr1, 1
.set cr2, 2
.set cr3, 3
.set cr4, 4
.set cr5, 5
.set cr6, 6
.set cr7, 7

# SPR numbers

.set srr0, 26
.set srr1, 27
.set epcr, 307
.set tar, 815
.set dsisr, 18
.set dar, 19

.set dbsr, 304
.set dbcr0, 308
.set dbcr1, 309
.set dbcr2, 310
.set dbcr3, 848

.set ivpr, 63

.set iucr0, 1011
.set iucr1, 883
.set iucr2, 884

.set iudbg0, 888
.set iudbg1, 889
.set iudbg2, 890
.set iulfsr, 891
.set iullcr, 892

.set mmucr0, 1020
.set mmucr1, 1021
.set mmucr2, 1022
.set mmucr3, 1023

.set tb, 268
.set tbl, 284
.set tbh, 285

.set dec, 22
.set udec, 550
.set tsr, 336
.set tcr, 340

.set xucr0, 1014
.set xucr1, 851
.set xucr2, 1016
.set xucr3, 852
.set xucr4, 853

.set tens, 438
.set tenc, 439
.set tensr, 437

.set pid, 48
.set pir, 286
.set pvr, 287
.set tir, 446

97
software/arci/readme.md
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@ -4,3 +4,100 @@

* test generation/build/run

### experimenting

* gen and run simple.tst

```
lxterm /dev/ttyUSB1 --kernel arci.bin --kernel-adr 0x120000
```

```
BIOS built on Nov 7 2021 11:47:53
BIOS CRC failed (expected 00000000, got ee67935c)
The system will continue, but expect problems.

Migen git sha1: 27dbf03
LiteX git sha1: 78c1751c

--=============== SoC ==================--
CPU: A2P_WB @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 512KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading arci.bin to 0x00120000 (17576 bytes)...
[LXTERM] Upload complete (9.8KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.

--============= Console ================--

litex> boot 0x120000
Executing booted program at 0x00120000

--============= Liftoff! ===============--
Thunderbirds are go!!!


Invoking test...
Test completed. Checking results...

Instructions
00123500: 38630001
00123504: 38630001
00123508: 38630001
0012350C: 3880FFFD
00123510: 7C841A15

Facilities
R00: 00000000 00000000 00000000
R01: 00000000 00000000 00000000
R02: 00000000 00000000 00000000
R03: 00000000 00000003 00000003
R04: 00000000 00000000 00000000
R05: 00000000 00000000 00000000
R06: 00000000 00000000 00000000
R07: 00000000 00000000 00000000
R08: 00000000 00000000 00000000
R09: 00000000 00000000 00000000
R10: 00000000 00000000 00000000
R11: 00000000 00000000 00000000
R12: 00000000 00000000 00000000
R13: 00000000 00000000 00000000
R14: 00000000 00000000 00000000
R15: 00000000 00000000 00000000
R16: 00000000 00000000 00000000
R17: 00000000 00000000 00000000
R18: 00000000 00000000 00000000
R19: 00000000 00000000 00000000
R20: 00000000 00000000 00000000
R21: 00000000 00000000 00000000
R22: 00000000 00000000 00000000
R23: 00000000 00000000 00000000
R24: 00000000 00000000 00000000
R25: 00000000 00000000 00000000
R26: 00000000 00000000 00000000
R27: 00000000 00000000 00000000
R28: 00000000 00000000 00000000
R29: 00000000 00000000 00000000
R30: 00000000 00000000 00000000
R31: 00000000 00000000 00000000
CR: 00000000 20000000 20000000
XER: 00000000 00000000 00000000
CTR: F0000000 F0000000 F0000000
LR: 00000000 00000000 00000000
TAR: 00000000 00000000 00000000


You has opulence.

Here you would run another test automatically, or temp halt, or reboot bios...
```

284
software/arci/simple.s
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@ -0,0 +1,284 @@
# architst

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_name: .asciz "simple"
tst_info: .asciz "wtf"

.set SAVESPR,tar
.set MAGIC,0x08675309

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .long 0x00000000
init_r1: .long 0x00000000
init_r2: .long 0x00000000
init_r3: .long 0x00000000
init_r4: .long 0x00000000
init_r5: .long 0x00000000
init_r6: .long 0x00000000
init_r7: .long 0x00000000
init_r8: .long 0x00000000
init_r9: .long 0x00000000
init_r10: .long 0x00000000
init_r11: .long 0x00000000
init_r12: .long 0x00000000
init_r13: .long 0x00000000
init_r14: .long 0x00000000
init_r15: .long 0x00000000
init_r16: .long 0x00000000
init_r17: .long 0x00000000
init_r18: .long 0x00000000
init_r19: .long 0x00000000
init_r20: .long 0x00000000
init_r21: .long 0x00000000
init_r22: .long 0x00000000
init_r23: .long 0x00000000
init_r24: .long 0x00000000
init_r25: .long 0x00000000
init_r26: .long 0x00000000
init_r27: .long 0x00000000
init_r28: .long 0x00000000
init_r29: .long 0x00000000
init_r30: .long 0x00000000
init_r31: .long 0x00000000

init_cr: .long 0x00000000
init_xer: .long 0x00000000
init_ctr: .long 0xF0000000
init_lr: .long 0x00000000
init_tar: .long 0x00000000

save_r1: .long 0

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)

# init test regs
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

b tst_start

# -------------------------------------------------------------------------------------------------
.align 5
tst_start:

# -------------------------------------------------------------------------------------------------
addi r3,r3,1
addi r3,r3,1
addi r3,r3,1
addi r4,r0,-3
add. r4,r4,r3
# -------------------------------------------------------------------------------------------------

tst_end:
b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

b tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .long 0xFFFFFFFF
rslt_r1: .long 0xFFFFFFFF
rslt_r2: .long 0xFFFFFFFF
rslt_r3: .long 0xFFFFFFFF
rslt_r4: .long 0xFFFFFFFF
rslt_r5: .long 0xFFFFFFFF
rslt_r6: .long 0xFFFFFFFF
rslt_r7: .long 0xFFFFFFFF
rslt_r8: .long 0xFFFFFFFF
rslt_r9: .long 0xFFFFFFFF
rslt_r10: .long 0xFFFFFFFF
rslt_r11: .long 0xFFFFFFFF
rslt_r12: .long 0xFFFFFFFF
rslt_r13: .long 0xFFFFFFFF
rslt_r14: .long 0xFFFFFFFF
rslt_r15: .long 0xFFFFFFFF
rslt_r16: .long 0xFFFFFFFF
rslt_r17: .long 0xFFFFFFFF
rslt_r18: .long 0xFFFFFFFF
rslt_r19: .long 0xFFFFFFFF
rslt_r20: .long 0xFFFFFFFF
rslt_r21: .long 0xFFFFFFFF
rslt_r22: .long 0xFFFFFFFF
rslt_r23: .long 0xFFFFFFFF
rslt_r24: .long 0xFFFFFFFF
rslt_r25: .long 0xFFFFFFFF
rslt_r26: .long 0xFFFFFFFF
rslt_r27: .long 0xFFFFFFFF
rslt_r28: .long 0xFFFFFFFF
rslt_r29: .long 0xFFFFFFFF
rslt_r30: .long 0xFFFFFFFF
rslt_r31: .long 0xFFFFFFFF

rslt_cr: .long 0xFFFFFFFF
rslt_xer: .long 0xFFFFFFFF
rslt_ctr: .long 0xFFFFFFFF
rslt_lr: .long 0xFFFFFFFF
rslt_tar: .long 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .long 0x00000000
expt_r1: .long 0x00000000
expt_r2: .long 0x00000000
expt_r3: .long 0x00000003
expt_r4: .long 0x00000000
expt_r5: .long 0x00000000
expt_r6: .long 0x00000000
expt_r7: .long 0x00000000
expt_r8: .long 0x00000000
expt_r9: .long 0x00000000
expt_r10: .long 0x00000000
expt_r11: .long 0x00000000
expt_r12: .long 0x00000000
expt_r13: .long 0x00000000
expt_r14: .long 0x00000000
expt_r15: .long 0x00000000
expt_r16: .long 0x00000000
expt_r17: .long 0x00000000
expt_r18: .long 0x00000000
expt_r19: .long 0x00000000
expt_r20: .long 0x00000000
expt_r21: .long 0x00000000
expt_r22: .long 0x00000000
expt_r23: .long 0x00000000
expt_r24: .long 0x00000000
expt_r25: .long 0x00000000
expt_r26: .long 0x00000000
expt_r27: .long 0x00000000
expt_r28: .long 0x00000000
expt_r29: .long 0x00000000
expt_r30: .long 0x00000000
expt_r31: .long 0x00000000

expt_cr: .long 0x20000000
expt_xer: .long 0x00000000
expt_ctr: .long 0xF0000000
expt_lr: .long 0x00000000
expt_tar: .long 0x00000000

2
software/arci/simple.tst
Unescape Escape View File

@ -1,7 +1,7 @@

* arci v.0.0001
* -----------------------------------------------------------------------------------------
* Generated: Nov 07 2021 01:44:35 AM GMT
* Generated: Nov 08 2021 11:43:59 AM GMT
*

* Initialization

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