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add some gcc stuff

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wtf 4 years ago
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115
software/gcc/gcc/config/rs6000/ppc-auxv.h
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/* PowerPC support for accessing the AUXV AT_PLATFORM, AT_HWCAP and AT_HWCAP2
values from the Thread Control Block (TCB).

Copyright (C) 2016-2021 Free Software Foundation, Inc.
Contributed by Peter Bergner <bergner@vnet.ibm.com>.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.

GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.

Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.

You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */

#ifndef _PPC_AUXV_H
#define _PPC_AUXV_H

/* The PLATFORM value stored in the TCB is offset by _DL_FIRST_PLATFORM. */
#define _DL_FIRST_PLATFORM 32

/* AT_PLATFORM bits. These must match the values defined in GLIBC. */
#define PPC_PLATFORM_POWER4 0
#define PPC_PLATFORM_PPC970 1
#define PPC_PLATFORM_POWER5 2
#define PPC_PLATFORM_POWER5_PLUS 3
#define PPC_PLATFORM_POWER6 4
#define PPC_PLATFORM_CELL_BE 5
#define PPC_PLATFORM_POWER6X 6
#define PPC_PLATFORM_POWER7 7
#define PPC_PLATFORM_PPCA2 8
#define PPC_PLATFORM_PPC405 9
#define PPC_PLATFORM_PPC440 10
#define PPC_PLATFORM_PPC464 11
#define PPC_PLATFORM_PPC476 12
#define PPC_PLATFORM_POWER8 13
#define PPC_PLATFORM_POWER9 14
#define PPC_PLATFORM_PPCA2P 9 // i guess? cant use my own if glibc needs it! 0x8675309

/* This is not yet official. */
#define PPC_PLATFORM_POWER10 15

/* AT_HWCAP bits. These must match the values defined in the Linux kernel. */
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
#define PPC_FEATURE_HAS_FPU 0x08000000
#define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
#define PPC_FEATURE_NO_TB 0x00100000
#define PPC_FEATURE_POWER4 0x00080000
#define PPC_FEATURE_POWER5 0x00040000
#define PPC_FEATURE_POWER5_PLUS 0x00020000
#define PPC_FEATURE_CELL_BE 0x00010000
#define PPC_FEATURE_BOOKE 0x00008000
#define PPC_FEATURE_SMT 0x00004000
#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
#define PPC_FEATURE_ARCH_2_05 0x00001000
#define PPC_FEATURE_PA6T 0x00000800
#define PPC_FEATURE_HAS_DFP 0x00000400
#define PPC_FEATURE_POWER6_EXT 0x00000200
#define PPC_FEATURE_ARCH_2_06 0x00000100
#define PPC_FEATURE_HAS_VSX 0x00000080
#define PPC_FEATURE_PERFMON_COMPAT 0x00000040
#define PPC_FEATURE_TRUE_LE 0x00000002
#define PPC_FEATURE_PPC_LE 0x00000001

/* AT_HWCAP2 bits. These must match the values defined in the Linux kernel. */
#define PPC_FEATURE2_ARCH_2_07 0x80000000
#define PPC_FEATURE2_HAS_HTM 0x40000000
#define PPC_FEATURE2_HAS_DSCR 0x20000000
#define PPC_FEATURE2_HAS_EBB 0x10000000
#define PPC_FEATURE2_HAS_ISEL 0x08000000
#define PPC_FEATURE2_HAS_TAR 0x04000000
#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000
#define PPC_FEATURE2_HTM_NOSC 0x01000000
#define PPC_FEATURE2_ARCH_3_00 0x00800000
#define PPC_FEATURE2_HAS_IEEE128 0x00400000
#define PPC_FEATURE2_DARN 0x00200000
#define PPC_FEATURE2_SCV 0x00100000
#define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000

/* These are not yet official. */
#define PPC_FEATURE2_ARCH_3_1 0x00040000
#define PPC_FEATURE2_MMA 0x00020000

/* Thread Control Block (TCB) offsets of the AT_PLATFORM, AT_HWCAP and
AT_HWCAP2 values. These must match the values defined in GLIBC. */
#define TCB_PLATFORM_OFFSET ((TARGET_64BIT) ? -28764 : -28724)
#define TCB_HWCAP_BASE_OFFSET ((TARGET_64BIT) ? -28776 : -28736)
#define TCB_HWCAP1_OFFSET \
((BYTES_BIG_ENDIAN) ? TCB_HWCAP_BASE_OFFSET : TCB_HWCAP_BASE_OFFSET+4)
#define TCB_HWCAP2_OFFSET \
((BYTES_BIG_ENDIAN) ? TCB_HWCAP_BASE_OFFSET+4 : TCB_HWCAP_BASE_OFFSET)
#define TCB_HWCAP_OFFSET(ID) \
(((ID) == 0) ? TCB_HWCAP1_OFFSET : TCB_HWCAP2_OFFSET)

#endif /* _PPC_AUXV_H */

14
software/gcc/gcc/config/rs6000/readme.md
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# GCC

## Links

* https://gcc.gnu.org/onlinedocs/gccint/Machine-Desc.html#Machine-Desc

* https://gcc.gnu.org/onlinedocs/gccint/Back-End.html

* https://www.cse.iitb.ac.in/grc/slides/cgotut-gcc/topic5-md-intro.pdf

##

* gcc/gcc/config/rs6000/ has all the Power stuff up to P10

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280
software/gcc/gcc/config/rs6000/rs6000-cpus.def
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/* IBM RS/6000 CPU names..
Copyright (C) 1991-2021 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.

GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */

/* ISA masks. */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS OPTION_MASK_MFCRF
#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)

/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
as optional. Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
| OPTION_MASK_CMPB \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
altivec is a win so enable it. */
#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)

/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
fusion here, instead set it in rs6000.c if we are tuning for a power8
system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC)

/* ISA masks setting fusion options. */
#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_FUSION_SIGN)

/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR) \
& ~OTHER_FUSION_MASKS)

/* Support for the IEEE 128-bit floating point hardware requires a lot of the
VSX instructions that are part of ISA 3.0. */
#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR)

/* Flags that need to be turned off if -mno-power10. */
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
performance was degraded by it. */
#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
| OPTION_MASK_PCREL \
/* | OPTION_MASK_PCREL_OPT */ \
| OPTION_MASK_PREFIXED)

#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
| OPTION_MASK_P10_FUSION_2STORE)

/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_P9_MINMAX)

/* Flags that need to be turned off if -mno-power8-vector. */
#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_CRYPTO)

/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_P8_VECTOR)

/* Flags that need to be turned off if -mno-altivec. */
#define OTHER_ALTIVEC_MASKS (OTHER_VSX_VECTOR_MASKS \
| OPTION_MASK_VSX)

#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align. */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_DLMZB \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
| OPTION_MASK_POWER10 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
| OPTION_MASK_P10_FUSION_2STORE \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
| OPTION_MASK_POPCNTB \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_POWERPC64 \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_PREFIXED \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_VSX)

#endif

/* This table occasionally claims that a processor does not support a
particular feature even though it does, but the feature is slower than the
alternative. Thus, it shouldn't be relied on as a complete description of
the processor's support.

Please keep this list in order, and don't forget to update the documentation
in invoke.texi when adding a new processor or flag.

Before including this file, define a macro:

RS6000_CPU (NAME, CPU, FLAGS)

where the arguments are the fields of struct rs6000_ptt. */

RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
| MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
| MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
| MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
//wtf - what about le, tar, etc.? PPC_FEATURE2_HAS_TAR - where do you use that???
RS6000_CPU ("a2p", PROCESSOR_PPCA2P,
OPTION_MASK_CMPB \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MULHW \
| OPTION_MASK_PCREL \
| OPTION_MASK_POPCNTB \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_SOFT_FLOAT \
)

156
software/gcc/gcc/config/rs6000/rs6000-opts.h
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/* Definitions of target machine needed for option handling for GNU compiler,
for IBM RS/6000.
Copyright (C) 2010-2021 Free Software Foundation, Inc.
Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.

GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.

Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.

You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */

#ifndef RS6000_OPTS_H
#define RS6000_OPTS_H

/* Processor type. Order must match cpu attribute in MD file. */
enum processor_type
{
PROCESSOR_PPC601,
PROCESSOR_PPC603,
PROCESSOR_PPC604,
PROCESSOR_PPC604e,
PROCESSOR_PPC620,
PROCESSOR_PPC630,

PROCESSOR_PPC750,
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,

PROCESSOR_PPC403,
PROCESSOR_PPC405,
PROCESSOR_PPC440,
PROCESSOR_PPC476,

PROCESSOR_PPC8540,
PROCESSOR_PPC8548,
PROCESSOR_PPCE300C2,
PROCESSOR_PPCE300C3,
PROCESSOR_PPCE500MC,
PROCESSOR_PPCE500MC64,
PROCESSOR_PPCE5500,
PROCESSOR_PPCE6500,

PROCESSOR_POWER4,
PROCESSOR_POWER5,
PROCESSOR_POWER6,
PROCESSOR_POWER7,
PROCESSOR_POWER8,
PROCESSOR_POWER9,
PROCESSOR_POWER10,

PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
PROCESSOR_PPCA2,
PROCESSOR_PPCA2P,
PROCESSOR_TITAN
};


/* Types of costly dependences. */
enum rs6000_dependence_cost
{
max_dep_latency = 1000,
no_dep_costly,
all_deps_costly,
true_store_to_load_dep_costly,
store_to_load_dep_costly
};

/* Types of nop insertion schemes in sched target hook sched_finish. */
enum rs6000_nop_insertion
{
sched_finish_regroup_exact = 1000,
sched_finish_pad_groups,
sched_finish_none
};

/* Dispatch group termination caused by an insn. */
enum group_termination
{
current_group,
previous_group
};

/* Enumeration to give which calling sequence to use. */
enum rs6000_abi {
ABI_NONE,
ABI_AIX, /* IBM's AIX, or Linux ELFv1 */
ABI_ELFv2, /* Linux ELFv2 ABI */
ABI_V4, /* System V.4/eabi */
ABI_DARWIN /* Apple's Darwin (OS X kernel) */
};

/* Small data support types. */
enum rs6000_sdata_type {
SDATA_NONE, /* No small data support. */
SDATA_DATA, /* Just put data in .sbss/.sdata, don't use relocs. */
SDATA_SYSV, /* Use r13 to point to .sdata/.sbss. */
SDATA_EABI /* Use r13 like above, r2 points to .sdata2/.sbss2. */
};

/* Type of traceback to use. */
enum rs6000_traceback_type {
traceback_default = 0,
traceback_none,
traceback_part,
traceback_full
};

/* Code model for 64-bit linux.
small: 16-bit toc offsets.
medium: 32-bit toc offsets, static data and code within 2G of TOC pointer.
large: 32-bit toc offsets, no limit on static data and code. */
enum rs6000_cmodel {
CMODEL_SMALL,
CMODEL_MEDIUM,
CMODEL_LARGE
};

/* Describe which vector unit to use for a given machine mode. The
VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and
P8_VECTOR are contiguous. */
enum rs6000_vector {
VECTOR_NONE, /* Type is not a vector or not supported */
VECTOR_ALTIVEC, /* Use altivec for vector processing */
VECTOR_VSX, /* Use VSX for vector processing */
VECTOR_P8_VECTOR /* Use ISA 2.07 VSX for vector processing */
};

/* Where to get the canary for the stack protector. */
enum stack_protector_guard {
SSP_TLS, /* per-thread canary in TLS block */
SSP_GLOBAL /* global canary */
};

/* No enumeration is defined to index the -mcpu= values (entries in
processor_target_table), with the type int being used instead, but
we need to distinguish the special "native" value. */
#define RS6000_CPU_OPTION_NATIVE -1

#endif

28617
software/gcc/gcc/config/rs6000/rs6000.c
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