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# A2 Interfaces to WB
* core interfaces
* A2I/A2O A2L2 bus
* Single (combined I/D) w/SMP extensions
* Dual (separate I/D) WB buses w/SMP extensions
3 years ago
* bus interfaces
3 years ago
* single WB
3 years ago
* dual WB
3 years ago
* functions
* queues one or more core commands
* point of coherncy for larx/stcx, sync, tlbie, etc. for multicores below it (single/mulithread)
* address compares necessary for ordering/coherency
* optional mailbox interface for core-core peer and broadcast
3 years ago
* arbitrates for WB bus(es)
* gen responses for cores
## Possible configurations
* one core, WB: pass-through with SMP functions
* one core, A2L2: bridge with SMP functions
3 years ago
* multi-core: identical or mixed WB1/WB2/A2L2, queueing, arbitration, and SMP functions
3 years ago
### syntax check
3 years ago
```verilator --lint-only a2wb.v -Wno-LITENDIAN```