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25 lines
760 B
Plaintext
25 lines
760 B
Plaintext
3 years ago
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set clk_name clk
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# make it easy
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set clk_period 50.0
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set input_delay_value 1
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set output_delay_value 1
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# define clock
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set clkPort [get_ports $clk_name]
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create_clock $clkPort -name clk -period $clk_period
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# apply clock to ins and outs
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set clk_index [lsearch [all_inputs] $clkPort]
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set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
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set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
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set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]
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# false paths
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set_false_path -from [get_ports {reset}] -to [get_clocks clk]
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#wtf - is this the dc write path?
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set_false_path -from [get_nets {dBusWB_ACK}]
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set_false_path -from [get_nets {a2p_wb/dbuswb_ack}]
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set_false_path -from [get_nets {a2p_wb/dbuswb*}]
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