Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :)
Namespace(build=True, bus_address_width=32, bus_data_width=32, bus_standard='wishbone', bus_timeout=1000000.0, cpu_cfu=None, cpu_reset_address=None, cpu_type=None, cpu_variant=None, csr_address_width=14, csr_csv='csr.csv', csr_data_width=None, csr_json=None, csr_ordering='big', csr_paging=2048, csr_svd=None, doc=False, gateware_dir=None, generated_dir=None, ident=None, ident_version=None, include_dir=None, integrated_main_ram_size=None, integrated_rom_init=None, integrated_rom_size=131072, integrated_sram_size=8192, l2_size=8192, load=False, memory_x=None, no_compile_gateware=False, no_compile_software=True, no_ctrl=False, no_timer=False, no_uart=False, output_dir=None, software_dir=None, sys_clk_freq=100000000.0, timer_uptime=False, uart_baudrate=None, uart_fifo_depth=16, uart_name='serial', with_analyzer=False)
directory0
csr_08000

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source cmod7.tcl
# create_project -force -name cmod7 -part xc7a35t-CPG236-1
# set_msg_config -id {Common 17-55} -new_severity {Warning}
# read_verilog {/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v}
# read_verilog {/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v}
# read_verilog {/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v}
# read_xdc cmod7.xdc
# set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc]
# synth_design -directive default -top cmod7 -part xc7a35t-CPG236-1
Command: synth_design -directive default -top cmod7 -part xc7a35t-CPG236-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 558463
WARNING: [Synth 8-2292] literal value truncated to fit in 1 bits [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:278]
WARNING: [Synth 8-2292] literal value truncated to fit in 1 bits [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2336]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 342 ; free virtual = 10273
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'cmod7' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:20]
INFO: [Synth 8-3876] $readmem data file 'mem.init' is read successfully [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2403]
INFO: [Synth 8-3876] $readmem data file 'mem_1.init' is read successfully [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2480]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1942]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2032]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2077]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2086]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2109]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2121]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2133]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2150]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2162]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2217]
INFO: [Synth 8-155] case statement is not full and has no default [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2259]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:1083]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2469]
INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060]
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (2#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060]
WARNING: [Synth 8-7071] port 'RDY' of module 'IDELAYCTRL' is unconnected for instance 'IDELAYCTRL' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2469]
WARNING: [Synth 8-7023] instance 'IDELAYCTRL' of module 'IDELAYCTRL' has 3 connections declared, but only 2 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2469]
INFO: [Synth 8-6157] synthesizing module 'issiram' [/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v:41]
	Parameter WB_BITWIDTH bound to: 32 - type: integer 
	Parameter RAM_BITWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'issiram' (3#1) [/home/wtf/projects/a2p-opf/build/litex/modules/issiram.v:41]
INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:11984]
	Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 
INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (4#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:11984]
INFO: [Synth 8-6157] synthesizing module 'XADC' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:82182]
	Parameter INIT_40 bound to: 16'b1001000000000000 
	Parameter INIT_41 bound to: 16'b0010111011110000 
	Parameter INIT_42 bound to: 16'b0000010000000000 
	Parameter INIT_43 bound to: 16'b0000000000000000 
	Parameter INIT_44 bound to: 16'b0000000000000000 
	Parameter INIT_45 bound to: 16'b0000000000000000 
	Parameter INIT_46 bound to: 16'b0000000000000000 
	Parameter INIT_47 bound to: 16'b0000000000000000 
	Parameter INIT_48 bound to: 16'b0100011100000001 
	Parameter INIT_49 bound to: 16'b0000000000001111 
	Parameter INIT_4A bound to: 16'b0100011100000000 
	Parameter INIT_4B bound to: 16'b0000000000000000 
	Parameter INIT_4C bound to: 16'b0000000000000000 
	Parameter INIT_4D bound to: 16'b0000000000000000 
	Parameter INIT_4E bound to: 16'b0000000000000000 
	Parameter INIT_4F bound to: 16'b0000000000000000 
	Parameter INIT_50 bound to: 16'b1011010111101101 
	Parameter INIT_51 bound to: 16'b0101100110011001 
	Parameter INIT_52 bound to: 16'b1010000101000111 
	Parameter INIT_53 bound to: 16'b1101110111011101 
	Parameter INIT_54 bound to: 16'b1010100100111010 
	Parameter INIT_55 bound to: 16'b0101000100010001 
	Parameter INIT_56 bound to: 16'b1001000111101011 
	Parameter INIT_57 bound to: 16'b1010111001001110 
	Parameter INIT_58 bound to: 16'b0101100110011001 
	Parameter INIT_59 bound to: 16'b0000000000000000 
	Parameter INIT_5A bound to: 16'b0000000000000000 
	Parameter INIT_5B bound to: 16'b0000000000000000 
	Parameter INIT_5C bound to: 16'b0101000100010001 
	Parameter INIT_5D bound to: 16'b0000000000000000 
	Parameter INIT_5E bound to: 16'b0000000000000000 
	Parameter INIT_5F bound to: 16'b0000000000000000 
	Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 
	Parameter IS_DCLK_INVERTED bound to: 1'b0 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SIM_MONITOR_FILE bound to: design.txt - type: string 
INFO: [Synth 8-6155] done synthesizing module 'XADC' (5#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:82182]
WARNING: [Synth 8-689] width (7) of port connection 'CHANNEL' does not match port width (5) of module 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2552]
WARNING: [Synth 8-7071] port 'JTAGBUSY' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537]
WARNING: [Synth 8-7071] port 'JTAGLOCKED' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537]
WARNING: [Synth 8-7071] port 'JTAGMODIFIED' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537]
WARNING: [Synth 8-7071] port 'MUXADDR' of module 'XADC' is unconnected for instance 'XADC' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537]
WARNING: [Synth 8-7023] instance 'XADC' of module 'XADC' has 24 connections declared, but only 20 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2537]
INFO: [Synth 8-6157] synthesizing module 'A2P_WB' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:1183]
INFO: [Synth 8-6157] synthesizing module 'InstructionCache' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:164]
INFO: [Synth 8-6155] done synthesizing module 'InstructionCache' (6#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:164]
INFO: [Synth 8-6157] synthesizing module 'DataCache' [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:465]
INFO: [Synth 8-6155] done synthesizing module 'DataCache' (7#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:465]
INFO: [Synth 8-6155] done synthesizing module 'A2P_WB' (8#1) [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:1183]
INFO: [Synth 8-6157] synthesizing module 'FD' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13483]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'FD' (9#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13483]
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 50.000000 - type: double 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKIN1_PERIOD bound to: 83.333333 - type: double 
	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double 
	Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: double 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT2_DIVIDE bound to: 3 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
	Parameter COMPENSATION bound to: ZHOLD - type: string 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
	Parameter IS_PSEN_INVERTED bound to: 1'b0 
	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
	Parameter IS_RST_INVERTED bound to: 1'b0 
	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
	Parameter REF_JITTER2 bound to: 0.010000 - type: double 
	Parameter SS_EN bound to: FALSE - type: string 
	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
	Parameter STARTUP_WAIT bound to: FALSE - type: string 
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (10#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:39998]
WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DO' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DRDY' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'PSDONE' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKIN2' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'CLKINSEL' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DADDR' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DCLK' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DEN' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DI' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'DWE' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'PSCLK' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'PSEN' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7071] port 'PSINCDEC' of module 'MMCME2_ADV' is unconnected for instance 'MMCME2_ADV' [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
WARNING: [Synth 8-7023] instance 'MMCME2_ADV' of module 'MMCME2_ADV' has 33 connections declared, but only 9 given [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2657]
INFO: [Synth 8-6157] synthesizing module 'FDPE' [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13664]
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_PRE_INVERTED bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'FDPE' (11#1) [/tools/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13664]
INFO: [Synth 8-6155] done synthesizing module 'cmod7' (12#1) [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:20]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1055 ; free virtual = 10988
---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1070 ; free virtual = 11003
---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1070 ; free virtual = 11003
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2298.785 ; gain = 0.000 ; free physical = 1054 ; free virtual = 10987
INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]
WARNING: [Vivado 12-507] No nets matched 'clk12'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:211]
CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_nets clk12]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:211]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets sys_clk]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets crg_clkin]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets sys_clk]]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_nets crg_clkin]]'. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
CRITICAL WARNING: [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Finished Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/cmod7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/cmod7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2406.531 ; gain = 0.000 ; free physical = 955 ; free virtual = 10888
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 8 instances were transformed.
  FD => FDRE: 8 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2406.531 ; gain = 0.000 ; free physical = 955 ; free virtual = 10888
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1054 ; free virtual = 10987
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1054 ; free virtual = 10987
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1054 ; free virtual = 10987
---------------------------------------------------------------------------------
INFO: [Synth 8-3971] The signal "A2P_WB:/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2406.531 ; gain = 107.746 ; free physical = 1033 ; free virtual = 10969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   64 Bit       Adders := 1     
	   3 Input   52 Bit       Adders := 1     
	   3 Input   33 Bit       Adders := 2     
	   2 Input   33 Bit       Adders := 5     
	   2 Input   32 Bit       Adders := 11    
	   2 Input   10 Bit       Adders := 1     
	   2 Input    8 Bit       Adders := 3     
	   2 Input    7 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 2     
	  31 Input    6 Bit       Adders := 1     
	   2 Input    5 Bit       Adders := 2     
	   7 Input    4 Bit       Adders := 4     
	   2 Input    4 Bit       Adders := 11    
	   2 Input    3 Bit       Adders := 5     
	   2 Input    2 Bit       Adders := 6     
	   4 Input    2 Bit       Adders := 2     
	  16 Input    1 Bit       Adders := 2     
	   8 Input    1 Bit       Adders := 1     
	  12 Input    1 Bit       Adders := 2     
	  13 Input    1 Bit       Adders := 1     
	  15 Input    1 Bit       Adders := 1     
	  19 Input    1 Bit       Adders := 1     
	   3 Input    1 Bit       Adders := 1     
	   4 Input    1 Bit       Adders := 1     
	  11 Input    1 Bit       Adders := 1     
	   2 Input    1 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 6     
	   4 Input      1 Bit         XORs := 1     
+---Registers : 
	               65 Bit    Registers := 1     
	               57 Bit    Registers := 1     
	               54 Bit    Registers := 1     
	               52 Bit    Registers := 1     
	               34 Bit    Registers := 1     
	               33 Bit    Registers := 1     
	               32 Bit    Registers := 76    
	               22 Bit    Registers := 2     
	               20 Bit    Registers := 2     
	               19 Bit    Registers := 1     
	               12 Bit    Registers := 4     
	               11 Bit    Registers := 2     
	               10 Bit    Registers := 1     
	                8 Bit    Registers := 19    
	                7 Bit    Registers := 1     
	                6 Bit    Registers := 2     
	                5 Bit    Registers := 21    
	                4 Bit    Registers := 18    
	                3 Bit    Registers := 14    
	                2 Bit    Registers := 28    
	                1 Bit    Registers := 213   
+---RAMs : 
	              54K Bit	(1024 X 54 bit)          RAMs := 1     
	              32K Bit	(1024 X 32 bit)          RAMs := 1     
	               8K Bit	(1024 X 8 bit)          RAMs := 4     
	               2K Bit	(128 X 22 bit)          RAMs := 2     
	             1024 Bit	(32 X 32 bit)          RAMs := 1     
	              160 Bit	(16 X 10 bit)          RAMs := 2     
+---ROMs : 
	                    ROMs := 1     
+---Muxes : 
	   2 Input   33 Bit        Muxes := 3     
	   2 Input   32 Bit        Muxes := 144   
	   3 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 7     
	   8 Input   32 Bit        Muxes := 5     
	  20 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 2     
	   7 Input   32 Bit        Muxes := 2     
	   2 Input   31 Bit        Muxes := 1     
	   2 Input   30 Bit        Muxes := 2     
	   2 Input   26 Bit        Muxes := 3     
	   2 Input   20 Bit        Muxes := 1     
	   2 Input   19 Bit        Muxes := 1     
	   2 Input   16 Bit        Muxes := 5     
	   2 Input   14 Bit        Muxes := 2     
	  18 Input   12 Bit        Muxes := 1     
	   2 Input   12 Bit        Muxes := 1     
	   2 Input   11 Bit        Muxes := 3     
	   3 Input   11 Bit        Muxes := 1     
	   2 Input   10 Bit        Muxes := 4     
	   4 Input    8 Bit        Muxes := 2     
	   2 Input    8 Bit        Muxes := 23    
	   3 Input    8 Bit        Muxes := 5     
	   7 Input    8 Bit        Muxes := 3     
	   5 Input    8 Bit        Muxes := 2     
	  25 Input    8 Bit        Muxes := 1     
	   2 Input    7 Bit        Muxes := 9     
	   2 Input    6 Bit        Muxes := 6     
	   7 Input    5 Bit        Muxes := 1     
	   2 Input    5 Bit        Muxes := 15    
	   3 Input    5 Bit        Muxes := 1     
	   8 Input    5 Bit        Muxes := 1     
	   6 Input    5 Bit        Muxes := 1     
	   4 Input    5 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 23    
	   8 Input    4 Bit        Muxes := 9     
	   3 Input    4 Bit        Muxes := 1     
	   3 Input    3 Bit        Muxes := 2     
	   2 Input    3 Bit        Muxes := 6     
	  20 Input    3 Bit        Muxes := 1     
	   8 Input    3 Bit        Muxes := 1     
	  10 Input    3 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 10    
	   4 Input    2 Bit        Muxes := 2     
	   7 Input    2 Bit        Muxes := 1     
	   6 Input    2 Bit        Muxes := 1     
	   2 Input    1 Bit        Muxes := 298   
	   5 Input    1 Bit        Muxes := 9     
	   8 Input    1 Bit        Muxes := 4     
	   7 Input    1 Bit        Muxes := 14    
	  20 Input    1 Bit        Muxes := 2     
	  32 Input    1 Bit        Muxes := 1     
	   6 Input    1 Bit        Muxes := 6     
	   4 Input    1 Bit        Muxes := 10    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
DSP Report: Generating DSP memory_to_writeBack_MUL_HH_reg, operation Mode is: (A*B)'.
DSP Report: register memory_to_writeBack_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
DSP Report: register execute_to_memory_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
DSP Report: operator execute_MUL_HH is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
DSP Report: Generating DSP execute_to_memory_MUL_LH_reg, operation Mode is: (A*B)'.
DSP Report: register execute_to_memory_MUL_LH_reg is absorbed into DSP execute_to_memory_MUL_LH_reg.
DSP Report: operator execute_MUL_LH is absorbed into DSP execute_to_memory_MUL_LH_reg.
DSP Report: Generating DSP execute_to_memory_MUL_HL_reg, operation Mode is: (A*B)'.
DSP Report: register execute_to_memory_MUL_HL_reg is absorbed into DSP execute_to_memory_MUL_HL_reg.
DSP Report: operator execute_MUL_HL is absorbed into DSP execute_to_memory_MUL_HL_reg.
DSP Report: Generating DSP execute_to_memory_MUL_LL_reg, operation Mode is: (A*B)'.
DSP Report: register execute_to_memory_MUL_LL_reg is absorbed into DSP execute_to_memory_MUL_LL_reg.
DSP Report: operator execute_MUL_LL is absorbed into DSP execute_to_memory_MUL_LL_reg.
INFO: [Synth 8-3971] The signal "A2P_WB/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:23 ; elapsed = 00:01:25 . Memory (MB): peak = 2443.516 ; gain = 144.730 ; free physical = 996 ; free virtual = 10945
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

ROM: Preliminary Mapping	Report
+------------+----------------+---------------+----------------+
|Module Name | RTL Object     | Depth x Width | Implemented As | 
+------------+----------------+---------------+----------------+
|cmod7       | mem_1_dat0_reg | 16384x32      | Block RAM      | 
+------------+----------------+---------------+----------------+


Block RAM: Preliminary Mapping	Report (see note below)
+------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name                   | RTL Object                             | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|A2P_WB/IBusCachedPlugin_cache | ways_0_datas_reg                       | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
|A2P_WB/IBusCachedPlugin_cache | ways_0_tags_reg                        | 128 x 22(READ_FIRST)   | W |   | 128 x 22(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_tags_reg                        | 128 x 22(READ_FIRST)   | W |   | 128 x 22(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol0_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol1_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol2_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol3_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB                        | IBusCachedPlugin_predictor_history_reg | 1 K x 54(READ_FIRST)   | W |   | 1 K x 54(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 

Distributed RAM: Preliminary Mapping	Report (see note below)
+------------+---------------+-----------+----------------------+-------------+
|Module Name | RTL Object    | Inference | Size (Depth x Width) | Primitives  | 
+------------+---------------+-----------+----------------------+-------------+
|cmod7       | storage_1_reg | Implied   | 16 x 8               | RAM32M x 2	 | 
|cmod7       | storage_reg   | Implied   | 16 x 8               | RAM32M x 2	 | 
+------------+---------------+-----------+----------------------+-------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping	Report (see note below)
+------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|A2P_WB      | (A*B)'      | 17     | 17     | -      | -      | 34     | 0    | 0    | -    | -    | -     | 1    | 1    | 
|A2P_WB      | (A*B)'      | 17     | 17     | -      | -      | 34     | 0    | 0    | -    | -    | -     | 1    | 0    | 
|A2P_WB      | (A*B)'      | 17     | 17     | -      | -      | 34     | 0    | 0    | -    | -    | -     | 1    | 0    | 
|A2P_WB      | (A*B)'      | 16     | 16     | -      | -      | 32     | 0    | 0    | -    | -    | -     | 1    | 0    | 
+------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:31 ; elapsed = 00:01:33 . Memory (MB): peak = 2443.516 ; gain = 144.730 ; free physical = 732 ; free virtual = 10701
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 2443.516 ; gain = 144.730 ; free physical = 788 ; free virtual = 10756
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Final Mapping	Report
+------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name                   | RTL Object                             | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|A2P_WB/IBusCachedPlugin_cache | ways_0_datas_reg                       | 1 K x 32(READ_FIRST)   | W |   | 1 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
|A2P_WB/IBusCachedPlugin_cache | ways_0_tags_reg                        | 128 x 22(READ_FIRST)   | W |   | 128 x 22(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_tags_reg                        | 128 x 22(READ_FIRST)   | W |   | 128 x 22(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol0_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol1_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol2_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB/dataCache_1_           | DC_DIR_data_symbol3_reg                | 1 K x 8(READ_FIRST)    | W |   | 1 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 1      | 0      | 
|A2P_WB                        | IBusCachedPlugin_predictor_history_reg | 1 K x 54(READ_FIRST)   | W |   | 1 K x 54(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+------------------------------+----------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+


Distributed RAM: Final Mapping	Report
+------------+---------------+-----------+----------------------+-------------+
|Module Name | RTL Object    | Inference | Size (Depth x Width) | Primitives  | 
+------------+---------------+-----------+----------------------+-------------+
|cmod7       | storage_1_reg | Implied   | 16 x 8               | RAM32M x 2	 | 
|cmod7       | storage_reg   | Implied   | 16 x 8               | RAM32M x 2	 | 
+------------+---------------+-----------+----------------------+-------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance A2P_WB/dataCache_1_/DC_DIR_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance A2P_WB/RegFilePlugin_regFile_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_10 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_11 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_12 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_13 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_14 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance mem_1_dat0_reg_15 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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Finished Technology Mapping : Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 736 ; free virtual = 10727
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13035]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8058]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:8733]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:1844]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2018]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2006]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2003]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.v:2009]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/wtf/projects/a2p-opf/build/litex/a2p/verilog/A2P_WB.v:13651]
INFO: [Common 17-14] Message 'Synth 8-5396' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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Finished IO Insertion : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 726 ; free virtual = 10702
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 726 ; free virtual = 10702
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 725 ; free virtual = 10701
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 724 ; free virtual = 10701
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 720 ; free virtual = 10697
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 721 ; free virtual = 10698
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Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-----------+------+
|      |Cell       |Count |
+------+-----------+------+
|1     |BUFG       |     4|
|2     |CARRY4     |   255|
|3     |DNA_PORT   |     1|
|4     |DSP48E1    |     4|
|6     |IDELAYCTRL |     1|
|7     |LUT1       |   304|
|8     |LUT2       |   348|
|9     |LUT3       |   882|
|10    |LUT4       |   855|
|11    |LUT5       |   962|
|12    |LUT6       |  2468|
|13    |MMCME2_ADV |     1|
|14    |MUXF7      |    35|
|15    |RAM32M     |     4|
|16    |RAMB18E1   |    10|
|19    |RAMB36E1   |    18|
|37    |XADC       |     1|
|38    |FD         |     8|
|39    |FDCE       |   283|
|40    |FDPE       |     7|
|41    |FDRE       |  2513|
|42    |FDSE       |    93|
|43    |IBUF       |     5|
|44    |IOBUF      |     9|
|45    |OBUF       |    27|
|46    |OBUFT      |     1|
+------+-----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.523 ; gain = 197.738 ; free physical = 722 ; free virtual = 10698
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2939 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:36 ; elapsed = 00:01:39 . Memory (MB): peak = 2496.523 ; gain = 89.992 ; free physical = 781 ; free virtual = 10757
Synthesis Optimization Complete : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2496.531 ; gain = 197.738 ; free physical = 781 ; free virtual = 10757
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2496.531 ; gain = 0.000 ; free physical = 866 ; free virtual = 10842
INFO: [Netlist 29-17] Analyzing 345 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
INFO: [Timing 38-2] Deriving generated clocks [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
WARNING: [Vivado 12-3521] Clock specified in more than one group: crg_clkout0 [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc:213]
Finished Parsing XDC File [/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2840.547 ; gain = 0.000 ; free physical = 555 ; free virtual = 10522
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 21 instances were transformed.
  FD => FDRE: 8 instances
  IOBUF => IOBUF (IBUF, OBUFT): 9 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 4 instances

INFO: [Common 17-83] Releasing license: Synthesis
82 Infos, 140 Warnings, 6 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:55 ; elapsed = 00:01:52 . Memory (MB): peak = 2840.547 ; gain = 541.859 ; free physical = 726 ; free virtual = 10693
# report_timing_summary -file cmod7_timing_synth.rpt
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt
# report_utilization -file cmod7_utilization_synth.rpt
# opt_design -directive default
Command: opt_design -directive default
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port pmod0 expects both input and output buffering but the buffers are incomplete.
INFO: [Project 1-461] DRC finished with 0 Errors, 1 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2911.605 ; gain = 64.031 ; free physical = 695 ; free virtual = 10660

Starting Cache Timing Information Task
Ending Cache Timing Information Task | Checksum: 16ae10926

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 695 ; free virtual = 10660

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: f3d65e6d

Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 597 ; free virtual = 10562
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 55 cells
INFO: [Opt 31-1021] In phase Retarget, 6 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 153537fc4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 599 ; free virtual = 10562
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 1 cells
INFO: [Opt 31-1021] In phase Constant propagation, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Sweep
Phase 3 Sweep | Checksum: cd080f35

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 19 cells
INFO: [Opt 31-1021] In phase Sweep, 20 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: cd080f35

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.92 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
INFO: [Opt 31-1021] In phase BUFG optimization, 3 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: cd080f35

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: cd080f35

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.99 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |              55  |                                              6  |
|  Constant propagation         |               0  |               1  |                                              2  |
|  Sweep                        |               0  |              19  |                                             20  |
|  BUFG optimization            |               0  |               0  |                                              3  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              1  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562
Ending Logic Optimization Task | Checksum: f008ea69

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2911.605 ; gain = 0.000 ; free physical = 603 ; free virtual = 10562

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for DNA_PORT
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 28 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 1 newly gated: 1 Total Ports: 56
Ending PowerOpt Patch Enables Task | Checksum: a01ec7fc

Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 728 ; free virtual = 10687
Ending Power Optimization Task | Checksum: a01ec7fc

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3172.551 ; gain = 260.945 ; free physical = 736 ; free virtual = 10694

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: a01ec7fc

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 736 ; free virtual = 10694

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 735 ; free virtual = 10694
Ending Netlist Obfuscation Task | Checksum: e791bb43

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 735 ; free virtual = 10694
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3172.551 ; gain = 324.977 ; free physical = 734 ; free virtual = 10693
# place_design -directive default
Command: place_design -directive default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[5] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[0]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[6] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[1]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[7] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[2]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port pmod0 expects both input and output buffering but the buffers are incomplete.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 43 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'default' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 87f2f39c

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
WARNING: [Place 30-568] A LUT 'clk12_inst' is driving clock pin of 8 registers. This could lead to large hold time violations. First few involved registers are:
	FD_4 {FDRE}
	FD {FDRE}
	FD_2 {FDRE}
	FD_1 {FDRE}
	FD_3 {FDRE}
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ba0c756b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.72 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 743 ; free virtual = 10702

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 29b4df3bb

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 739 ; free virtual = 10699

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 29b4df3bb

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 739 ; free virtual = 10699
Phase 1 Placer Initialization | Checksum: 29b4df3bb

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 739 ; free virtual = 10699

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 25d7745f4

Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 732 ; free virtual = 10691

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fb083423

Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 732 ; free virtual = 10691

Phase 2.3 Global Placement Core

Phase 2.3.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 122 LUTNM shape to break, 192 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 87, two critical 35, total 122, new lutff created 1
INFO: [Physopt 32-775] End 1 Pass. Optimized 187 nets or cells. Created 122 new cells, deleted 65 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/decodeStage_mmuRsp_physicalAddress_reg[31][6] could not be optimized because driver A2P_WB/dataCache_1_/ways_0_datas_reg_i_6 could not be replicated
INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/lastStageRegFileWrite_payload_data[20] could not be optimized because driver A2P_WB/dataCache_1_/RegFilePlugin_regFile_reg_1_i_38 could not be replicated
INFO: [Physopt 32-117] Net A2P_WB/dataCache_1_/lastStageRegFileWrite_payload_data[30] could not be optimized because driver A2P_WB/dataCache_1_/RegFilePlugin_regFile_reg_1_i_28 could not be replicated
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-527] Pass 1: Identified 3 candidate cells for BRAM register optimization
INFO: [Physopt 32-666] Processed cell A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg. No change.
INFO: [Physopt 32-665] Processed cell A2P_WB/dataCache_1_/DC_DIR_data_symbol1_reg. 8 registers were pushed out.
INFO: [Physopt 32-665] Processed cell A2P_WB/dataCache_1_/DC_DIR_data_symbol3_reg. 8 registers were pushed out.
INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 16 new cells, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 714 ; free virtual = 10673
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 714 ; free virtual = 10674

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |          122  |             65  |                   187  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Fanout                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Cell                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |           16  |              0  |                     2  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |          138  |             65  |                   189  |           0  |          10  |  00:00:01  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1a341b5d2

Time (s): cpu = 00:00:23 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 715 ; free virtual = 10674
Phase 2.3 Global Placement Core | Checksum: 1aa8e06dd

Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 714 ; free virtual = 10673
Phase 2 Global Placement | Checksum: 1aa8e06dd

Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 719 ; free virtual = 10678

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1f20bb7a9

Time (s): cpu = 00:00:25 ; elapsed = 00:00:11 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 719 ; free virtual = 10678

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ece0d326

Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10677

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2065d7a66

Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10676

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2991add41

Time (s): cpu = 00:00:28 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10676

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 2a8da495d

Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 716 ; free virtual = 10675

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 20e8bd739

Time (s): cpu = 00:00:35 ; elapsed = 00:00:16 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 715 ; free virtual = 10673

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1d656ef4e

Time (s): cpu = 00:00:35 ; elapsed = 00:00:17 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 716 ; free virtual = 10674

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 108f68281

Time (s): cpu = 00:00:35 ; elapsed = 00:00:17 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 716 ; free virtual = 10674

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 137b6925a

Time (s): cpu = 00:00:43 ; elapsed = 00:00:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 712 ; free virtual = 10671
Phase 3 Detail Placement | Checksum: 137b6925a

Time (s): cpu = 00:00:43 ; elapsed = 00:00:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 712 ; free virtual = 10671

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: ffb54392

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.486 | TNS=-10.492 |
Phase 1 Physical Synthesis Initialization | Checksum: 12be2a25c

Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 709 ; free virtual = 10667
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: b80880be

Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10665
Phase 4.1.1.1 BUFG Insertion | Checksum: ffb54392

Time (s): cpu = 00:00:48 ; elapsed = 00:00:23 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10665
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.503. For the most accurate timing information please run report_timing.

Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666
Phase 4.1 Post Commit Optimization | Checksum: e5c2f70b

Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: e5c2f70b

Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 707 ; free virtual = 10666

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                4x4|
|___________|___________________|___________________|
|      South|                1x1|                2x2|
|___________|___________________|___________________|
|       East|                1x1|                4x4|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: e5c2f70b

Time (s): cpu = 00:00:54 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665
Phase 4.3 Placer Reporting | Checksum: e5c2f70b

Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665

Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 706 ; free virtual = 10665
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 16e2ac428

Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 705 ; free virtual = 10664
Ending Placer Task | Checksum: 14f2dee0a

Time (s): cpu = 00:00:55 ; elapsed = 00:00:28 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 705 ; free virtual = 10664
INFO: [Common 17-83] Releasing license: Implementation
47 Infos, 44 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:01 ; elapsed = 00:00:30 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 720 ; free virtual = 10679
# report_utilization -hierarchical -file cmod7_utilization_hierarchical_place.rpt
# report_utilization -file cmod7_utilization_place.rpt
# report_io -file cmod7_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 713 ; free virtual = 10672
# report_control_sets -verbose -file cmod7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 718 ; free virtual = 10677
# report_clock_utilization -file cmod7_clock_utilization.rpt
# route_design -directive default
Command: route_design -directive default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'default'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Checksum: PlaceDB: 7c90c02d ConstDB: 0 ShapeSum: d29d2ddd RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: b88298ea

Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 587 ; free virtual = 10553
Post Restoration Checksum: NetGraph: adea1a45 NumContArr: a987ea5 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: b88298ea

Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 589 ; free virtual = 10556

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: b88298ea

Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 558 ; free virtual = 10525

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: b88298ea

Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 558 ; free virtual = 10524
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 203a8934b

Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 566 ; free virtual = 10529
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.660  | TNS=0.000  | WHS=-0.215 | THS=-46.957|

Phase 2 Router Initialization | Checksum: 25ab15ee4

Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 565 ; free virtual = 10528

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00191342 %
  Global Horizontal Routing Utilization  = 0.00143155 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 7823
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 7822
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0


Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 25ab15ee4

Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 564 ; free virtual = 10527
Phase 3 Initial Routing | Checksum: 8cae6c5c

Time (s): cpu = 00:00:27 ; elapsed = 00:00:14 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 562 ; free virtual = 10525

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 4313
 Number of Nodes with overlaps = 2004
 Number of Nodes with overlaps = 1086
 Number of Nodes with overlaps = 553
 Number of Nodes with overlaps = 291
 Number of Nodes with overlaps = 147
 Number of Nodes with overlaps = 49
 Number of Nodes with overlaps = 20
 Number of Nodes with overlaps = 19
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.339 | TNS=-4.313 | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1609ee9c0

Time (s): cpu = 00:02:11 ; elapsed = 00:00:43 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 565 ; free virtual = 10523

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 533
 Number of Nodes with overlaps = 386
 Number of Nodes with overlaps = 177
 Number of Nodes with overlaps = 138
 Number of Nodes with overlaps = 55
 Number of Nodes with overlaps = 32
 Number of Nodes with overlaps = 20
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.026  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 1bcfc8674

Time (s): cpu = 00:02:47 ; elapsed = 00:01:01 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 587 ; free virtual = 10545

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 390
 Number of Nodes with overlaps = 275
 Number of Nodes with overlaps = 120
 Number of Nodes with overlaps = 97
 Number of Nodes with overlaps = 57
 Number of Nodes with overlaps = 25
 Number of Nodes with overlaps = 13
 Number of Nodes with overlaps = 24
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.169  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.3 Global Iteration 2 | Checksum: 1138b2815

Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 587 ; free virtual = 10545
Phase 4 Rip-up And Reroute | Checksum: 1138b2815

Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1138b2815

Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1138b2815

Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544
Phase 5 Delay and Skew Optimization | Checksum: 1138b2815

Time (s): cpu = 00:03:20 ; elapsed = 00:01:19 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10544

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 14f05eee6

Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 586 ; free virtual = 10545
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.181  | TNS=0.000  | WHS=0.008  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 136d40aef

Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 585 ; free virtual = 10544
Phase 6 Post Hold Fix | Checksum: 136d40aef

Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 585 ; free virtual = 10544

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 4.60249 %
  Global Horizontal Routing Utilization  = 5.68961 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: f3d8b232

Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 585 ; free virtual = 10544

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: f3d8b232

Time (s): cpu = 00:03:22 ; elapsed = 00:01:20 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 584 ; free virtual = 10543

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1873629a4

Time (s): cpu = 00:03:23 ; elapsed = 00:01:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 583 ; free virtual = 10542

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.181  | TNS=0.000  | WHS=0.008  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1873629a4

Time (s): cpu = 00:03:23 ; elapsed = 00:01:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 583 ; free virtual = 10542
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:03:23 ; elapsed = 00:01:21 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 622 ; free virtual = 10581

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:03:30 ; elapsed = 00:01:23 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 622 ; free virtual = 10581
# phys_opt_design -directive default
Command: phys_opt_design -directive default
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: default
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
# write_checkpoint -force cmod7_route.dcp
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3172.551 ; gain = 0.000 ; free physical = 583 ; free virtual = 10555
INFO: [Common 17-1381] The checkpoint '/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7_route.dcp' has been generated.
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock (1)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (2)
5. checking no_input_delay (13)
6. checking no_output_delay (36)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (1)
------------------------
 There is 1 register/latch pin with no clock driven by root clock pin: dna_count_reg[0]/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (2)
------------------------------------------------
 There are 2 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (13)
-------------------------------
 There are 13 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (36)
--------------------------------
 There are 36 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.181        0.000                      0                 7495        0.007        0.000                      0                 7495        3.750        0.000                       0                  2991  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                   Waveform(ns)         Period(ns)      Frequency(MHz)
-----                   ------------         ----------      --------------
clk12                   {0.000 41.666}       83.333          12.000          
  crg_clkout0           {0.000 5.000}        10.000          100.000         
  subfragments_mmcm_fb  {0.000 41.666}       83.333          12.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                       WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                       -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk12                        81.512        0.000                      0                    7        0.160        0.000                      0                    7       16.667        0.000                       0                    10  
  crg_clkout0                 0.181        0.000                      0                 7202        0.007        0.000                      0                 7202        3.750        0.000                       0                  2979  
  subfragments_mmcm_fb                                                                                                                                                   16.667        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**  crg_clkout0        crg_clkout0              2.432        0.000                      0                  286        0.811        0.000                      0                  286  


# report_route_status -file cmod7_route_status.rpt
# report_drc -file cmod7_drc.rpt
Command: report_drc -file cmod7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/cmod7_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file cmod7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file cmod7_power.rpt
Command: report_power -file cmod7_power.rpt
INFO: [Power 33-23] Power model is not available for DNA_PORT
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force cmod7.bit 
Command: write_bitstream -force cmod7.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg input A2P_WB/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg input A2P_WB/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg input A2P_WB/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg input A2P_WB/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg input A2P_WB/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg input A2P_WB/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/memory_to_writeBack_MUL_HH_reg input A2P_WB/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP A2P_WB/memory_to_writeBack_MUL_HH_reg input A2P_WB/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_HL_reg multiplier stage A2P_WB/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_LH_reg multiplier stage A2P_WB/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP A2P_WB/execute_to_memory_MUL_LL_reg multiplier stage A2P_WB/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC PDRC-153] Gated clock check: Net crg_clkin is a gated clock net sourced by a combinational pin clk12_inst/O, cell clk12_inst. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT clk12_inst is driving clock pin of 8 cells. This could lead to large hold time violations. Involved cells are:
FD, FD_1, FD_2, FD_3, FD_4, FD_5, FD_6, and FD_7
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[5] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[0]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[6] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[1]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRARDADDR[7] (net: A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex[2]) which is driven by a register (A2P_WB/IBusCachedPlugin_cache/lineLoader_wordIndex_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_datas_reg/ADDRBWRADDR[14] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/IBusCachedPlugin_fetchPc_pcReg_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_hadException_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/SPRPlugin_pipelineLiberator_pcValids_2_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/_zz_359__reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/memory_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (A2P_WB/writeBack_arbitration_isValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg has an input control pin A2P_WB/IBusCachedPlugin_cache/ways_0_tags_reg/ADDRARDADDR[11] (net: A2P_WB/IBusCachedPlugin_cache/_zz_500_[9]) which is driven by a register (FDPE_1) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 56 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./cmod7.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/wtf/projects/a2p-opf/build/litex/build/cmod7/gateware/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Nov 11 08:23:23 2021. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
10 Infos, 56 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:16 . Memory (MB): peak = 3247.566 ; gain = 75.016 ; free physical = 557 ; free virtual = 10516
# quit
INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 08:23:23 2021...
Copying .v and .bit, and programming...



****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source pgmfpga.tcl
# open_hw_manager
# connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2020.2
  **** Build date : Nov 18 2020 at 09:50:49
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.


INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:


******** Xilinx cs_server v2020.2
  ****** Build date   : Nov 03 2020-15:02:56
    **** Build number : 2020.2.1604437376
      ** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved.



# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210328B04819A
# set dev [lindex [get_hw_devices] 0]
# current_hw_device $dev
# refresh_hw_device -update_hw_probes false $dev
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
# set_property PROGRAM.FILE {./cmod7.bit} $dev
# program_hw_devices $dev
INFO: [Labtools 27-3164] End of startup status: HIGH
# refresh_hw_device $dev
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
# puts "Device programmed."
Device programmed.
# quit
INFO: [Common 17-206] Exiting Vivado at Thu Nov 11 08:23:40 2021...


Done.
