246 lines
8.1 KiB
Verilog
246 lines
8.1 KiB
Verilog
// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Tri-Lam Array Wrapper
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//
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//*****************************************************************************
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// sim version, clk1x
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`include "tri_a2o.vh"
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module tri_64x72_1r1w (
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vdd,
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vcs,
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gnd,
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clk,
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rst,
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sg_0,
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abst_sl_thold_0,
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ary_nsl_thold_0,
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time_sl_thold_0,
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repr_sl_thold_0,
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rd0_act,
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rd0_adr,
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do0,
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wr_act,
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wr_adr,
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di,
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abst_scan_in,
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abst_scan_out,
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time_scan_in,
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time_scan_out,
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repr_scan_in,
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repr_scan_out,
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scan_dis_dc_b,
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scan_diag_dc,
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ccflush_dc,
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clkoff_dc_b,
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d_mode_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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delay_lclkr_dc,
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lcb_bolt_sl_thold_0,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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abist_di,
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abist_bw_odd,
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abist_bw_even,
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abist_wr_adr,
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wr_abst_act,
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abist_rd0_adr,
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rd0_abst_act,
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tc_lbist_ary_wrt_thru_dc,
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abist_ena_1,
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abist_g8t_rd0_comp_ena,
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abist_raw_dc_b,
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obs0_abist_cmp
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);
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// Power
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(* analysis_not_referenced="true" *)
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inout vdd;
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(* analysis_not_referenced="true" *)
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inout vcs;
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(* analysis_not_referenced="true" *)
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inout gnd;
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// Clock Pervasive
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input clk;
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input rst;
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input sg_0;
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input abst_sl_thold_0;
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input ary_nsl_thold_0;
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input time_sl_thold_0;
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input repr_sl_thold_0;
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// Reads
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input rd0_act;
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input [0:5] rd0_adr;
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output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
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// Writes
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input wr_act;
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input [0:5] wr_adr;
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input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;
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// Scan
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input abst_scan_in;
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output abst_scan_out;
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input time_scan_in;
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output time_scan_out;
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input repr_scan_in;
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output repr_scan_out;
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// Misc Pervasive
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input scan_dis_dc_b;
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input scan_diag_dc;
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input ccflush_dc;
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input clkoff_dc_b;
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input d_mode_dc;
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input [0:4] mpw1_dc_b;
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input mpw2_dc_b;
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input [0:4] delay_lclkr_dc;
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// BOLT-ON
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input lcb_bolt_sl_thold_0;
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input pc_bo_enable_2; // general bolt-on enable
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input pc_bo_reset; // reset
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input pc_bo_unload; // unload sticky bits
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input pc_bo_repair; // execute sticky bit decode
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input pc_bo_shdata; // shift data for timing write and diag loop
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input pc_bo_select; // select for mask and hier writes
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output bo_pc_failout; // fail/no-fix reg
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output bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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// ABIST
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input [0:3] abist_di;
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input abist_bw_odd;
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input abist_bw_even;
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input [0:5] abist_wr_adr;
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input wr_abst_act;
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input [0:5] abist_rd0_adr;
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input rd0_abst_act;
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input tc_lbist_ary_wrt_thru_dc;
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input abist_ena_1;
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input abist_g8t_rd0_comp_ena;
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input abist_raw_dc_b;
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input [0:3] obs0_abist_cmp;
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wire clk;
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wire sreset;
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wire [0:71] tidn;
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(* analysis_not_referenced="true" *)
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wire unused;
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// sim array
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reg [0:63] mem[0:71];
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reg r0_e_q;
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wire r0_e_d;
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reg [0:5] r0_a_q;
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wire [0:5] r0_a_d;
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reg [0:71] r0_d_q;
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wire [0:71] r0_d_d;
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reg w0_e_q;
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wire w0_e_d;
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reg [0:5] w0_a_q;
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wire [0:5] w0_a_d;
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reg [0:71] w0_d_q;
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wire [0:71] w0_d_d;
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integer i;
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initial begin
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for (i = 0; i < 64; i = i + 1)
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mem[i] = 0;
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end
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//wtf:icarus $dumpvars cannot dump a vpiMemory
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generate
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genvar j;
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for (j = 0; j < 63; j=j+1) begin: loc
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wire [0:63] dat;
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wire [0:7] par;
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assign dat = mem[j][0:63];
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assign par = mem[j][0:7];
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end
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endgenerate
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generate
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always @(posedge clk) begin
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r0_e_q <= rd0_act;
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r0_a_q <= rd0_adr;
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r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;
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if (w0_e_q) begin
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mem[w0_a_q] <= w0_d_q;
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end
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w0_e_q <= wr_act;
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w0_a_q <= wr_adr;
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w0_d_q <= di;
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end
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assign do0 = r0_d_q;
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assign abst_scan_out = abst_scan_in;
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assign time_scan_out = time_scan_in;
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assign repr_scan_out = repr_scan_in;
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assign bo_pc_failout = 1'b0;
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assign bo_pc_diagloop = 1'b0;
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assign unused = | ({sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
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endgenerate
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endmodule
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