623 lines
22 KiB
Verilog
623 lines
22 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_nrm(
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vdd,
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gnd,
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clk,
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rst,
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clkoff_b,
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act_dis,
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flush,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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sg_1,
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thold_1,
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fpu_enable,
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f_nrm_si,
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f_nrm_so,
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ex4_act_b,
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f_lza_ex5_lza_amt_cp1,
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f_lza_ex5_lza_dcd64_cp1,
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f_lza_ex5_lza_dcd64_cp2,
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f_lza_ex5_lza_dcd64_cp3,
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f_lza_ex5_sh_rgt_en,
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f_add_ex5_res,
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f_add_ex5_sticky,
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f_pic_ex5_byp_prod_nz,
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f_nrm_ex6_res,
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f_nrm_ex6_int_sign,
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f_nrm_ex6_int_lsbs,
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f_nrm_ex6_nrm_sticky_dp,
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f_nrm_ex6_nrm_guard_dp,
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f_nrm_ex6_nrm_lsb_dp,
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f_nrm_ex6_nrm_sticky_sp,
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f_nrm_ex6_nrm_guard_sp,
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f_nrm_ex6_nrm_lsb_sp,
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f_nrm_ex6_exact_zero,
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f_nrm_ex5_extra_shift,
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f_nrm_ex6_fpscr_wr_dat_dfp,
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f_nrm_ex6_fpscr_wr_dat
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);
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inout vdd;
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inout gnd;
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input clk;
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input rst;
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input clkoff_b; // tiup
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input act_dis; // ??tidn??
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input flush; // ??tidn??
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input [4:5] delay_lclkr; // tidn,
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input [4:5] mpw1_b; // tidn,
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input [0:1] mpw2_b; // tidn,
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input sg_1;
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input thold_1;
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input fpu_enable; //dc_act
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input f_nrm_si; // perv
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output f_nrm_so; // perv
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input ex4_act_b; // act
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input [0:7] f_lza_ex5_lza_amt_cp1; // shift amount
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input [0:2] f_lza_ex5_lza_dcd64_cp1; //fnrm
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input [0:1] f_lza_ex5_lza_dcd64_cp2; //fnrm
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input [0:0] f_lza_ex5_lza_dcd64_cp3; //fnrm
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input f_lza_ex5_sh_rgt_en;
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input [0:162] f_add_ex5_res; // data to shift
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input f_add_ex5_sticky; // or into sticky
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input f_pic_ex5_byp_prod_nz;
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output [0:52] f_nrm_ex6_res; //rnd,
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output f_nrm_ex6_int_sign; //rnd, (151:162)
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output [1:12] f_nrm_ex6_int_lsbs; //rnd, (151:162)
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output f_nrm_ex6_nrm_sticky_dp; //rnd,
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output f_nrm_ex6_nrm_guard_dp; //rnd,
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output f_nrm_ex6_nrm_lsb_dp; //rnd,
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output f_nrm_ex6_nrm_sticky_sp; //rnd,
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output f_nrm_ex6_nrm_guard_sp; //rnd,
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output f_nrm_ex6_nrm_lsb_sp; //rnd,
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output f_nrm_ex6_exact_zero; //rnd,
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output f_nrm_ex5_extra_shift; //expo_ov,
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output [0:3] f_nrm_ex6_fpscr_wr_dat_dfp; //fpscr, (17:20)
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output [0:31] f_nrm_ex6_fpscr_wr_dat; //fpscr, (21:52)
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// end ports
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// ENTITY
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire sg_0;
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wire thold_0_b;
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wire thold_0;
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wire force_t;
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wire ex4_act;
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wire ex5_act;
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wire [0:2] act_spare_unused;
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//-----------------
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wire [0:3] act_so; //SCAN
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wire [0:3] act_si; //SCAN
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wire [0:52] ex6_res_so; //SCAN
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wire [0:52] ex6_res_si; //SCAN
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wire [0:3] ex6_nrm_lg_so; //SCAN
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wire [0:3] ex6_nrm_lg_si; //SCAN
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wire [0:2] ex6_nrm_x_so; //SCAN
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wire [0:2] ex6_nrm_x_si; //SCAN
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wire [0:12] ex6_nrm_pass_so; //SCAN
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wire [0:12] ex6_nrm_pass_si; //SCAN
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wire [0:35] ex6_fmv_so; //SCAN
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wire [0:35] ex6_fmv_si; //SCAN
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//-----------------
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wire [26:72] ex5_sh2;
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wire ex5_sh4_25; //shifting
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wire ex5_sh4_54; //shifting
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wire [0:53] ex5_nrm_res; //shifting
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wire [0:53] ex5_sh5_x_b;
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wire [0:53] ex5_sh5_y_b;
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wire ex5_lt064_x; //sticky
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wire ex5_lt128_x; //sticky
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wire ex5_lt016_x; //sticky
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wire ex5_lt032_x; //sticky
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wire ex5_lt048_x; //sticky
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wire ex5_lt016; //sticky
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wire ex5_lt032; //sticky
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wire ex5_lt048; //sticky
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wire ex5_lt064; //sticky
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wire ex5_lt080; //sticky
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wire ex5_lt096; //sticky
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wire ex5_lt112; //sticky
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wire ex5_lt128; //sticky
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wire ex5_lt04_x; //sticky
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wire ex5_lt08_x; //sticky
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wire ex5_lt12_x; //sticky
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wire ex5_lt01_x; //sticky
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wire ex5_lt02_x; //sticky
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wire ex5_lt03_x; //sticky
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wire ex5_sticky_sp; //sticky
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wire ex5_sticky_dp; //sticky
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wire ex5_sticky16_dp; //sticky
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wire ex5_sticky16_sp; //sticky
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wire [0:10] ex5_or_grp16; //sticky
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wire [0:14] ex5_lt; //sticky
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wire ex5_exact_zero; //sticky
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wire ex5_exact_zero_b; //sticky
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//------------------
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wire [0:52] ex6_res; // LATCH OUTPUTS
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wire ex6_nrm_sticky_dp;
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wire ex6_nrm_guard_dp;
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wire ex6_nrm_lsb_dp;
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wire ex6_nrm_sticky_sp;
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wire ex6_nrm_guard_sp;
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wire ex6_nrm_lsb_sp;
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wire ex6_exact_zero;
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wire ex6_int_sign;
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wire [1:12] ex6_int_lsbs;
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wire [0:31] ex6_fpscr_wr_dat;
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wire [0:3] ex6_fpscr_wr_dat_dfp;
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wire ex5_rgt_4more;
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wire ex5_rgt_3more;
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wire ex5_rgt_2more;
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wire ex5_shift_extra_cp2;
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wire unused;
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wire ex5_sticky_dp_x2_b;
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wire ex5_sticky_dp_x1_b;
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wire ex5_sticky_dp_x1;
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wire ex5_sticky_sp_x2_b;
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wire ex5_sticky_sp_x1_b;
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wire ex5_sticky_sp_x1;
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wire ex6_d1clk;
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wire ex6_d2clk;
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//wire [0:`NCLK_WIDTH-1] ex6_lclk;
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wire ex6_lclk;
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wire ex5_sticky_stuff;
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// sticky bit sp/dp does not look at all the bits
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assign unused = |(ex5_sh2[41:54]) | |(ex5_nrm_res[0:53]) | ex5_sticky_sp | ex5_sticky_dp | ex5_exact_zero;
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////############################################
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//# pervasive
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////############################################
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tri_plat thold_reg_0(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(flush),
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.din(thold_1),
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.q(thold_0)
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);
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tri_plat sg_reg_0(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(flush),
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.din(sg_1),
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.q(sg_0)
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);
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tri_lcbor lcbor_0(
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.clkoff_b(clkoff_b),
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.thold(thold_0),
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.sg(sg_0),
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.act_dis(act_dis),
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.force_t(force_t),
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.thold_b(thold_0_b)
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);
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tri_lcbnd ex6_lcb(
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.delay_lclkr(delay_lclkr[5]), // tidn
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.mpw1_b(mpw1_b[5]), // tidn
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.mpw2_b(mpw2_b[1]), // tidn
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.force_t(force_t), // tidn
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.clk(clk),
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.rst(rst), //in
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.vd(vdd), //inout
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.gd(gnd), //inout
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.act(ex5_act), //in
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.sg(sg_0), //in
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.thold_b(thold_0_b), //in
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.d1clk(ex6_d1clk), //out
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.d2clk(ex6_d2clk), //out
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.lclk(ex6_lclk) //out
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);
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////############################################
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//# ACT LATCHES
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////############################################
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assign ex4_act = (~ex4_act_b);
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tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat(
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.force_t(force_t), //i-- tidn,
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.d_mode(tiup),
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.delay_lclkr(delay_lclkr[4]), //i-- tidn,
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.mpw1_b(mpw1_b[4]), //i-- tidn,
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.mpw2_b(mpw2_b[0]), //i-- tidn,
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.thold_b(thold_0_b),
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.sg(sg_0),
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.act(fpu_enable),
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.scout(act_so[0:3]),
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.scin(act_si[0:3]),
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//-----------------
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.din({ act_spare_unused[0],
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act_spare_unused[1],
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ex4_act,
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act_spare_unused[2]}),
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//-----------------
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.dout({ act_spare_unused[0],
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act_spare_unused[1],
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ex5_act,
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act_spare_unused[2]})
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);
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////##############################################
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//# EX5 logic: shifting
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////##############################################
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fu_nrm_sh sh(
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.f_lza_ex5_sh_rgt_en(f_lza_ex5_sh_rgt_en), //i--
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.f_lza_ex5_lza_amt_cp1(f_lza_ex5_lza_amt_cp1[2:7]), //i--
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.f_lza_ex5_lza_dcd64_cp1(f_lza_ex5_lza_dcd64_cp1[0:2]), //i--
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.f_lza_ex5_lza_dcd64_cp2(f_lza_ex5_lza_dcd64_cp2[0:1]), //i--
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.f_lza_ex5_lza_dcd64_cp3(f_lza_ex5_lza_dcd64_cp3[0:0]), //i--
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.f_add_ex5_res(f_add_ex5_res[0:162]), //i--
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.ex5_shift_extra_cp1(f_nrm_ex5_extra_shift), //o-- <30ish> loads feov
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.ex5_shift_extra_cp2(ex5_shift_extra_cp2), //o-- <2> loads sticky sp/dp
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.ex5_sh4_25(ex5_sh4_25), //o--
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.ex5_sh4_54(ex5_sh4_54), //o--
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.ex5_sh2_o(ex5_sh2[26:72]), //o--
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.ex5_sh5_x_b(ex5_sh5_x_b[0:53]), //o--
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.ex5_sh5_y_b(ex5_sh5_y_b[0:53]) //o--
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);
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assign ex5_nrm_res[0:53] = (~(ex5_sh5_x_b[0:53] & ex5_sh5_y_b[0:53]));
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////##############################################
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//# EX5 logic: stciky bit
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////##############################################
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//# thermometer decode 1 ---------------
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//#
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//# the smaller the shift the more sticky bits.
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//# the multiple of 16 shifter is 0:68 ... bits after 68 are known sticky DP.
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//# 53-24=29 extra sp bits 68-29 = 39
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//# bits after 39 are known sticky SP.
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assign ex5_lt064_x = (~(f_lza_ex5_lza_amt_cp1[0] | f_lza_ex5_lza_amt_cp1[1])); // 00
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assign ex5_lt128_x = (~(f_lza_ex5_lza_amt_cp1[0])); // 00 01
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assign ex5_lt016_x = (~(f_lza_ex5_lza_amt_cp1[2] | f_lza_ex5_lza_amt_cp1[3])); // 00
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assign ex5_lt032_x = (~(f_lza_ex5_lza_amt_cp1[2])); // 00 01
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assign ex5_lt048_x = (~(f_lza_ex5_lza_amt_cp1[2] & f_lza_ex5_lza_amt_cp1[3])); // 00 01 10
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assign ex5_lt016 = ex5_lt064_x & ex5_lt016_x; //tail=067 sticky_dp=069:162 sticky_sp=039:162
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assign ex5_lt032 = ex5_lt064_x & ex5_lt032_x; //tail=083 sticky_dp=085:162 sticky_sp=055:162
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assign ex5_lt048 = ex5_lt064_x & ex5_lt048_x; //tail=099 sticky_dp=101:162 sticky_sp=071:162
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assign ex5_lt064 = ex5_lt064_x; //tail=115 sticky_dp=117:162 sticky_sp=087:162
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assign ex5_lt080 = ex5_lt064_x | (ex5_lt128_x & ex5_lt016_x); //tail=131 sticky_dp=133:162 sticky_sp=103:162
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assign ex5_lt096 = ex5_lt064_x | (ex5_lt128_x & ex5_lt032_x); //tail=147 sticky_dp=149:162 sticky_sp=119:162
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assign ex5_lt112 = ex5_lt064_x | (ex5_lt128_x & ex5_lt048_x); //tail=163 sticky_dp=xxxxxxx sticky_sp=135:162
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assign ex5_lt128 = ex5_lt128_x; //tail=179 sticky_dp=xxxxxxx sticky_sp=151:162
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// 1111xxxx shift right 1 -> 16 (shift right sticky groups of 16 may be off by one from shift left sticky groups)
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// 1110xxxx shift right 17 -> 32
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// 1101xxxx shift right 33 -> 48
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// 1100xxxx shift right 49 -> 64
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// x0xxxxxx shift > 64
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// 0xxxxxxx shift > 64
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// for shift right Amt[0]==Amt[1]==shRgtEn
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// xx00_dddd Right64, then Left00 4 more sticky16 group than 0000_dddd
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// xx01_dddd Right64, then Left16 3 more sticky16 group than 0000_dddd
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// xx10_dddd Right64, then Left32 2 more sticky16 group than 0000_dddd
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// xx11_dddd Right64, then Left48 1 more sticky16 group than 0000_dddd
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assign ex5_rgt_2more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2]) | (~f_lza_ex5_lza_amt_cp1[3])); // 234
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assign ex5_rgt_3more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2])); // 23
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assign ex5_rgt_4more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2]) & (~f_lza_ex5_lza_amt_cp1[3])); // 2
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//#------------------------
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//# sticky group 16 ors
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//#------------------------
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fu_nrm_or16 or16(
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.f_add_ex5_res(f_add_ex5_res[0:162]), //i--
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.ex5_or_grp16(ex5_or_grp16[0:10]) //o--
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);
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//#------------------------
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//# enable the 16 bit ors
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//#------------------------
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assign ex5_sticky_stuff = (f_pic_ex5_byp_prod_nz) | (f_add_ex5_sticky);
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// 71: 86
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// 87:102
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//103:118
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//119:134
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//135:150
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//151:162
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// so group16s match for sp/dp
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assign ex5_sticky16_dp = (ex5_or_grp16[1] & ex5_rgt_4more) | (ex5_or_grp16[2] & ex5_rgt_3more) | (ex5_or_grp16[3] & ex5_rgt_2more) | (ex5_or_grp16[4] & f_lza_ex5_sh_rgt_en) | (ex5_or_grp16[5] & (ex5_lt016 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[6] & (ex5_lt032 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[7] & (ex5_lt048 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[8] & (ex5_lt064 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[9] & (ex5_lt080 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[10] & (ex5_lt096 | f_lza_ex5_sh_rgt_en)) | (ex5_sh2[70]) | (ex5_sh2[71]) | (ex5_sh2[72]) | (ex5_sticky_stuff); // so group16s match for sp/dp
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// 39: 54
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// 55: 70
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// 71: 86
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// 87:102
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//103:118
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//119:134
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//135:150
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assign ex5_sticky16_sp = (ex5_or_grp16[0] & ex5_rgt_3more) | (ex5_or_grp16[1] & ex5_rgt_2more) | (ex5_or_grp16[2] & f_lza_ex5_sh_rgt_en) | (ex5_or_grp16[3] & (ex5_lt016 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[4] & (ex5_lt032 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[5] & (ex5_lt048 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[6] & (ex5_lt064 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[7] & (ex5_lt080 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[8] & (ex5_lt096 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[9] & (ex5_lt112 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[10] & (ex5_lt128 | f_lza_ex5_sh_rgt_en)) | (ex5_sticky_stuff); //151:162
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assign ex5_exact_zero_b = ex5_or_grp16[0] | ex5_or_grp16[1] | ex5_or_grp16[2] | ex5_or_grp16[3] | ex5_or_grp16[4] | ex5_or_grp16[5] | ex5_or_grp16[6] | ex5_or_grp16[7] | ex5_or_grp16[8] | ex5_or_grp16[9] | ex5_or_grp16[10] | (ex5_sticky_stuff);
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assign ex5_exact_zero = (~ex5_exact_zero_b);
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//#------------------------
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//# thermometer decode 2
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//#------------------------
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assign ex5_lt04_x = (~(f_lza_ex5_lza_amt_cp1[4] | f_lza_ex5_lza_amt_cp1[5])); // 00
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assign ex5_lt08_x = (~(f_lza_ex5_lza_amt_cp1[4])); // 00 01
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assign ex5_lt12_x = (~(f_lza_ex5_lza_amt_cp1[4] & f_lza_ex5_lza_amt_cp1[5])); // 00 01 10
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assign ex5_lt01_x = (~(f_lza_ex5_lza_amt_cp1[6] | f_lza_ex5_lza_amt_cp1[7])); // 00
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assign ex5_lt02_x = (~(f_lza_ex5_lza_amt_cp1[6])); // 00 01
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assign ex5_lt03_x = (~(f_lza_ex5_lza_amt_cp1[6] & f_lza_ex5_lza_amt_cp1[7])); // 00 01 10
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assign ex5_lt[0] = ex5_lt04_x & ex5_lt01_x; // 1
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assign ex5_lt[1] = ex5_lt04_x & ex5_lt02_x; // 2
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assign ex5_lt[2] = ex5_lt04_x & ex5_lt03_x; // 3
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assign ex5_lt[3] = ex5_lt04_x; // 4
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assign ex5_lt[4] = ex5_lt04_x | (ex5_lt08_x & ex5_lt01_x); // 5
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assign ex5_lt[5] = ex5_lt04_x | (ex5_lt08_x & ex5_lt02_x); // 6
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assign ex5_lt[6] = ex5_lt04_x | (ex5_lt08_x & ex5_lt03_x); // 7
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assign ex5_lt[7] = (ex5_lt08_x); // 8
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assign ex5_lt[8] = ex5_lt08_x | (ex5_lt12_x & ex5_lt01_x); // 9
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assign ex5_lt[9] = ex5_lt08_x | (ex5_lt12_x & ex5_lt02_x); //10
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assign ex5_lt[10] = ex5_lt08_x | (ex5_lt12_x & ex5_lt03_x); //11
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assign ex5_lt[11] = (ex5_lt12_x); //12
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assign ex5_lt[12] = ex5_lt12_x | ex5_lt01_x; //13
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assign ex5_lt[13] = ex5_lt12_x | ex5_lt02_x; //14
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assign ex5_lt[14] = ex5_lt12_x | ex5_lt03_x; //15
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//#------------------------
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//# final sticky bits
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//#------------------------
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// lt 01
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// lt 02
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// lt 03
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// lt 04
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// lt 05
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// lt 06
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// lt 07
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// lt 08
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// lt 09
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// lt 10
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// lt 11
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// lt 12
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// lt 13
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// lt 14
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assign ex5_sticky_sp_x1 = (ex5_lt[14] & ex5_sh2[40]) | (ex5_lt[13] & ex5_sh2[39]) | (ex5_lt[12] & ex5_sh2[38]) | (ex5_lt[11] & ex5_sh2[37]) | (ex5_lt[10] & ex5_sh2[36]) | (ex5_lt[9] & ex5_sh2[35]) | (ex5_lt[8] & ex5_sh2[34]) | (ex5_lt[7] & ex5_sh2[33]) | (ex5_lt[6] & ex5_sh2[32]) | (ex5_lt[5] & ex5_sh2[31]) | (ex5_lt[4] & ex5_sh2[30]) | (ex5_lt[3] & ex5_sh2[29]) | (ex5_lt[2] & ex5_sh2[28]) | (ex5_lt[1] & ex5_sh2[27]) | (ex5_lt[0] & ex5_sh2[26]) | (ex5_sticky16_sp); // lt 15
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assign ex5_sticky_sp_x2_b = (~((~ex5_shift_extra_cp2) & ex5_sh4_25));
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assign ex5_sticky_sp_x1_b = (~ex5_sticky_sp_x1);
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assign ex5_sticky_sp = (~(ex5_sticky_sp_x1_b & ex5_sticky_sp_x2_b));
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|
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// lt 01
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// lt 02
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// lt 03
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// lt 04
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// lt 05
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// lt 06
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// lt 07
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// lt 08
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// lt 09
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// lt 10
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// lt 11
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// lt 12
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// lt 13
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// lt 14
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assign ex5_sticky_dp_x1 = (ex5_lt[14] & ex5_sh2[69]) | (ex5_lt[13] & ex5_sh2[68]) | (ex5_lt[12] & ex5_sh2[67]) | (ex5_lt[11] & ex5_sh2[66]) | (ex5_lt[10] & ex5_sh2[65]) | (ex5_lt[9] & ex5_sh2[64]) | (ex5_lt[8] & ex5_sh2[63]) | (ex5_lt[7] & ex5_sh2[62]) | (ex5_lt[6] & ex5_sh2[61]) | (ex5_lt[5] & ex5_sh2[60]) | (ex5_lt[4] & ex5_sh2[59]) | (ex5_lt[3] & ex5_sh2[58]) | (ex5_lt[2] & ex5_sh2[57]) | (ex5_lt[1] & ex5_sh2[56]) | (ex5_lt[0] & ex5_sh2[55]) | (ex5_sticky16_dp); // lt 15
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assign ex5_sticky_dp_x2_b = (~((~ex5_shift_extra_cp2) & ex5_sh4_54));
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assign ex5_sticky_dp_x1_b = (~ex5_sticky_dp_x1);
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assign ex5_sticky_dp = (~(ex5_sticky_dp_x1_b & ex5_sticky_dp_x2_b));
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|
|
////##############################################
|
|
//# EX6 latches
|
|
////##############################################
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|
|
|
|
|
// , ibuf => true,
|
|
tri_nand2_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex6_res_lat(
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.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk), //lclk.clk
|
|
.rst(rst),
|
|
.d1clk(ex6_d1clk),
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|
.d2clk(ex6_d2clk),
|
|
.scanin(ex6_res_si),
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|
.scanout(ex6_res_so),
|
|
.a1(ex5_sh5_x_b[0:52]),
|
|
.a2(ex5_sh5_y_b[0:52]),
|
|
.qb(ex6_res[0:52]) //LAT--
|
|
);
|
|
|
|
// , ibuf => true,
|
|
tri_nand2_nlats #(.WIDTH(4), .NEEDS_SRESET(0)) ex6_nrm_lg_lat(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk), //lclk.clk
|
|
.rst(rst),
|
|
.d1clk(ex6_d1clk),
|
|
.d2clk(ex6_d2clk),
|
|
.scanin(ex6_nrm_lg_si),
|
|
.scanout(ex6_nrm_lg_so),
|
|
//-----------------
|
|
.a1({ex5_sh5_x_b[23],
|
|
ex5_sh5_x_b[24],
|
|
ex5_sh5_x_b[52],
|
|
ex5_sh5_x_b[53]}),
|
|
//-----------------
|
|
.a2({ex5_sh5_y_b[23],
|
|
ex5_sh5_y_b[24],
|
|
ex5_sh5_y_b[52],
|
|
ex5_sh5_y_b[53]}),
|
|
//-----------------
|
|
.qb({ex6_nrm_lsb_sp, //LAT-- --sp lsb
|
|
ex6_nrm_guard_sp, //LAT-- --sp guard
|
|
ex6_nrm_lsb_dp, //LAT-- --dp lsb
|
|
ex6_nrm_guard_dp}) //LAT-- --dp guard
|
|
);
|
|
|
|
// , ibuf => true,
|
|
tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_nrm_x_lat(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk), //lclk.clk
|
|
.rst(rst),
|
|
.d1clk(ex6_d1clk),
|
|
.d2clk(ex6_d2clk),
|
|
.scanin(ex6_nrm_x_si),
|
|
.scanout(ex6_nrm_x_so),
|
|
//-----------------
|
|
.a1({ ex5_sticky_sp_x2_b,
|
|
ex5_sticky_dp_x2_b,
|
|
ex5_exact_zero_b}),
|
|
//-----------------
|
|
.a2({ ex5_sticky_sp_x1_b,
|
|
ex5_sticky_dp_x1_b,
|
|
tiup}),
|
|
//-----------------
|
|
.qb({ ex6_nrm_sticky_sp, //LAT--
|
|
ex6_nrm_sticky_dp, //LAT--
|
|
ex6_exact_zero}) //LAT--
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(13), .IBUF(1'B1), .NEEDS_SRESET(0)) ex6_nrm_pass_lat(
|
|
.force_t(force_t), //i-- tidn,
|
|
.d_mode(tiup),
|
|
.delay_lclkr(delay_lclkr[5]), //i-- tidn,
|
|
.mpw1_b(mpw1_b[5]), //i-- tidn,
|
|
.mpw2_b(mpw2_b[1]), //i-- tidn,
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.thold_b(thold_0_b),
|
|
.sg(sg_0),
|
|
.act(ex5_act),
|
|
.scout(ex6_nrm_pass_so),
|
|
.scin(ex6_nrm_pass_si),
|
|
//-----------------
|
|
.din({f_add_ex5_res[99],
|
|
f_add_ex5_res[151:162]}), // (151:162)
|
|
//-----------------
|
|
.dout({ex6_int_sign, //LAT--
|
|
ex6_int_lsbs[1:12]}) //LAT-- --(151:162)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(36), .IBUF(1'B1), .NEEDS_SRESET(1)) ex6_fmv_lat(
|
|
.force_t(force_t), //i-- tidn,
|
|
.d_mode(tiup),
|
|
.delay_lclkr(delay_lclkr[5]), //i-- tidn,
|
|
.mpw1_b(mpw1_b[5]), //i-- tidn,
|
|
.mpw2_b(mpw2_b[1]), //i-- tidn,
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.thold_b(thold_0_b),
|
|
.sg(sg_0),
|
|
.act(ex5_act),
|
|
.scout(ex6_fmv_so),
|
|
.scin(ex6_fmv_si),
|
|
//-----------------
|
|
.din(f_add_ex5_res[17:52]), //LAT
|
|
//-----------------
|
|
.dout({ex6_fpscr_wr_dat_dfp[0:3],
|
|
ex6_fpscr_wr_dat[0:31]}) //LAT
|
|
);
|
|
|
|
assign f_nrm_ex6_res = ex6_res[0:52]; //output--rnd
|
|
assign f_nrm_ex6_nrm_lsb_sp = ex6_nrm_lsb_sp; //output--rnd
|
|
assign f_nrm_ex6_nrm_guard_sp = ex6_nrm_guard_sp; //output--rnd
|
|
assign f_nrm_ex6_nrm_sticky_sp = ex6_nrm_sticky_sp; //output--rnd
|
|
assign f_nrm_ex6_nrm_lsb_dp = ex6_nrm_lsb_dp; //output--rnd
|
|
assign f_nrm_ex6_nrm_guard_dp = ex6_nrm_guard_dp; //output--rnd
|
|
assign f_nrm_ex6_nrm_sticky_dp = ex6_nrm_sticky_dp; //output--rnd
|
|
assign f_nrm_ex6_exact_zero = ex6_exact_zero; //output--rnd
|
|
assign f_nrm_ex6_int_lsbs = ex6_int_lsbs[1:12]; //output--rnd (151:162)
|
|
assign f_nrm_ex6_fpscr_wr_dat = ex6_fpscr_wr_dat[0:31]; //output--fpscr, (21:52)
|
|
assign f_nrm_ex6_fpscr_wr_dat_dfp = ex6_fpscr_wr_dat_dfp[0:3]; //output--fpscr (17:20)
|
|
assign f_nrm_ex6_int_sign = ex6_int_sign; //output--rnd (151:162)
|
|
|
|
////############################################
|
|
//# scan
|
|
////############################################
|
|
|
|
assign act_si[0:3] = {act_so[1:3], f_nrm_si};
|
|
assign ex6_res_si[0:52] = {ex6_res_so[1:52], act_so[0]};
|
|
assign ex6_nrm_lg_si[0:3] = {ex6_nrm_lg_so[1:3], ex6_res_so[0]};
|
|
assign ex6_nrm_x_si[0:2] = {ex6_nrm_x_so[1:2], ex6_nrm_lg_so[0]};
|
|
assign ex6_nrm_pass_si[0:12] = {ex6_nrm_pass_so[1:12], ex6_nrm_x_so[0]};
|
|
assign ex6_fmv_si[0:35] = {ex6_fmv_so[1:35], ex6_nrm_pass_so[0]};
|
|
assign f_nrm_so = ex6_fmv_so[0];
|
|
|
|
endmodule
|