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197 lines
7.7 KiB
Systemverilog
197 lines
7.7 KiB
Systemverilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`ifndef _tri_a2o_vh_
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`define _tri_a2o_vh_
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`include "tri.vh"
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// Use this line for 1 thread. Comment out for 2 thread design.
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`define THREADS1
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// 0: none 1: DP
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`define FLOAT_TYPE 1
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`define gpr_t 3'b000
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`define cr_t 3'b001
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`define lr_t 3'b010
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`define ctr_t 3'b011
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`define xer_t 3'b100
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`define spr_t 3'b101
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`define axu0_t 3'b110
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`define axu1_t 3'b111
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`ifdef THREADS1
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`define THREADS 1
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`define THREAD_POOL_ENC 0
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`define THREADS_POOL_ENC 0
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`else
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`define THREADS 2
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`define THREAD_POOL_ENC 1
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`define THREADS_POOL_ENC 1
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`endif
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`define EFF_IFAR_ARCH 62
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`define EFF_IFAR_WIDTH 20
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`define EFF_IFAR 20
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`define FPR_POOL_ENC 6
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`define REGMODE 6
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`define FPR_POOL 64
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`define REAL_IFAR_WIDTH 42
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`define EMQ_ENTRIES 4
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`define GPR_WIDTH 64
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`define ITAG_SIZE_ENC 7
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`define CPL_Q_DEPTH 32
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`define CPL_Q_DEPTH_ENC 6
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`define GPR_WIDTH_ENC 6
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`define GPR_POOL_ENC 6
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`define GPR_POOL 64
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`define GPR_UCODE_POOL 4
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`define CR_POOL_ENC 5
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`define CR_POOL 24
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`define CR_UCODE_POOL 1
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`define BR_POOL_ENC 3
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`define BR_POOL 8
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`define LR_POOL_ENC 3
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`define LR_POOL 8
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`define LR_UCODE_POOL 0
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`define CTR_POOL_ENC 3
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`define CTR_POOL 8
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`define CTR_UCODE_POOL 0
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`define XER_POOL_ENC 4
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`define XER_POOL 12
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`define XER_UCODE_POOL 0
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`define LDSTQ_ENTRIES 16
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`define LDSTQ_ENTRIES_ENC 4
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`define STQ_ENTRIES 12
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`define STQ_ENTRIES_ENC 4
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`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from
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`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported
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`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$
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`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE
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`define LMQ_ENTRIES 8
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`define LMQ_ENTRIES_ENC 3
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`define LGQ_ENTRIES 8
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`define AXU_SPARE_ENC 3
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`define RV_FX0_ENTRIES 12
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`define RV_FX1_ENTRIES 12
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`define RV_LQ_ENTRIES 16
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`define RV_AXU0_ENTRIES 12
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`define RV_AXU1_ENTRIES 0
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`define RV_FX0_ENTRIES_ENC 4
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`define RV_FX1_ENTRIES_ENC 4
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`define RV_LQ_ENTRIES_ENC 4
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`define RV_AXU0_ENTRIES_ENC 4
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`define RV_AXU1_ENTRIES_ENC 1
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`define UCODE_ENTRIES 8
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`define UCODE_ENTRIES_ENC 3
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`define FXU1_ENABLE 1
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`define TYPE_WIDTH 3
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`define IBUFF_INSTR_WIDTH 70
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`define IBUFF_IFAR_WIDTH 20
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`define IBUFF_DEPTH 16
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`define PF_IAR_BITS 12 // number of IAR bits used by prefetch
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`define FXU0_PIPE_START 1
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`define FXU0_PIPE_END 8
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`define FXU1_PIPE_START 1
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`define FXU1_PIPE_END 5
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`define LQ_LOAD_PIPE_START 4
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`define LQ_LOAD_PIPE_END 8
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`define LQ_REL_PIPE_START 2
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`define LQ_REL_PIPE_END 4
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`define LOAD_CREDITS 8
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`define STORE_CREDITS 4 //wtf 32 is normal; fpga bug needed 4
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`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size
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`define MMQ_ENTRIES 2 // MMU Queue Size
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`define CR_WIDTH 4
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`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch
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`define PF_IFAR_WIDTH 12
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`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch
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`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
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`define PFETCH_Q_SIZE 8 // number of entries
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`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
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`define XER_WIDTH 10
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//wtf: change for verilatorsim - didnt help
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//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
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`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
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//`define INIT_IUCR0 16'h0000 // BP disabled
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`define INIT_IUCR0 16'h00FA // BP enabled
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`define INIT_XUCR0 32'h00000460 // normal
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`define INIT_MASK 2'b10
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`define RELQ_INCLUDE 0 // Reload Queue Included
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`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1
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//wtf: add completion stuff
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/*
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assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39];
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assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47];
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assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55];
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assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63];
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*/
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`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132
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//`define INIT_CPCR0 32'h01010201 // 1/1/2/1
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/*
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assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47];
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assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55];
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*/
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`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
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//`define INIT_CPCR1 32'h00010100 // 1/1
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// table walks?
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`define MM_THREADS2
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// IERAT boot config entry values
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`define IERAT_BCFG_EPN_0TO15 0
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`define IERAT_BCFG_EPN_16TO31 0
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`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
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`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
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`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
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`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G
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`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
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`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
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`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
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`define IERAT_BCFG_ATTR 0 // u0-u3, endian
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// DERAT boot config entry values
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`define DERAT_BCFG_EPN_0TO15 0
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`define DERAT_BCFG_EPN_16TO31 0
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`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G
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`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
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`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff
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`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G
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`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G
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`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
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`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page
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`define DERAT_BCFG_ATTR 0 // u0-u3, endian
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// Do NOT add any defines below this line
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`endif //_tri_a2o_vh_
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