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139 lines
3.6 KiB
Verilog
139 lines
3.6 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//*****************************************************************************
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// Description: XU 64 bit Count Leading Zeros Macro
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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module tri_st_cntlz(
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dword,
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a,
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y
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);
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input dword;
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input [0:63] a;
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output [0:6] y;
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wire [0:23] ys;
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wire [0:7] z;
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wire [0:7] zh;
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wire [0:2] yh;
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wire [0:2] yh_sel;
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wire zero_b;
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assign y[0] = (dword == 1'b1) ? (~zero_b) :
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1'b0;
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assign y[1] = (dword == 1'b1) ? yh[0] :
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(~zero_b);
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assign y[2:3] = yh[1:2];
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// Force the select to the lower half for word ops
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assign yh_sel[0] = yh[0] | (~dword);
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assign yh_sel[1:2] = yh[1:2];
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// Force the select to be in the lower half for word
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assign y[4:6] = (yh_sel[0:2] == 3'b000) ? ys[0:2] :
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(yh_sel[0:2] == 3'b001) ? ys[3:5] :
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(yh_sel[0:2] == 3'b010) ? ys[6:8] :
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(yh_sel[0:2] == 3'b011) ? ys[9:11] :
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(yh_sel[0:2] == 3'b100) ? ys[12:14] :
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(yh_sel[0:2] == 3'b101) ? ys[15:17] :
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(yh_sel[0:2] == 3'b110) ? ys[18:20] :
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ys[21:23];
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assign zh[0:3] = z[0:3] & {4{dword}};
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assign zh[4:7] = z[4:7];
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tri_st_cntlz_8b clz_h(
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.a(zh[0:7]),
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.y(yh[0:2]),
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.z_b(zero_b)
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);
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tri_st_cntlz_8b clz_l0(
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.a(a[0:7]),
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.y(ys[0:2]),
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.z_b(z[0])
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);
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tri_st_cntlz_8b clz_l1(
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.a(a[8:15]),
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.y(ys[3:5]),
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.z_b(z[1])
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);
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tri_st_cntlz_8b clz_l2(
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.a(a[16:23]),
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.y(ys[6:8]),
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.z_b(z[2])
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);
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tri_st_cntlz_8b clz_l3(
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.a(a[24:31]),
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.y(ys[9:11]),
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.z_b(z[3])
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);
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tri_st_cntlz_8b clz_l4(
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.a(a[32:39]),
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.y(ys[12:14]),
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.z_b(z[4])
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);
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tri_st_cntlz_8b clz_l5(
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.a(a[40:47]),
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.y(ys[15:17]),
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.z_b(z[5])
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);
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tri_st_cntlz_8b clz_l6(
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.a(a[48:55]),
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.y(ys[18:20]),
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.z_b(z[6])
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);
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tri_st_cntlz_8b clz_l7(
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.a(a[56:63]),
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.y(ys[21:23]),
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.z_b(z[7])
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);
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endmodule
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