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314 lines
7.7 KiB
Verilog
314 lines
7.7 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// Description: Adder
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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module tri_st_add(
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x_b,
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y_b,
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ci,
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sum,
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cout_32,
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cout_0
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);
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input [0:63] x_b; // after xor
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input [0:63] y_b;
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input ci;
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output [0:63] sum;
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output cout_32;
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output cout_0;
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wire [0:63] g01;
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wire [0:63] g01_b;
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wire [0:63] t01;
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wire [0:63] t01_b;
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wire [0:63] sum_0;
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wire [0:63] sum_1;
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wire [0:7] g08;
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wire [0:7] t08;
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wire [0:7] c64_b;
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wire cout_32x;
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wire cout_32y_b;
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wire ci_cp1_lv1_b;
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wire ci_cp1_lv2;
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wire ci_cp1_lv3_b;
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wire ci_cp1_lv4;
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wire ci_cp2_lv2;
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wire ci_cp2_lv3_b;
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assign ci_cp1_lv1_b = (~ci); // x2
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assign ci_cp1_lv2 = (~ci_cp1_lv1_b); // x2
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assign ci_cp1_lv3_b = (~ci_cp1_lv2); // x3
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assign ci_cp1_lv4 = (~ci_cp1_lv3_b); // x4
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assign ci_cp2_lv2 = (~ci_cp1_lv1_b); // x2
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assign ci_cp2_lv3_b = (~ci_cp2_lv2); // x3
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////##################################################
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////## pgt
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////##################################################
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// extra logic on [63] is performance penalty to agen (dont need ci ).
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// ci*x + ci*y + xy
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// x(ci + y) + (ci * y )
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assign g01[0:63] = (~(x_b[0:63] | y_b[0:63]));
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assign t01[0:63] = (~(x_b[0:63] & y_b[0:63]));
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assign g01_b[0:63] = (~g01[0:63]); // small, buffer off
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assign t01_b[0:63] = (~t01[0:63]); // small, buffer off
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////##################################################
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////## local part of byte group
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////##################################################
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tri_st_add_loc loc_0(
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.g01_b(g01_b[0:7]), //i--
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.t01_b(t01_b[0:7]), //i--
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.sum_0(sum_0[0:7]), //o--
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.sum_1(sum_1[0:7]) //o--
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);
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tri_st_add_loc loc_1(
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.g01_b(g01_b[8:15]), //i--
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.t01_b(t01_b[8:15]), //i--
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.sum_0(sum_0[8:15]), //o--
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.sum_1(sum_1[8:15]) //o--
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);
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tri_st_add_loc loc_2(
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.g01_b(g01_b[16:23]), //i--
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.t01_b(t01_b[16:23]), //i--
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.sum_0(sum_0[16:23]), //o--
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.sum_1(sum_1[16:23]) //o--
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);
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tri_st_add_loc loc_3(
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.g01_b(g01_b[24:31]), //i--
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.t01_b(t01_b[24:31]), //i--
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.sum_0(sum_0[24:31]), //o--
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.sum_1(sum_1[24:31]) //o--
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);
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tri_st_add_loc loc_4(
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.g01_b(g01_b[32:39]), //i--
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.t01_b(t01_b[32:39]), //i--
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.sum_0(sum_0[32:39]), //o--
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.sum_1(sum_1[32:39]) //o--
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);
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tri_st_add_loc loc_5(
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.g01_b(g01_b[40:47]), //i--
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.t01_b(t01_b[40:47]), //i--
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.sum_0(sum_0[40:47]), //o--
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.sum_1(sum_1[40:47]) //o--
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);
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tri_st_add_loc loc_6(
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.g01_b(g01_b[48:55]), //i--
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.t01_b(t01_b[48:55]), //i--
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.sum_0(sum_0[48:55]), //o--
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.sum_1(sum_1[48:55]) //o--
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);
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tri_st_add_loc loc_7(
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.g01_b(g01_b[56:63]), //i--
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.t01_b(t01_b[56:63]), //i--
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.sum_0(sum_0[56:63]), //o--
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.sum_1(sum_1[56:63]) //o--
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);
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////##################################################
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////## local part of global carry
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////##################################################
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tri_st_add_glbloc gclc_0(
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.g01(g01[0:7]), //i--
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.t01(t01[0:7]), //i--
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.g08(g08[0]), //o--
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.t08(t08[0]) //o--
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);
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tri_st_add_glbloc gclc_1(
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.g01(g01[8:15]), //i--
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.t01(t01[8:15]), //i--
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.g08(g08[1]), //o--
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.t08(t08[1]) //o--
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);
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tri_st_add_glbloc gclc_2(
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.g01(g01[16:23]), //i--
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.t01(t01[16:23]), //i--
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.g08(g08[2]), //o--
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.t08(t08[2]) //o--
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);
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tri_st_add_glbloc gclc_3(
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.g01(g01[24:31]), //i--
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.t01(t01[24:31]), //i--
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.g08(g08[3]), //o--
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.t08(t08[3]) //o--
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);
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tri_st_add_glbloc gclc_4(
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.g01(g01[32:39]), //i--
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.t01(t01[32:39]), //i--
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.g08(g08[4]), //o--
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.t08(t08[4]) //o--
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);
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tri_st_add_glbloc gclc_5(
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.g01(g01[40:47]), //i--
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.t01(t01[40:47]), //i--
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.g08(g08[5]), //o--
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.t08(t08[5]) //o--
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);
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tri_st_add_glbloc gclc_6(
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.g01(g01[48:55]), //i--
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.t01(t01[48:55]), //i--
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.g08(g08[6]), //o--
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.t08(t08[6]) //o--
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);
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tri_st_add_glbloc gclc_7(
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.g01(g01[56:63]), //i--
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.t01(t01[56:63]), //i--
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.g08(g08[7]), //o--
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.t08(t08[7]) //o--
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);
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////##################################################
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////## global part of global carry
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////##################################################
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tri_st_add_glbglbci gc(
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.g08(g08[0:7]), //i--
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.t08(t08[0:7]), //i--
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.ci(ci_cp1_lv4), //i--
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.c64_b(c64_b[0:7]) //o--
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);
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assign cout_32x = (~c64_b[4]); //(small)
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assign cout_32y_b = (~cout_32x);
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assign cout_32 = (~cout_32y_b); //output--
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assign cout_0 = (~c64_b[0]); //output-- --rename--
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////##################################################
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////## final mux
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////##################################################
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tri_st_add_csmux fm_0(
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.ci_b(c64_b[1]), //i--
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.sum_0(sum_0[0:7]), //i--
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.sum_1(sum_1[0:7]), //i--
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.sum(sum[0:7]) //o--
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);
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tri_st_add_csmux fm_1(
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.ci_b(c64_b[2]), //i--
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.sum_0(sum_0[8:15]), //i--
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.sum_1(sum_1[8:15]), //i--
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.sum(sum[8:15]) //o--
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);
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tri_st_add_csmux fm_2(
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.ci_b(c64_b[3]), //i--
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.sum_0(sum_0[16:23]), //i--
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.sum_1(sum_1[16:23]), //i--
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.sum(sum[16:23]) //o--
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);
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tri_st_add_csmux fm_3(
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.ci_b(c64_b[4]), //i--
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.sum_0(sum_0[24:31]), //i--
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.sum_1(sum_1[24:31]), //i--
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.sum(sum[24:31]) //o--
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);
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tri_st_add_csmux fm_4(
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.ci_b(c64_b[5]), //i--
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.sum_0(sum_0[32:39]), //i--
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.sum_1(sum_1[32:39]), //i--
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.sum(sum[32:39]) //o--
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);
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tri_st_add_csmux fm_5(
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.ci_b(c64_b[6]), //i--
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.sum_0(sum_0[40:47]), //i--
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.sum_1(sum_1[40:47]), //i--
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.sum(sum[40:47]) //o--
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);
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tri_st_add_csmux fm_6(
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.ci_b(c64_b[7]), //i--
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.sum_0(sum_0[48:55]), //i--
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.sum_1(sum_1[48:55]), //i--
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.sum(sum[48:55]) //o--
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);
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tri_st_add_csmux fm_7(
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.ci_b(ci_cp2_lv3_b), //i--
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.sum_0(sum_0[56:63]), //i--
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.sum_1(sum_1[56:63]), //i--
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.sum(sum[56:63]) //o--
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);
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endmodule
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