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167 lines
6.0 KiB
Verilog
167 lines
6.0 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//********************************************************************
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//*
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//* TITLE: Performance Event Mux Component - 1 Thread; 4 bits
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//*
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//* NAME: tri_event_mux1t.v
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//*
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//********************************************************************
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module tri_event_mux1t(
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vd,
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gd,
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select_bits,
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unit_events_in,
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event_bus_in,
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event_bus_out
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);
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parameter EVENTS_IN = 32; // Valid Settings: 16; 32; 64
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parameter EVENTS_OUT = 4; // Valid Settings: 4 outputs per event mux
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// Select bit size depends on total events: 16 events=16, 32 events=20; 64 events=24
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input [0:((EVENTS_IN/32+4)*EVENTS_OUT)-1] select_bits;
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input [1:EVENTS_IN-1] unit_events_in;
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input [0:EVENTS_OUT-1] event_bus_in;
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output [0:EVENTS_OUT-1] event_bus_out;
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inout vd;
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inout gd;
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//=====================================================================
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// Signal and Function Declarations
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//=====================================================================
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// Constants used to split up select_bits for the decoder
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// Mux Size: 16 32 64
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parameter INCR = EVENTS_IN/32 + 4; // INCR: 4 5 6
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// For each output bit decode select bits to select an input mux to use.
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wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxDec;
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wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxOut;
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// Paramaterized decoder function - decode mux value based on input select_bits
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// Input size based on EVENTS_IN parameter: 16=4, 32=5, 64=6
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function [0:EVENTS_IN-1] decode_a;
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input [0:INCR-1] decode_input;
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//(* analysis_not_referenced="true" *)
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integer i;
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for(i=0; i<EVENTS_IN; i=i+1)
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begin
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if({{32-INCR{1'b0}},decode_input} == i)
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decode_a[i] = 1'b1;
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else
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decode_a[i] = 1'b0;
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end
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endfunction
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//=====================================================================
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// Start of event mux
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//=====================================================================
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// For each output bit, decode its select_bits to select the input mux it's using
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generate
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begin : xhdl0
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genvar X;
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for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
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begin : decode
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if (EVENTS_IN == 16)
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begin : Mux16 // 4to16 decode; select_bits(0:3, 4:7, 8:11, 12:15 ) per output bit
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assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 15] = decode_a(select_bits[X * INCR:X * INCR + 3]);
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end
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if (EVENTS_IN == 32)
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begin : Mux32 // 5to32 decode; select_bits(0:4, 5:9, 10:14, 15:19 ) per output bit
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assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 31] = decode_a(select_bits[X * INCR:X * INCR + 4]);
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end
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if (EVENTS_IN == 64)
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begin : Mux64 // 6to64 decode; select_bits(0:5, 6:11, 12:17, 18:23 ) per output bit
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assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 63] = decode_a(select_bits[X * INCR:X * INCR + 5]);
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end
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end
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end
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endgenerate
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// For each output bit, inMux decodes gate the selected unit event input; or event_bus_in when decode=0
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generate
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begin : xhdl2
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genvar X;
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for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
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begin : inpMux
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assign inMuxOut[X * EVENTS_IN + 0] = (inMuxDec[X * EVENTS_IN + 0] & event_bus_in[X]) ;
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begin : xhdl1
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genvar I;
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for (I = 1; I <= EVENTS_IN - 1; I = I + 1)
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begin : eventSel
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assign inMuxOut[X * EVENTS_IN + I] = (inMuxDec[X * EVENTS_IN + I] & unit_events_in[I]) ;
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end
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end
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end
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end
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endgenerate
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// ORing the input mux outputs to drive each event output bit.
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// Only one selected at a time by each output bit's inMux decode value.
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generate
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begin : xhdl5
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genvar X;
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for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
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begin : bitOutHi
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if (EVENTS_IN == 16)
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begin : Mux16
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assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 15]);
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end
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if (EVENTS_IN == 32)
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begin : Mux32
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assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 31]);
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end
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if (EVENTS_IN == 64)
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begin : Mux64
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assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 63]);
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end
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end
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end
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endgenerate
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endmodule
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