159 lines
5.3 KiB
Verilog
159 lines
5.3 KiB
Verilog
// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Tri-Lam Array Wrapper
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//
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//*****************************************************************************
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// sim version, clk1x
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`include "tri_a2o.vh"
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module tri_144x78_2r4w (
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// Inputs
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// Power
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inout vdd,
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inout gnd,
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// Clock & Scan
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input clk,
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input rst,
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input func_slp_sl_force,
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input func_slp_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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//-------------------------------------------------------------------
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// Read Port
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//-------------------------------------------------------------------
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input r_late_en_1,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
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output [64-`GPR_WIDTH:77] r_data_out_1,
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input r_late_en_2,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
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output [64-`GPR_WIDTH:77] r_data_out_2,
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//-------------------------------------------------------------------
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// Write Port
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//-------------------------------------------------------------------
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input w_late_en_1,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
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input [64-`GPR_WIDTH:77] w_data_in_1,
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input w_late_en_2,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
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input [64-`GPR_WIDTH:77] w_data_in_2,
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input w_late_en_3,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
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input [64-`GPR_WIDTH:77] w_data_in_3,
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input w_late_en_4,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
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input [64-`GPR_WIDTH:77] w_data_in_4
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);
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wire unused;
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// sim array
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reg [64-`GPR_WIDTH:77] mem[0:143];
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reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d;
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reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d;
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reg [64-`GPR_WIDTH:77] r1d_q;
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wire [64-`GPR_WIDTH:77] r1d_d;
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reg [64-`GPR_WIDTH:77] r2d_q;
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wire [64-`GPR_WIDTH:77] r2d_d;
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integer i;
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initial begin
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for (i = 0; i < 144; i = i + 1)
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mem[i] = 0;
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end
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//wtf:icarus $dumpvars cannot dump a vpiMemory
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generate
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genvar j;
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for (j = 0; j < 144; j=j+1) begin: loc
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wire [64-`GPR_WIDTH:63] dat;
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wire [0:7] par;
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// 4b0
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assign dat = mem[j][64-`GPR_WIDTH:63];
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assign par = mem[j][64:63 + `GPR_WIDTH/8];
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end
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endgenerate
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assign r1a_d = r_addr_in_1;
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assign r2a_d = r_addr_in_2;
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always @(posedge clk) begin
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r1a_q <= r1a_d;
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r2a_q <= r2a_d;
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r1d_q <= r1d_d;
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r2d_q <= r2d_d;
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if (w_late_en_1) begin
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mem[w_addr_in_1] <= w_data_in_1;
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end
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if (w_late_en_2) begin
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mem[w_addr_in_2] <= w_data_in_2;
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end
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if (w_late_en_3) begin
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mem[w_addr_in_3] <= w_data_in_3;
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end
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if (w_late_en_4) begin
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mem[w_addr_in_4] <= w_data_in_4;
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end
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end
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// r_late_en_x are unused in original also
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assign r1d_d = mem[r1a_q];
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assign r2d_d = mem[r2a_q];
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assign r_data_out_1 = r1d_q;
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assign r_data_out_2 = r2d_q;
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assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b};
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endmodule
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