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497 lines
20 KiB
Verilog
497 lines
20 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//
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// Description: XU LSU Store Data Rotator Wrapper
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module lq_ldq_rot(
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ldq_rel1_stg_act,
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ldq_rel1_rot_sel1,
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ldq_rel1_rot_sel2,
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ldq_rel1_rot_sel3,
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ldq_rel1_data,
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ldq_rel1_opsize,
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ldq_rel1_byte_swap,
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ldq_rel1_algebraic,
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ldq_rel1_algebraic_sel,
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ldq_rel1_gpr_val,
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ldq_rel1_dvc1_en,
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ldq_rel1_dvc2_en,
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ldq_rel2_thrd_id,
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ctl_lsq_spr_dvc1_dbg,
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ctl_lsq_spr_dvc2_dbg,
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ctl_lsq_spr_dbcr2_dvc1be,
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ctl_lsq_spr_dbcr2_dvc1m,
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ctl_lsq_spr_dbcr2_dvc2be,
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ctl_lsq_spr_dbcr2_dvc2m,
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ldq_rel2_rot_data,
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ldq_rel2_dvc,
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vdd,
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gnd,
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nclk,
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sg_0,
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func_sl_thold_0_b,
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func_sl_force,
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d_mode_dc,
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delay_lclkr_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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scan_in,
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scan_out
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);
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//-------------------------------------------------------------------
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// Generics
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//-------------------------------------------------------------------
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//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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//parameter `GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit
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//parameter `THREADS = 2; // Number of `THREADS
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// ACT
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input ldq_rel1_stg_act;
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// Reload Rotator Control
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input [0:7] ldq_rel1_rot_sel1;
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input [0:7] ldq_rel1_rot_sel2;
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input [0:7] ldq_rel1_rot_sel3;
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input [0:127] ldq_rel1_data;
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// Reload Data Fixup Control
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input [0:2] ldq_rel1_opsize;
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input ldq_rel1_byte_swap;
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input ldq_rel1_algebraic;
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input [0:3] ldq_rel1_algebraic_sel;
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input ldq_rel1_gpr_val;
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input ldq_rel1_dvc1_en;
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input ldq_rel1_dvc2_en;
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input [0:`THREADS-1] ldq_rel2_thrd_id;
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// Data Value Compare Registers
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input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc1_dbg;
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input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc2_dbg;
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input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1be;
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input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1m;
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input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2be;
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input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2m;
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// Reload Rotator Output
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output [0:127] ldq_rel2_rot_data;
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output [0:1] ldq_rel2_dvc;
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// Pervasive
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inout vdd;
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inout gnd;
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(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
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input [0:`NCLK_WIDTH-1] nclk;
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input sg_0;
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input func_sl_thold_0_b;
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input func_sl_force;
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input d_mode_dc;
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input delay_lclkr_dc;
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input mpw1_dc_b;
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input mpw2_dc_b;
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(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
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input scan_in;
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(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
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output scan_out;
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//--------------------------
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// components
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//--------------------------
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//--------------------------
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// signals
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//--------------------------
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wire [0:127] rel1_data_swzl;
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wire [0:127] rel1_rot_data;
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wire [0:15] be_byte_bit0;
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wire [0:15] le_byte_bit0;
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wire [0:15] rel1_alg_byte;
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wire rel1_alg_bit;
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wire [0:4] rel1_1hot_opsize;
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wire [0:7] rel1_byte_mask;
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wire [0:((2**`GPR_WIDTH_ENC)-1)/8] rel2_byte_mask_d;
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wire [0:((2**`GPR_WIDTH_ENC)-1)/8] rel2_byte_mask_q;
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wire [0:15] rel1_bittype_mask;
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wire [0:127] rel1_optype_mask;
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wire [0:127] rel1_msk_data;
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wire lh_algebraic;
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wire lw_algebraic;
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wire [0:47] lh_algebraic_msk;
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wire [0:47] lw_algebraic_msk;
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wire [0:47] rel1_algebraic_msk;
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wire [0:127] rel1_algebraic_msk_data;
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wire [0:127] rel1_swzl_data;
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wire [0:127] rel2_rot_data_d;
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wire [0:127] rel2_rot_data_q;
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wire rel2_dvc1_val_d;
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wire rel2_dvc1_val_q;
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wire rel2_dvc2_val_d;
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wire rel2_dvc2_val_q;
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wire [0:((2**`GPR_WIDTH_ENC)/8)-1] rel2_dvc1_cmp;
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wire [0:((2**`GPR_WIDTH_ENC)/8)-1] rel2_dvc2_cmp;
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wire rel2_dvc1r_cmpr;
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wire rel2_dvc2r_cmpr;
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reg [0:1] spr_dbcr2_dvc1m;
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reg [0:1] spr_dbcr2_dvc2m;
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reg [8-(2**`GPR_WIDTH_ENC)/8:7] spr_dbcr2_dvc1be;
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reg [8-(2**`GPR_WIDTH_ENC)/8:7] spr_dbcr2_dvc2be;
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wire [0:7] ctl_lsq_spr_dbcr2_dvc1be_int[0:`THREADS-1];
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wire [0:1] ctl_lsq_spr_dbcr2_dvc1m_int[0:`THREADS-1];
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wire [0:7] ctl_lsq_spr_dbcr2_dvc2be_int[0:`THREADS-1];
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wire [0:1] ctl_lsq_spr_dbcr2_dvc2m_int[0:`THREADS-1];
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//--------------------------
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// constants
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//--------------------------
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parameter rel2_byte_mask_offset = 0;
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parameter rel2_rot_data_offset = rel2_byte_mask_offset + (((2**`GPR_WIDTH_ENC)-1)/8-0+1);
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parameter rel2_dvc1_val_offset = rel2_rot_data_offset + 128;
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parameter rel2_dvc2_val_offset = rel2_dvc1_val_offset + 1;
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parameter scan_right = rel2_dvc2_val_offset + 1 - 1;
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wire tiup;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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assign tiup = 1'b1;
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// #############################################################################################
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// 16 Byte Reload Rotator
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// #############################################################################################
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// Thread Unpack
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generate begin : sprTid
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genvar tid;
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for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
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assign ctl_lsq_spr_dbcr2_dvc1be_int[tid] = ctl_lsq_spr_dbcr2_dvc1be[8*tid:8*(tid+1)-1];
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assign ctl_lsq_spr_dbcr2_dvc1m_int[tid] = ctl_lsq_spr_dbcr2_dvc1m[2*tid:2*(tid+1)-1];
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assign ctl_lsq_spr_dbcr2_dvc2be_int[tid] = ctl_lsq_spr_dbcr2_dvc2be[8*tid:8*(tid+1)-1];
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assign ctl_lsq_spr_dbcr2_dvc2m_int[tid] = ctl_lsq_spr_dbcr2_dvc2m[2*tid:2*(tid+1)-1];
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end
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end
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endgenerate
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// Swizzle Rotate Data
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generate begin : swzlRelData
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genvar t;
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for (t=0; t<8; t=t+1) begin : swzlRelData
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assign rel1_data_swzl[t*16:(t*16)+15] = {ldq_rel1_data[t+0], ldq_rel1_data[t+8], ldq_rel1_data[t+16], ldq_rel1_data[t+24],
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ldq_rel1_data[t+32], ldq_rel1_data[t+40], ldq_rel1_data[t+48], ldq_rel1_data[t+56],
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ldq_rel1_data[t+64], ldq_rel1_data[t+72], ldq_rel1_data[t+80], ldq_rel1_data[t+88],
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ldq_rel1_data[t+96], ldq_rel1_data[t+104], ldq_rel1_data[t+112], ldq_rel1_data[t+120]};
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end
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end
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endgenerate
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// Reload Data Rotate
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generate begin : rrotl
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genvar b;
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for (b=0; b<8; b=b+1) begin : rrotl
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tri_rot16_lu drotl(
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// Rotator Controls and Data
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.rot_sel1(ldq_rel1_rot_sel1),
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.rot_sel2(ldq_rel1_rot_sel2),
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.rot_sel3(ldq_rel1_rot_sel3),
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.rot_data(rel1_data_swzl[b*16:(b*16)+15]),
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// Rotated Data
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.data_rot(rel1_rot_data[b*16:(b*16)+15]),
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// Pervasive
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.vdd(vdd),
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.gnd(gnd)
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);
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end
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end
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endgenerate
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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// Reload Algebraic Bit Select
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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assign be_byte_bit0 = {ldq_rel1_data[0], ldq_rel1_data[8], ldq_rel1_data[16], ldq_rel1_data[24],
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ldq_rel1_data[32], ldq_rel1_data[40], ldq_rel1_data[48], ldq_rel1_data[56],
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ldq_rel1_data[64], ldq_rel1_data[72], ldq_rel1_data[80], ldq_rel1_data[88],
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ldq_rel1_data[96], ldq_rel1_data[104], ldq_rel1_data[112], ldq_rel1_data[120]};
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assign le_byte_bit0 = {ldq_rel1_data[120], ldq_rel1_data[112], ldq_rel1_data[104], ldq_rel1_data[96],
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ldq_rel1_data[88], ldq_rel1_data[80], ldq_rel1_data[72], ldq_rel1_data[64],
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ldq_rel1_data[56], ldq_rel1_data[48], ldq_rel1_data[40], ldq_rel1_data[32],
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ldq_rel1_data[24], ldq_rel1_data[16], ldq_rel1_data[8], ldq_rel1_data[0]};
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// Select between little endian data or big-endian data
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assign rel1_alg_byte = ldq_rel1_byte_swap ? le_byte_bit0 : be_byte_bit0;
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// Algebraic Bit Select
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assign rel1_alg_bit = (ldq_rel1_algebraic_sel == 4'b0000) ? rel1_alg_byte[0] :
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(ldq_rel1_algebraic_sel == 4'b0001) ? rel1_alg_byte[1] :
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(ldq_rel1_algebraic_sel == 4'b0010) ? rel1_alg_byte[2] :
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(ldq_rel1_algebraic_sel == 4'b0011) ? rel1_alg_byte[3] :
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(ldq_rel1_algebraic_sel == 4'b0100) ? rel1_alg_byte[4] :
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(ldq_rel1_algebraic_sel == 4'b0101) ? rel1_alg_byte[5] :
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(ldq_rel1_algebraic_sel == 4'b0110) ? rel1_alg_byte[6] :
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(ldq_rel1_algebraic_sel == 4'b0111) ? rel1_alg_byte[7] :
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(ldq_rel1_algebraic_sel == 4'b1000) ? rel1_alg_byte[8] :
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(ldq_rel1_algebraic_sel == 4'b1001) ? rel1_alg_byte[9] :
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(ldq_rel1_algebraic_sel == 4'b1010) ? rel1_alg_byte[10] :
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(ldq_rel1_algebraic_sel == 4'b1011) ? rel1_alg_byte[11] :
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(ldq_rel1_algebraic_sel == 4'b1100) ? rel1_alg_byte[12] :
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(ldq_rel1_algebraic_sel == 4'b1101) ? rel1_alg_byte[13] :
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(ldq_rel1_algebraic_sel == 4'b1110) ? rel1_alg_byte[14] :
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rel1_alg_byte[15];
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// #############################################################################################
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// Op Size Mask Generation for Reloads
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// #############################################################################################
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assign rel1_1hot_opsize = (ldq_rel1_opsize == 3'b110) ? 5'b10000 : // 16Bytes
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(ldq_rel1_opsize == 3'b101) ? 5'b01000 : // 8Bytes
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(ldq_rel1_opsize == 3'b100) ? 5'b00100 : // 4Bytes
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(ldq_rel1_opsize == 3'b010) ? 5'b00010 : // 2Bytes
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(ldq_rel1_opsize == 3'b001) ? 5'b00001 : // 1Bytes
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5'b00000;
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// Reload DVC Compare Byte Valid Generation
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assign rel1_byte_mask = (8'h01 & {8{rel1_1hot_opsize[4]}}) | (8'h03 & {8{rel1_1hot_opsize[3]}}) |
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(8'h0F & {8{rel1_1hot_opsize[2]}}) | (8'hFF & {8{rel1_1hot_opsize[1]}});
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assign rel2_byte_mask_d = rel1_byte_mask[(8 - ((2 ** `GPR_WIDTH_ENC)/8)):7];
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// Reload Bit Mask Generation
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assign rel1_bittype_mask = (16'h0001 & {16{rel1_1hot_opsize[4]}}) | (16'h0003 & {16{rel1_1hot_opsize[3]}}) |
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(16'h000F & {16{rel1_1hot_opsize[2]}}) | (16'h00FF & {16{rel1_1hot_opsize[1]}}) |
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(16'hFFFF & {16{rel1_1hot_opsize[0]}});
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generate begin : maskGen
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genvar b;
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for (b=0; b <8; b=b+1) begin : maskGen
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assign rel1_optype_mask[b*16:(b*16)+15] = rel1_bittype_mask;
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end
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end
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endgenerate
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assign rel1_msk_data = rel1_rot_data & rel1_optype_mask;
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// Reload Algebraic Sign Extension
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assign lh_algebraic = rel1_1hot_opsize[3] & ldq_rel1_algebraic;
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assign lw_algebraic = rel1_1hot_opsize[2] & ldq_rel1_algebraic;
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assign lh_algebraic_msk = {48{rel1_alg_bit}};
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assign lw_algebraic_msk = {{32{rel1_alg_bit}}, 16'h0000};
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assign rel1_algebraic_msk = (lh_algebraic_msk & {48{lh_algebraic}}) | (lw_algebraic_msk & {48{lw_algebraic}});
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// Swizzle Data to a proper format
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generate begin : swzlData
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genvar t;
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for (t=0; t<16; t=t+1) begin : swzlData
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assign rel1_swzl_data[t*8:(t*8)+7] = {rel1_msk_data[t], rel1_msk_data[t+16], rel1_msk_data[t+32], rel1_msk_data[t+48],
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rel1_msk_data[t+64], rel1_msk_data[t+80], rel1_msk_data[t+96], rel1_msk_data[t+112]};
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end
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end
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endgenerate
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assign rel1_algebraic_msk_data = {rel1_swzl_data[0:63], (rel1_swzl_data[64:111] | rel1_algebraic_msk), rel1_swzl_data[112:127]};
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assign rel2_rot_data_d = rel1_algebraic_msk_data;
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// #############################################################################################
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// RELOAD DEBUG Data Compare
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// #############################################################################################
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assign rel2_dvc1_val_d = ldq_rel1_gpr_val & ldq_rel1_dvc1_en;
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assign rel2_dvc2_val_d = ldq_rel1_gpr_val & ldq_rel1_dvc2_en;
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// Reload Data Compare
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generate begin : dvcCmpRl
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genvar t;
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for (t = 0; t <= ((2 ** `GPR_WIDTH_ENC)/8) - 1; t = t + 1) begin : dvcCmpRl
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assign rel2_dvc1_cmp[t] = (rel2_rot_data_q[(128 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(128 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)] ==
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ctl_lsq_spr_dvc1_dbg[(64 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(64 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)]) & rel2_byte_mask_q[t];
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assign rel2_dvc2_cmp[t] = (rel2_rot_data_q[(128 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(128 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)] ==
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ctl_lsq_spr_dvc2_dbg[(64 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(64 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)]) & rel2_byte_mask_q[t];
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end
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end
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endgenerate
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// Thread Select
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always @(*) begin: relTid
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reg [0:1] dvc1m;
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reg [0:1] dvc2m;
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reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc1be;
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reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc2be;
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//(* analysis_not_referenced="true" *)
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integer tid;
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dvc1m = {2{1'b0}};
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dvc2m = {2{1'b0}};
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dvc1be = {(2**`GPR_WIDTH_ENC)/8{1'b0}};
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dvc2be = {(2**`GPR_WIDTH_ENC)/8{1'b0}};
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for (tid=0; tid<`THREADS; tid=tid+1) begin
|
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dvc1m = (ctl_lsq_spr_dbcr2_dvc1m_int[tid] & { 2{ldq_rel2_thrd_id[tid]}}) | dvc1m;
|
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dvc2m = (ctl_lsq_spr_dbcr2_dvc2m_int[tid] & { 2{ldq_rel2_thrd_id[tid]}}) | dvc2m;
|
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dvc1be = (ctl_lsq_spr_dbcr2_dvc1be_int[tid][8-(2**`GPR_WIDTH_ENC)/8:7] & {(2**`GPR_WIDTH_ENC)/8{ldq_rel2_thrd_id[tid]}}) | dvc1be;
|
|
dvc2be = (ctl_lsq_spr_dbcr2_dvc2be_int[tid][8-(2**`GPR_WIDTH_ENC)/8:7] & {(2**`GPR_WIDTH_ENC)/8{ldq_rel2_thrd_id[tid]}}) | dvc2be;
|
|
end
|
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spr_dbcr2_dvc1m = dvc1m;
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spr_dbcr2_dvc2m = dvc2m;
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spr_dbcr2_dvc1be = dvc1be;
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|
spr_dbcr2_dvc2be = dvc2be;
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|
end
|
|
|
|
|
|
lq_spr_dvccmp #(.REGSIZE(2**`GPR_WIDTH_ENC)) dvc1Rel(
|
|
.en(rel2_dvc1_val_q),
|
|
.en00(1'b0),
|
|
.cmp(rel2_dvc1_cmp),
|
|
.dvcm(spr_dbcr2_dvc1m),
|
|
.dvcbe(spr_dbcr2_dvc1be),
|
|
.dvc_cmpr(rel2_dvc1r_cmpr)
|
|
);
|
|
|
|
|
|
lq_spr_dvccmp #(.REGSIZE(2**`GPR_WIDTH_ENC)) dvc2Rel(
|
|
.en(rel2_dvc2_val_q),
|
|
.en00(1'b0),
|
|
.cmp(rel2_dvc2_cmp),
|
|
.dvcm(spr_dbcr2_dvc2m),
|
|
.dvcbe(spr_dbcr2_dvc2be),
|
|
.dvc_cmpr(rel2_dvc2r_cmpr)
|
|
);
|
|
|
|
// #############################################################################################
|
|
// Outputs
|
|
// #############################################################################################
|
|
|
|
assign ldq_rel2_rot_data = rel2_rot_data_q;
|
|
assign ldq_rel2_dvc = {rel2_dvc1r_cmpr, rel2_dvc2r_cmpr};
|
|
|
|
// #############################################################################################
|
|
// Registers
|
|
// #############################################################################################
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) rel2_byte_mask_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(ldq_rel1_stg_act),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[rel2_byte_mask_offset:rel2_byte_mask_offset + ((2**`GPR_WIDTH_ENC)/8) - 1]),
|
|
.scout(sov[rel2_byte_mask_offset:rel2_byte_mask_offset + ((2**`GPR_WIDTH_ENC)/8) - 1]),
|
|
.din(rel2_byte_mask_d),
|
|
.dout(rel2_byte_mask_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) rel2_rot_data_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(ldq_rel1_stg_act),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[rel2_rot_data_offset:rel2_rot_data_offset + 128 - 1]),
|
|
.scout(sov[rel2_rot_data_offset:rel2_rot_data_offset + 128 - 1]),
|
|
.din(rel2_rot_data_d),
|
|
.dout(rel2_rot_data_q)
|
|
);
|
|
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc1_val_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[rel2_dvc1_val_offset]),
|
|
.scout(sov[rel2_dvc1_val_offset]),
|
|
.din(rel2_dvc1_val_d),
|
|
.dout(rel2_dvc1_val_q)
|
|
);
|
|
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc2_val_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[rel2_dvc2_val_offset]),
|
|
.scout(sov[rel2_dvc2_val_offset]),
|
|
.din(rel2_dvc2_val_d),
|
|
.dout(rel2_dvc2_val_q)
|
|
);
|
|
|
|
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
|
|
assign scan_out = sov[0];
|
|
|
|
endmodule
|