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191 lines
20 KiB
Verilog
191 lines
20 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// VHDL 1076 Macro Expander C version 07/11/00
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// job was run on Tue Feb 1 10:11:27 2011
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//********************************************************************
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//*
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//* TITLE:
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//*
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//* NAME: iuq_cpl_dec.v
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//*
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//*********************************************************************
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module iuq_cpl_dec(
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input [0:31] cp2_instr,
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output cp2_ld,
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output cp2_st,
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output cp2_epid);
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wire [1:7] TBL_EPID_DEC_PT;
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wire [1:41] TBL_LD_ST_PT;
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//@@ START OF EXECUTABLE CODE FOR IUQ_CPL_DEC
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//
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// Final Table Listing
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// *INPUTS*=============*OUTPUTS*=====*
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// | | |
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// | cp2_instr | cp2_epid |
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// | | cp2_instr | | |
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// | | | | | |
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// | 000000 2222222223 | | |
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// | 012345 1234567890 | | |
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// *TYPE*===============+=============+
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// | PPPPPP PPPPPPPPPP | P |
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// *POLARITY*---------->| + |
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// *PHASE*------------->| T |
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// *TERMS*==============+=============+
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// 1 | 011111 1110110110 | 1 |
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// 2 | 011111 1111-11111 | 1 |
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// 3 | 011111 00-00111-1 | 1 |
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// 4 | 011111 0-00-11111 | 1 |
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// 5 | 011111 -0-1011111 | 1 |
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// 6 | 011111 00-1-11111 | 1 |
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// 7 | 011111 0--0011111 | 1 |
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// *==================================*
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//
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// Table TBL_EPID_DEC Signal Assignments for Product Terms
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assign TBL_EPID_DEC_PT[1] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111110110110);
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assign TBL_EPID_DEC_PT[2] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111111111111);
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assign TBL_EPID_DEC_PT[3] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111100001111);
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assign TBL_EPID_DEC_PT[4] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100011111);
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assign TBL_EPID_DEC_PT[5] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[22], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101011111);
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assign TBL_EPID_DEC_PT[6] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100111111);
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assign TBL_EPID_DEC_PT[7] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100011111);
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// Table TBL_EPID_DEC Signal Assignments for Outputs
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assign cp2_epid = (TBL_EPID_DEC_PT[1] | TBL_EPID_DEC_PT[2] | TBL_EPID_DEC_PT[3] | TBL_EPID_DEC_PT[4] | TBL_EPID_DEC_PT[5] | TBL_EPID_DEC_PT[6] | TBL_EPID_DEC_PT[7]);
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//
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// Final Table Listing
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// *INPUTS*===========================*OUTPUTS*============*
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// | | |
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// | cp2_instr | |
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// | | cp2_instr | |
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// | | | cp2_instr | |
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// | | | | cp2_instr | |
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// | | | | | | cp2_ld |
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// | | | | | | | cp2_st |
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// | 000000 0 2222222223 33 | | | |
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// | 012345 9 1234567890 01 | | | |
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// *TYPE*=============================+====================+
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// | PPPPPP P PPPPPPPPPP PP | P P |
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// *POLARITY*------------------------>| + + |
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// *PHASE*--------------------------->| T T |
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// *TERMS*============================+====================+
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// 1 | 011111 - 1-10-10110 0- | . 1 |
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// 2 | 011111 - 000-01011- -- | 1 . |
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// 3 | 011111 - 0-1001011- 0- | . 1 |
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// 4 | 011111 - 101001010- -- | . 1 |
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// 5 | 011111 - -00001010- -- | 1 . |
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// 6 | 011111 - 1111111111 -- | . 1 |
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// 7 | 011111 - 0-11100110 -- | 1 . |
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// 8 | 011111 - 1111110110 -- | . 1 |
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// 9 | 011111 - 1111011111 -- | 1 . |
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// 10 | 011111 - 0101-101-1 -- | 1 . |
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// 11 | 011111 - 101-010101 -- | . 1 |
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// 12 | 011111 - 0110000110 -- | 1 . |
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// 13 | 011111 - 001-100110 -- | 1 . |
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// 14 | 011111 - 0-00-1-111 -- | 1 . |
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// 15 | 011111 - 001001-1-1 -- | . 1 |
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// 16 | 011111 - 0011-1-111 -- | . 1 |
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// 17 | 011111 - 100-010101 -- | 1 . |
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// 18 | 011111 - 00100-0110 -- | . 1 |
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// 19 | 011111 - 000001-1-1 -- | 1 . |
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// 20 | 011111 - 000--1-111 -- | 1 . |
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// 21 | 011111 - 1-10010110 -- | . 1 |
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// 22 | 011111 - 1010-10110 -- | . 1 |
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// 23 | 011111 - 1111010110 -- | 1 . |
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// 24 | 011111 - 0-1001-111 -- | . 1 |
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// 25 | 011111 - --00010110 -- | 1 . |
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// 26 | 011111 - -01-010110 -- | . 1 |
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// 27 | 011111 - 0010-101-1 -- | . 1 |
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// 28 | 011111 - 00-1010100 -- | 1 . |
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// 29 | 011111 - 0000-101-1 -- | 1 . |
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// 30 | 011111 - 0-11010110 -- | . 1 |
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// 31 | 011111 - 0-10-10111 -- | . 1 |
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// 32 | 011111 - 00111-0110 -- | 1 . |
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// 33 | 011111 - 0000-1011- -- | 1 . |
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// 34 | 10-0-- - ---------- -- | 1 . |
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// 35 | 1-1010 - ---------- -0 | 1 . |
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// 36 | 1-1010 - ---------- 0- | 1 . |
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// 37 | 10-10- - ---------- -- | . 1 |
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// 38 | 111110 - ---------- 0- | . 1 |
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// 39 | 1001-- - ---------- -- | . 1 |
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// 40 | 101-10 - ---------- -- | 1 . |
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// 41 | 10-1-1 - ---------- -- | . 1 |
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// *=======================================================*
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//
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// Table TBL_LD_ST Signal Assignments for Product Terms
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assign TBL_LD_ST_PT[1] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30], cp2_instr[30]}) === 15'b011111110101100);
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assign TBL_LD_ST_PT[2] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 14'b01111100001011);
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assign TBL_LD_ST_PT[3] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111010010110);
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assign TBL_LD_ST_PT[4] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 15'b011111101001010);
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assign TBL_LD_ST_PT[5] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 14'b01111100001010);
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assign TBL_LD_ST_PT[6] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111111111);
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assign TBL_LD_ST_PT[7] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111011100110);
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assign TBL_LD_ST_PT[8] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111110110);
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assign TBL_LD_ST_PT[9] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111011111);
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assign TBL_LD_ST_PT[10] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111101011011);
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assign TBL_LD_ST_PT[11] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111101010101);
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assign TBL_LD_ST_PT[12] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111110110000110);
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assign TBL_LD_ST_PT[13] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001100110);
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assign TBL_LD_ST_PT[14] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 13'b0111110001111);
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assign TBL_LD_ST_PT[15] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[28], cp2_instr[30]}) === 14'b01111100100111);
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assign TBL_LD_ST_PT[16] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100111111);
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assign TBL_LD_ST_PT[17] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111100010101);
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assign TBL_LD_ST_PT[18] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001000110);
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assign TBL_LD_ST_PT[19] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[28], cp2_instr[30]}) === 14'b01111100000111);
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assign TBL_LD_ST_PT[20] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 13'b0111110001111);
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assign TBL_LD_ST_PT[21] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111110010110);
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assign TBL_LD_ST_PT[22] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111101010110);
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assign TBL_LD_ST_PT[23] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111010110);
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assign TBL_LD_ST_PT[24] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101001111);
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assign TBL_LD_ST_PT[25] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100010110);
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assign TBL_LD_ST_PT[26] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101010110);
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assign TBL_LD_ST_PT[27] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111100101011);
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assign TBL_LD_ST_PT[28] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001010100);
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assign TBL_LD_ST_PT[29] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111100001011);
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assign TBL_LD_ST_PT[30] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111011010110);
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assign TBL_LD_ST_PT[31] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101010111);
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assign TBL_LD_ST_PT[32] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001110110);
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assign TBL_LD_ST_PT[33] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 14'b01111100001011);
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assign TBL_LD_ST_PT[34] = (({cp2_instr[00], cp2_instr[01], cp2_instr[03]}) === 3'b100);
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assign TBL_LD_ST_PT[35] = (({cp2_instr[00], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[31]}) === 6'b110100);
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assign TBL_LD_ST_PT[36] = (({cp2_instr[00], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[30]}) === 6'b110100);
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assign TBL_LD_ST_PT[37] = (({cp2_instr[00], cp2_instr[01], cp2_instr[03], cp2_instr[04]}) === 4'b1010);
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assign TBL_LD_ST_PT[38] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[30]}) === 7'b1111100);
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assign TBL_LD_ST_PT[39] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03]}) === 4'b1001);
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assign TBL_LD_ST_PT[40] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[04], cp2_instr[05]}) === 5'b10110);
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assign TBL_LD_ST_PT[41] = (({cp2_instr[00], cp2_instr[01], cp2_instr[03], cp2_instr[05]}) === 4'b1011);
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// Table TBL_LD_ST Signal Assignments for Outputs
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assign cp2_ld = (TBL_LD_ST_PT[2] | TBL_LD_ST_PT[5] | TBL_LD_ST_PT[7] | TBL_LD_ST_PT[9] | TBL_LD_ST_PT[10] | TBL_LD_ST_PT[12] | TBL_LD_ST_PT[13] | TBL_LD_ST_PT[14] | TBL_LD_ST_PT[17] | TBL_LD_ST_PT[19] | TBL_LD_ST_PT[20] | TBL_LD_ST_PT[23] | TBL_LD_ST_PT[25] | TBL_LD_ST_PT[28] | TBL_LD_ST_PT[29] | TBL_LD_ST_PT[32] | TBL_LD_ST_PT[33] | TBL_LD_ST_PT[34] | TBL_LD_ST_PT[35] | TBL_LD_ST_PT[36] | TBL_LD_ST_PT[40]);
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assign cp2_st = (TBL_LD_ST_PT[1] | TBL_LD_ST_PT[3] | TBL_LD_ST_PT[4] | TBL_LD_ST_PT[6] | TBL_LD_ST_PT[8] | TBL_LD_ST_PT[11] | TBL_LD_ST_PT[15] | TBL_LD_ST_PT[16] | TBL_LD_ST_PT[18] | TBL_LD_ST_PT[21] | TBL_LD_ST_PT[22] | TBL_LD_ST_PT[24] | TBL_LD_ST_PT[26] | TBL_LD_ST_PT[27] | TBL_LD_ST_PT[30] | TBL_LD_ST_PT[31] | TBL_LD_ST_PT[37] | TBL_LD_ST_PT[38] | TBL_LD_ST_PT[39] | TBL_LD_ST_PT[41]);
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endmodule
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