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107 lines
5.1 KiB
Verilog
107 lines
5.1 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_add_all1(
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ex4_inc_byt_c_b,
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ex4_inc_byt_c_glb,
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ex4_inc_byt_c_glb_b,
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ex4_inc_all1
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);
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input [0:6] ex4_inc_byt_c_b; // from each byte section
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output [1:6] ex4_inc_byt_c_glb;
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output [1:6] ex4_inc_byt_c_glb_b;
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output ex4_inc_all1;
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// ATTRIBUTE BTR_NAME OF fu_add_all1 : ENTITY IS "fu_add_all1";
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire [0:6] ex4_inc_byt_g1;
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wire [0:6] ex4_inc_byt_g2_b;
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wire [0:6] ex4_inc_byt_g4;
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wire [0:6] ex4_inc_byt_g8_b;
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wire [1:6] ex4_inc_byt_g_glb_int;
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assign ex4_inc_byt_g1[0:6] = (~ex4_inc_byt_c_b[0:6]); //expect some wire distance between latches
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// drive to a common location
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assign ex4_inc_byt_g2_b[6] = (~(ex4_inc_byt_g1[6]));
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assign ex4_inc_byt_g2_b[5] = (~(ex4_inc_byt_g1[5] & ex4_inc_byt_g1[6]));
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assign ex4_inc_byt_g2_b[4] = (~(ex4_inc_byt_g1[4] & ex4_inc_byt_g1[5]));
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assign ex4_inc_byt_g2_b[3] = (~(ex4_inc_byt_g1[3] & ex4_inc_byt_g1[4]));
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assign ex4_inc_byt_g2_b[2] = (~(ex4_inc_byt_g1[2] & ex4_inc_byt_g1[3]));
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assign ex4_inc_byt_g2_b[1] = (~(ex4_inc_byt_g1[1] & ex4_inc_byt_g1[2]));
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assign ex4_inc_byt_g2_b[0] = (~(ex4_inc_byt_g1[0] & ex4_inc_byt_g1[1]));
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assign ex4_inc_byt_g4[6] = (~(ex4_inc_byt_g2_b[6]));
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assign ex4_inc_byt_g4[5] = (~(ex4_inc_byt_g2_b[5]));
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assign ex4_inc_byt_g4[4] = (~(ex4_inc_byt_g2_b[4] | ex4_inc_byt_g2_b[6]));
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assign ex4_inc_byt_g4[3] = (~(ex4_inc_byt_g2_b[3] | ex4_inc_byt_g2_b[5]));
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assign ex4_inc_byt_g4[2] = (~(ex4_inc_byt_g2_b[2] | ex4_inc_byt_g2_b[4]));
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assign ex4_inc_byt_g4[1] = (~(ex4_inc_byt_g2_b[1] | ex4_inc_byt_g2_b[3]));
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assign ex4_inc_byt_g4[0] = (~(ex4_inc_byt_g2_b[0] | ex4_inc_byt_g2_b[2]));
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assign ex4_inc_byt_g8_b[6] = (~(ex4_inc_byt_g4[6]));
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assign ex4_inc_byt_g8_b[5] = (~(ex4_inc_byt_g4[5]));
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assign ex4_inc_byt_g8_b[4] = (~(ex4_inc_byt_g4[4]));
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assign ex4_inc_byt_g8_b[3] = (~(ex4_inc_byt_g4[3]));
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assign ex4_inc_byt_g8_b[2] = (~(ex4_inc_byt_g4[2] & ex4_inc_byt_g4[6]));
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assign ex4_inc_byt_g8_b[1] = (~(ex4_inc_byt_g4[1] & ex4_inc_byt_g4[5]));
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assign ex4_inc_byt_g8_b[0] = (~(ex4_inc_byt_g4[0] & ex4_inc_byt_g4[4]));
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assign ex4_inc_all1 = (~ex4_inc_byt_g8_b[0]);
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assign ex4_inc_byt_c_glb[1] = (~ex4_inc_byt_g8_b[1]); // drive back from common
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assign ex4_inc_byt_c_glb[2] = (~ex4_inc_byt_g8_b[2]); // drive back from common
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assign ex4_inc_byt_c_glb[3] = (~ex4_inc_byt_g8_b[3]); // drive back from common
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assign ex4_inc_byt_c_glb[4] = (~ex4_inc_byt_g8_b[4]); // drive back from common
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assign ex4_inc_byt_c_glb[5] = (~ex4_inc_byt_g8_b[5]); // drive back from common
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assign ex4_inc_byt_c_glb[6] = (~ex4_inc_byt_g8_b[6]); // drive back from common
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assign ex4_inc_byt_g_glb_int[1] = (~ex4_inc_byt_g8_b[1]);
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assign ex4_inc_byt_g_glb_int[2] = (~ex4_inc_byt_g8_b[2]);
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assign ex4_inc_byt_g_glb_int[3] = (~ex4_inc_byt_g8_b[3]);
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assign ex4_inc_byt_g_glb_int[4] = (~ex4_inc_byt_g8_b[4]);
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assign ex4_inc_byt_g_glb_int[5] = (~ex4_inc_byt_g8_b[5]);
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assign ex4_inc_byt_g_glb_int[6] = (~ex4_inc_byt_g8_b[6]);
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assign ex4_inc_byt_c_glb_b[1] = (~ex4_inc_byt_g_glb_int[1]); // drive back from common
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assign ex4_inc_byt_c_glb_b[2] = (~ex4_inc_byt_g_glb_int[2]); // drive back from common
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assign ex4_inc_byt_c_glb_b[3] = (~ex4_inc_byt_g_glb_int[3]); // drive back from common
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assign ex4_inc_byt_c_glb_b[4] = (~ex4_inc_byt_g_glb_int[4]); // drive back from common
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assign ex4_inc_byt_c_glb_b[5] = (~ex4_inc_byt_g_glb_int[5]); // drive back from common
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assign ex4_inc_byt_c_glb_b[6] = (~ex4_inc_byt_g_glb_int[6]); // drive back from common
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endmodule
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