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512 lines
21 KiB
Verilog
512 lines
21 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_256x144_8w_1r1w.v
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// *! DESCRIPTION : 256 Entry x 144 bit x 8 way array, 9 bit writeable
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// *!
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_256x144_8w_1r1w(
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gnd,
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vdd,
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vcs,
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nclk,
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rd_act,
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wr_act,
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sg_0,
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abst_sl_thold_0,
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ary_nsl_thold_0,
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time_sl_thold_0,
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repr_sl_thold_0,
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func_sl_force,
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func_sl_thold_0_b,
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g8t_clkoff_dc_b,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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g8t_d_mode_dc,
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g8t_mpw1_dc_b,
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g8t_mpw2_dc_b,
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g8t_delay_lclkr_dc,
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d_mode_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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delay_lclkr_dc,
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wr_abst_act,
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rd0_abst_act,
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abist_di,
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abist_bw_odd,
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abist_bw_even,
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abist_wr_adr,
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abist_rd0_adr,
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tc_lbist_ary_wrt_thru_dc,
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abist_ena_1,
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abist_g8t_rd0_comp_ena,
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abist_raw_dc_b,
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obs0_abist_cmp,
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abst_scan_in,
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time_scan_in,
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repr_scan_in,
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func_scan_in,
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abst_scan_out,
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time_scan_out,
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repr_scan_out,
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func_scan_out,
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lcb_bolt_sl_thold_0,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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wr_way,
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wr_addr,
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data_in0,
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data_in1,
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rd_addr,
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data_out
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);
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parameter addressable_ports = 256; // number of addressable register in this array
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parameter addressbus_width = 8; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
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parameter port_bitwidth = 144; // bitwidth of ports (per way)
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parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array
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parameter ways = 8; // number of ways
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// POWER PINS
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inout gnd;
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inout vdd;
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inout vcs;
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// CLOCK and CLOCKCONTROL ports
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input [0:`NCLK_WIDTH-1] nclk;
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input [0:7] rd_act;
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input [0:7] wr_act;
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input sg_0;
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input abst_sl_thold_0;
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input ary_nsl_thold_0;
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input time_sl_thold_0;
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input repr_sl_thold_0;
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input func_sl_force;
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input func_sl_thold_0_b;
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input g8t_clkoff_dc_b;
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input ccflush_dc;
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input scan_dis_dc_b;
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input scan_diag_dc;
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input g8t_d_mode_dc;
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input [0:4] g8t_mpw1_dc_b;
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input g8t_mpw2_dc_b;
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input [0:4] g8t_delay_lclkr_dc;
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input d_mode_dc;
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input mpw1_dc_b;
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input mpw2_dc_b;
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input delay_lclkr_dc;
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// ABIST
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input wr_abst_act;
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input rd0_abst_act;
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input [0:3] abist_di;
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input abist_bw_odd;
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input abist_bw_even;
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input [0:addressbus_width-1] abist_wr_adr;
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input [0:addressbus_width-1] abist_rd0_adr;
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input tc_lbist_ary_wrt_thru_dc;
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input abist_ena_1;
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input abist_g8t_rd0_comp_ena;
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input abist_raw_dc_b;
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input [0:3] obs0_abist_cmp;
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// SCAN
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input [0:3] abst_scan_in;
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input time_scan_in;
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input repr_scan_in;
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input [0:3] func_scan_in;
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output [0:3] abst_scan_out;
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output time_scan_out;
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output repr_scan_out;
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output [0:3] func_scan_out;
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// BOLT-ON
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input lcb_bolt_sl_thold_0;
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input pc_bo_enable_2; // general bolt-on enable
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input pc_bo_reset; // reset
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input pc_bo_unload; // unload sticky bits
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input pc_bo_repair; // execute sticky bit decode
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input pc_bo_shdata; // shift data for timing write and diag loop
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input [0:3] pc_bo_select; // select for mask and hier writes
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output [0:3] bo_pc_failout; // fail/no-fix reg
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output [0:3] bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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// FUNCTIONAL PORTS
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input [0:ways-1] wr_way;
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input [0:(addressbus_width-1)] wr_addr;
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input [0:(port_bitwidth-1)] data_in0;
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input [0:(port_bitwidth-1)] data_in1;
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input [0:(addressbus_width-1)] rd_addr;
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output [0:(port_bitwidth*ways-1)] data_out;
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parameter ramb_base_addr = 16;
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parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
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parameter numBytes = (dataWidth/9);
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parameter addresswidth = addressbus_width;
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parameter rd_act_offset = 0;
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parameter data_out_offset = rd_act_offset + ways;
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parameter scan_right = data_out_offset + (port_bitwidth*ways) - 1;
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wire [0:dataWidth] data_in0_pad;
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wire [0:dataWidth] data_in1_pad;
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wire [0:dataWidth] data_in_swzl[0:ways-1];
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wire [0:dataWidth] p0_data_out_pad[0:ways-1];
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wire [0:dataWidth] p1_data_out_pad[0:ways-1];
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wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_in[0:ways-1];
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wire [0:(dataWidth)/9] p0_arr_par_in[0:ways-1];
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wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_in[0:ways-1];
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wire [0:(dataWidth)/9] p1_arr_par_in[0:ways-1];
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wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_out[0:ways-1];
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wire [0:(dataWidth)/9] p0_arr_par_out[0:ways-1];
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wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_out[0:ways-1];
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wire [0:(dataWidth)/9] p1_arr_par_out[0:ways-1];
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wire [0:ramb_base_addr-1] ramb_rd_addr;
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wire [0:ramb_base_addr-1] ramb_wr_addr;
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wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p0_wayEn[0:ways-1];
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wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p1_wayEn[0:ways-1];
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wire [0:(port_bitwidth*ways-1)] p0_data_out_swzl;
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wire [0:(port_bitwidth*ways-1)] p1_data_out_swzl;
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wire [0:(port_bitwidth*ways-1)] data_out_fix;
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wire [0:((port_bitwidth-1)/36)] cascadeoutlata;
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wire [0:((port_bitwidth-1)/36)] cascadeoutlatb;
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wire [0:((port_bitwidth-1)/36)] cascadeoutrega;
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wire [0:((port_bitwidth-1)/36)] cascadeoutregb;
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wire [0:ways-1] rd_act_d;
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wire [0:ways-1] rd_act_q;
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wire [0:(port_bitwidth*ways)-1] data_out_d;
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wire [0:(port_bitwidth*ways)-1] data_out_b_q;
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wire [0:ways-1] my_d1clk;
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wire [0:ways-1] my_d2clk;
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wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1];
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wire tiup;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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(* analysis_not_referenced="true" *)
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wire unused;
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generate
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// Read/Write Port Address Generate
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assign ramb_rd_addr[11:15] = 5'b0;
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assign ramb_wr_addr[11:15] = 5'b0;
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assign rd_act_d = rd_act;
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assign tiup = 1'b1;
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genvar bb;
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genvar way;
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genvar b;
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for (bb = 0; bb <= numBytes; bb = bb + 1) begin : swzl
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for (way = 0; way < ways; way = way + 1) begin : perWay
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if (way < (ways/2)) begin : fhalf
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assign data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = {data_in0_pad[bb + (0 * (numBytes + 1))], data_in0_pad[bb + (1 * (numBytes + 1))],
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data_in0_pad[bb + (2 * (numBytes + 1))], data_in0_pad[bb + (3 * (numBytes + 1))],
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data_in0_pad[bb + (4 * (numBytes + 1))], data_in0_pad[bb + (5 * (numBytes + 1))],
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data_in0_pad[bb + (6 * (numBytes + 1))], data_in0_pad[bb + (7 * (numBytes + 1))]};
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assign data_in_swzl[way][(((bb * 8) + bb) + 8)] = data_in0_pad[bb + (8 * (numBytes + 1))];
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end
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if (way >= (ways/2)) begin : shalf
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assign data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = {data_in1_pad[bb + (0 * (numBytes + 1))], data_in1_pad[bb + (1 * (numBytes + 1))],
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data_in1_pad[bb + (2 * (numBytes + 1))], data_in1_pad[bb + (3 * (numBytes + 1))],
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data_in1_pad[bb + (4 * (numBytes + 1))], data_in1_pad[bb + (5 * (numBytes + 1))],
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data_in1_pad[bb + (6 * (numBytes + 1))], data_in1_pad[bb + (7 * (numBytes + 1))]};
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assign data_in_swzl[way][(((bb * 8) + bb) + 8)] = data_in1_pad[bb + (8 * (numBytes + 1))];
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end
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end
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end
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genvar t;
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for (t = 0; t < 11; t = t + 1) begin : rambAddrCalc
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if (t < (11-addresswidth)) begin
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assign ramb_rd_addr[t] = 1'b0;
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assign ramb_wr_addr[t] = 1'b0;
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end
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if (t >= (11-addresswidth)) begin
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assign ramb_rd_addr[t] = rd_addr[t - (11 - addresswidth)];
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assign ramb_wr_addr[t] = wr_addr[t - (11 - addresswidth)];
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end
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end
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for (b = 0; b <= dataWidth; b = b + 1) begin : dFixUp
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if (b < port_bitwidth) begin
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assign data_in0_pad[b] = data_in0[b];
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assign data_in1_pad[b] = data_in1[b];
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end
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if (b >= port_bitwidth) begin
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assign data_in0_pad[b] = 1'b0;
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assign data_in1_pad[b] = 1'b0;
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end
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end
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//genvar way;
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for (way = 0; way < ways; way = way + 1) begin : NwayDatInFix
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//genvar bb;
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for (bb = 0; bb <= (dataWidth)/9; bb = bb + 1) begin : dFixUp
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assign p0_arr_data_in[way][bb * 8:(bb * 8) + 7] = 8'h00;
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assign p0_arr_par_in[way][bb] = 1'b0;
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assign p1_arr_data_in[way][bb * 8:(bb * 8) + 7] = data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)];
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assign p1_arr_par_in[way][bb] = data_in_swzl[way][(((bb * 8) + bb) + 8)];
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end
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end
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//genvar way;
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for (way = 0; way < ways; way = way + 1) begin : NwayDatOutFix
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//genvar bb;
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for (bb = 0; bb <= (dataWidth)/9; bb = bb + 1) begin : dFixUp
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assign p0_data_out_pad[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = p0_arr_data_out[way][bb * 8:(bb * 8) + 7];
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assign p0_data_out_pad[way][(((bb * 8) + bb) + 8)] = p0_arr_par_out[way][bb];
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assign p1_data_out_pad[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = p1_arr_data_out[way][bb * 8:(bb * 8) + 7];
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assign p1_data_out_pad[way][(((bb * 8) + bb) + 8)] = p1_arr_par_out[way][bb];
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end
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end
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//genvar way;
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for (way = 0; way < ways; way = way + 1) begin : NwayDatOut
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assign p0_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p0_data_out_pad[way][0:port_bitwidth - 1];
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assign p1_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p1_data_out_pad[way][0:port_bitwidth - 1];
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//genvar bb;
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for (bb = 0; bb <= numBytes; bb = bb + 1) begin : swzl
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assign data_out_fix[(way * port_bitwidth) + (0 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 0];
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assign data_out_fix[(way * port_bitwidth) + (1 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 1];
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assign data_out_fix[(way * port_bitwidth) + (2 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 2];
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assign data_out_fix[(way * port_bitwidth) + (3 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 3];
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assign data_out_fix[(way * port_bitwidth) + (4 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 4];
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assign data_out_fix[(way * port_bitwidth) + (5 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 5];
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assign data_out_fix[(way * port_bitwidth) + (6 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 6];
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assign data_out_fix[(way * port_bitwidth) + (7 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 7];
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assign data_out_fix[(way * port_bitwidth) + (8 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 8];
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end
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end
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assign data_out_d = data_out_fix;
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assign data_out = ~data_out_b_q;
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//genvar way;
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for (way = 0; way < ways; way = way + 1) begin : Nways
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//genvar bb;
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for (bb = 0; bb < ((((port_bitwidth - 1)/36) + 1) * 4); bb = bb + 1) begin : BEn
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if (bb <= (port_bitwidth - 1)/9) begin
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assign p0_wayEn[way][bb] = 1'b0;
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assign p1_wayEn[way][bb] = wr_way[way];
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end
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if (bb > (port_bitwidth - 1)/9) begin
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assign p0_wayEn[way][bb] = 1'b0;
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assign p1_wayEn[way][bb] = 1'b0;
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end
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end
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// Port A => Read Port
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// Port B => Write Port
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genvar arr;
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for (arr = 0; arr <= ((port_bitwidth - 1)/36); arr = arr + 1) begin : Narrs
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RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) wayArr(
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.CASCADEOUTLATA(cascadeoutlata[arr]),
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.CASCADEOUTLATB(cascadeoutlatb[arr]),
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.CASCADEOUTREGA(cascadeoutrega[arr]),
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.CASCADEOUTREGB(cascadeoutregb[arr]),
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.DOA(p0_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]),
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.DOB(p1_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]),
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.DOPA(p0_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]),
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.DOPB(p1_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]),
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.ADDRA(ramb_rd_addr),
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.ADDRB(ramb_wr_addr),
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.CASCADEINLATA(1'b0),
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.CASCADEINLATB(1'b0),
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.CASCADEINREGA(1'b0),
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.CASCADEINREGB(1'b0),
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.CLKA(nclk[0]),
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.CLKB(nclk[0]),
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.DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
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.DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
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|
.DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
|
|
.DIPB(p1_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
|
|
.ENA(rd_act[way]),
|
|
.ENB(wr_act[way]),
|
|
.REGCEA(1'b0),
|
|
.REGCEB(1'b0),
|
|
.SSRA(nclk[1]), //sreset
|
|
.SSRB(nclk[1]), //sreset
|
|
.WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]),
|
|
.WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3])
|
|
);
|
|
end
|
|
end //Nways
|
|
|
|
assign abst_scan_out = 4'b0;
|
|
assign time_scan_out = 1'b0;
|
|
assign repr_scan_out = 1'b0;
|
|
assign bo_pc_failout = 4'h0;
|
|
assign bo_pc_diagloop = 4'h0;
|
|
endgenerate
|
|
|
|
assign unused = |({
|
|
cascadeoutlata ,
|
|
cascadeoutlatb ,
|
|
cascadeoutrega ,
|
|
cascadeoutregb ,
|
|
nclk[0:`NCLK_WIDTH-1] ,
|
|
gnd ,
|
|
vdd ,
|
|
vcs ,
|
|
sg_0 ,
|
|
ary_nsl_thold_0 ,
|
|
abst_sl_thold_0 ,
|
|
time_sl_thold_0 ,
|
|
repr_sl_thold_0 ,
|
|
g8t_clkoff_dc_b,
|
|
ccflush_dc,
|
|
scan_dis_dc_b,
|
|
scan_diag_dc,
|
|
g8t_d_mode_dc,
|
|
g8t_mpw1_dc_b,
|
|
g8t_mpw2_dc_b,
|
|
g8t_delay_lclkr_dc,
|
|
wr_abst_act,
|
|
rd0_abst_act,
|
|
abist_di,
|
|
abist_bw_odd,
|
|
abist_bw_even,
|
|
abist_wr_adr,
|
|
abist_rd0_adr,
|
|
tc_lbist_ary_wrt_thru_dc,
|
|
abist_ena_1,
|
|
abist_g8t_rd0_comp_ena,
|
|
abist_raw_dc_b,
|
|
obs0_abist_cmp,
|
|
abst_scan_in,
|
|
time_scan_in,
|
|
repr_scan_in,
|
|
func_scan_in,
|
|
lcb_bolt_sl_thold_0,
|
|
pc_bo_enable_2,
|
|
pc_bo_reset,
|
|
pc_bo_unload,
|
|
pc_bo_repair,
|
|
pc_bo_shdata,
|
|
pc_bo_select,
|
|
tri_lcb_mpw1_dc_b,
|
|
tri_lcb_mpw2_dc_b,
|
|
tri_lcb_delay_lclkr_dc,
|
|
tri_lcb_clkoff_dc_b,
|
|
tri_lcb_act_dis_dc,
|
|
p1_data_out_swzl});
|
|
|
|
// ###############################################################
|
|
// ## Latches
|
|
// ###############################################################
|
|
tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[rd_act_offset:rd_act_offset + ways - 1]),
|
|
.scout(sov[rd_act_offset:rd_act_offset + ways - 1]),
|
|
.din(rd_act_d),
|
|
.dout(rd_act_q)
|
|
);
|
|
|
|
generate
|
|
//genvar way;
|
|
for (way=0; way<ways; way=way+1) begin : wayReg
|
|
// ###############################################################
|
|
// ## LCB
|
|
// ###############################################################
|
|
tri_lcbnd my_lcb(
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.force_t(func_sl_force),
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(rd_act_q[way]),
|
|
.sg(sg_0),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d1clk(my_d1clk[way]),
|
|
.d2clk(my_d2clk[way]),
|
|
.lclk(my_lclk[way])
|
|
);
|
|
|
|
// ###############################################################
|
|
// ## Placed Latch
|
|
// ###############################################################
|
|
tri_inv_nlats #(.WIDTH(port_bitwidth), .INIT(0), .BTR("NLI0001_X4_A12TH"), .NEEDS_SRESET(0)) data_out_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.lclk(my_lclk[way]),
|
|
.d1clk(my_d1clk[way]),
|
|
.d2clk(my_d2clk[way]),
|
|
.scanin(siv[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),
|
|
.scanout(sov[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),
|
|
.d(data_out_d[(way*port_bitwidth):((way+1)*port_bitwidth)-1]),
|
|
.qb(data_out_b_q[(way*port_bitwidth):((way+1)*port_bitwidth)-1])
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
assign siv[0:(2*port_bitwidth)-1] = {sov[1:(2*port_bitwidth)-1], func_scan_in[0]};
|
|
assign func_scan_out[0] = sov[0];
|
|
assign siv[(2*port_bitwidth):(4*port_bitwidth)-1] = {sov[(2*port_bitwidth)+1:(4*port_bitwidth)-1], func_scan_in[1]};
|
|
assign func_scan_out[1] = sov[(2*port_bitwidth)];
|
|
assign siv[(4*port_bitwidth):(6*port_bitwidth)-1] = {sov[(4*port_bitwidth)+1:(6*port_bitwidth)-1], func_scan_in[3]};
|
|
assign func_scan_out[2] = sov[(4*port_bitwidth)];
|
|
assign siv[(6*port_bitwidth):scan_right] = {sov[(6*port_bitwidth)+1:scan_right], func_scan_in[3]};
|
|
assign func_scan_out[3] = sov[(6*port_bitwidth)];
|
|
|
|
endmodule
|